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gerrit-public.fairphone.software / kernel / msm-4.9 / 48af7215405215e81e72aba1ae8031ca2fea840c / . / include / sound / emu10k1.h
blob: 43b6786abae527e4a7ecbaae77def5a778fa7503 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1#ifndef __SOUND_EMU10K1_H
2#define __SOUND_EMU10K1_H
3
4/*
5 * Copyright (c) by Jaroslav Kysela <perex@suse.cz>,
6 * Creative Labs, Inc.
7 * Definitions for EMU10K1 (SB Live!) chips
8 *
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
24 */
25
26#ifdef __KERNEL__
27
28#include <sound/pcm.h>
29#include <sound/rawmidi.h>
30#include <sound/hwdep.h>
31#include <sound/ac97_codec.h>
32#include <sound/util_mem.h>
33#include <sound/pcm-indirect.h>
34#include <sound/timer.h>
35#include <linux/interrupt.h>
36#include <asm/io.h>
37
38#ifndef PCI_VENDOR_ID_CREATIVE
39#define PCI_VENDOR_ID_CREATIVE 0x1102
40#endif
41#ifndef PCI_DEVICE_ID_CREATIVE_EMU10K1
42#define PCI_DEVICE_ID_CREATIVE_EMU10K1 0x0002
43#endif
44
45/* ------------------- DEFINES -------------------- */
46
47#define EMUPAGESIZE 4096
48#define MAXREQVOICES 8
49#define MAXPAGES 8192
50#define RESERVED 0
51#define NUM_MIDI 16
52#define NUM_G 64 /* use all channels */
53#define NUM_FXSENDS 4
54#define NUM_EFX_PLAYBACK 16
55
56/* FIXME? - according to the OSS driver the EMU10K1 needs a 29 bit DMA mask */
57#define EMU10K1_DMA_MASK 0x7fffffffUL /* 31bit */
58#define AUDIGY_DMA_MASK 0xffffffffUL /* 32bit */
59
60#define TMEMSIZE 256*1024
61#define TMEMSIZEREG 4
62
63#define IP_TO_CP(ip) ((ip == 0) ? 0 : (((0x00001000uL | (ip & 0x00000FFFL)) << (((ip >> 12) & 0x000FL) + 4)) & 0xFFFF0000uL))
64
65// Audigy specify registers are prefixed with 'A_'
66
67/************************************************************************************************/
68/* PCI function 0 registers, address = <val> + PCIBASE0 */
69/************************************************************************************************/
70
71#define PTR 0x00 /* Indexed register set pointer register */
72 /* NOTE: The CHANNELNUM and ADDRESS words can */
73 /* be modified independently of each other. */
74#define PTR_CHANNELNUM_MASK 0x0000003f /* For each per-channel register, indicates the */
75 /* channel number of the register to be */
76 /* accessed. For non per-channel registers the */
77 /* value should be set to zero. */
78#define PTR_ADDRESS_MASK 0x07ff0000 /* Register index */
79#define A_PTR_ADDRESS_MASK 0x0fff0000
80
81#define DATA 0x04 /* Indexed register set data register */
82
83#define IPR 0x08 /* Global interrupt pending register */
84 /* Clear pending interrupts by writing a 1 to */
85 /* the relevant bits and zero to the other bits */
86
87#define IPR_GPIOMSG 0x20000000 /* GPIO message interrupt (RE'd, still not sure
88 which INTE bits enable it) */
89
90/* The next two interrupts are for the midi port on the Audigy Drive (A_MPU1) */
91#define IPR_A_MIDITRANSBUFEMPTY2 0x10000000 /* MIDI UART transmit buffer empty */
92#define IPR_A_MIDIRECVBUFEMPTY2 0x08000000 /* MIDI UART receive buffer empty */
93
94#define IPR_SPDIFBUFFULL 0x04000000 /* SPDIF capture related, 10k2 only? (RE) */
95#define IPR_SPDIFBUFHALFFULL 0x02000000 /* SPDIF capture related? (RE) */
96
97#define IPR_SAMPLERATETRACKER 0x01000000 /* Sample rate tracker lock status change */
98#define IPR_FXDSP 0x00800000 /* Enable FX DSP interrupts */
99#define IPR_FORCEINT 0x00400000 /* Force Sound Blaster interrupt */
100#define IPR_PCIERROR 0x00200000 /* PCI bus error */
101#define IPR_VOLINCR 0x00100000 /* Volume increment button pressed */
102#define IPR_VOLDECR 0x00080000 /* Volume decrement button pressed */
103#define IPR_MUTE 0x00040000 /* Mute button pressed */
104#define IPR_MICBUFFULL 0x00020000 /* Microphone buffer full */
105#define IPR_MICBUFHALFFULL 0x00010000 /* Microphone buffer half full */
106#define IPR_ADCBUFFULL 0x00008000 /* ADC buffer full */
107#define IPR_ADCBUFHALFFULL 0x00004000 /* ADC buffer half full */
108#define IPR_EFXBUFFULL 0x00002000 /* Effects buffer full */
109#define IPR_EFXBUFHALFFULL 0x00001000 /* Effects buffer half full */
110#define IPR_GPSPDIFSTATUSCHANGE 0x00000800 /* GPSPDIF channel status change */
111#define IPR_CDROMSTATUSCHANGE 0x00000400 /* CD-ROM channel status change */
112#define IPR_INTERVALTIMER 0x00000200 /* Interval timer terminal count */
113#define IPR_MIDITRANSBUFEMPTY 0x00000100 /* MIDI UART transmit buffer empty */
114#define IPR_MIDIRECVBUFEMPTY 0x00000080 /* MIDI UART receive buffer empty */
115#define IPR_CHANNELLOOP 0x00000040 /* Channel (half) loop interrupt(s) pending */
116#define IPR_CHANNELNUMBERMASK 0x0000003f /* When IPR_CHANNELLOOP is set, indicates the */
117 /* highest set channel in CLIPL, CLIPH, HLIPL, */
118 /* or HLIPH. When IP is written with CL set, */
119 /* the bit in H/CLIPL or H/CLIPH corresponding */
120 /* to the CIN value written will be cleared. */
121
122#define INTE 0x0c /* Interrupt enable register */
123#define INTE_VIRTUALSB_MASK 0xc0000000 /* Virtual Soundblaster I/O port capture */
124#define INTE_VIRTUALSB_220 0x00000000 /* Capture at I/O base address 0x220-0x22f */
125#define INTE_VIRTUALSB_240 0x40000000 /* Capture at I/O base address 0x240 */
126#define INTE_VIRTUALSB_260 0x80000000 /* Capture at I/O base address 0x260 */
127#define INTE_VIRTUALSB_280 0xc0000000 /* Capture at I/O base address 0x280 */
128#define INTE_VIRTUALMPU_MASK 0x30000000 /* Virtual MPU I/O port capture */
129#define INTE_VIRTUALMPU_300 0x00000000 /* Capture at I/O base address 0x300-0x301 */
130#define INTE_VIRTUALMPU_310 0x10000000 /* Capture at I/O base address 0x310 */
131#define INTE_VIRTUALMPU_320 0x20000000 /* Capture at I/O base address 0x320 */
132#define INTE_VIRTUALMPU_330 0x30000000 /* Capture at I/O base address 0x330 */
133#define INTE_MASTERDMAENABLE 0x08000000 /* Master DMA emulation at 0x000-0x00f */
134#define INTE_SLAVEDMAENABLE 0x04000000 /* Slave DMA emulation at 0x0c0-0x0df */
135#define INTE_MASTERPICENABLE 0x02000000 /* Master PIC emulation at 0x020-0x021 */
136#define INTE_SLAVEPICENABLE 0x01000000 /* Slave PIC emulation at 0x0a0-0x0a1 */
137#define INTE_VSBENABLE 0x00800000 /* Enable virtual Soundblaster */
138#define INTE_ADLIBENABLE 0x00400000 /* Enable AdLib emulation at 0x388-0x38b */
139#define INTE_MPUENABLE 0x00200000 /* Enable virtual MPU */
140#define INTE_FORCEINT 0x00100000 /* Continuously assert INTAN */
141
142#define INTE_MRHANDENABLE 0x00080000 /* Enable the "Mr. Hand" logic */
143 /* NOTE: There is no reason to use this under */
144 /* Linux, and it will cause odd hardware */
145 /* behavior and possibly random segfaults and */
146 /* lockups if enabled. */
147
148/* The next two interrupts are for the midi port on the Audigy Drive (A_MPU1) */
149#define INTE_A_MIDITXENABLE2 0x00020000 /* Enable MIDI transmit-buffer-empty interrupts */
150#define INTE_A_MIDIRXENABLE2 0x00010000 /* Enable MIDI receive-buffer-empty interrupts */
151
152
153#define INTE_SAMPLERATETRACKER 0x00002000 /* Enable sample rate tracker interrupts */
154 /* NOTE: This bit must always be enabled */
155#define INTE_FXDSPENABLE 0x00001000 /* Enable FX DSP interrupts */
156#define INTE_PCIERRORENABLE 0x00000800 /* Enable PCI bus error interrupts */
157#define INTE_VOLINCRENABLE 0x00000400 /* Enable volume increment button interrupts */
158#define INTE_VOLDECRENABLE 0x00000200 /* Enable volume decrement button interrupts */
159#define INTE_MUTEENABLE 0x00000100 /* Enable mute button interrupts */
160#define INTE_MICBUFENABLE 0x00000080 /* Enable microphone buffer interrupts */
161#define INTE_ADCBUFENABLE 0x00000040 /* Enable ADC buffer interrupts */
162#define INTE_EFXBUFENABLE 0x00000020 /* Enable Effects buffer interrupts */
163#define INTE_GPSPDIFENABLE 0x00000010 /* Enable GPSPDIF status interrupts */
164#define INTE_CDSPDIFENABLE 0x00000008 /* Enable CDSPDIF status interrupts */
165#define INTE_INTERVALTIMERENB 0x00000004 /* Enable interval timer interrupts */
166#define INTE_MIDITXENABLE 0x00000002 /* Enable MIDI transmit-buffer-empty interrupts */
167#define INTE_MIDIRXENABLE 0x00000001 /* Enable MIDI receive-buffer-empty interrupts */
168
169#define WC 0x10 /* Wall Clock register */
170#define WC_SAMPLECOUNTER_MASK 0x03FFFFC0 /* Sample periods elapsed since reset */
171#define WC_SAMPLECOUNTER 0x14060010
172#define WC_CURRENTCHANNEL 0x0000003F /* Channel [0..63] currently being serviced */
173 /* NOTE: Each channel takes 1/64th of a sample */
174 /* period to be serviced. */
175
176#define HCFG 0x14 /* Hardware config register */
177 /* NOTE: There is no reason to use the legacy */
178 /* SoundBlaster emulation stuff described below */
179 /* under Linux, and all kinds of weird hardware */
180 /* behavior can result if you try. Don't. */
181#define HCFG_LEGACYFUNC_MASK 0xe0000000 /* Legacy function number */
182#define HCFG_LEGACYFUNC_MPU 0x00000000 /* Legacy MPU */
183#define HCFG_LEGACYFUNC_SB 0x40000000 /* Legacy SB */
184#define HCFG_LEGACYFUNC_AD 0x60000000 /* Legacy AD */
185#define HCFG_LEGACYFUNC_MPIC 0x80000000 /* Legacy MPIC */
186#define HCFG_LEGACYFUNC_MDMA 0xa0000000 /* Legacy MDMA */
187#define HCFG_LEGACYFUNC_SPCI 0xc0000000 /* Legacy SPCI */
188#define HCFG_LEGACYFUNC_SDMA 0xe0000000 /* Legacy SDMA */
189#define HCFG_IOCAPTUREADDR 0x1f000000 /* The 4 LSBs of the captured I/O address. */
190#define HCFG_LEGACYWRITE 0x00800000 /* 1 = write, 0 = read */
191#define HCFG_LEGACYWORD 0x00400000 /* 1 = word, 0 = byte */
192#define HCFG_LEGACYINT 0x00200000 /* 1 = legacy event captured. Write 1 to clear. */
193 /* NOTE: The rest of the bits in this register */
194 /* _are_ relevant under Linux. */
195#define HCFG_CODECFORMAT_MASK 0x00070000 /* CODEC format */
196#define HCFG_CODECFORMAT_AC97 0x00000000 /* AC97 CODEC format -- Primary Output */
197#define HCFG_CODECFORMAT_I2S 0x00010000 /* I2S CODEC format -- Secondary (Rear) Output */
198#define HCFG_GPINPUT0 0x00004000 /* External pin112 */
199#define HCFG_GPINPUT1 0x00002000 /* External pin110 */
200#define HCFG_GPOUTPUT_MASK 0x00001c00 /* External pins which may be controlled */
201#define HCFG_GPOUT0 0x00001000 /* External pin? (spdif enable on 5.1) */
202#define HCFG_GPOUT1 0x00000800 /* External pin? (IR) */
203#define HCFG_GPOUT2 0x00000400 /* External pin? (IR) */
204#define HCFG_JOYENABLE 0x00000200 /* Internal joystick enable */
205#define HCFG_PHASETRACKENABLE 0x00000100 /* Phase tracking enable */
206 /* 1 = Force all 3 async digital inputs to use */
207 /* the same async sample rate tracker (ZVIDEO) */
208#define HCFG_AC3ENABLE_MASK 0x000000e0 /* AC3 async input control - Not implemented */
209#define HCFG_AC3ENABLE_ZVIDEO 0x00000080 /* Channels 0 and 1 replace ZVIDEO */
210#define HCFG_AC3ENABLE_CDSPDIF 0x00000040 /* Channels 0 and 1 replace CDSPDIF */
211#define HCFG_AC3ENABLE_GPSPDIF 0x00000020 /* Channels 0 and 1 replace GPSPDIF */
212#define HCFG_AUTOMUTE 0x00000010 /* When set, the async sample rate convertors */
213 /* will automatically mute their output when */
214 /* they are not rate-locked to the external */
215 /* async audio source */
216#define HCFG_LOCKSOUNDCACHE 0x00000008 /* 1 = Cancel bustmaster accesses to soundcache */
217 /* NOTE: This should generally never be used. */
218#define HCFG_LOCKTANKCACHE_MASK 0x00000004 /* 1 = Cancel bustmaster accesses to tankcache */
219 /* NOTE: This should generally never be used. */
220#define HCFG_LOCKTANKCACHE 0x01020014
221#define HCFG_MUTEBUTTONENABLE 0x00000002 /* 1 = Master mute button sets AUDIOENABLE = 0. */
222 /* NOTE: This is a 'cheap' way to implement a */
223 /* master mute function on the mute button, and */
224 /* in general should not be used unless a more */
225 /* sophisticated master mute function has not */
226 /* been written. */
227#define HCFG_AUDIOENABLE 0x00000001 /* 0 = CODECs transmit zero-valued samples */
228 /* Should be set to 1 when the EMU10K1 is */
229 /* completely initialized. */
230
231//For Audigy, MPU port move to 0x70-0x74 ptr register
232
233#define MUDATA 0x18 /* MPU401 data register (8 bits) */
234
235#define MUCMD 0x19 /* MPU401 command register (8 bits) */
236#define MUCMD_RESET 0xff /* RESET command */
237#define MUCMD_ENTERUARTMODE 0x3f /* Enter_UART_mode command */
238 /* NOTE: All other commands are ignored */
239
240#define MUSTAT MUCMD /* MPU401 status register (8 bits) */
241#define MUSTAT_IRDYN 0x80 /* 0 = MIDI data or command ACK */
242#define MUSTAT_ORDYN 0x40 /* 0 = MUDATA can accept a command or data */
243
244#define A_IOCFG 0x18 /* GPIO on Audigy card (16bits) */
245#define A_GPINPUT_MASK 0xff00
246#define A_GPOUTPUT_MASK 0x00ff
247
248// Audigy output/GPIO stuff taken from the kX drivers
249#define A_IOCFG_GPOUT0 0x0044 /* analog/digital */
250#define A_IOCFG_DISABLE_ANALOG 0x0040 /* = 'enable' for Audigy2 (chiprev=4) */
251#define A_IOCFG_ENABLE_DIGITAL 0x0004
252#define A_IOCFG_UNKNOWN_20 0x0020
253#define A_IOCFG_DISABLE_AC97_FRONT 0x0080 /* turn off ac97 front -> front (10k2.1) */
254#define A_IOCFG_GPOUT1 0x0002 /* IR? drive's internal bypass (?) */
255#define A_IOCFG_GPOUT2 0x0001 /* IR */
256#define A_IOCFG_MULTIPURPOSE_JACK 0x2000 /* center+lfe+rear_center (a2/a2ex) */
257 /* + digital for generic 10k2 */
258#define A_IOCFG_DIGITAL_JACK 0x1000 /* digital for a2 platinum */
259#define A_IOCFG_FRONT_JACK 0x4000
260#define A_IOCFG_REAR_JACK 0x8000
261#define A_IOCFG_PHONES_JACK 0x0100 /* LiveDrive */
262
263/* outputs:
264 * for audigy2 platinum: 0xa00
265 * for a2 platinum ex: 0x1c00
266 * for a1 platinum: 0x0
267 */
268
269#define TIMER 0x1a /* Timer terminal count register */
270 /* NOTE: After the rate is changed, a maximum */
271 /* of 1024 sample periods should be allowed */
272 /* before the new rate is guaranteed accurate. */
273#define TIMER_RATE_MASK 0x000003ff /* Timer interrupt rate in sample periods */
274 /* 0 == 1024 periods, [1..4] are not useful */
275#define TIMER_RATE 0x0a00001a
276
277#define AC97DATA 0x1c /* AC97 register set data register (16 bit) */
278
279#define AC97ADDRESS 0x1e /* AC97 register set address register (8 bit) */
280#define AC97ADDRESS_READY 0x80 /* Read-only bit, reflects CODEC READY signal */
281#define AC97ADDRESS_ADDRESS 0x7f /* Address of indexed AC97 register */
282
283/* Available on the Audigy 2 and Audigy 4 only. This is the P16V chip. */
284#define PTR2 0x20 /* Indexed register set pointer register */
285#define DATA2 0x24 /* Indexed register set data register */
286#define IPR2 0x28 /* P16V interrupt pending register */
287#define IPR2_PLAYBACK_CH_0_LOOP 0x00001000 /* Playback Channel 0 loop */
288#define IPR2_PLAYBACK_CH_0_HALF_LOOP 0x00000100 /* Playback Channel 0 half loop */
289#define IPR2_CAPTURE_CH_0_LOOP 0x00100000 /* Capture Channel 0 loop */
290#define IPR2_CAPTURE_CH_0_HALF_LOOP 0x00010000 /* Capture Channel 0 half loop */
291 /* 0x00000100 Playback. Only in once per period.
292 * 0x00110000 Capture. Int on half buffer.
293 */
294#define INTE2 0x2c /* P16V Interrupt enable register. */
295#define INTE2_PLAYBACK_CH_0_LOOP 0x00001000 /* Playback Channel 0 loop */
296#define INTE2_PLAYBACK_CH_0_HALF_LOOP 0x00000100 /* Playback Channel 0 half loop */
297#define INTE2_PLAYBACK_CH_1_LOOP 0x00002000 /* Playback Channel 1 loop */
298#define INTE2_PLAYBACK_CH_1_HALF_LOOP 0x00000200 /* Playback Channel 1 half loop */
299#define INTE2_PLAYBACK_CH_2_LOOP 0x00004000 /* Playback Channel 2 loop */
300#define INTE2_PLAYBACK_CH_2_HALF_LOOP 0x00000400 /* Playback Channel 2 half loop */
301#define INTE2_PLAYBACK_CH_3_LOOP 0x00008000 /* Playback Channel 3 loop */
302#define INTE2_PLAYBACK_CH_3_HALF_LOOP 0x00000800 /* Playback Channel 3 half loop */
303#define INTE2_CAPTURE_CH_0_LOOP 0x00100000 /* Capture Channel 0 loop */
304#define INTE2_CAPTURE_CH_0_HALF_LOOP 0x00010000 /* Caputre Channel 0 half loop */
305#define HCFG2 0x34 /* Defaults: 0, win2000 sets it to 00004201 */
306 /* 0x00000000 2-channel output. */
307 /* 0x00000200 8-channel output. */
308 /* 0x00000004 pauses stream/irq fail. */
309 /* Rest of bits no nothing to sound output */
310 /* bit 0: Enable P16V audio.
311 * bit 1: Lock P16V record memory cache.
312 * bit 2: Lock P16V playback memory cache.
313 * bit 3: Dummy record insert zero samples.
314 * bit 8: Record 8-channel in phase.
315 * bit 9: Playback 8-channel in phase.
316 * bit 11-12: Playback mixer attenuation: 0=0dB, 1=-6dB, 2=-12dB, 3=Mute.
317 * bit 13: Playback mixer enable.
318 * bit 14: Route SRC48 mixer output to fx engine.
319 * bit 15: Enable IEEE 1394 chip.
320 */
321#define IPR3 0x38 /* Cdif interrupt pending register */
322#define INTE3 0x3c /* Cdif interrupt enable register. */
323/************************************************************************************************/
324/* PCI function 1 registers, address = <val> + PCIBASE1 */
325/************************************************************************************************/
326
327#define JOYSTICK1 0x00 /* Analog joystick port register */
328#define JOYSTICK2 0x01 /* Analog joystick port register */
329#define JOYSTICK3 0x02 /* Analog joystick port register */
330#define JOYSTICK4 0x03 /* Analog joystick port register */
331#define JOYSTICK5 0x04 /* Analog joystick port register */
332#define JOYSTICK6 0x05 /* Analog joystick port register */
333#define JOYSTICK7 0x06 /* Analog joystick port register */
334#define JOYSTICK8 0x07 /* Analog joystick port register */
335
336/* When writing, any write causes JOYSTICK_COMPARATOR output enable to be pulsed on write. */
337/* When reading, use these bitfields: */
338#define JOYSTICK_BUTTONS 0x0f /* Joystick button data */
339#define JOYSTICK_COMPARATOR 0xf0 /* Joystick comparator data */
340
341
342/********************************************************************************************************/
343/* Emu10k1 pointer-offset register set, accessed through the PTR and DATA registers */
344/********************************************************************************************************/
345
346#define CPF 0x00 /* Current pitch and fraction register */
347#define CPF_CURRENTPITCH_MASK 0xffff0000 /* Current pitch (linear, 0x4000 == unity pitch shift) */
348#define CPF_CURRENTPITCH 0x10100000
349#define CPF_STEREO_MASK 0x00008000 /* 1 = Even channel interleave, odd channel locked */
350#define CPF_STOP_MASK 0x00004000 /* 1 = Current pitch forced to 0 */
351#define CPF_FRACADDRESS_MASK 0x00003fff /* Linear fractional address of the current channel */
352
353#define PTRX 0x01 /* Pitch target and send A/B amounts register */
354#define PTRX_PITCHTARGET_MASK 0xffff0000 /* Pitch target of specified channel */
355#define PTRX_PITCHTARGET 0x10100001
356#define PTRX_FXSENDAMOUNT_A_MASK 0x0000ff00 /* Linear level of channel output sent to FX send bus A */
357#define PTRX_FXSENDAMOUNT_A 0x08080001
358#define PTRX_FXSENDAMOUNT_B_MASK 0x000000ff /* Linear level of channel output sent to FX send bus B */
359#define PTRX_FXSENDAMOUNT_B 0x08000001
360
361#define CVCF 0x02 /* Current volume and filter cutoff register */
362#define CVCF_CURRENTVOL_MASK 0xffff0000 /* Current linear volume of specified channel */
363#define CVCF_CURRENTVOL 0x10100002
364#define CVCF_CURRENTFILTER_MASK 0x0000ffff /* Current filter cutoff frequency of specified channel */
365#define CVCF_CURRENTFILTER 0x10000002
366
367#define VTFT 0x03 /* Volume target and filter cutoff target register */
368#define VTFT_VOLUMETARGET_MASK 0xffff0000 /* Volume target of specified channel */
369#define VTFT_VOLUMETARGET 0x10100003
370#define VTFT_FILTERTARGET_MASK 0x0000ffff /* Filter cutoff target of specified channel */
371#define VTFT_FILTERTARGET 0x10000003
372
373#define Z1 0x05 /* Filter delay memory 1 register */
374
375#define Z2 0x04 /* Filter delay memory 2 register */
376
377#define PSST 0x06 /* Send C amount and loop start address register */
378#define PSST_FXSENDAMOUNT_C_MASK 0xff000000 /* Linear level of channel output sent to FX send bus C */
379
380#define PSST_FXSENDAMOUNT_C 0x08180006
381
382#define PSST_LOOPSTARTADDR_MASK 0x00ffffff /* Loop start address of the specified channel */
383#define PSST_LOOPSTARTADDR 0x18000006
384
385#define DSL 0x07 /* Send D amount and loop start address register */
386#define DSL_FXSENDAMOUNT_D_MASK 0xff000000 /* Linear level of channel output sent to FX send bus D */
387
388#define DSL_FXSENDAMOUNT_D 0x08180007
389
390#define DSL_LOOPENDADDR_MASK 0x00ffffff /* Loop end address of the specified channel */
391#define DSL_LOOPENDADDR 0x18000007
392
393#define CCCA 0x08 /* Filter Q, interp. ROM, byte size, cur. addr register */
394#define CCCA_RESONANCE 0xf0000000 /* Lowpass filter resonance (Q) height */
395#define CCCA_INTERPROMMASK 0x0e000000 /* Selects passband of interpolation ROM */
396 /* 1 == full band, 7 == lowpass */
397 /* ROM 0 is used when pitch shifting downward or less */
398 /* then 3 semitones upward. Increasingly higher ROM */
399 /* numbers are used, typically in steps of 3 semitones, */
400 /* as upward pitch shifting is performed. */
401#define CCCA_INTERPROM_0 0x00000000 /* Select interpolation ROM 0 */
402#define CCCA_INTERPROM_1 0x02000000 /* Select interpolation ROM 1 */
403#define CCCA_INTERPROM_2 0x04000000 /* Select interpolation ROM 2 */
404#define CCCA_INTERPROM_3 0x06000000 /* Select interpolation ROM 3 */
405#define CCCA_INTERPROM_4 0x08000000 /* Select interpolation ROM 4 */
406#define CCCA_INTERPROM_5 0x0a000000 /* Select interpolation ROM 5 */
407#define CCCA_INTERPROM_6 0x0c000000 /* Select interpolation ROM 6 */
408#define CCCA_INTERPROM_7 0x0e000000 /* Select interpolation ROM 7 */
409#define CCCA_8BITSELECT 0x01000000 /* 1 = Sound memory for this channel uses 8-bit samples */
410#define CCCA_CURRADDR_MASK 0x00ffffff /* Current address of the selected channel */
411#define CCCA_CURRADDR 0x18000008
412
413#define CCR 0x09 /* Cache control register */
414#define CCR_CACHEINVALIDSIZE 0x07190009
415#define CCR_CACHEINVALIDSIZE_MASK 0xfe000000 /* Number of invalid samples cache for this channel */
416#define CCR_CACHELOOPFLAG 0x01000000 /* 1 = Cache has a loop service pending */
417#define CCR_INTERLEAVEDSAMPLES 0x00800000 /* 1 = A cache service will fetch interleaved samples */
418#define CCR_WORDSIZEDSAMPLES 0x00400000 /* 1 = A cache service will fetch word sized samples */
419#define CCR_READADDRESS 0x06100009
420#define CCR_READADDRESS_MASK 0x003f0000 /* Location of cache just beyond current cache service */
421#define CCR_LOOPINVALSIZE 0x0000fe00 /* Number of invalid samples in cache prior to loop */
422 /* NOTE: This is valid only if CACHELOOPFLAG is set */
423#define CCR_LOOPFLAG 0x00000100 /* Set for a single sample period when a loop occurs */
424#define CCR_CACHELOOPADDRHI 0x000000ff /* DSL_LOOPSTARTADDR's hi byte if CACHELOOPFLAG is set */
425
426#define CLP 0x0a /* Cache loop register (valid if CCR_CACHELOOPFLAG = 1) */
427 /* NOTE: This register is normally not used */
428#define CLP_CACHELOOPADDR 0x0000ffff /* Cache loop address (DSL_LOOPSTARTADDR [0..15]) */
429
430#define FXRT 0x0b /* Effects send routing register */
431 /* NOTE: It is illegal to assign the same routing to */
432 /* two effects sends. */
433#define FXRT_CHANNELA 0x000f0000 /* Effects send bus number for channel's effects send A */
434#define FXRT_CHANNELB 0x00f00000 /* Effects send bus number for channel's effects send B */
435#define FXRT_CHANNELC 0x0f000000 /* Effects send bus number for channel's effects send C */
436#define FXRT_CHANNELD 0xf0000000 /* Effects send bus number for channel's effects send D */
437
438#define MAPA 0x0c /* Cache map A */
439
440#define MAPB 0x0d /* Cache map B */
441
442#define MAP_PTE_MASK 0xffffe000 /* The 19 MSBs of the PTE indexed by the PTI */
443#define MAP_PTI_MASK 0x00001fff /* The 13 bit index to one of the 8192 PTE dwords */
444
445#define ENVVOL 0x10 /* Volume envelope register */
446#define ENVVOL_MASK 0x0000ffff /* Current value of volume envelope state variable */
447 /* 0x8000-n == 666*n usec delay */
448
449#define ATKHLDV 0x11 /* Volume envelope hold and attack register */
450#define ATKHLDV_PHASE0 0x00008000 /* 0 = Begin attack phase */
451#define ATKHLDV_HOLDTIME_MASK 0x00007f00 /* Envelope hold time (127-n == n*88.2msec) */
452#define ATKHLDV_ATTACKTIME_MASK 0x0000007f /* Envelope attack time, log encoded */
453 /* 0 = infinite, 1 = 10.9msec, ... 0x7f = 5.5msec */
454
455#define DCYSUSV 0x12 /* Volume envelope sustain and decay register */
456#define DCYSUSV_PHASE1_MASK 0x00008000 /* 0 = Begin attack phase, 1 = begin release phase */
457#define DCYSUSV_SUSTAINLEVEL_MASK 0x00007f00 /* 127 = full, 0 = off, 0.75dB increments */
458#define DCYSUSV_CHANNELENABLE_MASK 0x00000080 /* 1 = Inhibit envelope engine from writing values in */
459 /* this channel and from writing to pitch, filter and */
460 /* volume targets. */
461#define DCYSUSV_DECAYTIME_MASK 0x0000007f /* Volume envelope decay time, log encoded */
462 /* 0 = 43.7msec, 1 = 21.8msec, 0x7f = 22msec */
463
464#define LFOVAL1 0x13 /* Modulation LFO value */
465#define LFOVAL_MASK 0x0000ffff /* Current value of modulation LFO state variable */
466 /* 0x8000-n == 666*n usec delay */
467
468#define ENVVAL 0x14 /* Modulation envelope register */
469#define ENVVAL_MASK 0x0000ffff /* Current value of modulation envelope state variable */
470 /* 0x8000-n == 666*n usec delay */
471
472#define ATKHLDM 0x15 /* Modulation envelope hold and attack register */
473#define ATKHLDM_PHASE0 0x00008000 /* 0 = Begin attack phase */
474#define ATKHLDM_HOLDTIME 0x00007f00 /* Envelope hold time (127-n == n*42msec) */
475#define ATKHLDM_ATTACKTIME 0x0000007f /* Envelope attack time, log encoded */
476 /* 0 = infinite, 1 = 11msec, ... 0x7f = 5.5msec */
477
478#define DCYSUSM 0x16 /* Modulation envelope decay and sustain register */
479#define DCYSUSM_PHASE1_MASK 0x00008000 /* 0 = Begin attack phase, 1 = begin release phase */
480#define DCYSUSM_SUSTAINLEVEL_MASK 0x00007f00 /* 127 = full, 0 = off, 0.75dB increments */
481#define DCYSUSM_DECAYTIME_MASK 0x0000007f /* Envelope decay time, log encoded */
482 /* 0 = 43.7msec, 1 = 21.8msec, 0x7f = 22msec */
483
484#define LFOVAL2 0x17 /* Vibrato LFO register */
485#define LFOVAL2_MASK 0x0000ffff /* Current value of vibrato LFO state variable */
486 /* 0x8000-n == 666*n usec delay */
487
488#define IP 0x18 /* Initial pitch register */
489#define IP_MASK 0x0000ffff /* Exponential initial pitch shift */
490 /* 4 bits of octave, 12 bits of fractional octave */
491#define IP_UNITY 0x0000e000 /* Unity pitch shift */
492
493#define IFATN 0x19 /* Initial filter cutoff and attenuation register */
494#define IFATN_FILTERCUTOFF_MASK 0x0000ff00 /* Initial filter cutoff frequency in exponential units */
495 /* 6 most significant bits are semitones */
496 /* 2 least significant bits are fractions */
497#define IFATN_FILTERCUTOFF 0x08080019
498#define IFATN_ATTENUATION_MASK 0x000000ff /* Initial attenuation in 0.375dB steps */
499#define IFATN_ATTENUATION 0x08000019
500
501
502#define PEFE 0x1a /* Pitch envelope and filter envelope amount register */
503#define PEFE_PITCHAMOUNT_MASK 0x0000ff00 /* Pitch envlope amount */
504 /* Signed 2's complement, +/- one octave peak extremes */
505#define PEFE_PITCHAMOUNT 0x0808001a
506#define PEFE_FILTERAMOUNT_MASK 0x000000ff /* Filter envlope amount */
507 /* Signed 2's complement, +/- six octaves peak extremes */
508#define PEFE_FILTERAMOUNT 0x0800001a
509#define FMMOD 0x1b /* Vibrato/filter modulation from LFO register */
510#define FMMOD_MODVIBRATO 0x0000ff00 /* Vibrato LFO modulation depth */
511 /* Signed 2's complement, +/- one octave extremes */
512#define FMMOD_MOFILTER 0x000000ff /* Filter LFO modulation depth */
513 /* Signed 2's complement, +/- three octave extremes */
514
515
516#define TREMFRQ 0x1c /* Tremolo amount and modulation LFO frequency register */
517#define TREMFRQ_DEPTH 0x0000ff00 /* Tremolo depth */
518 /* Signed 2's complement, with +/- 12dB extremes */
519
520#define TREMFRQ_FREQUENCY 0x000000ff /* Tremolo LFO frequency */
521 /* ??Hz steps, maximum of ?? Hz. */
522#define FM2FRQ2 0x1d /* Vibrato amount and vibrato LFO frequency register */
523#define FM2FRQ2_DEPTH 0x0000ff00 /* Vibrato LFO vibrato depth */
524 /* Signed 2's complement, +/- one octave extremes */
525#define FM2FRQ2_FREQUENCY 0x000000ff /* Vibrato LFO frequency */
526 /* 0.039Hz steps, maximum of 9.85 Hz. */
527
528#define TEMPENV 0x1e /* Tempory envelope register */
529#define TEMPENV_MASK 0x0000ffff /* 16-bit value */
530 /* NOTE: All channels contain internal variables; do */
531 /* not write to these locations. */
532
533/* 1f something */
534
535#define CD0 0x20 /* Cache data 0 register */
536#define CD1 0x21 /* Cache data 1 register */
537#define CD2 0x22 /* Cache data 2 register */
538#define CD3 0x23 /* Cache data 3 register */
539#define CD4 0x24 /* Cache data 4 register */
540#define CD5 0x25 /* Cache data 5 register */
541#define CD6 0x26 /* Cache data 6 register */
542#define CD7 0x27 /* Cache data 7 register */
543#define CD8 0x28 /* Cache data 8 register */
544#define CD9 0x29 /* Cache data 9 register */
545#define CDA 0x2a /* Cache data A register */
546#define CDB 0x2b /* Cache data B register */
547#define CDC 0x2c /* Cache data C register */
548#define CDD 0x2d /* Cache data D register */
549#define CDE 0x2e /* Cache data E register */
550#define CDF 0x2f /* Cache data F register */
551
552/* 0x30-3f seem to be the same as 0x20-2f */
553
554#define PTB 0x40 /* Page table base register */
555#define PTB_MASK 0xfffff000 /* Physical address of the page table in host memory */
556
557#define TCB 0x41 /* Tank cache base register */
558#define TCB_MASK 0xfffff000 /* Physical address of the bottom of host based TRAM */
559
560#define ADCCR 0x42 /* ADC sample rate/stereo control register */
561#define ADCCR_RCHANENABLE 0x00000010 /* Enables right channel for writing to the host */
562#define ADCCR_LCHANENABLE 0x00000008 /* Enables left channel for writing to the host */
563 /* NOTE: To guarantee phase coherency, both channels */
564 /* must be disabled prior to enabling both channels. */
565#define A_ADCCR_RCHANENABLE 0x00000020
566#define A_ADCCR_LCHANENABLE 0x00000010
567
568#define A_ADCCR_SAMPLERATE_MASK 0x0000000F /* Audigy sample rate convertor output rate */
569#define ADCCR_SAMPLERATE_MASK 0x00000007 /* Sample rate convertor output rate */
570#define ADCCR_SAMPLERATE_48 0x00000000 /* 48kHz sample rate */
571#define ADCCR_SAMPLERATE_44 0x00000001 /* 44.1kHz sample rate */
572#define ADCCR_SAMPLERATE_32 0x00000002 /* 32kHz sample rate */
573#define ADCCR_SAMPLERATE_24 0x00000003 /* 24kHz sample rate */
574#define ADCCR_SAMPLERATE_22 0x00000004 /* 22.05kHz sample rate */
575#define ADCCR_SAMPLERATE_16 0x00000005 /* 16kHz sample rate */
576#define ADCCR_SAMPLERATE_11 0x00000006 /* 11.025kHz sample rate */
577#define ADCCR_SAMPLERATE_8 0x00000007 /* 8kHz sample rate */
578#define A_ADCCR_SAMPLERATE_12 0x00000006 /* 12kHz sample rate */
579#define A_ADCCR_SAMPLERATE_11 0x00000007 /* 11.025kHz sample rate */
580#define A_ADCCR_SAMPLERATE_8 0x00000008 /* 8kHz sample rate */
581
582#define FXWC 0x43 /* FX output write channels register */
583 /* When set, each bit enables the writing of the */
584 /* corresponding FX output channel (internal registers */
585 /* 0x20-0x3f) to host memory. This mode of recording */
586 /* is 16bit, 48KHz only. All 32 channels can be enabled */
587 /* simultaneously. */
588
589#define FXWC_DEFAULTROUTE_C (1<<0) /* left emu out? */
590#define FXWC_DEFAULTROUTE_B (1<<1) /* right emu out? */
591#define FXWC_DEFAULTROUTE_A (1<<12)
592#define FXWC_DEFAULTROUTE_D (1<<13)
593#define FXWC_ADCLEFT (1<<18)
594#define FXWC_CDROMSPDIFLEFT (1<<18)
595#define FXWC_ADCRIGHT (1<<19)
596#define FXWC_CDROMSPDIFRIGHT (1<<19)
597#define FXWC_MIC (1<<20)
598#define FXWC_ZOOMLEFT (1<<20)
599#define FXWC_ZOOMRIGHT (1<<21)
600#define FXWC_SPDIFLEFT (1<<22) /* 0x00400000 */
601#define FXWC_SPDIFRIGHT (1<<23) /* 0x00800000 */
602
603#define TCBS 0x44 /* Tank cache buffer size register */
604#define TCBS_MASK 0x00000007 /* Tank cache buffer size field */
605#define TCBS_BUFFSIZE_16K 0x00000000
606#define TCBS_BUFFSIZE_32K 0x00000001
607#define TCBS_BUFFSIZE_64K 0x00000002
608#define TCBS_BUFFSIZE_128K 0x00000003
609#define TCBS_BUFFSIZE_256K 0x00000004
610#define TCBS_BUFFSIZE_512K 0x00000005
611#define TCBS_BUFFSIZE_1024K 0x00000006
612#define TCBS_BUFFSIZE_2048K 0x00000007
613
614#define MICBA 0x45 /* AC97 microphone buffer address register */
615#define MICBA_MASK 0xfffff000 /* 20 bit base address */
616
617#define ADCBA 0x46 /* ADC buffer address register */
618#define ADCBA_MASK 0xfffff000 /* 20 bit base address */
619
620#define FXBA 0x47 /* FX Buffer Address */
621#define FXBA_MASK 0xfffff000 /* 20 bit base address */
622
623/* 0x48 something - word access, defaults to 3f */
624
625#define MICBS 0x49 /* Microphone buffer size register */
626
627#define ADCBS 0x4a /* ADC buffer size register */
628
629#define FXBS 0x4b /* FX buffer size register */
630
631/* register: 0x4c..4f: ffff-ffff current amounts, per-channel */
632
633/* The following mask values define the size of the ADC, MIX and FX buffers in bytes */
634#define ADCBS_BUFSIZE_NONE 0x00000000
635#define ADCBS_BUFSIZE_384 0x00000001
636#define ADCBS_BUFSIZE_448 0x00000002
637#define ADCBS_BUFSIZE_512 0x00000003
638#define ADCBS_BUFSIZE_640 0x00000004
639#define ADCBS_BUFSIZE_768 0x00000005
640#define ADCBS_BUFSIZE_896 0x00000006
641#define ADCBS_BUFSIZE_1024 0x00000007
642#define ADCBS_BUFSIZE_1280 0x00000008
643#define ADCBS_BUFSIZE_1536 0x00000009
644#define ADCBS_BUFSIZE_1792 0x0000000a
645#define ADCBS_BUFSIZE_2048 0x0000000b
646#define ADCBS_BUFSIZE_2560 0x0000000c
647#define ADCBS_BUFSIZE_3072 0x0000000d
648#define ADCBS_BUFSIZE_3584 0x0000000e
649#define ADCBS_BUFSIZE_4096 0x0000000f
650#define ADCBS_BUFSIZE_5120 0x00000010
651#define ADCBS_BUFSIZE_6144 0x00000011
652#define ADCBS_BUFSIZE_7168 0x00000012
653#define ADCBS_BUFSIZE_8192 0x00000013
654#define ADCBS_BUFSIZE_10240 0x00000014
655#define ADCBS_BUFSIZE_12288 0x00000015
656#define ADCBS_BUFSIZE_14366 0x00000016
657#define ADCBS_BUFSIZE_16384 0x00000017
658#define ADCBS_BUFSIZE_20480 0x00000018
659#define ADCBS_BUFSIZE_24576 0x00000019
660#define ADCBS_BUFSIZE_28672 0x0000001a
661#define ADCBS_BUFSIZE_32768 0x0000001b
662#define ADCBS_BUFSIZE_40960 0x0000001c
663#define ADCBS_BUFSIZE_49152 0x0000001d
664#define ADCBS_BUFSIZE_57344 0x0000001e
665#define ADCBS_BUFSIZE_65536 0x0000001f
666
667
668#define CDCS 0x50 /* CD-ROM digital channel status register */
669
670#define GPSCS 0x51 /* General Purpose SPDIF channel status register*/
671
672#define DBG 0x52 /* DO NOT PROGRAM THIS REGISTER!!! MAY DESTROY CHIP */
673
674#define REG53 0x53 /* DO NOT PROGRAM THIS REGISTER!!! MAY DESTROY CHIP */
675
676#define A_DBG 0x53
677#define A_DBG_SINGLE_STEP 0x00020000 /* Set to zero to start dsp */
678#define A_DBG_ZC 0x40000000 /* zero tram counter */
679#define A_DBG_STEP_ADDR 0x000003ff
680#define A_DBG_SATURATION_OCCURED 0x20000000
681#define A_DBG_SATURATION_ADDR 0x0ffc0000
682
683// NOTE: 0x54,55,56: 64-bit
684#define SPCS0 0x54 /* SPDIF output Channel Status 0 register */
685
686#define SPCS1 0x55 /* SPDIF output Channel Status 1 register */
687
688#define SPCS2 0x56 /* SPDIF output Channel Status 2 register */
689
690#define SPCS_CLKACCYMASK 0x30000000 /* Clock accuracy */
691#define SPCS_CLKACCY_1000PPM 0x00000000 /* 1000 parts per million */
692#define SPCS_CLKACCY_50PPM 0x10000000 /* 50 parts per million */
693#define SPCS_CLKACCY_VARIABLE 0x20000000 /* Variable accuracy */
694#define SPCS_SAMPLERATEMASK 0x0f000000 /* Sample rate */
695#define SPCS_SAMPLERATE_44 0x00000000 /* 44.1kHz sample rate */
696#define SPCS_SAMPLERATE_48 0x02000000 /* 48kHz sample rate */
697#define SPCS_SAMPLERATE_32 0x03000000 /* 32kHz sample rate */
698#define SPCS_CHANNELNUMMASK 0x00f00000 /* Channel number */
699#define SPCS_CHANNELNUM_UNSPEC 0x00000000 /* Unspecified channel number */
700#define SPCS_CHANNELNUM_LEFT 0x00100000 /* Left channel */
701#define SPCS_CHANNELNUM_RIGHT 0x00200000 /* Right channel */
702#define SPCS_SOURCENUMMASK 0x000f0000 /* Source number */
703#define SPCS_SOURCENUM_UNSPEC 0x00000000 /* Unspecified source number */
704#define SPCS_GENERATIONSTATUS 0x00008000 /* Originality flag (see IEC-958 spec) */
705#define SPCS_CATEGORYCODEMASK 0x00007f00 /* Category code (see IEC-958 spec) */
706#define SPCS_MODEMASK 0x000000c0 /* Mode (see IEC-958 spec) */
707#define SPCS_EMPHASISMASK 0x00000038 /* Emphasis */
708#define SPCS_EMPHASIS_NONE 0x00000000 /* No emphasis */
709#define SPCS_EMPHASIS_50_15 0x00000008 /* 50/15 usec 2 channel */
710#define SPCS_COPYRIGHT 0x00000004 /* Copyright asserted flag -- do not modify */
711#define SPCS_NOTAUDIODATA 0x00000002 /* 0 = Digital audio, 1 = not audio */
712#define SPCS_PROFESSIONAL 0x00000001 /* 0 = Consumer (IEC-958), 1 = pro (AES3-1992) */
713
714/* The 32-bit CLIx and SOLx registers all have one bit per channel control/status */
715#define CLIEL 0x58 /* Channel loop interrupt enable low register */
716
717#define CLIEH 0x59 /* Channel loop interrupt enable high register */
718
719#define CLIPL 0x5a /* Channel loop interrupt pending low register */
720
721#define CLIPH 0x5b /* Channel loop interrupt pending high register */
722
723#define SOLEL 0x5c /* Stop on loop enable low register */
724
725#define SOLEH 0x5d /* Stop on loop enable high register */
726
727#define SPBYPASS 0x5e /* SPDIF BYPASS mode register */
728#define SPBYPASS_SPDIF0_MASK 0x00000003 /* SPDIF 0 bypass mode */
729#define SPBYPASS_SPDIF1_MASK 0x0000000c /* SPDIF 1 bypass mode */
730/* bypass mode: 0 - DSP; 1 - SPDIF A, 2 - SPDIF B, 3 - SPDIF C */
731#define SPBYPASS_FORMAT 0x00000f00 /* If 1, SPDIF XX uses 24 bit, if 0 - 20 bit */
732
733#define AC97SLOT 0x5f /* additional AC97 slots enable bits */
734#define AC97SLOT_REAR_RIGHT 0x01 /* Rear left */
735#define AC97SLOT_REAR_LEFT 0x02 /* Rear right */
736#define AC97SLOT_CNTR 0x10 /* Center enable */
737#define AC97SLOT_LFE 0x20 /* LFE enable */
738
739// NOTE: 0x60,61,62: 64-bit
740#define CDSRCS 0x60 /* CD-ROM Sample Rate Converter status register */
741
742#define GPSRCS 0x61 /* General Purpose SPDIF sample rate cvt status */
743
744#define ZVSRCS 0x62 /* ZVideo sample rate converter status */
745 /* NOTE: This one has no SPDIFLOCKED field */
746 /* Assumes sample lock */
747
748/* These three bitfields apply to CDSRCS, GPSRCS, and (except as noted) ZVSRCS. */
749#define SRCS_SPDIFLOCKED 0x02000000 /* SPDIF stream locked */
750#define SRCS_RATELOCKED 0x01000000 /* Sample rate locked */
751#define SRCS_ESTSAMPLERATE 0x0007ffff /* Do not modify this field. */
752
753/* Note that these values can vary +/- by a small amount */
754#define SRCS_SPDIFRATE_44 0x0003acd9
755#define SRCS_SPDIFRATE_48 0x00040000
756#define SRCS_SPDIFRATE_96 0x00080000
757
758#define MICIDX 0x63 /* Microphone recording buffer index register */
759#define MICIDX_MASK 0x0000ffff /* 16-bit value */
760#define MICIDX_IDX 0x10000063
761
762#define ADCIDX 0x64 /* ADC recording buffer index register */
763#define ADCIDX_MASK 0x0000ffff /* 16 bit index field */
764#define ADCIDX_IDX 0x10000064
765
766#define A_ADCIDX 0x63
767#define A_ADCIDX_IDX 0x10000063
768
769#define A_MICIDX 0x64
770#define A_MICIDX_IDX 0x10000064
771
772#define FXIDX 0x65 /* FX recording buffer index register */
773#define FXIDX_MASK 0x0000ffff /* 16-bit value */
774#define FXIDX_IDX 0x10000065
775
776/* The 32-bit HLIx and HLIPx registers all have one bit per channel control/status */
777#define HLIEL 0x66 /* Channel half loop interrupt enable low register */
778
779#define HLIEH 0x67 /* Channel half loop interrupt enable high register */
780
781#define HLIPL 0x68 /* Channel half loop interrupt pending low register */
782
783#define HLIPH 0x69 /* Channel half loop interrupt pending high register */
784
785// 0x6a,6b,6c used for some recording
786// 0x6d unused
787// 0x6e,6f - tanktable base / offset
788
789/* This is the MPU port on the card (via the game port) */
790#define A_MUDATA1 0x70
791#define A_MUCMD1 0x71
792#define A_MUSTAT1 A_MUCMD1
793
794/* This is the MPU port on the Audigy Drive */
795#define A_MUDATA2 0x72
796#define A_MUCMD2 0x73
797#define A_MUSTAT2 A_MUCMD2
798
799/* The next two are the Audigy equivalent of FXWC */
800/* the Audigy can record any output (16bit, 48kHz, up to 64 channel simultaneously) */
801/* Each bit selects a channel for recording */
802#define A_FXWC1 0x74 /* Selects 0x7f-0x60 for FX recording */
803#define A_FXWC2 0x75 /* Selects 0x9f-0x80 for FX recording */
804
805#define A_SPDIF_SAMPLERATE 0x76 /* Set the sample rate of SPDIF output */
806#define A_SPDIF_RATE_MASK 0x000000c0
807#define A_SPDIF_48000 0x00000000
808#define A_SPDIF_44100 0x00000080
809#define A_SPDIF_96000 0x00000040
810
811/* 0x77,0x78,0x79 "something i2s-related" - default to 0x01080000 on my audigy 2 ZS --rlrevell */
812/* 0x7a, 0x7b - lookup tables */
813
814#define A_FXRT2 0x7c
815#define A_FXRT_CHANNELE 0x0000003f /* Effects send bus number for channel's effects send E */
816#define A_FXRT_CHANNELF 0x00003f00 /* Effects send bus number for channel's effects send F */
817#define A_FXRT_CHANNELG 0x003f0000 /* Effects send bus number for channel's effects send G */
818#define A_FXRT_CHANNELH 0x3f000000 /* Effects send bus number for channel's effects send H */
819
820#define A_SENDAMOUNTS 0x7d
821#define A_FXSENDAMOUNT_E_MASK 0xFF000000
822#define A_FXSENDAMOUNT_F_MASK 0x00FF0000
823#define A_FXSENDAMOUNT_G_MASK 0x0000FF00
824#define A_FXSENDAMOUNT_H_MASK 0x000000FF
825/* 0x7c, 0x7e "high bit is used for filtering" */
826
827/* The send amounts for this one are the same as used with the emu10k1 */
828#define A_FXRT1 0x7e
829#define A_FXRT_CHANNELA 0x0000003f
830#define A_FXRT_CHANNELB 0x00003f00
831#define A_FXRT_CHANNELC 0x003f0000
832#define A_FXRT_CHANNELD 0x3f000000
833
834
835/* Each FX general purpose register is 32 bits in length, all bits are used */
836#define FXGPREGBASE 0x100 /* FX general purpose registers base */
837#define A_FXGPREGBASE 0x400 /* Audigy GPRs, 0x400 to 0x5ff */
838
839#define A_TANKMEMCTLREGBASE 0x100 /* Tank memory control registers base - only for Audigy */
840#define A_TANKMEMCTLREG_MASK 0x1f /* only 5 bits used - only for Audigy */
841
842/* Tank audio data is logarithmically compressed down to 16 bits before writing to TRAM and is */
843/* decompressed back to 20 bits on a read. There are a total of 160 locations, the last 32 */
844/* locations are for external TRAM. */
845#define TANKMEMDATAREGBASE 0x200 /* Tank memory data registers base */
846#define TANKMEMDATAREG_MASK 0x000fffff /* 20 bit tank audio data field */
847
848/* Combined address field and memory opcode or flag field. 160 locations, last 32 are external */
849#define TANKMEMADDRREGBASE 0x300 /* Tank memory address registers base */
850#define TANKMEMADDRREG_ADDR_MASK 0x000fffff /* 20 bit tank address field */
851#define TANKMEMADDRREG_CLEAR 0x00800000 /* Clear tank memory */
852#define TANKMEMADDRREG_ALIGN 0x00400000 /* Align read or write relative to tank access */
853#define TANKMEMADDRREG_WRITE 0x00200000 /* Write to tank memory */
854#define TANKMEMADDRREG_READ 0x00100000 /* Read from tank memory */
855
856#define MICROCODEBASE 0x400 /* Microcode data base address */
857
858/* Each DSP microcode instruction is mapped into 2 doublewords */
859/* NOTE: When writing, always write the LO doubleword first. Reads can be in either order. */
860#define LOWORD_OPX_MASK 0x000ffc00 /* Instruction operand X */
861#define LOWORD_OPY_MASK 0x000003ff /* Instruction operand Y */
862#define HIWORD_OPCODE_MASK 0x00f00000 /* Instruction opcode */
863#define HIWORD_RESULT_MASK 0x000ffc00 /* Instruction result */
864#define HIWORD_OPA_MASK 0x000003ff /* Instruction operand A */
865
866
867/* Audigy Soundcard have a different instruction format */
868#define A_MICROCODEBASE 0x600
869#define A_LOWORD_OPY_MASK 0x000007ff
870#define A_LOWORD_OPX_MASK 0x007ff000
871#define A_HIWORD_OPCODE_MASK 0x0f000000
872#define A_HIWORD_RESULT_MASK 0x007ff000
873#define A_HIWORD_OPA_MASK 0x000007ff
874
875
876/* ------------------- STRUCTURES -------------------- */
877
878typedef struct _snd_emu10k1 emu10k1_t;
879typedef struct _snd_emu10k1_voice emu10k1_voice_t;
880typedef struct _snd_emu10k1_pcm emu10k1_pcm_t;
881
882typedef enum {
883 EMU10K1_EFX,
884 EMU10K1_PCM,
885 EMU10K1_SYNTH,
886 EMU10K1_MIDI
887} emu10k1_voice_type_t;
888
889struct _snd_emu10k1_voice {
890 emu10k1_t *emu;
891 int number;
892 unsigned int use: 1,
893 pcm: 1,
894 efx: 1,
895 synth: 1,
896 midi: 1;
897 void (*interrupt)(emu10k1_t *emu, emu10k1_voice_t *pvoice);
898
899 emu10k1_pcm_t *epcm;
900};
901
902typedef enum {
903 PLAYBACK_EMUVOICE,
904 PLAYBACK_EFX,
905 CAPTURE_AC97ADC,
906 CAPTURE_AC97MIC,
907 CAPTURE_EFX
908} snd_emu10k1_pcm_type_t;
909
910struct _snd_emu10k1_pcm {
911 emu10k1_t *emu;
912 snd_emu10k1_pcm_type_t type;
913 snd_pcm_substream_t *substream;
914 emu10k1_voice_t *voices[NUM_EFX_PLAYBACK];
915 emu10k1_voice_t *extra;
916 unsigned short running;
917 unsigned short first_ptr;
918 snd_util_memblk_t *memblk;
919 unsigned int start_addr;
920 unsigned int ccca_start_addr;
921 unsigned int capture_ipr; /* interrupt acknowledge mask */
922 unsigned int capture_inte; /* interrupt enable mask */
923 unsigned int capture_ba_reg; /* buffer address register */
924 unsigned int capture_bs_reg; /* buffer size register */
925 unsigned int capture_idx_reg; /* buffer index register */
926 unsigned int capture_cr_val; /* control value */
927 unsigned int capture_cr_val2; /* control value2 (for audigy) */
928 unsigned int capture_bs_val; /* buffer size value */
929 unsigned int capture_bufsize; /* buffer size in bytes */
930};
931
932typedef struct {
933 /* mono, left, right x 8 sends (4 on emu10k1) */
934 unsigned char send_routing[3][8];
935 unsigned char send_volume[3][8];
936 unsigned short attn[3];
937 emu10k1_pcm_t *epcm;
938} emu10k1_pcm_mixer_t;
939
940#define snd_emu10k1_compose_send_routing(route) \
941((route[0] | (route[1] << 4) | (route[2] << 8) | (route[3] << 12)) << 16)
942
943#define snd_emu10k1_compose_audigy_fxrt1(route) \
944((unsigned int)route[0] | ((unsigned int)route[1] << 8) | ((unsigned int)route[2] << 16) | ((unsigned int)route[3] << 24))
945
946#define snd_emu10k1_compose_audigy_fxrt2(route) \
947((unsigned int)route[4] | ((unsigned int)route[5] << 8) | ((unsigned int)route[6] << 16) | ((unsigned int)route[7] << 24))
948
949typedef struct snd_emu10k1_memblk {
950 snd_util_memblk_t mem;
951 /* private part */
952 int first_page, last_page, pages, mapped_page;
953 unsigned int map_locked;
954 struct list_head mapped_link;
955 struct list_head mapped_order_link;
956} emu10k1_memblk_t;
957
958#define snd_emu10k1_memblk_offset(blk) (((blk)->mapped_page << PAGE_SHIFT) | ((blk)->mem.offset & (PAGE_SIZE - 1)))
959
960#define EMU10K1_MAX_TRAM_BLOCKS_PER_CODE 16
961
962typedef struct {
963 struct list_head list; /* list link container */
964 unsigned int vcount;
965 unsigned int count; /* count of GPR (1..16) */
966 unsigned short gpr[32]; /* GPR number(s) */
967 unsigned int value[32];
968 unsigned int min; /* minimum range */
969 unsigned int max; /* maximum range */
970 unsigned int translation; /* translation type (EMU10K1_GPR_TRANSLATION*) */
971 snd_kcontrol_t *kcontrol;
972} snd_emu10k1_fx8010_ctl_t;
973
974typedef void (snd_fx8010_irq_handler_t)(emu10k1_t *emu, void *private_data);
975
976typedef struct _snd_emu10k1_fx8010_irq {
977 struct _snd_emu10k1_fx8010_irq *next;
978 snd_fx8010_irq_handler_t *handler;
979 unsigned short gpr_running;
980 void *private_data;
981} snd_emu10k1_fx8010_irq_t;
982
983typedef struct {
984 unsigned int valid: 1,
985 opened: 1,
986 active: 1;
987 unsigned int channels; /* 16-bit channels count */
988 unsigned int tram_start; /* initial ring buffer position in TRAM (in samples) */
989 unsigned int buffer_size; /* count of buffered samples */
990 unsigned short gpr_size; /* GPR containing size of ring buffer in samples (host) */
991 unsigned short gpr_ptr; /* GPR containing current pointer in the ring buffer (host = reset, FX8010) */
992 unsigned short gpr_count; /* GPR containing count of samples between two interrupts (host) */
993 unsigned short gpr_tmpcount; /* GPR containing current count of samples to interrupt (host = set, FX8010) */
994 unsigned short gpr_trigger; /* GPR containing trigger (activate) information (host) */
995 unsigned short gpr_running; /* GPR containing info if PCM is running (FX8010) */
996 unsigned char etram[32]; /* external TRAM address & data */
997 snd_pcm_indirect_t pcm_rec;
998 unsigned int tram_pos;
999 unsigned int tram_shift;
1000 snd_emu10k1_fx8010_irq_t *irq;
1001} snd_emu10k1_fx8010_pcm_t;
1002
1003typedef struct {
1004 unsigned short fxbus_mask; /* used FX buses (bitmask) */
1005 unsigned short extin_mask; /* used external inputs (bitmask) */
1006 unsigned short extout_mask; /* used external outputs (bitmask) */
1007 unsigned short pad1;
1008 unsigned int itram_size; /* internal TRAM size in samples */
1009 struct snd_dma_buffer etram_pages; /* external TRAM pages and size */
1010 unsigned int dbg; /* FX debugger register */
1011 unsigned char name[128];
1012 int gpr_size; /* size of allocated GPR controls */
1013 int gpr_count; /* count of used kcontrols */
1014 struct list_head gpr_ctl; /* GPR controls */
1015 struct semaphore lock;
1016 snd_emu10k1_fx8010_pcm_t pcm[8];
1017 spinlock_t irq_lock;
1018 snd_emu10k1_fx8010_irq_t *irq_handlers;
1019} snd_emu10k1_fx8010_t;
1020
1021#define emu10k1_gpr_ctl(n) list_entry(n, snd_emu10k1_fx8010_ctl_t, list)
1022
1023typedef struct {
1024 struct _snd_emu10k1 *emu;
1025 snd_rawmidi_t *rmidi;
1026 snd_rawmidi_substream_t *substream_input;
1027 snd_rawmidi_substream_t *substream_output;
1028 unsigned int midi_mode;
1029 spinlock_t input_lock;
1030 spinlock_t output_lock;
1031 spinlock_t open_lock;
1032 int tx_enable, rx_enable;
1033 int port;
1034 int ipr_tx, ipr_rx;
1035 void (*interrupt)(emu10k1_t *emu, unsigned int status);
1036} emu10k1_midi_t;
1037
1038typedef struct {
1039 u32 vendor;
1040 u32 device;
1041 u32 subsystem;
1042 unsigned char emu10k1_chip; /* Original SB Live. Not SB Live 24bit. */
1043 unsigned char emu10k2_chip; /* Audigy 1 or Audigy 2. */
1044 unsigned char ca0102_chip; /* Audigy 1 or Audigy 2. Not SB Audigy 2 Value. */
1045 unsigned char ca0108_chip; /* Audigy 2 Value */
1046 unsigned char ca0151_chip; /* P16V */
1047 unsigned char spk71; /* Has 7.1 speakers */
1048 unsigned char spdif_bug; /* Has Spdif phasing bug */
1049 unsigned char ac97_chip; /* Has an AC97 chip */
1050 unsigned char ecard; /* APS EEPROM */
1051 char * driver;
1052 char * name;
1053} emu_chip_details_t;
1054
1055struct _snd_emu10k1 {
1056 int irq;
1057
1058 unsigned long port; /* I/O port number */
1059 unsigned int APS: 1, /* APS flag */
1060 no_ac97: 1, /* no AC'97 */
1061 tos_link: 1, /* tos link detected */
1062 rear_ac97: 1, /* rear channels are on AC'97 */
1063 spk71:1; /* 7.1 configuration (Audigy 2 ZS) */
1064 const emu_chip_details_t *card_capabilities; /* Contains profile of card capabilities */
1065 unsigned int audigy; /* is Audigy? */
1066 unsigned int revision; /* chip revision */
1067 unsigned int serial; /* serial number */
1068 unsigned short model; /* subsystem id */
1069 unsigned int card_type; /* EMU10K1_CARD_* */
1070 unsigned int ecard_ctrl; /* ecard control bits */
1071 unsigned long dma_mask; /* PCI DMA mask */
1072 int max_cache_pages; /* max memory size / PAGE_SIZE */
1073 struct snd_dma_buffer silent_page; /* silent page */
1074 struct snd_dma_buffer ptb_pages; /* page table pages */
1075 struct snd_dma_device p16v_dma_dev;
1076 struct snd_dma_buffer p16v_buffer;
1077
1078 snd_util_memhdr_t *memhdr; /* page allocation list */
1079 emu10k1_memblk_t *reserved_page; /* reserved page */
1080
1081 struct list_head mapped_link_head;
1082 struct list_head mapped_order_link_head;
1083 void **page_ptr_table;
1084 unsigned long *page_addr_table;
1085 spinlock_t memblk_lock;
1086
1087 unsigned int spdif_bits[3]; /* s/pdif out setup */
1088
1089 snd_emu10k1_fx8010_t fx8010; /* FX8010 info */
1090 int gpr_base;
1091
1092 ac97_t *ac97;
1093
1094 struct pci_dev *pci;
1095 snd_card_t *card;
1096 snd_pcm_t *pcm;
1097 snd_pcm_t *pcm_mic;
1098 snd_pcm_t *pcm_efx;
1099 snd_pcm_t *pcm_p16v;
1100
1101 spinlock_t synth_lock;
1102 void *synth;
1103 int (*get_synth_voice)(emu10k1_t *emu);
1104
1105 spinlock_t reg_lock;
1106 spinlock_t emu_lock;
1107 spinlock_t voice_lock;
1108 struct semaphore ptb_lock;
1109
1110 emu10k1_voice_t voices[NUM_G];
1111 emu10k1_voice_t p16v_voices[4];
1112 int p16v_device_offset;
1113 emu10k1_pcm_mixer_t pcm_mixer[32];
1114 emu10k1_pcm_mixer_t efx_pcm_mixer[NUM_EFX_PLAYBACK];
1115 snd_kcontrol_t *ctl_send_routing;
1116 snd_kcontrol_t *ctl_send_volume;
1117 snd_kcontrol_t *ctl_attn;
1118 snd_kcontrol_t *ctl_efx_send_routing;
1119 snd_kcontrol_t *ctl_efx_send_volume;
1120 snd_kcontrol_t *ctl_efx_attn;
1121
1122 void (*hwvol_interrupt)(emu10k1_t *emu, unsigned int status);
1123 void (*capture_interrupt)(emu10k1_t *emu, unsigned int status);
1124 void (*capture_mic_interrupt)(emu10k1_t *emu, unsigned int status);
1125 void (*capture_efx_interrupt)(emu10k1_t *emu, unsigned int status);
1126 void (*spdif_interrupt)(emu10k1_t *emu, unsigned int status);
1127 void (*dsp_interrupt)(emu10k1_t *emu);
1128
1129 snd_pcm_substream_t *pcm_capture_substream;
1130 snd_pcm_substream_t *pcm_capture_mic_substream;
1131 snd_pcm_substream_t *pcm_capture_efx_substream;
1132 snd_pcm_substream_t *pcm_playback_efx_substream;
1133
1134 snd_timer_t *timer;
1135
1136 emu10k1_midi_t midi;
1137 emu10k1_midi_t midi2; /* for audigy */
1138
1139 unsigned int efx_voices_mask[2];
1140 unsigned int next_free_voice;
1141};
1142
1143int snd_emu10k1_create(snd_card_t * card,
1144 struct pci_dev *pci,
1145 unsigned short extin_mask,
1146 unsigned short extout_mask,
1147 long max_cache_bytes,
1148 int enable_ir,
1149 emu10k1_t ** remu);
1150
1151int snd_emu10k1_pcm(emu10k1_t * emu, int device, snd_pcm_t ** rpcm);
1152int snd_emu10k1_pcm_mic(emu10k1_t * emu, int device, snd_pcm_t ** rpcm);
1153int snd_emu10k1_pcm_efx(emu10k1_t * emu, int device, snd_pcm_t ** rpcm);
1154int snd_p16v_pcm(emu10k1_t * emu, int device, snd_pcm_t ** rpcm);
1155int snd_p16v_free(emu10k1_t * emu);
1156int snd_p16v_mixer(emu10k1_t * emu);
1157int snd_emu10k1_pcm_multi(emu10k1_t * emu, int device, snd_pcm_t ** rpcm);
1158int snd_emu10k1_fx8010_pcm(emu10k1_t * emu, int device, snd_pcm_t ** rpcm);
1159int snd_emu10k1_mixer(emu10k1_t * emu);
1160int snd_emu10k1_timer(emu10k1_t * emu, int device);
1161int snd_emu10k1_fx8010_new(emu10k1_t *emu, int device, snd_hwdep_t ** rhwdep);
1162
1163irqreturn_t snd_emu10k1_interrupt(int irq, void *dev_id, struct pt_regs *regs);
1164
1165/* initialization */
1166void snd_emu10k1_voice_init(emu10k1_t * emu, int voice);
1167int snd_emu10k1_init_efx(emu10k1_t *emu);
1168void snd_emu10k1_free_efx(emu10k1_t *emu);
1169int snd_emu10k1_fx8010_tram_setup(emu10k1_t *emu, u32 size);
1170
1171/* I/O functions */
1172unsigned int snd_emu10k1_ptr_read(emu10k1_t * emu, unsigned int reg, unsigned int chn);
1173void snd_emu10k1_ptr_write(emu10k1_t *emu, unsigned int reg, unsigned int chn, unsigned int data);
1174unsigned int snd_emu10k1_ptr20_read(emu10k1_t * emu, unsigned int reg, unsigned int chn);
1175void snd_emu10k1_ptr20_write(emu10k1_t *emu, unsigned int reg, unsigned int chn, unsigned int data);
1176unsigned int snd_emu10k1_efx_read(emu10k1_t *emu, unsigned int pc);
1177void snd_emu10k1_intr_enable(emu10k1_t *emu, unsigned int intrenb);
1178void snd_emu10k1_intr_disable(emu10k1_t *emu, unsigned int intrenb);
1179void snd_emu10k1_voice_intr_enable(emu10k1_t *emu, unsigned int voicenum);
1180void snd_emu10k1_voice_intr_disable(emu10k1_t *emu, unsigned int voicenum);
1181void snd_emu10k1_voice_intr_ack(emu10k1_t *emu, unsigned int voicenum);
1182void snd_emu10k1_voice_half_loop_intr_enable(emu10k1_t *emu, unsigned int voicenum);
1183void snd_emu10k1_voice_half_loop_intr_disable(emu10k1_t *emu, unsigned int voicenum);
1184void snd_emu10k1_voice_half_loop_intr_ack(emu10k1_t *emu, unsigned int voicenum);
1185void snd_emu10k1_voice_set_loop_stop(emu10k1_t *emu, unsigned int voicenum);
1186void snd_emu10k1_voice_clear_loop_stop(emu10k1_t *emu, unsigned int voicenum);
1187void snd_emu10k1_wait(emu10k1_t *emu, unsigned int wait);
1188static inline unsigned int snd_emu10k1_wc(emu10k1_t *emu) { return (inl(emu->port + WC) >> 6) & 0xfffff; }
1189unsigned short snd_emu10k1_ac97_read(ac97_t *ac97, unsigned short reg);
1190void snd_emu10k1_ac97_write(ac97_t *ac97, unsigned short reg, unsigned short data);
1191unsigned int snd_emu10k1_rate_to_pitch(unsigned int rate);
1192
1193/* memory allocation */
1194snd_util_memblk_t *snd_emu10k1_alloc_pages(emu10k1_t *emu, snd_pcm_substream_t *substream);
1195int snd_emu10k1_free_pages(emu10k1_t *emu, snd_util_memblk_t *blk);
1196snd_util_memblk_t *snd_emu10k1_synth_alloc(emu10k1_t *emu, unsigned int size);
1197int snd_emu10k1_synth_free(emu10k1_t *emu, snd_util_memblk_t *blk);
1198int snd_emu10k1_synth_bzero(emu10k1_t *emu, snd_util_memblk_t *blk, int offset, int size);
1199int snd_emu10k1_synth_copy_from_user(emu10k1_t *emu, snd_util_memblk_t *blk, int offset, const char __user *data, int size);
1200int snd_emu10k1_memblk_map(emu10k1_t *emu, emu10k1_memblk_t *blk);
1201
1202/* voice allocation */
1203int snd_emu10k1_voice_alloc(emu10k1_t *emu, emu10k1_voice_type_t type, int pair, emu10k1_voice_t **rvoice);
1204int snd_emu10k1_voice_free(emu10k1_t *emu, emu10k1_voice_t *pvoice);
1205
1206/* MIDI uart */
1207int snd_emu10k1_midi(emu10k1_t * emu);
1208int snd_emu10k1_audigy_midi(emu10k1_t * emu);
1209
1210/* proc interface */
1211int snd_emu10k1_proc_init(emu10k1_t * emu);
1212
1213/* fx8010 irq handler */
1214int snd_emu10k1_fx8010_register_irq_handler(emu10k1_t *emu,
1215 snd_fx8010_irq_handler_t *handler,
1216 unsigned char gpr_running,
1217 void *private_data,
1218 snd_emu10k1_fx8010_irq_t **r_irq);
1219int snd_emu10k1_fx8010_unregister_irq_handler(emu10k1_t *emu,
1220 snd_emu10k1_fx8010_irq_t *irq);
1221
1222#endif /* __KERNEL__ */
1223
1224/*
1225 * ---- FX8010 ----
1226 */
1227
1228#define EMU10K1_CARD_CREATIVE 0x00000000
1229#define EMU10K1_CARD_EMUAPS 0x00000001
1230
1231#define EMU10K1_FX8010_PCM_COUNT 8
1232
1233/* instruction set */
1234#define iMAC0 0x00 /* R = A + (X * Y >> 31) ; saturation */
1235#define iMAC1 0x01 /* R = A + (-X * Y >> 31) ; saturation */
1236#define iMAC2 0x02 /* R = A + (X * Y >> 31) ; wraparound */
1237#define iMAC3 0x03 /* R = A + (-X * Y >> 31) ; wraparound */
1238#define iMACINT0 0x04 /* R = A + X * Y ; saturation */
1239#define iMACINT1 0x05 /* R = A + X * Y ; wraparound (31-bit) */
1240#define iACC3 0x06 /* R = A + X + Y ; saturation */
1241#define iMACMV 0x07 /* R = A, acc += X * Y >> 31 */
1242#define iANDXOR 0x08 /* R = (A & X) ^ Y */
1243#define iTSTNEG 0x09 /* R = (A >= Y) ? X : ~X */
1244#define iLIMITGE 0x0a /* R = (A >= Y) ? X : Y */
1245#define iLIMITLT 0x0b /* R = (A < Y) ? X : Y */
1246#define iLOG 0x0c /* R = linear_data, A (log_data), X (max_exp), Y (format_word) */
1247#define iEXP 0x0d /* R = log_data, A (linear_data), X (max_exp), Y (format_word) */
1248#define iINTERP 0x0e /* R = A + (X * (Y - A) >> 31) ; saturation */
1249#define iSKIP 0x0f /* R = A (cc_reg), X (count), Y (cc_test) */
1250
1251/* GPRs */
1252#define FXBUS(x) (0x00 + (x)) /* x = 0x00 - 0x0f */
1253#define EXTIN(x) (0x10 + (x)) /* x = 0x00 - 0x0f */
1254#define EXTOUT(x) (0x20 + (x)) /* x = 0x00 - 0x0f physical outs -> FXWC low 16 bits */
1255#define FXBUS2(x) (0x30 + (x)) /* x = 0x00 - 0x0f copies of fx buses for capture -> FXWC high 16 bits */
1256 /* NB: 0x31 and 0x32 are shared with Center/LFE on SB live 5.1 */
1257
1258#define C_00000000 0x40
1259#define C_00000001 0x41
1260#define C_00000002 0x42
1261#define C_00000003 0x43
1262#define C_00000004 0x44
1263#define C_00000008 0x45
1264#define C_00000010 0x46
1265#define C_00000020 0x47
1266#define C_00000100 0x48
1267#define C_00010000 0x49
1268#define C_00080000 0x4a
1269#define C_10000000 0x4b
1270#define C_20000000 0x4c
1271#define C_40000000 0x4d
1272#define C_80000000 0x4e
1273#define C_7fffffff 0x4f
1274#define C_ffffffff 0x50
1275#define C_fffffffe 0x51
1276#define C_c0000000 0x52
1277#define C_4f1bbcdc 0x53
1278#define C_5a7ef9db 0x54
1279#define C_00100000 0x55 /* ?? */
1280#define GPR_ACCU 0x56 /* ACCUM, accumulator */
1281#define GPR_COND 0x57 /* CCR, condition register */
1282#define GPR_NOISE0 0x58 /* noise source */
1283#define GPR_NOISE1 0x59 /* noise source */
1284#define GPR_IRQ 0x5a /* IRQ register */
1285#define GPR_DBAC 0x5b /* TRAM Delay Base Address Counter */
1286#define GPR(x) (FXGPREGBASE + (x)) /* free GPRs: x = 0x00 - 0xff */
1287#define ITRAM_DATA(x) (TANKMEMDATAREGBASE + 0x00 + (x)) /* x = 0x00 - 0x7f */
1288#define ETRAM_DATA(x) (TANKMEMDATAREGBASE + 0x80 + (x)) /* x = 0x00 - 0x1f */
1289#define ITRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x00 + (x)) /* x = 0x00 - 0x7f */
1290#define ETRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x80 + (x)) /* x = 0x00 - 0x1f */
1291
1292#define A_ITRAM_DATA(x) (TANKMEMDATAREGBASE + 0x00 + (x)) /* x = 0x00 - 0xbf */
1293#define A_ETRAM_DATA(x) (TANKMEMDATAREGBASE + 0xc0 + (x)) /* x = 0x00 - 0x3f */
1294#define A_ITRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x00 + (x)) /* x = 0x00 - 0xbf */
1295#define A_ETRAM_ADDR(x) (TANKMEMADDRREGBASE + 0xc0 + (x)) /* x = 0x00 - 0x3f */
1296#define A_ITRAM_CTL(x) (A_TANKMEMCTLREGBASE + 0x00 + (x)) /* x = 0x00 - 0xbf */
1297#define A_ETRAM_CTL(x) (A_TANKMEMCTLREGBASE + 0xc0 + (x)) /* x = 0x00 - 0x3f */
1298
1299#define A_FXBUS(x) (0x00 + (x)) /* x = 0x00 - 0x3f FX buses */
1300#define A_EXTIN(x) (0x40 + (x)) /* x = 0x00 - 0x0f physical ins */
1301#define A_P16VIN(x) (0x50 + (x)) /* x = 0x00 - 0x0f p16v ins (A2 only) "EMU32 inputs" */
1302#define A_EXTOUT(x) (0x60 + (x)) /* x = 0x00 - 0x1f physical outs -> A_FXWC1 0x79-7f unknown */
1303#define A_FXBUS2(x) (0x80 + (x)) /* x = 0x00 - 0x1f extra outs used for EFX capture -> A_FXWC2 */
1304#define A_EMU32OUTH(x) (0xa0 + (x)) /* x = 0x00 - 0x0f "EMU32_OUT_10 - _1F" - ??? */
1305#define A_EMU32OUTL(x) (0xb0 + (x)) /* x = 0x00 - 0x0f "EMU32_OUT_1 - _F" - ??? */
1306#define A_GPR(x) (A_FXGPREGBASE + (x))
1307
1308/* cc_reg constants */
1309#define CC_REG_NORMALIZED C_00000001
1310#define CC_REG_BORROW C_00000002
1311#define CC_REG_MINUS C_00000004
1312#define CC_REG_ZERO C_00000008
1313#define CC_REG_SATURATE C_00000010
1314#define CC_REG_NONZERO C_00000100
1315
1316/* FX buses */
1317#define FXBUS_PCM_LEFT 0x00
1318#define FXBUS_PCM_RIGHT 0x01
1319#define FXBUS_PCM_LEFT_REAR 0x02
1320#define FXBUS_PCM_RIGHT_REAR 0x03
1321#define FXBUS_MIDI_LEFT 0x04
1322#define FXBUS_MIDI_RIGHT 0x05
1323#define FXBUS_PCM_CENTER 0x06
1324#define FXBUS_PCM_LFE 0x07
1325#define FXBUS_PCM_LEFT_FRONT 0x08
1326#define FXBUS_PCM_RIGHT_FRONT 0x09
1327#define FXBUS_MIDI_REVERB 0x0c
1328#define FXBUS_MIDI_CHORUS 0x0d
1329#define FXBUS_PCM_LEFT_SIDE 0x0e
1330#define FXBUS_PCM_RIGHT_SIDE 0x0f
1331#define FXBUS_PT_LEFT 0x14
1332#define FXBUS_PT_RIGHT 0x15
1333
1334/* Inputs */
1335#define EXTIN_AC97_L 0x00 /* AC'97 capture channel - left */
1336#define EXTIN_AC97_R 0x01 /* AC'97 capture channel - right */
1337#define EXTIN_SPDIF_CD_L 0x02 /* internal S/PDIF CD - onboard - left */
1338#define EXTIN_SPDIF_CD_R 0x03 /* internal S/PDIF CD - onboard - right */
1339#define EXTIN_ZOOM_L 0x04 /* Zoom Video I2S - left */
1340#define EXTIN_ZOOM_R 0x05 /* Zoom Video I2S - right */
1341#define EXTIN_TOSLINK_L 0x06 /* LiveDrive - TOSLink Optical - left */
1342#define EXTIN_TOSLINK_R 0x07 /* LiveDrive - TOSLink Optical - right */
1343#define EXTIN_LINE1_L 0x08 /* LiveDrive - Line/Mic 1 - left */
1344#define EXTIN_LINE1_R 0x09 /* LiveDrive - Line/Mic 1 - right */
1345#define EXTIN_COAX_SPDIF_L 0x0a /* LiveDrive - Coaxial S/PDIF - left */
1346#define EXTIN_COAX_SPDIF_R 0x0b /* LiveDrive - Coaxial S/PDIF - right */
1347#define EXTIN_LINE2_L 0x0c /* LiveDrive - Line/Mic 2 - left */
1348#define EXTIN_LINE2_R 0x0d /* LiveDrive - Line/Mic 2 - right */
1349
1350/* Outputs */
1351#define EXTOUT_AC97_L 0x00 /* AC'97 playback channel - left */
1352#define EXTOUT_AC97_R 0x01 /* AC'97 playback channel - right */
1353#define EXTOUT_TOSLINK_L 0x02 /* LiveDrive - TOSLink Optical - left */
1354#define EXTOUT_TOSLINK_R 0x03 /* LiveDrive - TOSLink Optical - right */
1355#define EXTOUT_AC97_CENTER 0x04 /* SB Live 5.1 - center */
1356#define EXTOUT_AC97_LFE 0x05 /* SB Live 5.1 - LFE */
1357#define EXTOUT_HEADPHONE_L 0x06 /* LiveDrive - Headphone - left */
1358#define EXTOUT_HEADPHONE_R 0x07 /* LiveDrive - Headphone - right */
1359#define EXTOUT_REAR_L 0x08 /* Rear channel - left */
1360#define EXTOUT_REAR_R 0x09 /* Rear channel - right */
1361#define EXTOUT_ADC_CAP_L 0x0a /* ADC Capture buffer - left */
1362#define EXTOUT_ADC_CAP_R 0x0b /* ADC Capture buffer - right */
1363#define EXTOUT_MIC_CAP 0x0c /* MIC Capture buffer */
1364#define EXTOUT_AC97_REAR_L 0x0d /* SB Live 5.1 (c) 2003 - Rear Left */
1365#define EXTOUT_AC97_REAR_R 0x0e /* SB Live 5.1 (c) 2003 - Rear Right */
1366#define EXTOUT_ACENTER 0x11 /* Analog Center */
1367#define EXTOUT_ALFE 0x12 /* Analog LFE */
1368
1369/* Audigy Inputs */
1370#define A_EXTIN_AC97_L 0x00 /* AC'97 capture channel - left */
1371#define A_EXTIN_AC97_R 0x01 /* AC'97 capture channel - right */
1372#define A_EXTIN_SPDIF_CD_L 0x02 /* digital CD left */
1373#define A_EXTIN_SPDIF_CD_R 0x03 /* digital CD left */
1374#define A_EXTIN_OPT_SPDIF_L 0x04 /* audigy drive Optical SPDIF - left */
1375#define A_EXTIN_OPT_SPDIF_R 0x05 /* right */
1376#define A_EXTIN_LINE2_L 0x08 /* audigy drive line2/mic2 - left */
1377#define A_EXTIN_LINE2_R 0x09 /* right */
1378#define A_EXTIN_ADC_L 0x0a /* Philips ADC - left */
1379#define A_EXTIN_ADC_R 0x0b /* right */
1380#define A_EXTIN_AUX2_L 0x0c /* audigy drive aux2 - left */
1381#define A_EXTIN_AUX2_R 0x0d /* - right */
1382
1383/* Audigiy Outputs */
1384#define A_EXTOUT_FRONT_L 0x00 /* digital front left */
1385#define A_EXTOUT_FRONT_R 0x01 /* right */
1386#define A_EXTOUT_CENTER 0x02 /* digital front center */
1387#define A_EXTOUT_LFE 0x03 /* digital front lfe */
1388#define A_EXTOUT_HEADPHONE_L 0x04 /* headphone audigy drive left */
1389#define A_EXTOUT_HEADPHONE_R 0x05 /* right */
1390#define A_EXTOUT_REAR_L 0x06 /* digital rear left */
1391#define A_EXTOUT_REAR_R 0x07 /* right */
1392#define A_EXTOUT_AFRONT_L 0x08 /* analog front left */
1393#define A_EXTOUT_AFRONT_R 0x09 /* right */
1394#define A_EXTOUT_ACENTER 0x0a /* analog center */
1395#define A_EXTOUT_ALFE 0x0b /* analog LFE */
1396#define A_EXTOUT_ASIDE_L 0x0c /* analog side left - Audigy 2 ZS */
1397#define A_EXTOUT_ASIDE_R 0x0d /* right - Audigy 2 ZS */
1398#define A_EXTOUT_AREAR_L 0x0e /* analog rear left */
1399#define A_EXTOUT_AREAR_R 0x0f /* right */
1400#define A_EXTOUT_AC97_L 0x10 /* AC97 left (front) */
1401#define A_EXTOUT_AC97_R 0x11 /* right */
1402#define A_EXTOUT_ADC_CAP_L 0x16 /* ADC capture buffer left */
1403#define A_EXTOUT_ADC_CAP_R 0x17 /* right */
1404#define A_EXTOUT_MIC_CAP 0x18 /* Mic capture buffer */
1405
1406/* Audigy constants */
1407#define A_C_00000000 0xc0
1408#define A_C_00000001 0xc1
1409#define A_C_00000002 0xc2
1410#define A_C_00000003 0xc3
1411#define A_C_00000004 0xc4
1412#define A_C_00000008 0xc5
1413#define A_C_00000010 0xc6
1414#define A_C_00000020 0xc7
1415#define A_C_00000100 0xc8
1416#define A_C_00010000 0xc9
1417#define A_C_00000800 0xca
1418#define A_C_10000000 0xcb
1419#define A_C_20000000 0xcc
1420#define A_C_40000000 0xcd
1421#define A_C_80000000 0xce
1422#define A_C_7fffffff 0xcf
1423#define A_C_ffffffff 0xd0
1424#define A_C_fffffffe 0xd1
1425#define A_C_c0000000 0xd2
1426#define A_C_4f1bbcdc 0xd3
1427#define A_C_5a7ef9db 0xd4
1428#define A_C_00100000 0xd5
1429#define A_GPR_ACCU 0xd6 /* ACCUM, accumulator */
1430#define A_GPR_COND 0xd7 /* CCR, condition register */
1431#define A_GPR_NOISE0 0xd8 /* noise source */
1432#define A_GPR_NOISE1 0xd9 /* noise source */
1433#define A_GPR_IRQ 0xda /* IRQ register */
1434#define A_GPR_DBAC 0xdb /* TRAM Delay Base Address Counter - internal */
1435#define A_GPR_DBACE 0xde /* TRAM Delay Base Address Counter - external */
1436
1437/* definitions for debug register */
1438#define EMU10K1_DBG_ZC 0x80000000 /* zero tram counter */
1439#define EMU10K1_DBG_SATURATION_OCCURED 0x02000000 /* saturation control */
1440#define EMU10K1_DBG_SATURATION_ADDR 0x01ff0000 /* saturation address */
1441#define EMU10K1_DBG_SINGLE_STEP 0x00008000 /* single step mode */
1442#define EMU10K1_DBG_STEP 0x00004000 /* start single step */
1443#define EMU10K1_DBG_CONDITION_CODE 0x00003e00 /* condition code */
1444#define EMU10K1_DBG_SINGLE_STEP_ADDR 0x000001ff /* single step address */
1445
1446/* tank memory address line */
1447#ifndef __KERNEL__
1448#define TANKMEMADDRREG_ADDR_MASK 0x000fffff /* 20 bit tank address field */
1449#define TANKMEMADDRREG_CLEAR 0x00800000 /* Clear tank memory */
1450#define TANKMEMADDRREG_ALIGN 0x00400000 /* Align read or write relative to tank access */
1451#define TANKMEMADDRREG_WRITE 0x00200000 /* Write to tank memory */
1452#define TANKMEMADDRREG_READ 0x00100000 /* Read from tank memory */
1453#endif
1454
1455typedef struct {
1456 unsigned int card; /* card type */
1457 unsigned int internal_tram_size; /* in samples */
1458 unsigned int external_tram_size; /* in samples */
1459 char fxbus_names[16][32]; /* names of FXBUSes */
1460 char extin_names[16][32]; /* names of external inputs */
1461 char extout_names[32][32]; /* names of external outputs */
1462 unsigned int gpr_controls; /* count of GPR controls */
1463} emu10k1_fx8010_info_t;
1464
1465#define EMU10K1_GPR_TRANSLATION_NONE 0
1466#define EMU10K1_GPR_TRANSLATION_TABLE100 1
1467#define EMU10K1_GPR_TRANSLATION_BASS 2
1468#define EMU10K1_GPR_TRANSLATION_TREBLE 3
1469#define EMU10K1_GPR_TRANSLATION_ONOFF 4
1470
1471typedef struct {
1472 snd_ctl_elem_id_t id; /* full control ID definition */
1473 unsigned int vcount; /* visible count */
1474 unsigned int count; /* count of GPR (1..16) */
1475 unsigned short gpr[32]; /* GPR number(s) */
1476 unsigned int value[32]; /* initial values */
1477 unsigned int min; /* minimum range */
1478 unsigned int max; /* maximum range */
1479 unsigned int translation; /* translation type (EMU10K1_GPR_TRANSLATION*) */
1480} emu10k1_fx8010_control_gpr_t;
1481
1482typedef struct {
1483 char name[128];
1484
1485 DECLARE_BITMAP(gpr_valid, 0x200); /* bitmask of valid initializers */
1486 u_int32_t __user *gpr_map; /* initializers */
1487
1488 unsigned int gpr_add_control_count; /* count of GPR controls to add/replace */
1489 emu10k1_fx8010_control_gpr_t __user *gpr_add_controls; /* GPR controls to add/replace */
1490
1491 unsigned int gpr_del_control_count; /* count of GPR controls to remove */
1492 snd_ctl_elem_id_t __user *gpr_del_controls; /* IDs of GPR controls to remove */
1493
1494 unsigned int gpr_list_control_count; /* count of GPR controls to list */
1495 unsigned int gpr_list_control_total; /* total count of GPR controls */
1496 emu10k1_fx8010_control_gpr_t __user *gpr_list_controls; /* listed GPR controls */
1497
1498 DECLARE_BITMAP(tram_valid, 0x100); /* bitmask of valid initializers */
1499 u_int32_t __user *tram_data_map; /* data initializers */
1500 u_int32_t __user *tram_addr_map; /* map initializers */
1501
1502 DECLARE_BITMAP(code_valid, 1024); /* bitmask of valid instructions */
1503 u_int32_t __user *code; /* one instruction - 64 bits */
1504} emu10k1_fx8010_code_t;
1505
1506typedef struct {
1507 unsigned int address; /* 31.bit == 1 -> external TRAM */
1508 unsigned int size; /* size in samples (4 bytes) */
1509 unsigned int *samples; /* pointer to samples (20-bit) */
1510 /* NULL->clear memory */
1511} emu10k1_fx8010_tram_t;
1512
1513typedef struct {
1514 unsigned int substream; /* substream number */
1515 unsigned int res1; /* reserved */
1516 unsigned int channels; /* 16-bit channels count, zero = remove this substream */
1517 unsigned int tram_start; /* ring buffer position in TRAM (in samples) */
1518 unsigned int buffer_size; /* count of buffered samples */
1519 unsigned short gpr_size; /* GPR containing size of ringbuffer in samples (host) */
1520 unsigned short gpr_ptr; /* GPR containing current pointer in the ring buffer (host = reset, FX8010) */
1521 unsigned short gpr_count; /* GPR containing count of samples between two interrupts (host) */
1522 unsigned short gpr_tmpcount; /* GPR containing current count of samples to interrupt (host = set, FX8010) */
1523 unsigned short gpr_trigger; /* GPR containing trigger (activate) information (host) */
1524 unsigned short gpr_running; /* GPR containing info if PCM is running (FX8010) */
1525 unsigned char pad; /* reserved */
1526 unsigned char etram[32]; /* external TRAM address & data (one per channel) */
1527 unsigned int res2; /* reserved */
1528} emu10k1_fx8010_pcm_t;
1529
1530#define SNDRV_EMU10K1_IOCTL_INFO _IOR ('H', 0x10, emu10k1_fx8010_info_t)
1531#define SNDRV_EMU10K1_IOCTL_CODE_POKE _IOW ('H', 0x11, emu10k1_fx8010_code_t)
1532#define SNDRV_EMU10K1_IOCTL_CODE_PEEK _IOWR('H', 0x12, emu10k1_fx8010_code_t)
1533#define SNDRV_EMU10K1_IOCTL_TRAM_SETUP _IOW ('H', 0x20, int)
1534#define SNDRV_EMU10K1_IOCTL_TRAM_POKE _IOW ('H', 0x21, emu10k1_fx8010_tram_t)
1535#define SNDRV_EMU10K1_IOCTL_TRAM_PEEK _IOWR('H', 0x22, emu10k1_fx8010_tram_t)
1536#define SNDRV_EMU10K1_IOCTL_PCM_POKE _IOW ('H', 0x30, emu10k1_fx8010_pcm_t)
1537#define SNDRV_EMU10K1_IOCTL_PCM_PEEK _IOWR('H', 0x31, emu10k1_fx8010_pcm_t)
1538#define SNDRV_EMU10K1_IOCTL_STOP _IO ('H', 0x80)
1539#define SNDRV_EMU10K1_IOCTL_CONTINUE _IO ('H', 0x81)
1540#define SNDRV_EMU10K1_IOCTL_ZERO_TRAM_COUNTER _IO ('H', 0x82)
1541#define SNDRV_EMU10K1_IOCTL_SINGLE_STEP _IOW ('H', 0x83, int)
1542#define SNDRV_EMU10K1_IOCTL_DBG_READ _IOR ('H', 0x84, int)
1543
1544#endif /* __SOUND_EMU10K1_H */