blob: 2e2bc406a18d69f93de13600732bb3d6fa329135 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * linux/arch/arm/mm/cache-v3.S
3 *
4 * Copyright (C) 1997-2002 Russell king
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#include <linux/linkage.h>
11#include <linux/init.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070012#include <asm/page.h>
13#include "proc-macros.S"
14
15/*
Mika Westerbergc8c90862010-10-28 11:27:40 +010016 * flush_icache_all()
17 *
18 * Unconditionally clean and invalidate the entire icache.
19 */
20ENTRY(v3_flush_icache_all)
21 mov pc, lr
22ENDPROC(v3_flush_icache_all)
23
24/*
Linus Torvalds1da177e2005-04-16 15:20:36 -070025 * flush_user_cache_all()
26 *
27 * Invalidate all cache entries in a particular address
28 * space.
29 *
30 * - mm - mm_struct describing address space
31 */
32ENTRY(v3_flush_user_cache_all)
33 /* FALLTHROUGH */
34/*
35 * flush_kern_cache_all()
36 *
37 * Clean and invalidate the entire cache.
38 */
39ENTRY(v3_flush_kern_cache_all)
40 /* FALLTHROUGH */
41
42/*
43 * flush_user_cache_range(start, end, flags)
44 *
45 * Invalidate a range of cache entries in the specified
46 * address space.
47 *
48 * - start - start address (may not be aligned)
49 * - end - end address (exclusive, may not be aligned)
50 * - flags - vma_area_struct flags describing address space
51 */
52ENTRY(v3_flush_user_cache_range)
53 mov ip, #0
54 mcreq p15, 0, ip, c7, c0, 0 @ flush ID cache
55 mov pc, lr
56
57/*
58 * coherent_kern_range(start, end)
59 *
60 * Ensure coherency between the Icache and the Dcache in the
61 * region described by start. If you have non-snooping
62 * Harvard caches, you need to implement this function.
63 *
64 * - start - virtual start address
65 * - end - virtual end address
66 */
67ENTRY(v3_coherent_kern_range)
68 /* FALLTHROUGH */
69
70/*
71 * coherent_user_range(start, end)
72 *
73 * Ensure coherency between the Icache and the Dcache in the
74 * region described by start. If you have non-snooping
75 * Harvard caches, you need to implement this function.
76 *
77 * - start - virtual start address
78 * - end - virtual end address
79 */
80ENTRY(v3_coherent_user_range)
81 mov pc, lr
82
83/*
Russell King2c9b9c82009-11-26 12:56:21 +000084 * flush_kern_dcache_area(void *page, size_t size)
Linus Torvalds1da177e2005-04-16 15:20:36 -070085 *
86 * Ensure no D cache aliasing occurs, either with itself or
87 * the I cache
88 *
Russell King2c9b9c82009-11-26 12:56:21 +000089 * - addr - kernel address
90 * - size - region size
Linus Torvalds1da177e2005-04-16 15:20:36 -070091 */
Russell King2c9b9c82009-11-26 12:56:21 +000092ENTRY(v3_flush_kern_dcache_area)
Linus Torvalds1da177e2005-04-16 15:20:36 -070093 /* FALLTHROUGH */
94
95/*
Linus Torvalds1da177e2005-04-16 15:20:36 -070096 * dma_flush_range(start, end)
97 *
98 * Clean and invalidate the specified virtual address range.
99 *
100 * - start - virtual start address
101 * - end - virtual end address
102 */
103ENTRY(v3_dma_flush_range)
104 mov r0, #0
105 mcr p15, 0, r0, c7, c0, 0 @ flush ID cache
Linus Torvalds1da177e2005-04-16 15:20:36 -0700106 mov pc, lr
107
Russell Kinga9c91472009-11-26 16:19:58 +0000108/*
109 * dma_unmap_area(start, size, dir)
110 * - start - kernel virtual start address
111 * - size - size of region
112 * - dir - DMA direction
113 */
114ENTRY(v3_dma_unmap_area)
115 teq r2, #DMA_TO_DEVICE
Russell King702b94b2009-11-26 16:24:19 +0000116 bne v3_dma_flush_range
Russell Kinga9c91472009-11-26 16:19:58 +0000117 /* FALLTHROUGH */
118
119/*
120 * dma_map_area(start, size, dir)
121 * - start - kernel virtual start address
122 * - size - size of region
123 * - dir - DMA direction
124 */
125ENTRY(v3_dma_map_area)
126 mov pc, lr
127ENDPROC(v3_dma_unmap_area)
128ENDPROC(v3_dma_map_area)
129
Linus Torvalds1da177e2005-04-16 15:20:36 -0700130 __INITDATA
131
132 .type v3_cache_fns, #object
133ENTRY(v3_cache_fns)
Mika Westerbergc8c90862010-10-28 11:27:40 +0100134 .long v3_flush_icache_all
Linus Torvalds1da177e2005-04-16 15:20:36 -0700135 .long v3_flush_kern_cache_all
136 .long v3_flush_user_cache_all
137 .long v3_flush_user_cache_range
138 .long v3_coherent_kern_range
139 .long v3_coherent_user_range
Russell King2c9b9c82009-11-26 12:56:21 +0000140 .long v3_flush_kern_dcache_area
Russell Kinga9c91472009-11-26 16:19:58 +0000141 .long v3_dma_map_area
142 .long v3_dma_unmap_area
Linus Torvalds1da177e2005-04-16 15:20:36 -0700143 .long v3_dma_flush_range
144 .size v3_cache_fns, . - v3_cache_fns