blob: 54baa0b8ec7c937a17b8f2ae984e2799831cb9c6 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/************************************************************************
ravinandan.arakali@neterion.com776bd202005-09-06 21:36:56 -07002 * s2io.h: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
Ramkrishna Vepa0c61ed52007-03-09 18:28:32 -08003 * Copyright(c) 2002-2007 Neterion Inc.
Linus Torvalds1da177e2005-04-16 15:20:36 -07004
5 * This software may be used and distributed according to the terms of
6 * the GNU General Public License (GPL), incorporated herein by reference.
7 * Drivers based on or derived from this code fall under the GPL and must
8 * retain the authorship, copyright and license notice. This file is not
9 * a complete program and may only be used when the entire operating
10 * system is licensed under the GPL.
11 * See the file COPYING in this distribution for more information.
12 ************************************************************************/
13#ifndef _S2IO_H
14#define _S2IO_H
15
16#define TBD 0
17#define BIT(loc) (0x8000000000000000ULL >> (loc))
18#define vBIT(val, loc, sz) (((u64)val) << (64-loc-sz))
19#define INV(d) ((d&0xff)<<24) | (((d>>8)&0xff)<<16) | (((d>>16)&0xff)<<8)| ((d>>24)&0xff)
20
21#ifndef BOOL
22#define BOOL int
23#endif
24
25#ifndef TRUE
26#define TRUE 1
27#define FALSE 0
28#endif
29
30#undef SUCCESS
31#define SUCCESS 0
32#define FAILURE -1
Sivakumar Subramani19a60522007-01-31 13:30:49 -050033#define S2IO_MINUS_ONE 0xFFFFFFFFFFFFFFFFULL
34#define S2IO_MAX_PCI_CONFIG_SPACE_REINIT 100
Sivakumar Subramani9fc93a42007-02-24 01:57:32 -050035#define S2IO_BIT_RESET 1
36#define S2IO_BIT_SET 2
Ananda Rajubd1034f2006-04-21 19:20:22 -040037#define CHECKBIT(value, nbit) (value & (1 << nbit))
38
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -070039/* Maximum time to flicker LED when asked to identify NIC using ethtool */
40#define MAX_FLICKER_TIME 60000 /* 60 Secs */
41
Linus Torvalds1da177e2005-04-16 15:20:36 -070042/* Maximum outstanding splits to be configured into xena. */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -050043enum {
Linus Torvalds1da177e2005-04-16 15:20:36 -070044 XENA_ONE_SPLIT_TRANSACTION = 0,
45 XENA_TWO_SPLIT_TRANSACTION = 1,
46 XENA_THREE_SPLIT_TRANSACTION = 2,
47 XENA_FOUR_SPLIT_TRANSACTION = 3,
48 XENA_EIGHT_SPLIT_TRANSACTION = 4,
49 XENA_TWELVE_SPLIT_TRANSACTION = 5,
50 XENA_SIXTEEN_SPLIT_TRANSACTION = 6,
51 XENA_THIRTYTWO_SPLIT_TRANSACTION = 7
Ralf Baechle1ee6dd72007-01-31 14:09:29 -050052};
Linus Torvalds1da177e2005-04-16 15:20:36 -070053#define XENA_MAX_OUTSTANDING_SPLITS(n) (n << 4)
54
55/* OS concerned variables and constants */
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -070056#define WATCH_DOG_TIMEOUT 15*HZ
57#define EFILL 0x1234
58#define ALIGN_SIZE 127
59#define PCIX_COMMAND_REGISTER 0x62
Linus Torvalds1da177e2005-04-16 15:20:36 -070060
61/*
62 * Debug related variables.
63 */
64/* different debug levels. */
65#define ERR_DBG 0
66#define INIT_DBG 1
67#define INFO_DBG 2
68#define TX_DBG 3
69#define INTR_DBG 4
70
71/* Global variable that defines the present debug level of the driver. */
Adrian Bunk26df54b2006-01-14 03:09:40 +010072static int debug_level = ERR_DBG;
Linus Torvalds1da177e2005-04-16 15:20:36 -070073
74/* DEBUG message print. */
75#define DBG_PRINT(dbg_level, args...) if(!(debug_level<dbg_level)) printk(args)
76
77/* Protocol assist features of the NIC */
78#define L3_CKSUM_OK 0xFFFF
79#define L4_CKSUM_OK 0xFFFF
80#define S2IO_JUMBO_SIZE 9600
81
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -070082/* Driver statistics maintained by driver */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -050083struct swStat {
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -070084 unsigned long long single_ecc_errs;
85 unsigned long long double_ecc_errs;
Ananda Rajubd1034f2006-04-21 19:20:22 -040086 unsigned long long parity_err_cnt;
87 unsigned long long serious_err_cnt;
88 unsigned long long soft_reset_cnt;
89 unsigned long long fifo_full_cnt;
90 unsigned long long ring_full_cnt;
Ravinandan Arakali7d3d04392006-01-25 14:53:07 -050091 /* LRO statistics */
92 unsigned long long clubbed_frms_cnt;
93 unsigned long long sending_both;
94 unsigned long long outof_sequence_pkts;
95 unsigned long long flush_max_pkts;
96 unsigned long long sum_avg_pkts_aggregated;
97 unsigned long long num_aggregations;
Sreenivasa Honnurc53d4942007-05-10 04:18:54 -040098 /* Other statistics */
99 unsigned long long mem_alloc_fail_cnt;
100 unsigned long long watchdog_timer_cnt;
Sreenivasa Honnur491976b2007-05-10 04:22:25 -0400101 unsigned long long mem_allocated;
102 unsigned long long mem_freed;
103 unsigned long long link_up_cnt;
104 unsigned long long link_down_cnt;
105 unsigned long long link_up_time;
106 unsigned long long link_down_time;
107
108 /* Transfer Code statistics */
109 unsigned long long tx_buf_abort_cnt;
110 unsigned long long tx_desc_abort_cnt;
111 unsigned long long tx_parity_err_cnt;
112 unsigned long long tx_link_loss_cnt;
113 unsigned long long tx_list_proc_err_cnt;
114
115 unsigned long long rx_parity_err_cnt;
116 unsigned long long rx_abort_cnt;
117 unsigned long long rx_parity_abort_cnt;
118 unsigned long long rx_rda_fail_cnt;
119 unsigned long long rx_unkn_prot_cnt;
120 unsigned long long rx_fcs_err_cnt;
121 unsigned long long rx_buf_size_err_cnt;
122 unsigned long long rx_rxd_corrupt_cnt;
123 unsigned long long rx_unkn_err_cnt;
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500124};
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700125
Ananda Rajubd1034f2006-04-21 19:20:22 -0400126/* Xpak releated alarm and warnings */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500127struct xpakStat {
Ananda Rajubd1034f2006-04-21 19:20:22 -0400128 u64 alarm_transceiver_temp_high;
129 u64 alarm_transceiver_temp_low;
130 u64 alarm_laser_bias_current_high;
131 u64 alarm_laser_bias_current_low;
132 u64 alarm_laser_output_power_high;
133 u64 alarm_laser_output_power_low;
134 u64 warn_transceiver_temp_high;
135 u64 warn_transceiver_temp_low;
136 u64 warn_laser_bias_current_high;
137 u64 warn_laser_bias_current_low;
138 u64 warn_laser_output_power_high;
139 u64 warn_laser_output_power_low;
140 u64 xpak_regs_stat;
141 u32 xpak_timer_count;
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500142};
Ananda Rajubd1034f2006-04-21 19:20:22 -0400143
144
Linus Torvalds1da177e2005-04-16 15:20:36 -0700145/* The statistics block of Xena */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500146struct stat_block {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700147/* Tx MAC statistics counters. */
Al Viro107c3a72006-08-13 15:38:04 -0400148 __le32 tmac_data_octets;
149 __le32 tmac_frms;
150 __le64 tmac_drop_frms;
151 __le32 tmac_bcst_frms;
152 __le32 tmac_mcst_frms;
153 __le64 tmac_pause_ctrl_frms;
154 __le32 tmac_ucst_frms;
155 __le32 tmac_ttl_octets;
156 __le32 tmac_any_err_frms;
157 __le32 tmac_nucst_frms;
158 __le64 tmac_ttl_less_fb_octets;
159 __le64 tmac_vld_ip_octets;
160 __le32 tmac_drop_ip;
161 __le32 tmac_vld_ip;
162 __le32 tmac_rst_tcp;
163 __le32 tmac_icmp;
164 __le64 tmac_tcp;
165 __le32 reserved_0;
166 __le32 tmac_udp;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700167
168/* Rx MAC Statistics counters. */
Al Viro107c3a72006-08-13 15:38:04 -0400169 __le32 rmac_data_octets;
170 __le32 rmac_vld_frms;
171 __le64 rmac_fcs_err_frms;
172 __le64 rmac_drop_frms;
173 __le32 rmac_vld_bcst_frms;
174 __le32 rmac_vld_mcst_frms;
175 __le32 rmac_out_rng_len_err_frms;
176 __le32 rmac_in_rng_len_err_frms;
177 __le64 rmac_long_frms;
178 __le64 rmac_pause_ctrl_frms;
179 __le64 rmac_unsup_ctrl_frms;
180 __le32 rmac_accepted_ucst_frms;
181 __le32 rmac_ttl_octets;
182 __le32 rmac_discarded_frms;
183 __le32 rmac_accepted_nucst_frms;
184 __le32 reserved_1;
185 __le32 rmac_drop_events;
186 __le64 rmac_ttl_less_fb_octets;
187 __le64 rmac_ttl_frms;
188 __le64 reserved_2;
189 __le32 rmac_usized_frms;
190 __le32 reserved_3;
191 __le32 rmac_frag_frms;
192 __le32 rmac_osized_frms;
193 __le32 reserved_4;
194 __le32 rmac_jabber_frms;
195 __le64 rmac_ttl_64_frms;
196 __le64 rmac_ttl_65_127_frms;
197 __le64 reserved_5;
198 __le64 rmac_ttl_128_255_frms;
199 __le64 rmac_ttl_256_511_frms;
200 __le64 reserved_6;
201 __le64 rmac_ttl_512_1023_frms;
202 __le64 rmac_ttl_1024_1518_frms;
203 __le32 rmac_ip;
204 __le32 reserved_7;
205 __le64 rmac_ip_octets;
206 __le32 rmac_drop_ip;
207 __le32 rmac_hdr_err_ip;
208 __le32 reserved_8;
209 __le32 rmac_icmp;
210 __le64 rmac_tcp;
211 __le32 rmac_err_drp_udp;
212 __le32 rmac_udp;
213 __le64 rmac_xgmii_err_sym;
214 __le64 rmac_frms_q0;
215 __le64 rmac_frms_q1;
216 __le64 rmac_frms_q2;
217 __le64 rmac_frms_q3;
218 __le64 rmac_frms_q4;
219 __le64 rmac_frms_q5;
220 __le64 rmac_frms_q6;
221 __le64 rmac_frms_q7;
222 __le16 rmac_full_q3;
223 __le16 rmac_full_q2;
224 __le16 rmac_full_q1;
225 __le16 rmac_full_q0;
226 __le16 rmac_full_q7;
227 __le16 rmac_full_q6;
228 __le16 rmac_full_q5;
229 __le16 rmac_full_q4;
230 __le32 reserved_9;
231 __le32 rmac_pause_cnt;
232 __le64 rmac_xgmii_data_err_cnt;
233 __le64 rmac_xgmii_ctrl_err_cnt;
234 __le32 rmac_err_tcp;
235 __le32 rmac_accepted_ip;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700236
237/* PCI/PCI-X Read transaction statistics. */
Al Viro107c3a72006-08-13 15:38:04 -0400238 __le32 new_rd_req_cnt;
239 __le32 rd_req_cnt;
240 __le32 rd_rtry_cnt;
241 __le32 new_rd_req_rtry_cnt;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700242
243/* PCI/PCI-X Write/Read transaction statistics. */
Al Viro107c3a72006-08-13 15:38:04 -0400244 __le32 wr_req_cnt;
245 __le32 wr_rtry_rd_ack_cnt;
246 __le32 new_wr_req_rtry_cnt;
247 __le32 new_wr_req_cnt;
248 __le32 wr_disc_cnt;
249 __le32 wr_rtry_cnt;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700250
251/* PCI/PCI-X Write / DMA Transaction statistics. */
Al Viro107c3a72006-08-13 15:38:04 -0400252 __le32 txp_wr_cnt;
253 __le32 rd_rtry_wr_ack_cnt;
254 __le32 txd_wr_cnt;
255 __le32 txd_rd_cnt;
256 __le32 rxd_wr_cnt;
257 __le32 rxd_rd_cnt;
258 __le32 rxf_wr_cnt;
259 __le32 txf_rd_cnt;
raghavendra.koushik@neterion.com7ba013a2005-08-03 12:29:20 -0700260
raghavendra.koushik@neterion.com541ae682005-08-03 12:36:55 -0700261/* Tx MAC statistics overflow counters. */
Al Viro107c3a72006-08-13 15:38:04 -0400262 __le32 tmac_data_octets_oflow;
263 __le32 tmac_frms_oflow;
264 __le32 tmac_bcst_frms_oflow;
265 __le32 tmac_mcst_frms_oflow;
266 __le32 tmac_ucst_frms_oflow;
267 __le32 tmac_ttl_octets_oflow;
268 __le32 tmac_any_err_frms_oflow;
269 __le32 tmac_nucst_frms_oflow;
270 __le64 tmac_vlan_frms;
271 __le32 tmac_drop_ip_oflow;
272 __le32 tmac_vld_ip_oflow;
273 __le32 tmac_rst_tcp_oflow;
274 __le32 tmac_icmp_oflow;
275 __le32 tpa_unknown_protocol;
276 __le32 tmac_udp_oflow;
277 __le32 reserved_10;
278 __le32 tpa_parse_failure;
raghavendra.koushik@neterion.com541ae682005-08-03 12:36:55 -0700279
280/* Rx MAC Statistics overflow counters. */
Al Viro107c3a72006-08-13 15:38:04 -0400281 __le32 rmac_data_octets_oflow;
282 __le32 rmac_vld_frms_oflow;
283 __le32 rmac_vld_bcst_frms_oflow;
284 __le32 rmac_vld_mcst_frms_oflow;
285 __le32 rmac_accepted_ucst_frms_oflow;
286 __le32 rmac_ttl_octets_oflow;
287 __le32 rmac_discarded_frms_oflow;
288 __le32 rmac_accepted_nucst_frms_oflow;
289 __le32 rmac_usized_frms_oflow;
290 __le32 rmac_drop_events_oflow;
291 __le32 rmac_frag_frms_oflow;
292 __le32 rmac_osized_frms_oflow;
293 __le32 rmac_ip_oflow;
294 __le32 rmac_jabber_frms_oflow;
295 __le32 rmac_icmp_oflow;
296 __le32 rmac_drop_ip_oflow;
297 __le32 rmac_err_drp_udp_oflow;
298 __le32 rmac_udp_oflow;
299 __le32 reserved_11;
300 __le32 rmac_pause_cnt_oflow;
301 __le64 rmac_ttl_1519_4095_frms;
302 __le64 rmac_ttl_4096_8191_frms;
303 __le64 rmac_ttl_8192_max_frms;
304 __le64 rmac_ttl_gt_max_frms;
305 __le64 rmac_osized_alt_frms;
306 __le64 rmac_jabber_alt_frms;
307 __le64 rmac_gt_max_alt_frms;
308 __le64 rmac_vlan_frms;
309 __le32 rmac_len_discard;
310 __le32 rmac_fcs_discard;
311 __le32 rmac_pf_discard;
312 __le32 rmac_da_discard;
313 __le32 rmac_red_discard;
314 __le32 rmac_rts_discard;
315 __le32 reserved_12;
316 __le32 rmac_ingm_full_discard;
317 __le32 reserved_13;
318 __le32 rmac_accepted_ip_oflow;
319 __le32 reserved_14;
320 __le32 link_fault_cnt;
Ananda Rajubd1034f2006-04-21 19:20:22 -0400321 u8 buffer[20];
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500322 struct swStat sw_stat;
323 struct xpakStat xpak_stat;
324};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700325
Sivakumar Subramani926930b2007-02-24 01:59:39 -0500326/* Default value for 'vlan_strip_tag' configuration parameter */
327#define NO_STRIP_IN_PROMISC 2
328
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700329/*
330 * Structures representing different init time configuration
Linus Torvalds1da177e2005-04-16 15:20:36 -0700331 * parameters of the NIC.
332 */
333
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700334#define MAX_TX_FIFOS 8
335#define MAX_RX_RINGS 8
336
Sreenivasa Honnur0cec35e2007-05-10 04:06:28 -0400337#define MAX_RX_DESC_1 (MAX_RX_RINGS * MAX_RX_BLOCKS_PER_RING * 127 )
338#define MAX_RX_DESC_2 (MAX_RX_RINGS * MAX_RX_BLOCKS_PER_RING * 85 )
339#define MAX_RX_DESC_3 (MAX_RX_RINGS * MAX_RX_BLOCKS_PER_RING * 85 )
340#define MAX_TX_DESC (MAX_AVAILABLE_TXDS)
341
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700342/* FIFO mappings for all possible number of fifos configured */
Adrian Bunk26df54b2006-01-14 03:09:40 +0100343static int fifo_map[][MAX_TX_FIFOS] = {
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700344 {0, 0, 0, 0, 0, 0, 0, 0},
345 {0, 0, 0, 0, 1, 1, 1, 1},
346 {0, 0, 0, 1, 1, 1, 2, 2},
347 {0, 0, 1, 1, 2, 2, 3, 3},
348 {0, 0, 1, 1, 2, 2, 3, 4},
349 {0, 0, 1, 1, 2, 3, 4, 5},
350 {0, 0, 1, 2, 3, 4, 5, 6},
351 {0, 1, 2, 3, 4, 5, 6, 7},
352};
353
Linus Torvalds1da177e2005-04-16 15:20:36 -0700354/* Maintains Per FIFO related information. */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500355struct tx_fifo_config {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700356#define MAX_AVAILABLE_TXDS 8192
357 u32 fifo_len; /* specifies len of FIFO upto 8192, ie no of TxDLs */
358/* Priority definition */
359#define TX_FIFO_PRI_0 0 /*Highest */
360#define TX_FIFO_PRI_1 1
361#define TX_FIFO_PRI_2 2
362#define TX_FIFO_PRI_3 3
363#define TX_FIFO_PRI_4 4
364#define TX_FIFO_PRI_5 5
365#define TX_FIFO_PRI_6 6
366#define TX_FIFO_PRI_7 7 /*lowest */
367 u8 fifo_priority; /* specifies pointer level for FIFO */
368 /* user should not set twos fifos with same pri */
369 u8 f_no_snoop;
370#define NO_SNOOP_TXD 0x01
371#define NO_SNOOP_TXD_BUFFER 0x02
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500372};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700373
374
375/* Maintains per Ring related information */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500376struct rx_ring_config {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700377 u32 num_rxd; /*No of RxDs per Rx Ring */
378#define RX_RING_PRI_0 0 /* highest */
379#define RX_RING_PRI_1 1
380#define RX_RING_PRI_2 2
381#define RX_RING_PRI_3 3
382#define RX_RING_PRI_4 4
383#define RX_RING_PRI_5 5
384#define RX_RING_PRI_6 6
385#define RX_RING_PRI_7 7 /* lowest */
386
387 u8 ring_priority; /*Specifies service priority of ring */
388 /* OSM should not set any two rings with same priority */
389 u8 ring_org; /*Organization of ring */
390#define RING_ORG_BUFF1 0x01
391#define RX_RING_ORG_BUFF3 0x03
392#define RX_RING_ORG_BUFF5 0x05
393
394 u8 f_no_snoop;
395#define NO_SNOOP_RXD 0x01
396#define NO_SNOOP_RXD_BUFFER 0x02
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500397};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700398
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700399/* This structure provides contains values of the tunable parameters
400 * of the H/W
Linus Torvalds1da177e2005-04-16 15:20:36 -0700401 */
402struct config_param {
403/* Tx Side */
404 u32 tx_fifo_num; /*Number of Tx FIFOs */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700405
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700406 u8 fifo_mapping[MAX_TX_FIFOS];
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500407 struct tx_fifo_config tx_cfg[MAX_TX_FIFOS]; /*Per-Tx FIFO config */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700408 u32 max_txds; /*Max no. of Tx buffer descriptor per TxDL */
409 u64 tx_intr_type;
410 /* Specifies if Tx Intr is UTILZ or PER_LIST type. */
411
412/* Rx Side */
413 u32 rx_ring_num; /*Number of receive rings */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700414#define MAX_RX_BLOCKS_PER_RING 150
415
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500416 struct rx_ring_config rx_cfg[MAX_RX_RINGS]; /*Per-Rx Ring config */
raghavendra.koushik@neterion.comb6e3f982005-08-03 12:38:01 -0700417 u8 bimodal; /*Flag for setting bimodal interrupts*/
Linus Torvalds1da177e2005-04-16 15:20:36 -0700418
419#define HEADER_ETHERNET_II_802_3_SIZE 14
420#define HEADER_802_2_SIZE 3
421#define HEADER_SNAP_SIZE 5
422#define HEADER_VLAN_SIZE 4
423
424#define MIN_MTU 46
425#define MAX_PYLD 1500
426#define MAX_MTU (MAX_PYLD+18)
427#define MAX_MTU_VLAN (MAX_PYLD+22)
428#define MAX_PYLD_JUMBO 9600
429#define MAX_MTU_JUMBO (MAX_PYLD_JUMBO+18)
430#define MAX_MTU_JUMBO_VLAN (MAX_PYLD_JUMBO+22)
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700431 u16 bus_speed;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700432};
433
434/* Structure representing MAC Addrs */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500435struct mac_addr {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700436 u8 mac_addr[ETH_ALEN];
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500437};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700438
439/* Structure that represent every FIFO element in the BAR1
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700440 * Address location.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700441 */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500442struct TxFIFO_element {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700443 u64 TxDL_Pointer;
444
445 u64 List_Control;
446#define TX_FIFO_LAST_TXD_NUM( val) vBIT(val,0,8)
447#define TX_FIFO_FIRST_LIST BIT(14)
448#define TX_FIFO_LAST_LIST BIT(15)
449#define TX_FIFO_FIRSTNLAST_LIST vBIT(3,14,2)
450#define TX_FIFO_SPECIAL_FUNC BIT(23)
451#define TX_FIFO_DS_NO_SNOOP BIT(31)
452#define TX_FIFO_BUFF_NO_SNOOP BIT(30)
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500453};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700454
455/* Tx descriptor structure */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500456struct TxD {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700457 u64 Control_1;
458/* bit mask */
459#define TXD_LIST_OWN_XENA BIT(7)
460#define TXD_T_CODE (BIT(12)|BIT(13)|BIT(14)|BIT(15))
461#define TXD_T_CODE_OK(val) (|(val & TXD_T_CODE))
462#define GET_TXD_T_CODE(val) ((val & TXD_T_CODE)<<12)
463#define TXD_GATHER_CODE (BIT(22) | BIT(23))
464#define TXD_GATHER_CODE_FIRST BIT(22)
465#define TXD_GATHER_CODE_LAST BIT(23)
466#define TXD_TCP_LSO_EN BIT(30)
467#define TXD_UDP_COF_EN BIT(31)
Ananda Rajufed5ecc2005-11-14 15:25:08 -0500468#define TXD_UFO_EN BIT(31) | BIT(30)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700469#define TXD_TCP_LSO_MSS(val) vBIT(val,34,14)
Ananda Rajufed5ecc2005-11-14 15:25:08 -0500470#define TXD_UFO_MSS(val) vBIT(val,34,14)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700471#define TXD_BUFFER0_SIZE(val) vBIT(val,48,16)
472
473 u64 Control_2;
474#define TXD_TX_CKO_CONTROL (BIT(5)|BIT(6)|BIT(7))
475#define TXD_TX_CKO_IPV4_EN BIT(5)
476#define TXD_TX_CKO_TCP_EN BIT(6)
477#define TXD_TX_CKO_UDP_EN BIT(7)
478#define TXD_VLAN_ENABLE BIT(15)
479#define TXD_VLAN_TAG(val) vBIT(val,16,16)
480#define TXD_INT_NUMBER(val) vBIT(val,34,6)
481#define TXD_INT_TYPE_PER_LIST BIT(47)
482#define TXD_INT_TYPE_UTILZ BIT(46)
483#define TXD_SET_MARKER vBIT(0x6,0,4)
484
485 u64 Buffer_Pointer;
486 u64 Host_Control; /* reserved for host */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500487};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700488
489/* Structure to hold the phy and virt addr of every TxDL. */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500490struct list_info_hold {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700491 dma_addr_t list_phy_addr;
492 void *list_virt_addr;
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500493};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700494
Ananda Rajuda6971d2005-10-31 16:55:31 -0500495/* Rx descriptor structure for 1 buffer mode */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500496struct RxD_t {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700497 u64 Host_Control; /* reserved for host */
498 u64 Control_1;
499#define RXD_OWN_XENA BIT(7)
500#define RXD_T_CODE (BIT(12)|BIT(13)|BIT(14)|BIT(15))
501#define RXD_FRAME_PROTO vBIT(0xFFFF,24,8)
502#define RXD_FRAME_PROTO_IPV4 BIT(27)
503#define RXD_FRAME_PROTO_IPV6 BIT(28)
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700504#define RXD_FRAME_IP_FRAG BIT(29)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700505#define RXD_FRAME_PROTO_TCP BIT(30)
506#define RXD_FRAME_PROTO_UDP BIT(31)
507#define TCP_OR_UDP_FRAME (RXD_FRAME_PROTO_TCP | RXD_FRAME_PROTO_UDP)
508#define RXD_GET_L3_CKSUM(val) ((u16)(val>> 16) & 0xFFFF)
509#define RXD_GET_L4_CKSUM(val) ((u16)(val) & 0xFFFF)
510
511 u64 Control_2;
raghavendra.koushik@neterion.com5e25b9d2005-08-03 12:27:09 -0700512#define THE_RXD_MARK 0x3
513#define SET_RXD_MARKER vBIT(THE_RXD_MARK, 0, 2)
514#define GET_RXD_MARKER(ctrl) ((ctrl & SET_RXD_MARKER) >> 62)
515
Linus Torvalds1da177e2005-04-16 15:20:36 -0700516#define MASK_VLAN_TAG vBIT(0xFFFF,48,16)
517#define SET_VLAN_TAG(val) vBIT(val,48,16)
518#define SET_NUM_TAG(val) vBIT(val,16,32)
519
Ananda Rajuda6971d2005-10-31 16:55:31 -0500520
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500521};
Ananda Rajuda6971d2005-10-31 16:55:31 -0500522/* Rx descriptor structure for 1 buffer mode */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500523struct RxD1 {
524 struct RxD_t h;
Ananda Rajuda6971d2005-10-31 16:55:31 -0500525
526#define MASK_BUFFER0_SIZE_1 vBIT(0x3FFF,2,14)
527#define SET_BUFFER0_SIZE_1(val) vBIT(val,2,14)
528#define RXD_GET_BUFFER0_SIZE_1(_Control_2) \
529 (u16)((_Control_2 & MASK_BUFFER0_SIZE_1) >> 48)
530 u64 Buffer0_ptr;
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500531};
Ananda Rajuda6971d2005-10-31 16:55:31 -0500532/* Rx descriptor structure for 3 or 2 buffer mode */
533
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500534struct RxD3 {
535 struct RxD_t h;
Ananda Rajuda6971d2005-10-31 16:55:31 -0500536
537#define MASK_BUFFER0_SIZE_3 vBIT(0xFF,2,14)
538#define MASK_BUFFER1_SIZE_3 vBIT(0xFFFF,16,16)
539#define MASK_BUFFER2_SIZE_3 vBIT(0xFFFF,32,16)
540#define SET_BUFFER0_SIZE_3(val) vBIT(val,8,8)
541#define SET_BUFFER1_SIZE_3(val) vBIT(val,16,16)
542#define SET_BUFFER2_SIZE_3(val) vBIT(val,32,16)
543#define RXD_GET_BUFFER0_SIZE_3(Control_2) \
544 (u8)((Control_2 & MASK_BUFFER0_SIZE_3) >> 48)
545#define RXD_GET_BUFFER1_SIZE_3(Control_2) \
546 (u16)((Control_2 & MASK_BUFFER1_SIZE_3) >> 32)
547#define RXD_GET_BUFFER2_SIZE_3(Control_2) \
548 (u16)((Control_2 & MASK_BUFFER2_SIZE_3) >> 16)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700549#define BUF0_LEN 40
550#define BUF1_LEN 1
Linus Torvalds1da177e2005-04-16 15:20:36 -0700551
552 u64 Buffer0_ptr;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700553 u64 Buffer1_ptr;
554 u64 Buffer2_ptr;
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500555};
Ananda Rajuda6971d2005-10-31 16:55:31 -0500556
Linus Torvalds1da177e2005-04-16 15:20:36 -0700557
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700558/* Structure that represents the Rx descriptor block which contains
Linus Torvalds1da177e2005-04-16 15:20:36 -0700559 * 128 Rx descriptors.
560 */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500561struct RxD_block {
Ananda Rajuda6971d2005-10-31 16:55:31 -0500562#define MAX_RXDS_PER_BLOCK_1 127
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500563 struct RxD1 rxd[MAX_RXDS_PER_BLOCK_1];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700564
565 u64 reserved_0;
566#define END_OF_BLOCK 0xFEFFFFFFFFFFFFFFULL
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700567 u64 reserved_1; /* 0xFEFFFFFFFFFFFFFF to mark last
Linus Torvalds1da177e2005-04-16 15:20:36 -0700568 * Rxd in this blk */
569 u64 reserved_2_pNext_RxD_block; /* Logical ptr to next */
570 u64 pNext_RxD_Blk_physical; /* Buff0_ptr.In a 32 bit arch
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700571 * the upper 32 bits should
Linus Torvalds1da177e2005-04-16 15:20:36 -0700572 * be 0 */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500573};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700574
Linus Torvalds1da177e2005-04-16 15:20:36 -0700575#define SIZE_OF_BLOCK 4096
576
Sivakumar Subramani19a60522007-01-31 13:30:49 -0500577#define RXD_MODE_1 0 /* One Buffer mode */
578#define RXD_MODE_3A 1 /* Three Buffer mode */
579#define RXD_MODE_3B 2 /* Two Buffer mode */
Ananda Rajuda6971d2005-10-31 16:55:31 -0500580
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700581/* Structure to hold virtual addresses of Buf0 and Buf1 in
Linus Torvalds1da177e2005-04-16 15:20:36 -0700582 * 2buf mode. */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500583struct buffAdd {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700584 void *ba_0_org;
585 void *ba_1_org;
586 void *ba_0;
587 void *ba_1;
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500588};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700589
590/* Structure which stores all the MAC control parameters */
591
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700592/* This structure stores the offset of the RxD in the ring
593 * from which the Rx Interrupt processor can start picking
Linus Torvalds1da177e2005-04-16 15:20:36 -0700594 * up the RxDs for processing.
595 */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500596struct rx_curr_get_info {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700597 u32 block_index;
598 u32 offset;
599 u32 ring_len;
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500600};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700601
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500602struct rx_curr_put_info {
603 u32 block_index;
604 u32 offset;
605 u32 ring_len;
606};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700607
608/* This structure stores the offset of the TxDl in the FIFO
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700609 * from which the Tx Interrupt processor can start picking
Linus Torvalds1da177e2005-04-16 15:20:36 -0700610 * up the TxDLs for send complete interrupt processing.
611 */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500612struct tx_curr_get_info {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700613 u32 offset;
614 u32 fifo_len;
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500615};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700616
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500617struct tx_curr_put_info {
618 u32 offset;
619 u32 fifo_len;
620};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700621
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500622struct rxd_info {
Ananda Rajuda6971d2005-10-31 16:55:31 -0500623 void *virt_addr;
624 dma_addr_t dma_addr;
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500625};
Ananda Rajuda6971d2005-10-31 16:55:31 -0500626
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700627/* Structure that holds the Phy and virt addresses of the Blocks */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500628struct rx_block_info {
Ananda Rajuda6971d2005-10-31 16:55:31 -0500629 void *block_virt_addr;
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700630 dma_addr_t block_dma_addr;
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500631 struct rxd_info *rxds;
632};
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700633
634/* Ring specific structure */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500635struct ring_info {
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700636 /* The ring number */
637 int ring_no;
638
639 /*
640 * Place holders for the virtual and physical addresses of
641 * all the Rx Blocks
642 */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500643 struct rx_block_info rx_blocks[MAX_RX_BLOCKS_PER_RING];
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700644 int block_count;
645 int pkt_cnt;
646
647 /*
648 * Put pointer info which indictes which RxD has to be replenished
649 * with a new buffer.
650 */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500651 struct rx_curr_put_info rx_curr_put_info;
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700652
653 /*
654 * Get pointer info which indictes which is the last RxD that was
655 * processed by the driver.
656 */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500657 struct rx_curr_get_info rx_curr_get_info;
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700658
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700659 /* Index to the absolute position of the put pointer of Rx ring */
660 int put_pos;
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700661
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700662 /* Buffer Address store. */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500663 struct buffAdd **ba;
664 struct s2io_nic *nic;
665};
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700666
667/* Fifo specific structure */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500668struct fifo_info {
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700669 /* FIFO number */
670 int fifo_no;
671
672 /* Maximum TxDs per TxDL */
673 int max_txds;
674
675 /* Place holder of all the TX List's Phy and Virt addresses. */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500676 struct list_info_hold *list_info;
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700677
678 /*
679 * Current offset within the tx FIFO where driver would write
680 * new Tx frame
681 */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500682 struct tx_curr_put_info tx_curr_put_info;
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700683
684 /*
685 * Current offset within tx FIFO from where the driver would start freeing
686 * the buffers
687 */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500688 struct tx_curr_get_info tx_curr_get_info;
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700689
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500690 struct s2io_nic *nic;
691};
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700692
Adrian Bunk47bdd712006-06-30 18:25:18 +0200693/* Information related to the Tx and Rx FIFOs and Rings of Xena
Linus Torvalds1da177e2005-04-16 15:20:36 -0700694 * is maintained in this structure.
695 */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500696struct mac_info {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700697/* tx side stuff */
698 /* logical pointer of start of each Tx FIFO */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500699 struct TxFIFO_element __iomem *tx_FIFO_start[MAX_TX_FIFOS];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700700
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700701 /* Fifo specific structure */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500702 struct fifo_info fifos[MAX_TX_FIFOS];
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700703
ravinandan.arakali@neterion.com776bd202005-09-06 21:36:56 -0700704 /* Save virtual address of TxD page with zero DMA addr(if any) */
705 void *zerodma_virt_addr;
706
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700707/* rx side stuff */
708 /* Ring specific structure */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500709 struct ring_info rings[MAX_RX_RINGS];
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700710
711 u16 rmac_pause_time;
712 u16 mc_pause_threshold_q0q3;
713 u16 mc_pause_threshold_q4q7;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700714
715 void *stats_mem; /* orignal pointer to allocated mem */
716 dma_addr_t stats_mem_phy; /* Physical address of the stat block */
717 u32 stats_mem_sz;
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500718 struct stat_block *stats_info; /* Logical address of the stat block */
719};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700720
721/* structure representing the user defined MAC addresses */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500722struct usr_addr {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700723 char addr[ETH_ALEN];
724 int usage_cnt;
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500725};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700726
Linus Torvalds1da177e2005-04-16 15:20:36 -0700727/* Default Tunable parameters of the NIC. */
Ananda Raju9dc737a2006-04-21 19:05:41 -0400728#define DEFAULT_FIFO_0_LEN 4096
729#define DEFAULT_FIFO_1_7_LEN 512
Ananda Rajuc92ca042006-04-21 19:18:03 -0400730#define SMALL_BLK_CNT 30
731#define LARGE_BLK_CNT 100
Linus Torvalds1da177e2005-04-16 15:20:36 -0700732
Ravinandan Arakalicc6e7c42005-10-04 06:41:24 -0400733/*
734 * Structure to keep track of the MSI-X vectors and the corresponding
735 * argument registered against each vector
736 */
737#define MAX_REQUESTED_MSI_X 17
738struct s2io_msix_entry
739{
740 u16 vector;
741 u16 entry;
742 void *arg;
743
744 u8 type;
745#define MSIX_FIFO_TYPE 1
746#define MSIX_RING_TYPE 2
747
748 u8 in_use;
749#define MSIX_REGISTERED_SUCCESS 0xAA
750};
751
752struct msix_info_st {
753 u64 addr;
754 u64 data;
755};
756
Ravinandan Arakali7d3d04392006-01-25 14:53:07 -0500757/* Data structure to represent a LRO session */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500758struct lro {
Ravinandan Arakali7d3d04392006-01-25 14:53:07 -0500759 struct sk_buff *parent;
Ananda Raju75c30b12006-07-24 19:55:09 -0400760 struct sk_buff *last_frag;
Ravinandan Arakali7d3d04392006-01-25 14:53:07 -0500761 u8 *l2h;
762 struct iphdr *iph;
763 struct tcphdr *tcph;
764 u32 tcp_next_seq;
Al Virobd4f3ae2007-02-09 16:40:15 +0000765 __be32 tcp_ack;
Ravinandan Arakali7d3d04392006-01-25 14:53:07 -0500766 int total_len;
767 int frags_len;
768 int sg_num;
769 int in_use;
Al Virobd4f3ae2007-02-09 16:40:15 +0000770 __be16 window;
Ravinandan Arakali7d3d04392006-01-25 14:53:07 -0500771 u32 cur_tsval;
772 u32 cur_tsecr;
773 u8 saw_ts;
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500774};
Ravinandan Arakali7d3d04392006-01-25 14:53:07 -0500775
Linus Torvalds1da177e2005-04-16 15:20:36 -0700776/* Structure representing one instance of the NIC */
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700777struct s2io_nic {
Ananda Rajuda6971d2005-10-31 16:55:31 -0500778 int rxd_mode;
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700779 /*
780 * Count of packets to be processed in a given iteration, it will be indicated
781 * by the quota field of the device structure when NAPI is enabled.
782 */
783 int pkts_to_process;
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700784 struct net_device *dev;
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500785 struct mac_info mac_control;
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700786 struct config_param config;
787 struct pci_dev *pdev;
788 void __iomem *bar0;
789 void __iomem *bar1;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700790#define MAX_MAC_SUPPORTED 16
791#define MAX_SUPPORTED_MULTICASTS MAX_MAC_SUPPORTED
792
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500793 struct mac_addr def_mac_addr[MAX_MAC_SUPPORTED];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700794
795 struct net_device_stats stats;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700796 int high_dma_flag;
797 int device_close_flag;
798 int device_enabled_once;
799
Ananda Rajuc92ca042006-04-21 19:18:03 -0400800 char name[60];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700801 struct tasklet_struct task;
802 volatile unsigned long tasklet_status;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700803
raghavendra.koushik@neterion.com25fff882005-08-03 12:34:11 -0700804 /* Timer that handles I/O errors/exceptions */
805 struct timer_list alarm_timer;
806
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700807 /* Space to back up the PCI config space */
808 u32 config_space[256 / sizeof(u32)];
809
Linus Torvalds1da177e2005-04-16 15:20:36 -0700810 atomic_t rx_bufs_left[MAX_RX_RINGS];
811
812 spinlock_t tx_lock;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700813 spinlock_t put_lock;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700814
815#define PROMISC 1
816#define ALL_MULTI 2
817
818#define MAX_ADDRS_SUPPORTED 64
819 u16 usr_addr_count;
820 u16 mc_addr_count;
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500821 struct usr_addr usr_addrs[MAX_ADDRS_SUPPORTED];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700822
823 u16 m_cast_flg;
824 u16 all_multi_pos;
825 u16 promisc_flg;
826
Linus Torvalds1da177e2005-04-16 15:20:36 -0700827 /* Id timer, used to blink NIC to physically identify NIC. */
828 struct timer_list id_timer;
829
830 /* Restart timer, used to restart NIC if the device is stuck and
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700831 * a schedule task that will set the correct Link state once the
Linus Torvalds1da177e2005-04-16 15:20:36 -0700832 * NIC's PHY has stabilized after a state change.
833 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700834 struct work_struct rst_timer_task;
835 struct work_struct set_link_task;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700836
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700837 /* Flag that can be used to turn on or turn off the Rx checksum
Linus Torvalds1da177e2005-04-16 15:20:36 -0700838 * offload feature.
839 */
840 int rx_csum;
841
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700842 /* after blink, the adapter must be restored with original
Linus Torvalds1da177e2005-04-16 15:20:36 -0700843 * values.
844 */
845 u64 adapt_ctrl_org;
846
847 /* Last known link state. */
848 u16 last_link_state;
849#define LINK_DOWN 1
850#define LINK_UP 2
851
Linus Torvalds1da177e2005-04-16 15:20:36 -0700852 int task_flag;
Sreenivasa Honnur491976b2007-05-10 04:22:25 -0400853 unsigned long long start_time;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700854#define CARD_DOWN 1
855#define CARD_UP 2
856 atomic_t card_state;
857 volatile unsigned long link_state;
raghavendra.koushik@neterion.combe3a6b02005-08-03 12:35:55 -0700858 struct vlan_group *vlgrp;
Ravinandan Arakalicc6e7c42005-10-04 06:41:24 -0400859#define MSIX_FLG 0xA5
860 struct msix_entry *entries;
861 struct s2io_msix_entry *s2io_entries;
Ananda Rajue6a8fee2006-07-06 23:58:23 -0700862 char desc[MAX_REQUESTED_MSI_X][25];
Ravinandan Arakalicc6e7c42005-10-04 06:41:24 -0400863
Ananda Rajuc92ca042006-04-21 19:18:03 -0400864 int avail_msix_vectors; /* No. of MSI-X vectors granted by system */
865
Ravinandan Arakalicc6e7c42005-10-04 06:41:24 -0400866 struct msix_info_st msix_info[0x3f];
867
raghavendra.koushik@neterion.com541ae682005-08-03 12:36:55 -0700868#define XFRAME_I_DEVICE 1
869#define XFRAME_II_DEVICE 2
870 u8 device_type;
raghavendra.koushik@neterion.combe3a6b02005-08-03 12:35:55 -0700871
Ravinandan Arakali7d3d04392006-01-25 14:53:07 -0500872#define MAX_LRO_SESSIONS 32
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500873 struct lro lro0_n[MAX_LRO_SESSIONS];
Ravinandan Arakali7d3d04392006-01-25 14:53:07 -0500874 unsigned long clubbed_frms_cnt;
875 unsigned long sending_both;
876 u8 lro;
877 u16 lro_max_aggr_per_sess;
878
Ravinandan Arakalicc6e7c42005-10-04 06:41:24 -0400879#define INTA 0
880#define MSI 1
881#define MSI_X 2
882 u8 intr_type;
883
raghavendra.koushik@neterion.com7ba013a2005-08-03 12:29:20 -0700884 spinlock_t rx_lock;
885 atomic_t isr_cnt;
Ananda Rajufed5ecc2005-11-14 15:25:08 -0500886 u64 *ufo_in_band_v;
Sivakumar Subramani19a60522007-01-31 13:30:49 -0500887#define VPD_STRING_LEN 80
888 u8 product_name[VPD_STRING_LEN];
889 u8 serial_num[VPD_STRING_LEN];
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700890};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700891
892#define RESET_ERROR 1;
893#define CMD_ERROR 2;
894
895/* OS related system calls */
896#ifndef readq
897static inline u64 readq(void __iomem *addr)
898{
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700899 u64 ret = 0;
900 ret = readl(addr + 4);
Andrew Morton7ef24b62005-08-25 17:14:46 -0700901 ret <<= 32;
902 ret |= readl(addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700903
904 return ret;
905}
906#endif
907
908#ifndef writeq
909static inline void writeq(u64 val, void __iomem *addr)
910{
911 writel((u32) (val), addr);
912 writel((u32) (val >> 32), (addr + 4));
913}
Ananda Rajuc92ca042006-04-21 19:18:03 -0400914#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700915
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400916/*
917 * Some registers have to be written in a particular order to
918 * expect correct hardware operation. The macro SPECIAL_REG_WRITE
919 * is used to perform such ordered writes. Defines UF (Upper First)
Ananda Rajuc92ca042006-04-21 19:18:03 -0400920 * and LF (Lower First) will be used to specify the required write order.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700921 */
922#define UF 1
923#define LF 2
924static inline void SPECIAL_REG_WRITE(u64 val, void __iomem *addr, int order)
925{
Ananda Rajuc92ca042006-04-21 19:18:03 -0400926 u32 ret;
927
Linus Torvalds1da177e2005-04-16 15:20:36 -0700928 if (order == LF) {
929 writel((u32) (val), addr);
Ananda Rajuc92ca042006-04-21 19:18:03 -0400930 ret = readl(addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700931 writel((u32) (val >> 32), (addr + 4));
Ananda Rajuc92ca042006-04-21 19:18:03 -0400932 ret = readl(addr + 4);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700933 } else {
934 writel((u32) (val >> 32), (addr + 4));
Ananda Rajuc92ca042006-04-21 19:18:03 -0400935 ret = readl(addr + 4);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700936 writel((u32) (val), addr);
Ananda Rajuc92ca042006-04-21 19:18:03 -0400937 ret = readl(addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700938 }
939}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700940
941/* Interrupt related values of Xena */
942
943#define ENABLE_INTRS 1
944#define DISABLE_INTRS 2
945
946/* Highest level interrupt blocks */
947#define TX_PIC_INTR (0x0001<<0)
948#define TX_DMA_INTR (0x0001<<1)
949#define TX_MAC_INTR (0x0001<<2)
950#define TX_XGXS_INTR (0x0001<<3)
951#define TX_TRAFFIC_INTR (0x0001<<4)
952#define RX_PIC_INTR (0x0001<<5)
953#define RX_DMA_INTR (0x0001<<6)
954#define RX_MAC_INTR (0x0001<<7)
955#define RX_XGXS_INTR (0x0001<<8)
956#define RX_TRAFFIC_INTR (0x0001<<9)
957#define MC_INTR (0x0001<<10)
958#define ENA_ALL_INTRS ( TX_PIC_INTR | \
959 TX_DMA_INTR | \
960 TX_MAC_INTR | \
961 TX_XGXS_INTR | \
962 TX_TRAFFIC_INTR | \
963 RX_PIC_INTR | \
964 RX_DMA_INTR | \
965 RX_MAC_INTR | \
966 RX_XGXS_INTR | \
967 RX_TRAFFIC_INTR | \
968 MC_INTR )
969
970/* Interrupt masks for the general interrupt mask register */
971#define DISABLE_ALL_INTRS 0xFFFFFFFFFFFFFFFFULL
972
973#define TXPIC_INT_M BIT(0)
974#define TXDMA_INT_M BIT(1)
975#define TXMAC_INT_M BIT(2)
976#define TXXGXS_INT_M BIT(3)
977#define TXTRAFFIC_INT_M BIT(8)
978#define PIC_RX_INT_M BIT(32)
979#define RXDMA_INT_M BIT(33)
980#define RXMAC_INT_M BIT(34)
981#define MC_INT_M BIT(35)
982#define RXXGXS_INT_M BIT(36)
983#define RXTRAFFIC_INT_M BIT(40)
984
985/* PIC level Interrupts TODO*/
986
987/* DMA level Inressupts */
988#define TXDMA_PFC_INT_M BIT(0)
989#define TXDMA_PCC_INT_M BIT(2)
990
991/* PFC block interrupts */
992#define PFC_MISC_ERR_1 BIT(0) /* Interrupt to indicate FIFO full */
993
994/* PCC block interrupts. */
995#define PCC_FB_ECC_ERR vBIT(0xff, 16, 8) /* Interrupt to indicate
996 PCC_FB_ECC Error. */
997
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700998#define RXD_GET_VLAN_TAG(Control_2) (u16)(Control_2 & MASK_VLAN_TAG)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700999/*
1000 * Prototype declaration.
1001 */
1002static int __devinit s2io_init_nic(struct pci_dev *pdev,
1003 const struct pci_device_id *pre);
1004static void __devexit s2io_rem_nic(struct pci_dev *pdev);
1005static int init_shared_mem(struct s2io_nic *sp);
1006static void free_shared_mem(struct s2io_nic *sp);
1007static int init_nic(struct s2io_nic *nic);
Ralf Baechle1ee6dd72007-01-31 14:09:29 -05001008static void rx_intr_handler(struct ring_info *ring_data);
1009static void tx_intr_handler(struct fifo_info *fifo_data);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001010static void alarm_intr_handler(struct s2io_nic *sp);
1011
1012static int s2io_starter(void);
Sivakumar Subramani19a60522007-01-31 13:30:49 -05001013static void s2io_closer(void);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001014static void s2io_tx_watchdog(struct net_device *dev);
1015static void s2io_tasklet(unsigned long dev_addr);
1016static void s2io_set_multicast(struct net_device *dev);
Ralf Baechle1ee6dd72007-01-31 14:09:29 -05001017static int rx_osm_handler(struct ring_info *ring_data, struct RxD_t * rxdp);
1018static void s2io_link(struct s2io_nic * sp, int link);
1019static void s2io_reset(struct s2io_nic * sp);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001020static int s2io_poll(struct net_device *dev, int *budget);
Ralf Baechle1ee6dd72007-01-31 14:09:29 -05001021static void s2io_init_pci(struct s2io_nic * sp);
Adrian Bunk26df54b2006-01-14 03:09:40 +01001022static int s2io_set_mac_addr(struct net_device *dev, u8 * addr);
raghavendra.koushik@neterion.com25fff882005-08-03 12:34:11 -07001023static void s2io_alarm_handle(unsigned long data);
Ralf Baechle1ee6dd72007-01-31 14:09:29 -05001024static int s2io_enable_msi(struct s2io_nic *nic);
David Howells7d12e782006-10-05 14:55:46 +01001025static irqreturn_t s2io_msi_handle(int irq, void *dev_id);
Ravinandan Arakalicc6e7c42005-10-04 06:41:24 -04001026static irqreturn_t
David Howells7d12e782006-10-05 14:55:46 +01001027s2io_msix_ring_handle(int irq, void *dev_id);
Ravinandan Arakalicc6e7c42005-10-04 06:41:24 -04001028static irqreturn_t
David Howells7d12e782006-10-05 14:55:46 +01001029s2io_msix_fifo_handle(int irq, void *dev_id);
1030static irqreturn_t s2io_isr(int irq, void *dev_id);
Ralf Baechle1ee6dd72007-01-31 14:09:29 -05001031static int verify_xena_quiescence(struct s2io_nic *sp);
Jeff Garzik7282d492006-09-13 14:30:00 -04001032static const struct ethtool_ops netdev_ethtool_ops;
David Howellsc4028952006-11-22 14:57:56 +00001033static void s2io_set_link(struct work_struct *work);
Ralf Baechle1ee6dd72007-01-31 14:09:29 -05001034static int s2io_set_swapper(struct s2io_nic * sp);
1035static void s2io_card_down(struct s2io_nic *nic);
1036static int s2io_card_up(struct s2io_nic *nic);
Adrian Bunk26df54b2006-01-14 03:09:40 +01001037static int get_xena_rev_id(struct pci_dev *pdev);
Sivakumar Subramani9fc93a42007-02-24 01:57:32 -05001038static int wait_for_cmd_complete(void __iomem *addr, u64 busy_bit,
1039 int bit_state);
Ralf Baechle1ee6dd72007-01-31 14:09:29 -05001040static int s2io_add_isr(struct s2io_nic * sp);
1041static void s2io_rem_isr(struct s2io_nic * sp);
Sivakumar Subramani19a60522007-01-31 13:30:49 -05001042
Ralf Baechle1ee6dd72007-01-31 14:09:29 -05001043static void restore_xmsi_data(struct s2io_nic *nic);
Ravinandan Arakali7d3d04392006-01-25 14:53:07 -05001044
Ralf Baechle1ee6dd72007-01-31 14:09:29 -05001045static int
1046s2io_club_tcp_session(u8 *buffer, u8 **tcp, u32 *tcp_len, struct lro **lro,
1047 struct RxD_t *rxdp, struct s2io_nic *sp);
1048static void clear_lro_session(struct lro *lro);
Ravinandan Arakali7d3d04392006-01-25 14:53:07 -05001049static void queue_rx_frame(struct sk_buff *skb);
Ralf Baechle1ee6dd72007-01-31 14:09:29 -05001050static void update_L3L4_header(struct s2io_nic *sp, struct lro *lro);
1051static void lro_append_pkt(struct s2io_nic *sp, struct lro *lro,
1052 struct sk_buff *skb, u32 tcp_len);
Sivakumar Subramani9fc93a42007-02-24 01:57:32 -05001053static int rts_ds_steer(struct s2io_nic *nic, u8 ds_codepoint, u8 ring);
Ananda Rajub41477f2006-07-24 19:52:49 -04001054
Ananda Raju75c30b12006-07-24 19:55:09 -04001055#define s2io_tcp_mss(skb) skb_shinfo(skb)->gso_size
1056#define s2io_udp_mss(skb) skb_shinfo(skb)->gso_size
1057#define s2io_offload_type(skb) skb_shinfo(skb)->gso_type
1058
Ananda Rajub41477f2006-07-24 19:52:49 -04001059#define S2IO_PARM_INT(X, def_val) \
1060 static unsigned int X = def_val;\
1061 module_param(X , uint, 0);
1062
Linus Torvalds1da177e2005-04-16 15:20:36 -07001063#endif /* _S2IO_H */