blob: 20fa7c84109d5ddff278b993cd0bb9de709dba00 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * Exceptions for specific devices. Usually work-arounds for fatal design flaws.
3 */
4
Jesse Barnesf8977d02005-10-25 10:28:42 -07005#include <linux/delay.h>
6#include <linux/dmi.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -07007#include <linux/pci.h>
Dave Airliedb2e0342012-05-17 08:31:29 +01008#include <linux/vgaarb.h>
Bjorn Helgaas44c8bdb2014-04-14 15:35:21 -06009#include <asm/hpet.h>
Jaswinder Singh Rajput82487712008-12-27 18:32:28 +053010#include <asm/pci_x86.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070011
Greg Kroah-Hartmana18e3692012-12-21 14:02:53 -080012static void pci_fixup_i450nx(struct pci_dev *d)
Linus Torvalds1da177e2005-04-16 15:20:36 -070013{
14 /*
15 * i450NX -- Find and scan all secondary buses on all PXB's.
16 */
17 int pxb, reg;
18 u8 busno, suba, subb;
19
bjorn.helgaas@hp.com9ed88552007-12-17 14:09:40 -070020 dev_warn(&d->dev, "Searching for i450NX host bridges\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -070021 reg = 0xd0;
Paolo Ciarrocchi938f6672008-01-30 13:33:00 +010022 for(pxb = 0; pxb < 2; pxb++) {
Linus Torvalds1da177e2005-04-16 15:20:36 -070023 pci_read_config_byte(d, reg++, &busno);
24 pci_read_config_byte(d, reg++, &suba);
25 pci_read_config_byte(d, reg++, &subb);
Bjorn Helgaas12c0b202008-07-23 17:00:13 -060026 dev_dbg(&d->dev, "i450NX PXB %d: %02x/%02x/%02x\n", pxb, busno,
27 suba, subb);
Linus Torvalds1da177e2005-04-16 15:20:36 -070028 if (busno)
Bjorn Helgaas8d7d8182014-01-24 11:47:05 -070029 pcibios_scan_root(busno); /* Bus A */
Linus Torvalds1da177e2005-04-16 15:20:36 -070030 if (suba < subb)
Bjorn Helgaas8d7d8182014-01-24 11:47:05 -070031 pcibios_scan_root(suba+1); /* Bus B */
Linus Torvalds1da177e2005-04-16 15:20:36 -070032 }
33 pcibios_last_bus = -1;
34}
35DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82451NX, pci_fixup_i450nx);
36
Greg Kroah-Hartmana18e3692012-12-21 14:02:53 -080037static void pci_fixup_i450gx(struct pci_dev *d)
Linus Torvalds1da177e2005-04-16 15:20:36 -070038{
39 /*
40 * i450GX and i450KX -- Find and scan all secondary buses.
41 * (called separately for each PCI bridge found)
42 */
43 u8 busno;
44 pci_read_config_byte(d, 0x4a, &busno);
bjorn.helgaas@hp.com9ed88552007-12-17 14:09:40 -070045 dev_info(&d->dev, "i440KX/GX host bridge; secondary bus %02x\n", busno);
Bjorn Helgaas8d7d8182014-01-24 11:47:05 -070046 pcibios_scan_root(busno);
Linus Torvalds1da177e2005-04-16 15:20:36 -070047 pcibios_last_bus = -1;
48}
49DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454GX, pci_fixup_i450gx);
50
Greg Kroah-Hartmana18e3692012-12-21 14:02:53 -080051static void pci_fixup_umc_ide(struct pci_dev *d)
Linus Torvalds1da177e2005-04-16 15:20:36 -070052{
53 /*
54 * UM8886BF IDE controller sets region type bits incorrectly,
55 * therefore they look like memory despite of them being I/O.
56 */
57 int i;
58
bjorn.helgaas@hp.com9ed88552007-12-17 14:09:40 -070059 dev_warn(&d->dev, "Fixing base address flags\n");
Paolo Ciarrocchi938f6672008-01-30 13:33:00 +010060 for(i = 0; i < 4; i++)
Linus Torvalds1da177e2005-04-16 15:20:36 -070061 d->resource[i].flags |= PCI_BASE_ADDRESS_SPACE_IO;
62}
63DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_UMC, PCI_DEVICE_ID_UMC_UM8886BF, pci_fixup_umc_ide);
64
Greg Kroah-Hartmana18e3692012-12-21 14:02:53 -080065static void pci_fixup_latency(struct pci_dev *d)
Linus Torvalds1da177e2005-04-16 15:20:36 -070066{
67 /*
68 * SiS 5597 and 5598 chipsets require latency timer set to
69 * at most 32 to avoid lockups.
70 */
bjorn.helgaas@hp.com9ed88552007-12-17 14:09:40 -070071 dev_dbg(&d->dev, "Setting max latency to 32\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -070072 pcibios_max_latency = 32;
73}
74DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, pci_fixup_latency);
75DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5598, pci_fixup_latency);
76
Greg Kroah-Hartmana18e3692012-12-21 14:02:53 -080077static void pci_fixup_piix4_acpi(struct pci_dev *d)
Linus Torvalds1da177e2005-04-16 15:20:36 -070078{
79 /*
80 * PIIX4 ACPI device: hardwired IRQ9
81 */
82 d->irq = 9;
83}
84DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, pci_fixup_piix4_acpi);
85
86/*
87 * Addresses issues with problems in the memory write queue timer in
88 * certain VIA Northbridges. This bugfix is per VIA's specifications,
89 * except for the KL133/KM133: clearing bit 5 on those Northbridges seems
90 * to trigger a bug in its integrated ProSavage video card, which
91 * causes screen corruption. We only clear bits 6 and 7 for that chipset,
92 * until VIA can provide us with definitive information on why screen
93 * corruption occurs, and what exactly those bits do.
94 *
95 * VIA 8363,8622,8361 Northbridges:
96 * - bits 5, 6, 7 at offset 0x55 need to be turned off
97 * VIA 8367 (KT266x) Northbridges:
98 * - bits 5, 6, 7 at offset 0x95 need to be turned off
99 * VIA 8363 rev 0x81/0x84 (KL133/KM133) Northbridges:
100 * - bits 6, 7 at offset 0x55 need to be turned off
101 */
102
103#define VIA_8363_KL133_REVISION_ID 0x81
104#define VIA_8363_KM133_REVISION_ID 0x84
105
Alan Cox1597cac2006-12-04 15:14:45 -0800106static void pci_fixup_via_northbridge_bug(struct pci_dev *d)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700107{
108 u8 v;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700109 int where = 0x55;
110 int mask = 0x1f; /* clear bits 5, 6, 7 by default */
111
Linus Torvalds1da177e2005-04-16 15:20:36 -0700112 if (d->device == PCI_DEVICE_ID_VIA_8367_0) {
113 /* fix pci bus latency issues resulted by NB bios error
114 it appears on bug free^Wreduced kt266x's bios forces
115 NB latency to zero */
116 pci_write_config_byte(d, PCI_LATENCY_TIMER, 0);
117
Paolo Ciarrocchi938f6672008-01-30 13:33:00 +0100118 where = 0x95; /* the memory write queue timer register is
Linus Torvalds1da177e2005-04-16 15:20:36 -0700119 different for the KT266x's: 0x95 not 0x55 */
120 } else if (d->device == PCI_DEVICE_ID_VIA_8363_0 &&
Auke Kok44c10132007-06-08 15:46:36 -0700121 (d->revision == VIA_8363_KL133_REVISION_ID ||
122 d->revision == VIA_8363_KM133_REVISION_ID)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700123 mask = 0x3f; /* clear only bits 6 and 7; clearing bit 5
124 causes screen corruption on the KL133/KM133 */
125 }
126
127 pci_read_config_byte(d, where, &v);
128 if (v & ~mask) {
bjorn.helgaas@hp.com9ed88552007-12-17 14:09:40 -0700129 dev_warn(&d->dev, "Disabling VIA memory write queue (PCI ID %04x, rev %02x): [%02x] %02x & %02x -> %02x\n", \
Auke Kok44c10132007-06-08 15:46:36 -0700130 d->device, d->revision, where, v, mask, v & mask);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700131 v &= mask;
132 pci_write_config_byte(d, where, v);
133 }
134}
135DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, pci_fixup_via_northbridge_bug);
136DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8622, pci_fixup_via_northbridge_bug);
137DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, pci_fixup_via_northbridge_bug);
138DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8367_0, pci_fixup_via_northbridge_bug);
Alan Cox1597cac2006-12-04 15:14:45 -0800139DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, pci_fixup_via_northbridge_bug);
140DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8622, pci_fixup_via_northbridge_bug);
141DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, pci_fixup_via_northbridge_bug);
142DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8367_0, pci_fixup_via_northbridge_bug);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700143
144/*
145 * For some reasons Intel decided that certain parts of their
146 * 815, 845 and some other chipsets must look like PCI-to-PCI bridges
147 * while they are obviously not. The 82801 family (AA, AB, BAM/CAM,
148 * BA/CA/DB and E) PCI bridges are actually HUB-to-PCI ones, according
149 * to Intel terminology. These devices do forward all addresses from
150 * system to PCI bus no matter what are their window settings, so they are
151 * "transparent" (or subtractive decoding) from programmers point of view.
152 */
Greg Kroah-Hartmana18e3692012-12-21 14:02:53 -0800153static void pci_fixup_transparent_bridge(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700154{
Yinghai Lu4082cf22012-02-23 23:46:51 -0800155 if ((dev->device & 0xff00) == 0x2400)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700156 dev->transparent = 1;
157}
Yinghai Lu4082cf22012-02-23 23:46:51 -0800158DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
159 PCI_CLASS_BRIDGE_PCI, 8, pci_fixup_transparent_bridge);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700160
161/*
162 * Fixup for C1 Halt Disconnect problem on nForce2 systems.
163 *
164 * From information provided by "Allen Martin" <AMartin@nvidia.com>:
165 *
166 * A hang is caused when the CPU generates a very fast CONNECT/HALT cycle
167 * sequence. Workaround is to set the SYSTEM_IDLE_TIMEOUT to 80 ns.
168 * This allows the state-machine and timer to return to a proper state within
169 * 80 ns of the CONNECT and probe appearing together. Since the CPU will not
170 * issue another HALT within 80 ns of the initial HALT, the failure condition
171 * is avoided.
172 */
Alan Cox1597cac2006-12-04 15:14:45 -0800173static void pci_fixup_nforce2(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700174{
175 u32 val;
176
177 /*
178 * Chip Old value New value
179 * C17 0x1F0FFF01 0x1F01FF01
180 * C18D 0x9F0FFF01 0x9F01FF01
181 *
182 * Northbridge chip version may be determined by
183 * reading the PCI revision ID (0xC1 or greater is C18D).
184 */
185 pci_read_config_dword(dev, 0x6c, &val);
186
187 /*
188 * Apply fixup if needed, but don't touch disconnect state
189 */
190 if ((val & 0x00FF0000) != 0x00010000) {
bjorn.helgaas@hp.com9ed88552007-12-17 14:09:40 -0700191 dev_warn(&dev->dev, "nForce2 C1 Halt Disconnect fixup\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700192 pci_write_config_dword(dev, 0x6c, (val & 0xFF00FFFF) | 0x00010000);
193 }
194}
195DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2, pci_fixup_nforce2);
Alan Cox1597cac2006-12-04 15:14:45 -0800196DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2, pci_fixup_nforce2);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700197
198/* Max PCI Express root ports */
199#define MAX_PCIEROOT 6
200static int quirk_aspm_offset[MAX_PCIEROOT << 3];
201
Christoph Lameterff0d2f92005-05-17 08:48:16 -0700202#define GET_INDEX(a, b) ((((a) - PCI_DEVICE_ID_INTEL_MCH_PA) << 3) + ((b) & 7))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700203
204static int quirk_pcie_aspm_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *value)
205{
Matthew Wilcoxb6ce0682008-02-10 09:45:28 -0500206 return raw_pci_read(pci_domain_nr(bus), bus->number,
207 devfn, where, size, value);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700208}
209
210/*
211 * Replace the original pci bus ops for write with a new one that will filter
212 * the request to insure ASPM cannot be enabled.
213 */
214static int quirk_pcie_aspm_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value)
215{
216 u8 offset;
217
218 offset = quirk_aspm_offset[GET_INDEX(bus->self->device, devfn)];
219
220 if ((offset) && (where == offset))
Yijing Wangf8a26fe2013-09-05 15:55:28 +0800221 value = value & ~PCI_EXP_LNKCTL_ASPMC;
Paolo Ciarrocchi938f6672008-01-30 13:33:00 +0100222
Matthew Wilcoxb6ce0682008-02-10 09:45:28 -0500223 return raw_pci_write(pci_domain_nr(bus), bus->number,
224 devfn, where, size, value);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700225}
226
227static struct pci_ops quirk_pcie_aspm_ops = {
228 .read = quirk_pcie_aspm_read,
229 .write = quirk_pcie_aspm_write,
230};
231
232/*
233 * Prevents PCI Express ASPM (Active State Power Management) being enabled.
234 *
235 * Save the register offset, where the ASPM control bits are located,
236 * for each PCI Express device that is in the device list of
237 * the root port in an array for fast indexing. Replace the bus ops
238 * with the modified one.
239 */
240static void pcie_rootport_aspm_quirk(struct pci_dev *pdev)
241{
Yijing Wangf8a26fe2013-09-05 15:55:28 +0800242 int i;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700243 struct pci_bus *pbus;
244 struct pci_dev *dev;
245
246 if ((pbus = pdev->subordinate) == NULL)
247 return;
248
249 /*
250 * Check if the DID of pdev matches one of the six root ports. This
251 * check is needed in the case this function is called directly by the
252 * hot-plug driver.
253 */
254 if ((pdev->device < PCI_DEVICE_ID_INTEL_MCH_PA) ||
255 (pdev->device > PCI_DEVICE_ID_INTEL_MCH_PC1))
256 return;
257
258 if (list_empty(&pbus->devices)) {
259 /*
260 * If no device is attached to the root port at power-up or
261 * after hot-remove, the pbus->devices is empty and this code
262 * will set the offsets to zero and the bus ops to parent's bus
263 * ops, which is unmodified.
Paolo Ciarrocchi938f6672008-01-30 13:33:00 +0100264 */
265 for (i = GET_INDEX(pdev->device, 0); i <= GET_INDEX(pdev->device, 7); ++i)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700266 quirk_aspm_offset[i] = 0;
267
Yijing Wangf8a26fe2013-09-05 15:55:28 +0800268 pci_bus_set_ops(pbus, pbus->parent->ops);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700269 } else {
270 /*
271 * If devices are attached to the root port at power-up or
272 * after hot-add, the code loops through the device list of
273 * each root port to save the register offsets and replace the
274 * bus ops.
275 */
Yijing Wangf8a26fe2013-09-05 15:55:28 +0800276 list_for_each_entry(dev, &pbus->devices, bus_list)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700277 /* There are 0 to 8 devices attached to this bus */
Yijing Wangf8a26fe2013-09-05 15:55:28 +0800278 quirk_aspm_offset[GET_INDEX(pdev->device, dev->devfn)] =
279 dev->pcie_cap + PCI_EXP_LNKCTL;
280
281 pci_bus_set_ops(pbus, &quirk_pcie_aspm_ops);
282 dev_info(&pbus->dev, "writes to ASPM control bits will be ignored\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700283 }
Yijing Wangf8a26fe2013-09-05 15:55:28 +0800284
Linus Torvalds1da177e2005-04-16 15:20:36 -0700285}
Paolo Ciarrocchi938f6672008-01-30 13:33:00 +0100286DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PA, pcie_rootport_aspm_quirk);
287DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PA1, pcie_rootport_aspm_quirk);
288DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PB, pcie_rootport_aspm_quirk);
289DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PB1, pcie_rootport_aspm_quirk);
290DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PC, pcie_rootport_aspm_quirk);
291DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PC1, pcie_rootport_aspm_quirk);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700292
293/*
Eiichiro Oiwa6b5c76b2006-10-23 15:14:07 +0900294 * Fixup to mark boot BIOS video selected by BIOS before it changes
295 *
296 * From information provided by "Jon Smirl" <jonsmirl@gmail.com>
297 *
298 * The standard boot ROM sequence for an x86 machine uses the BIOS
299 * to select an initial video card for boot display. This boot video
Bjorn Helgaas0c0e0732016-03-01 11:38:46 -0600300 * card will have its BIOS copied to 0xC0000 in system RAM.
Eiichiro Oiwa6b5c76b2006-10-23 15:14:07 +0900301 * IORESOURCE_ROM_SHADOW is used to associate the boot video
302 * card with this copy. On laptops this copy has to be used since
303 * the main ROM may be compressed or combined with another image.
Sander Eikelenboomd8801e42014-01-31 10:28:23 +0100304 * See pci_map_rom() for use of this flag. Before marking the device
305 * with IORESOURCE_ROM_SHADOW check if a vga_default_device is already set
Bjorn Helgaas0c0e0732016-03-01 11:38:46 -0600306 * by either arch code or vga-arbitration; if so only apply the fixup to this
307 * already-determined primary video card.
Eiichiro Oiwa6b5c76b2006-10-23 15:14:07 +0900308 */
309
Greg Kroah-Hartmana18e3692012-12-21 14:02:53 -0800310static void pci_fixup_video(struct pci_dev *pdev)
Eiichiro Oiwa6b5c76b2006-10-23 15:14:07 +0900311{
312 struct pci_dev *bridge;
313 struct pci_bus *bus;
314 u16 config;
Bjorn Helgaas0c0e0732016-03-01 11:38:46 -0600315 struct resource *res;
Eiichiro Oiwa6b5c76b2006-10-23 15:14:07 +0900316
Eiichiro Oiwa6b5c76b2006-10-23 15:14:07 +0900317 /* Is VGA routed to us? */
318 bus = pdev->bus;
319 while (bus) {
320 bridge = bus->self;
321
322 /*
323 * From information provided by
324 * "David Miller" <davem@davemloft.net>
325 * The bridge control register is valid for PCI header
326 * type BRIDGE, or CARDBUS. Host to PCI controllers use
327 * PCI header type NORMAL.
328 */
Yijing Wang56a41f92014-05-04 12:23:39 +0800329 if (bridge && (pci_is_bridge(bridge))) {
Eiichiro Oiwa6b5c76b2006-10-23 15:14:07 +0900330 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
331 &config);
332 if (!(config & PCI_BRIDGE_CTL_VGA))
333 return;
334 }
335 bus = bus->parent;
336 }
Sander Eikelenboomd8801e42014-01-31 10:28:23 +0100337 if (!vga_default_device() || pdev == vga_default_device()) {
338 pci_read_config_word(pdev, PCI_COMMAND, &config);
339 if (config & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) {
Bjorn Helgaas0c0e0732016-03-01 11:38:46 -0600340 res = &pdev->resource[PCI_ROM_RESOURCE];
341
342 pci_disable_rom(pdev);
343 if (res->parent)
344 release_resource(res);
345
346 res->start = 0xC0000;
347 res->end = res->start + 0x20000 - 1;
348 res->flags = IORESOURCE_MEM | IORESOURCE_ROM_SHADOW |
349 IORESOURCE_PCI_FIXED;
350 dev_info(&pdev->dev, "Video device with shadowed ROM at %pR\n",
351 res);
Sander Eikelenboomd8801e42014-01-31 10:28:23 +0100352 }
Eiichiro Oiwa6b5c76b2006-10-23 15:14:07 +0900353 }
354}
Yinghai Lu73e3b592012-02-23 23:46:52 -0800355DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
356 PCI_CLASS_DISPLAY_VGA, 8, pci_fixup_video);
Eiichiro Oiwa6b5c76b2006-10-23 15:14:07 +0900357
Johannes Goecke346ca042007-09-10 10:46:52 +0200358
Greg Kroah-Hartmana18e3692012-12-21 14:02:53 -0800359static const struct dmi_system_id msi_k8t_dmi_table[] = {
Johannes Goecke346ca042007-09-10 10:46:52 +0200360 {
361 .ident = "MSI-K8T-Neo2Fir",
362 .matches = {
363 DMI_MATCH(DMI_SYS_VENDOR, "MSI"),
364 DMI_MATCH(DMI_PRODUCT_NAME, "MS-6702E"),
365 },
366 },
367 {}
368};
369
370/*
371 * The AMD-Athlon64 board MSI "K8T Neo2-FIR" disables the onboard sound
372 * card if a PCI-soundcard is added.
373 *
374 * The BIOS only gives options "DISABLED" and "AUTO". This code sets
375 * the corresponding register-value to enable the soundcard.
376 *
377 * The soundcard is only enabled, if the mainborad is identified
378 * via DMI-tables and the soundcard is detected to be off.
379 */
Greg Kroah-Hartmana18e3692012-12-21 14:02:53 -0800380static void pci_fixup_msi_k8t_onboard_sound(struct pci_dev *dev)
Johannes Goecke346ca042007-09-10 10:46:52 +0200381{
382 unsigned char val;
383 if (!dmi_check_system(msi_k8t_dmi_table))
384 return; /* only applies to MSI K8T Neo2-FIR */
385
386 pci_read_config_byte(dev, 0x50, &val);
387 if (val & 0x40) {
388 pci_write_config_byte(dev, 0x50, val & (~0x40));
389
390 /* verify the change for status output */
391 pci_read_config_byte(dev, 0x50, &val);
392 if (val & 0x40)
bjorn.helgaas@hp.com9ed88552007-12-17 14:09:40 -0700393 dev_info(&dev->dev, "Detected MSI K8T Neo2-FIR; "
Johannes Goecke346ca042007-09-10 10:46:52 +0200394 "can't enable onboard soundcard!\n");
395 else
bjorn.helgaas@hp.com9ed88552007-12-17 14:09:40 -0700396 dev_info(&dev->dev, "Detected MSI K8T Neo2-FIR; "
397 "enabled onboard soundcard\n");
Johannes Goecke346ca042007-09-10 10:46:52 +0200398 }
399}
400DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237,
401 pci_fixup_msi_k8t_onboard_sound);
402DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237,
403 pci_fixup_msi_k8t_onboard_sound);
404
Eiichiro Oiwa6b5c76b2006-10-23 15:14:07 +0900405/*
Jesse Barnesf8977d02005-10-25 10:28:42 -0700406 * Some Toshiba laptops need extra code to enable their TI TSB43AB22/A.
407 *
408 * We pretend to bring them out of full D3 state, and restore the proper
409 * IRQ, PCI cache line size, and BARs, otherwise the device won't function
410 * properly. In some cases, the device will generate an interrupt on
Matt LaPlante4b3f6862006-10-03 22:21:02 +0200411 * the wrong IRQ line, causing any devices sharing the line it's
Jesse Barnesf8977d02005-10-25 10:28:42 -0700412 * *supposed* to use to be disabled by the kernel's IRQ debug code.
413 */
414static u16 toshiba_line_size;
415
Greg Kroah-Hartmana18e3692012-12-21 14:02:53 -0800416static const struct dmi_system_id toshiba_ohci1394_dmi_table[] = {
Jesse Barnesf8977d02005-10-25 10:28:42 -0700417 {
418 .ident = "Toshiba PS5 based laptop",
419 .matches = {
420 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
421 DMI_MATCH(DMI_PRODUCT_VERSION, "PS5"),
422 },
423 },
424 {
425 .ident = "Toshiba PSM4 based laptop",
426 .matches = {
427 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
428 DMI_MATCH(DMI_PRODUCT_VERSION, "PSM4"),
429 },
430 },
Jesse Barnes19272682005-12-17 09:27:50 -0800431 {
432 .ident = "Toshiba A40 based laptop",
433 .matches = {
434 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
435 DMI_MATCH(DMI_PRODUCT_VERSION, "PSA40U"),
436 },
437 },
Jesse Barnesf8977d02005-10-25 10:28:42 -0700438 { }
439};
440
Greg Kroah-Hartmana18e3692012-12-21 14:02:53 -0800441static void pci_pre_fixup_toshiba_ohci1394(struct pci_dev *dev)
Jesse Barnesf8977d02005-10-25 10:28:42 -0700442{
443 if (!dmi_check_system(toshiba_ohci1394_dmi_table))
444 return; /* only applies to certain Toshibas (so far) */
445
446 dev->current_state = PCI_D3cold;
447 pci_read_config_word(dev, PCI_CACHE_LINE_SIZE, &toshiba_line_size);
448}
449DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TI, 0x8032,
450 pci_pre_fixup_toshiba_ohci1394);
451
Greg Kroah-Hartmana18e3692012-12-21 14:02:53 -0800452static void pci_post_fixup_toshiba_ohci1394(struct pci_dev *dev)
Jesse Barnesf8977d02005-10-25 10:28:42 -0700453{
454 if (!dmi_check_system(toshiba_ohci1394_dmi_table))
455 return; /* only applies to certain Toshibas (so far) */
456
457 /* Restore config space on Toshiba laptops */
Jesse Barnesf8977d02005-10-25 10:28:42 -0700458 pci_write_config_word(dev, PCI_CACHE_LINE_SIZE, toshiba_line_size);
Jesse Barnes6e6ece52005-11-08 20:13:02 -0800459 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, (u8 *)&dev->irq);
Jesse Barnesf8977d02005-10-25 10:28:42 -0700460 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0,
461 pci_resource_start(dev, 0));
462 pci_write_config_dword(dev, PCI_BASE_ADDRESS_1,
463 pci_resource_start(dev, 1));
464}
465DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_TI, 0x8032,
466 pci_post_fixup_toshiba_ohci1394);
David Vrabela80da732006-01-14 13:21:23 -0800467
468
469/*
470 * Prevent the BIOS trapping accesses to the Cyrix CS5530A video device
471 * configuration space.
472 */
Alan Cox1597cac2006-12-04 15:14:45 -0800473static void pci_early_fixup_cyrix_5530(struct pci_dev *dev)
David Vrabela80da732006-01-14 13:21:23 -0800474{
475 u8 r;
476 /* clear 'F4 Video Configuration Trap' bit */
477 pci_read_config_byte(dev, 0x42, &r);
478 r &= 0xfd;
479 pci_write_config_byte(dev, 0x42, r);
480}
481DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5530_LEGACY,
482 pci_early_fixup_cyrix_5530);
Alan Cox1597cac2006-12-04 15:14:45 -0800483DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5530_LEGACY,
484 pci_early_fixup_cyrix_5530);
Ivan Kokshaysky73a74ed2007-05-23 14:50:02 -0700485
486/*
487 * Siemens Nixdorf AG FSC Multiprocessor Interrupt Controller:
488 * prevent update of the BAR0, which doesn't look like a normal BAR.
489 */
Greg Kroah-Hartmana18e3692012-12-21 14:02:53 -0800490static void pci_siemens_interrupt_controller(struct pci_dev *dev)
Ivan Kokshaysky73a74ed2007-05-23 14:50:02 -0700491{
492 dev->resource[0].flags |= IORESOURCE_PCI_FIXED;
493}
494DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SIEMENS, 0x0015,
495 pci_siemens_interrupt_controller);
Yinghai Lu57741a72008-02-15 01:32:50 -0800496
497/*
Jordan Croused7451fc2008-09-12 11:45:22 -0600498 * SB600: Disable BAR1 on device 14.0 to avoid HPET resources from
499 * confusing the PCI engine:
500 */
501static void sb600_disable_hpet_bar(struct pci_dev *dev)
502{
503 u8 val;
504
505 /*
506 * The SB600 and SB700 both share the same device
507 * ID, but the PM register 0x55 does something different
508 * for the SB700, so make sure we are dealing with the
509 * SB600 before touching the bit:
510 */
511
512 pci_read_config_byte(dev, 0x08, &val);
513
514 if (val < 0x2F) {
515 outb(0x55, 0xCD6);
516 val = inb(0xCD7);
517
518 /* Set bit 7 in PM register 0x55 */
519 outb(0x55, 0xCD6);
520 outb(val | 0x80, 0xCD7);
521 }
522}
523DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATI, 0x4385, sb600_disable_hpet_bar);
Alan Cox80b3e552012-05-15 18:44:15 +0100524
Bjorn Helgaas44c8bdb2014-04-14 15:35:21 -0600525#ifdef CONFIG_HPET_TIMER
526static void sb600_hpet_quirk(struct pci_dev *dev)
527{
528 struct resource *r = &dev->resource[1];
529
530 if (r->flags & IORESOURCE_MEM && r->start == hpet_address) {
531 r->flags |= IORESOURCE_PCI_FIXED;
532 dev_info(&dev->dev, "reg 0x14 contains HPET; making it immovable\n");
533 }
534}
535DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, 0x4385, sb600_hpet_quirk);
536#endif
537
Alan Cox80b3e552012-05-15 18:44:15 +0100538/*
539 * Twinhead H12Y needs us to block out a region otherwise we map devices
540 * there and any access kills the box.
541 *
542 * See: https://bugzilla.kernel.org/show_bug.cgi?id=10231
543 *
544 * Match off the LPC and svid/sdid (older kernels lose the bridge subvendor)
545 */
Greg Kroah-Hartmana18e3692012-12-21 14:02:53 -0800546static void twinhead_reserve_killing_zone(struct pci_dev *dev)
Alan Cox80b3e552012-05-15 18:44:15 +0100547{
548 if (dev->subsystem_vendor == 0x14FF && dev->subsystem_device == 0xA003) {
549 pr_info("Reserving memory on Twinhead H12Y\n");
550 request_mem_region(0xFFB00000, 0x100000, "twinhead");
551 }
552}
553DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x27B9, twinhead_reserve_killing_zone);
Bjorn Helgaasb8941572016-02-26 09:15:11 -0600554
Prarit Bhargavada77b672016-05-11 12:27:15 -0400555/*
Bjorn Helgaas6af7e4f2016-09-01 08:52:29 -0500556 * Device [8086:2fc0]
557 * Erratum HSE43
558 * CONFIG_TDP_NOMINAL CSR Implemented at Incorrect Offset
559 * http://www.intel.com/content/www/us/en/processors/xeon/xeon-e5-v3-spec-update.html
Prarit Bhargavada77b672016-05-11 12:27:15 -0400560 *
Bjorn Helgaas6af7e4f2016-09-01 08:52:29 -0500561 * Devices [8086:6f60,6fa0,6fc0]
562 * Erratum BDF2
563 * PCI BARs in the Home Agent Will Return Non-Zero Values During Enumeration
564 * http://www.intel.com/content/www/us/en/processors/xeon/xeon-e5-v4-spec-update.html
Prarit Bhargavada77b672016-05-11 12:27:15 -0400565 */
Bjorn Helgaas6af7e4f2016-09-01 08:52:29 -0500566static void pci_invalid_bar(struct pci_dev *dev)
Bjorn Helgaasb8941572016-02-26 09:15:11 -0600567{
568 dev->non_compliant_bars = 1;
569}
Bjorn Helgaas6af7e4f2016-09-01 08:52:29 -0500570DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x2fc0, pci_invalid_bar);
571DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x6f60, pci_invalid_bar);
572DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x6fa0, pci_invalid_bar);
573DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x6fc0, pci_invalid_bar);
Bjorn Helgaas13b2f9f2016-08-19 16:30:25 +0800574
575/*
576 * Apple MacBook Pro: Avoid [mem 0x7fa00000-0x7fbfffff]
577 *
578 * Using the [mem 0x7fa00000-0x7fbfffff] region, e.g., by assigning it to
579 * the 00:1c.0 Root Port, causes a conflict with [io 0x1804], which is used
580 * for soft poweroff and suspend-to-RAM.
581 *
582 * As far as we know, this is related to the address space, not to the Root
583 * Port itself. Attaching the quirk to the Root Port is a convenience, but
584 * it could probably also be a standalone DMI quirk.
585 *
586 * https://bugzilla.kernel.org/show_bug.cgi?id=103211
587 */
588static void quirk_apple_mbp_poweroff(struct pci_dev *pdev)
589{
590 struct device *dev = &pdev->dev;
591 struct resource *res;
592
593 if ((!dmi_match(DMI_PRODUCT_NAME, "MacBookPro11,4") &&
594 !dmi_match(DMI_PRODUCT_NAME, "MacBookPro11,5")) ||
595 pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x1c, 0))
596 return;
597
598 res = request_mem_region(0x7fa00000, 0x200000,
599 "MacBook Pro poweroff workaround");
600 if (res)
601 dev_info(dev, "claimed %s %pR\n", res->name, res);
602 else
603 dev_info(dev, "can't work around MacBook Pro poweroff issue\n");
604}
605DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8c10, quirk_apple_mbp_poweroff);