blob: 3ee1db1407b054bad37ae3c9f86d050614f05892 [file] [log] [blame]
Jani Nikula4e646492013-08-27 15:12:20 +03001/*
2 * Copyright © 2013 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Author: Jani Nikula <jani.nikula@intel.com>
24 */
25
26#include <drm/drmP.h>
27#include <drm/drm_crtc.h>
28#include <drm/drm_edid.h>
29#include <drm/i915_drm.h>
30#include <linux/slab.h>
31#include "i915_drv.h"
32#include "intel_drv.h"
33#include "intel_dsi.h"
34#include "intel_dsi_cmd.h"
35
36/* the sub-encoders aka panel drivers */
37static const struct intel_dsi_device intel_dsi_devices[] = {
38};
39
Shobhit Kumare9fe51c2013-12-10 12:14:55 +053040static void band_gap_reset(struct drm_i915_private *dev_priv)
Shobhit Kumar4ce8c9a2013-08-27 15:12:24 +030041{
42 mutex_lock(&dev_priv->dpio_lock);
43
Shobhit Kumare9fe51c2013-12-10 12:14:55 +053044 vlv_flisdsi_write(dev_priv, 0x08, 0x0001);
45 vlv_flisdsi_write(dev_priv, 0x0F, 0x0005);
46 vlv_flisdsi_write(dev_priv, 0x0F, 0x0025);
47 udelay(150);
48 vlv_flisdsi_write(dev_priv, 0x0F, 0x0000);
49 vlv_flisdsi_write(dev_priv, 0x08, 0x0000);
Shobhit Kumar4ce8c9a2013-08-27 15:12:24 +030050
51 mutex_unlock(&dev_priv->dpio_lock);
Shobhit Kumar4ce8c9a2013-08-27 15:12:24 +030052}
53
Jani Nikula4e646492013-08-27 15:12:20 +030054static struct intel_dsi *intel_attached_dsi(struct drm_connector *connector)
55{
56 return container_of(intel_attached_encoder(connector),
57 struct intel_dsi, base);
58}
59
60static inline bool is_vid_mode(struct intel_dsi *intel_dsi)
61{
62 return intel_dsi->dev.type == INTEL_DSI_VIDEO_MODE;
63}
64
65static inline bool is_cmd_mode(struct intel_dsi *intel_dsi)
66{
67 return intel_dsi->dev.type == INTEL_DSI_COMMAND_MODE;
68}
69
70static void intel_dsi_hot_plug(struct intel_encoder *encoder)
71{
72 DRM_DEBUG_KMS("\n");
73}
74
75static bool intel_dsi_compute_config(struct intel_encoder *encoder,
76 struct intel_crtc_config *config)
77{
78 struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi,
79 base);
80 struct intel_connector *intel_connector = intel_dsi->attached_connector;
81 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
82 struct drm_display_mode *adjusted_mode = &config->adjusted_mode;
83 struct drm_display_mode *mode = &config->requested_mode;
84
85 DRM_DEBUG_KMS("\n");
86
87 if (fixed_mode)
88 intel_fixed_panel_mode(fixed_mode, adjusted_mode);
89
90 if (intel_dsi->dev.dev_ops->mode_fixup)
91 return intel_dsi->dev.dev_ops->mode_fixup(&intel_dsi->dev,
92 mode, adjusted_mode);
93
94 return true;
95}
96
97static void intel_dsi_pre_pll_enable(struct intel_encoder *encoder)
98{
99 DRM_DEBUG_KMS("\n");
ymohanmabe4fc042013-08-27 23:40:56 +0300100
101 vlv_enable_dsi_pll(encoder);
Jani Nikula4e646492013-08-27 15:12:20 +0300102}
103
Shobhit Kumar1dbd7cb2013-12-11 17:52:05 +0530104static void intel_dsi_device_ready(struct intel_encoder *encoder)
105{
106 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
107 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
108 int pipe = intel_crtc->pipe;
109 u32 val;
110
111 DRM_DEBUG_KMS("\n");
112
113 val = I915_READ(MIPI_PORT_CTRL(pipe));
114 I915_WRITE(MIPI_PORT_CTRL(pipe), val | LP_OUTPUT_HOLD);
115 usleep_range(1000, 1500);
116 I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY | ULPS_STATE_EXIT);
117 usleep_range(2000, 2500);
118 I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY);
119 usleep_range(2000, 2500);
120 I915_WRITE(MIPI_DEVICE_READY(pipe), 0x00);
121 usleep_range(2000, 2500);
122 I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY);
123 usleep_range(2000, 2500);
124}
Jani Nikula4e646492013-08-27 15:12:20 +0300125static void intel_dsi_pre_enable(struct intel_encoder *encoder)
126{
Shobhit Kumar1dbd7cb2013-12-11 17:52:05 +0530127 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
128
Jani Nikula4e646492013-08-27 15:12:20 +0300129 DRM_DEBUG_KMS("\n");
Shobhit Kumar1dbd7cb2013-12-11 17:52:05 +0530130
131 if (intel_dsi->dev.dev_ops->panel_reset)
132 intel_dsi->dev.dev_ops->panel_reset(&intel_dsi->dev);
133
134 /* put device in ready state */
135 intel_dsi_device_ready(encoder);
136
137 if (intel_dsi->dev.dev_ops->send_otp_cmds)
138 intel_dsi->dev.dev_ops->send_otp_cmds(&intel_dsi->dev);
Jani Nikula4e646492013-08-27 15:12:20 +0300139}
140
141static void intel_dsi_enable(struct intel_encoder *encoder)
142{
Shobhit Kumar1dbd7cb2013-12-11 17:52:05 +0530143 struct drm_device *dev = encoder->base.dev;
144 struct drm_i915_private *dev_priv = dev->dev_private;
Jani Nikula4e646492013-08-27 15:12:20 +0300145 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
146 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
147 int pipe = intel_crtc->pipe;
148 u32 temp;
149
150 DRM_DEBUG_KMS("\n");
151
Jani Nikula4e646492013-08-27 15:12:20 +0300152 if (is_cmd_mode(intel_dsi))
153 I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(pipe), 8 * 4);
Shobhit Kumar1dbd7cb2013-12-11 17:52:05 +0530154 else {
Jani Nikula4e646492013-08-27 15:12:20 +0300155 msleep(20); /* XXX */
156 dpi_send_cmd(intel_dsi, TURN_ON);
157 msleep(100);
158
159 /* assert ip_tg_enable signal */
Shobhit Kumarf6da2842013-12-10 12:15:00 +0530160 temp = I915_READ(MIPI_PORT_CTRL(pipe)) & ~LANE_CONFIGURATION_MASK;
161 temp = temp | intel_dsi->port_bits;
Jani Nikula4e646492013-08-27 15:12:20 +0300162 I915_WRITE(MIPI_PORT_CTRL(pipe), temp | DPI_ENABLE);
163 POSTING_READ(MIPI_PORT_CTRL(pipe));
164 }
165
Shobhit Kumarb9f5e072013-12-10 12:14:54 +0530166 if (intel_dsi->dev.dev_ops->enable)
167 intel_dsi->dev.dev_ops->enable(&intel_dsi->dev);
Jani Nikula4e646492013-08-27 15:12:20 +0300168}
169
170static void intel_dsi_disable(struct intel_encoder *encoder)
171{
Shobhit Kumar1dbd7cb2013-12-11 17:52:05 +0530172 struct drm_device *dev = encoder->base.dev;
173 struct drm_i915_private *dev_priv = dev->dev_private;
Jani Nikula4e646492013-08-27 15:12:20 +0300174 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
175 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
176 int pipe = intel_crtc->pipe;
177 u32 temp;
178
179 DRM_DEBUG_KMS("\n");
180
Jani Nikula4e646492013-08-27 15:12:20 +0300181 if (is_vid_mode(intel_dsi)) {
182 dpi_send_cmd(intel_dsi, SHUTDOWN);
183 msleep(10);
184
185 /* de-assert ip_tg_enable signal */
186 temp = I915_READ(MIPI_PORT_CTRL(pipe));
187 I915_WRITE(MIPI_PORT_CTRL(pipe), temp & ~DPI_ENABLE);
188 POSTING_READ(MIPI_PORT_CTRL(pipe));
189
190 msleep(2);
191 }
192
Shobhit Kumar1dbd7cb2013-12-11 17:52:05 +0530193 /* if disable packets are sent before sending shutdown packet then in
194 * some next enable sequence send turn on packet error is observed */
195 if (intel_dsi->dev.dev_ops->disable)
196 intel_dsi->dev.dev_ops->disable(&intel_dsi->dev);
Jani Nikula4e646492013-08-27 15:12:20 +0300197}
198
Shobhit Kumar1dbd7cb2013-12-11 17:52:05 +0530199static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
Jani Nikula4e646492013-08-27 15:12:20 +0300200{
Shobhit Kumar1dbd7cb2013-12-11 17:52:05 +0530201 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
202 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
203 int pipe = intel_crtc->pipe;
204 u32 val;
205
Jani Nikula4e646492013-08-27 15:12:20 +0300206 DRM_DEBUG_KMS("\n");
ymohanmabe4fc042013-08-27 23:40:56 +0300207
Shobhit Kumar1dbd7cb2013-12-11 17:52:05 +0530208 I915_WRITE(MIPI_DEVICE_READY(pipe), ULPS_STATE_ENTER);
209 usleep_range(2000, 2500);
210
211 I915_WRITE(MIPI_DEVICE_READY(pipe), ULPS_STATE_EXIT);
212 usleep_range(2000, 2500);
213
214 I915_WRITE(MIPI_DEVICE_READY(pipe), ULPS_STATE_ENTER);
215 usleep_range(2000, 2500);
216
217 val = I915_READ(MIPI_PORT_CTRL(pipe));
218 I915_WRITE(MIPI_PORT_CTRL(pipe), val & ~LP_OUTPUT_HOLD);
219 usleep_range(1000, 1500);
220
221 if (wait_for(((I915_READ(MIPI_PORT_CTRL(pipe)) & AFE_LATCHOUT)
222 == 0x00000), 30))
223 DRM_ERROR("DSI LP not going Low\n");
224
225 I915_WRITE(MIPI_DEVICE_READY(pipe), 0x00);
226 usleep_range(2000, 2500);
227
ymohanmabe4fc042013-08-27 23:40:56 +0300228 vlv_disable_dsi_pll(encoder);
Jani Nikula4e646492013-08-27 15:12:20 +0300229}
Shobhit Kumar1dbd7cb2013-12-11 17:52:05 +0530230static void intel_dsi_post_disable(struct intel_encoder *encoder)
231{
232 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
233
234 DRM_DEBUG_KMS("\n");
235
236 intel_dsi_clear_device_ready(encoder);
237
238 if (intel_dsi->dev.dev_ops->disable_panel_power)
239 intel_dsi->dev.dev_ops->disable_panel_power(&intel_dsi->dev);
240}
Jani Nikula4e646492013-08-27 15:12:20 +0300241
242static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
243 enum pipe *pipe)
244{
245 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
246 u32 port, func;
247 enum pipe p;
248
249 DRM_DEBUG_KMS("\n");
250
251 /* XXX: this only works for one DSI output */
252 for (p = PIPE_A; p <= PIPE_B; p++) {
253 port = I915_READ(MIPI_PORT_CTRL(p));
254 func = I915_READ(MIPI_DSI_FUNC_PRG(p));
255
256 if ((port & DPI_ENABLE) || (func & CMD_MODE_DATA_WIDTH_MASK)) {
257 if (I915_READ(MIPI_DEVICE_READY(p)) & DEVICE_READY) {
258 *pipe = p;
259 return true;
260 }
261 }
262 }
263
264 return false;
265}
266
267static void intel_dsi_get_config(struct intel_encoder *encoder,
268 struct intel_crtc_config *pipe_config)
269{
270 DRM_DEBUG_KMS("\n");
271
272 /* XXX: read flags, set to adjusted_mode */
273}
274
Damien Lespiauc19de8e2013-11-28 15:29:18 +0000275static enum drm_mode_status
276intel_dsi_mode_valid(struct drm_connector *connector,
277 struct drm_display_mode *mode)
Jani Nikula4e646492013-08-27 15:12:20 +0300278{
279 struct intel_connector *intel_connector = to_intel_connector(connector);
280 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
281 struct intel_dsi *intel_dsi = intel_attached_dsi(connector);
282
283 DRM_DEBUG_KMS("\n");
284
285 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) {
286 DRM_DEBUG_KMS("MODE_NO_DBLESCAN\n");
287 return MODE_NO_DBLESCAN;
288 }
289
290 if (fixed_mode) {
291 if (mode->hdisplay > fixed_mode->hdisplay)
292 return MODE_PANEL;
293 if (mode->vdisplay > fixed_mode->vdisplay)
294 return MODE_PANEL;
295 }
296
297 return intel_dsi->dev.dev_ops->mode_valid(&intel_dsi->dev, mode);
298}
299
300/* return txclkesc cycles in terms of divider and duration in us */
301static u16 txclkesc(u32 divider, unsigned int us)
302{
303 switch (divider) {
304 case ESCAPE_CLOCK_DIVIDER_1:
305 default:
306 return 20 * us;
307 case ESCAPE_CLOCK_DIVIDER_2:
308 return 10 * us;
309 case ESCAPE_CLOCK_DIVIDER_4:
310 return 5 * us;
311 }
312}
313
314/* return pixels in terms of txbyteclkhs */
315static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count)
316{
317 return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp, 8), lane_count);
318}
319
320static void set_dsi_timings(struct drm_encoder *encoder,
321 const struct drm_display_mode *mode)
322{
323 struct drm_device *dev = encoder->dev;
324 struct drm_i915_private *dev_priv = dev->dev_private;
325 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
326 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
327 int pipe = intel_crtc->pipe;
328 unsigned int bpp = intel_crtc->config.pipe_bpp;
329 unsigned int lane_count = intel_dsi->lane_count;
330
331 u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp;
332
333 hactive = mode->hdisplay;
334 hfp = mode->hsync_start - mode->hdisplay;
335 hsync = mode->hsync_end - mode->hsync_start;
336 hbp = mode->htotal - mode->hsync_end;
337
338 vfp = mode->vsync_start - mode->vdisplay;
339 vsync = mode->vsync_end - mode->vsync_start;
340 vbp = mode->vtotal - mode->vsync_end;
341
342 /* horizontal values are in terms of high speed byte clock */
343 hactive = txbyteclkhs(hactive, bpp, lane_count);
344 hfp = txbyteclkhs(hfp, bpp, lane_count);
345 hsync = txbyteclkhs(hsync, bpp, lane_count);
346 hbp = txbyteclkhs(hbp, bpp, lane_count);
347
348 I915_WRITE(MIPI_HACTIVE_AREA_COUNT(pipe), hactive);
349 I915_WRITE(MIPI_HFP_COUNT(pipe), hfp);
350
351 /* meaningful for video mode non-burst sync pulse mode only, can be zero
352 * for non-burst sync events and burst modes */
353 I915_WRITE(MIPI_HSYNC_PADDING_COUNT(pipe), hsync);
354 I915_WRITE(MIPI_HBP_COUNT(pipe), hbp);
355
356 /* vertical values are in terms of lines */
357 I915_WRITE(MIPI_VFP_COUNT(pipe), vfp);
358 I915_WRITE(MIPI_VSYNC_PADDING_COUNT(pipe), vsync);
359 I915_WRITE(MIPI_VBP_COUNT(pipe), vbp);
360}
361
362static void intel_dsi_mode_set(struct intel_encoder *intel_encoder)
363{
364 struct drm_encoder *encoder = &intel_encoder->base;
365 struct drm_device *dev = encoder->dev;
366 struct drm_i915_private *dev_priv = dev->dev_private;
367 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
368 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
369 struct drm_display_mode *adjusted_mode =
370 &intel_crtc->config.adjusted_mode;
371 int pipe = intel_crtc->pipe;
372 unsigned int bpp = intel_crtc->config.pipe_bpp;
373 u32 val, tmp;
374
Damien Lespiau6f2bcce2013-10-16 12:29:54 +0100375 DRM_DEBUG_KMS("pipe %c\n", pipe_name(pipe));
Jani Nikula4e646492013-08-27 15:12:20 +0300376
Shobhit Kumar4ce8c9a2013-08-27 15:12:24 +0300377 /* XXX: Location of the call */
Shobhit Kumare9fe51c2013-12-10 12:14:55 +0530378 band_gap_reset(dev_priv);
Shobhit Kumar4ce8c9a2013-08-27 15:12:24 +0300379
Jani Nikula4e646492013-08-27 15:12:20 +0300380 /* escape clock divider, 20MHz, shared for A and C. device ready must be
381 * off when doing this! txclkesc? */
382 tmp = I915_READ(MIPI_CTRL(0));
383 tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
384 I915_WRITE(MIPI_CTRL(0), tmp | ESCAPE_CLOCK_DIVIDER_1);
385
386 /* read request priority is per pipe */
387 tmp = I915_READ(MIPI_CTRL(pipe));
388 tmp &= ~READ_REQUEST_PRIORITY_MASK;
389 I915_WRITE(MIPI_CTRL(pipe), tmp | READ_REQUEST_PRIORITY_HIGH);
390
391 /* XXX: why here, why like this? handling in irq handler?! */
392 I915_WRITE(MIPI_INTR_STAT(pipe), 0xffffffff);
393 I915_WRITE(MIPI_INTR_EN(pipe), 0xffffffff);
394
Shobhit Kumarf6da2842013-12-10 12:15:00 +0530395 I915_WRITE(MIPI_DPHY_PARAM(pipe), intel_dsi->dphy_reg);
Jani Nikula4e646492013-08-27 15:12:20 +0300396
397 I915_WRITE(MIPI_DPI_RESOLUTION(pipe),
398 adjusted_mode->vdisplay << VERTICAL_ADDRESS_SHIFT |
399 adjusted_mode->hdisplay << HORIZONTAL_ADDRESS_SHIFT);
400
401 set_dsi_timings(encoder, adjusted_mode);
402
403 val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT;
404 if (is_cmd_mode(intel_dsi)) {
405 val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT;
406 val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */
407 } else {
408 val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT;
409
410 /* XXX: cross-check bpp vs. pixel format? */
411 val |= intel_dsi->pixel_format;
412 }
413 I915_WRITE(MIPI_DSI_FUNC_PRG(pipe), val);
414
415 /* timeouts for recovery. one frame IIUC. if counter expires, EOT and
416 * stop state. */
417
418 /*
419 * In burst mode, value greater than one DPI line Time in byte clock
420 * (txbyteclkhs) To timeout this timer 1+ of the above said value is
421 * recommended.
422 *
423 * In non-burst mode, Value greater than one DPI frame time in byte
424 * clock(txbyteclkhs) To timeout this timer 1+ of the above said value
425 * is recommended.
426 *
427 * In DBI only mode, value greater than one DBI frame time in byte
428 * clock(txbyteclkhs) To timeout this timer 1+ of the above said value
429 * is recommended.
430 */
431
432 if (is_vid_mode(intel_dsi) &&
433 intel_dsi->video_mode_format == VIDEO_MODE_BURST) {
434 I915_WRITE(MIPI_HS_TX_TIMEOUT(pipe),
435 txbyteclkhs(adjusted_mode->htotal, bpp,
436 intel_dsi->lane_count) + 1);
437 } else {
438 I915_WRITE(MIPI_HS_TX_TIMEOUT(pipe),
439 txbyteclkhs(adjusted_mode->vtotal *
440 adjusted_mode->htotal,
441 bpp, intel_dsi->lane_count) + 1);
442 }
Shobhit Kumarf6da2842013-12-10 12:15:00 +0530443 I915_WRITE(MIPI_LP_RX_TIMEOUT(pipe), intel_dsi->lp_rx_timeout);
444 I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(pipe), intel_dsi->turn_arnd_val);
445 I915_WRITE(MIPI_DEVICE_RESET_TIMER(pipe), intel_dsi->rst_timer_val);
Jani Nikula4e646492013-08-27 15:12:20 +0300446
447 /* dphy stuff */
448
449 /* in terms of low power clock */
450 I915_WRITE(MIPI_INIT_COUNT(pipe), txclkesc(ESCAPE_CLOCK_DIVIDER_1, 100));
451
452 /* recovery disables */
453 I915_WRITE(MIPI_EOT_DISABLE(pipe), intel_dsi->eot_disable);
454
455 /* in terms of txbyteclkhs. actual high to low switch +
456 * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK.
457 *
458 * XXX: write MIPI_STOP_STATE_STALL?
459 */
Shobhit Kumarf6da2842013-12-10 12:15:00 +0530460 I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(pipe),
461 intel_dsi->hs_to_lp_count);
Jani Nikula4e646492013-08-27 15:12:20 +0300462
463 /* XXX: low power clock equivalence in terms of byte clock. the number
464 * of byte clocks occupied in one low power clock. based on txbyteclkhs
465 * and txclkesc. txclkesc time / txbyteclk time * (105 +
466 * MIPI_STOP_STATE_STALL) / 105.???
467 */
Shobhit Kumarf6da2842013-12-10 12:15:00 +0530468 I915_WRITE(MIPI_LP_BYTECLK(pipe), intel_dsi->lp_byte_clk);
Jani Nikula4e646492013-08-27 15:12:20 +0300469
470 /* the bw essential for transmitting 16 long packets containing 252
471 * bytes meant for dcs write memory command is programmed in this
472 * register in terms of byte clocks. based on dsi transfer rate and the
473 * number of lanes configured the time taken to transmit 16 long packets
474 * in a dsi stream varies. */
Shobhit Kumarf6da2842013-12-10 12:15:00 +0530475 I915_WRITE(MIPI_DBI_BW_CTRL(pipe), intel_dsi->bw_timer);
Jani Nikula4e646492013-08-27 15:12:20 +0300476
477 I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(pipe),
Shobhit Kumarf6da2842013-12-10 12:15:00 +0530478 intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT |
479 intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT);
Jani Nikula4e646492013-08-27 15:12:20 +0300480
481 if (is_vid_mode(intel_dsi))
482 I915_WRITE(MIPI_VIDEO_MODE_FORMAT(pipe),
Shobhit Kumarf6da2842013-12-10 12:15:00 +0530483 intel_dsi->video_frmt_cfg_bits |
484 intel_dsi->video_mode_format);
Jani Nikula4e646492013-08-27 15:12:20 +0300485}
486
487static enum drm_connector_status
488intel_dsi_detect(struct drm_connector *connector, bool force)
489{
490 struct intel_dsi *intel_dsi = intel_attached_dsi(connector);
491 DRM_DEBUG_KMS("\n");
492 return intel_dsi->dev.dev_ops->detect(&intel_dsi->dev);
493}
494
495static int intel_dsi_get_modes(struct drm_connector *connector)
496{
497 struct intel_connector *intel_connector = to_intel_connector(connector);
498 struct drm_display_mode *mode;
499
500 DRM_DEBUG_KMS("\n");
501
502 if (!intel_connector->panel.fixed_mode) {
503 DRM_DEBUG_KMS("no fixed mode\n");
504 return 0;
505 }
506
507 mode = drm_mode_duplicate(connector->dev,
508 intel_connector->panel.fixed_mode);
509 if (!mode) {
510 DRM_DEBUG_KMS("drm_mode_duplicate failed\n");
511 return 0;
512 }
513
514 drm_mode_probed_add(connector, mode);
515 return 1;
516}
517
518static void intel_dsi_destroy(struct drm_connector *connector)
519{
520 struct intel_connector *intel_connector = to_intel_connector(connector);
521
522 DRM_DEBUG_KMS("\n");
523 intel_panel_fini(&intel_connector->panel);
Jani Nikula4e646492013-08-27 15:12:20 +0300524 drm_connector_cleanup(connector);
525 kfree(connector);
526}
527
528static const struct drm_encoder_funcs intel_dsi_funcs = {
529 .destroy = intel_encoder_destroy,
530};
531
532static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = {
533 .get_modes = intel_dsi_get_modes,
534 .mode_valid = intel_dsi_mode_valid,
535 .best_encoder = intel_best_encoder,
536};
537
538static const struct drm_connector_funcs intel_dsi_connector_funcs = {
539 .dpms = intel_connector_dpms,
540 .detect = intel_dsi_detect,
541 .destroy = intel_dsi_destroy,
542 .fill_modes = drm_helper_probe_single_connector_modes,
543};
544
545bool intel_dsi_init(struct drm_device *dev)
546{
547 struct intel_dsi *intel_dsi;
548 struct intel_encoder *intel_encoder;
549 struct drm_encoder *encoder;
550 struct intel_connector *intel_connector;
551 struct drm_connector *connector;
552 struct drm_display_mode *fixed_mode = NULL;
553 const struct intel_dsi_device *dsi;
554 unsigned int i;
555
556 DRM_DEBUG_KMS("\n");
557
558 intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL);
559 if (!intel_dsi)
560 return false;
561
562 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
563 if (!intel_connector) {
564 kfree(intel_dsi);
565 return false;
566 }
567
568 intel_encoder = &intel_dsi->base;
569 encoder = &intel_encoder->base;
570 intel_dsi->attached_connector = intel_connector;
571
572 connector = &intel_connector->base;
573
574 drm_encoder_init(dev, encoder, &intel_dsi_funcs, DRM_MODE_ENCODER_DSI);
575
576 /* XXX: very likely not all of these are needed */
577 intel_encoder->hot_plug = intel_dsi_hot_plug;
578 intel_encoder->compute_config = intel_dsi_compute_config;
579 intel_encoder->pre_pll_enable = intel_dsi_pre_pll_enable;
580 intel_encoder->pre_enable = intel_dsi_pre_enable;
581 intel_encoder->enable = intel_dsi_enable;
582 intel_encoder->mode_set = intel_dsi_mode_set;
583 intel_encoder->disable = intel_dsi_disable;
584 intel_encoder->post_disable = intel_dsi_post_disable;
585 intel_encoder->get_hw_state = intel_dsi_get_hw_state;
586 intel_encoder->get_config = intel_dsi_get_config;
587
588 intel_connector->get_hw_state = intel_connector_get_hw_state;
Imre Deak4932e2c2014-02-11 17:12:48 +0200589 intel_connector->unregister = intel_connector_unregister;
Jani Nikula4e646492013-08-27 15:12:20 +0300590
591 for (i = 0; i < ARRAY_SIZE(intel_dsi_devices); i++) {
592 dsi = &intel_dsi_devices[i];
593 intel_dsi->dev = *dsi;
594
595 if (dsi->dev_ops->init(&intel_dsi->dev))
596 break;
597 }
598
599 if (i == ARRAY_SIZE(intel_dsi_devices)) {
600 DRM_DEBUG_KMS("no device found\n");
601 goto err;
602 }
603
604 intel_encoder->type = INTEL_OUTPUT_DSI;
605 intel_encoder->crtc_mask = (1 << 0); /* XXX */
606
607 intel_encoder->cloneable = false;
608 drm_connector_init(dev, connector, &intel_dsi_connector_funcs,
609 DRM_MODE_CONNECTOR_DSI);
610
611 drm_connector_helper_add(connector, &intel_dsi_connector_helper_funcs);
612
613 connector->display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/
614 connector->interlace_allowed = false;
615 connector->doublescan_allowed = false;
616
617 intel_connector_attach_encoder(intel_connector, intel_encoder);
618
619 drm_sysfs_connector_add(connector);
620
621 fixed_mode = dsi->dev_ops->get_modes(&intel_dsi->dev);
622 if (!fixed_mode) {
623 DRM_DEBUG_KMS("no fixed mode\n");
624 goto err;
625 }
626
627 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
Vandana Kannan4b6ed682014-02-11 14:26:36 +0530628 intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
Jani Nikula4e646492013-08-27 15:12:20 +0300629
630 return true;
631
632err:
633 drm_encoder_cleanup(&intel_encoder->base);
634 kfree(intel_dsi);
635 kfree(intel_connector);
636
637 return false;
638}