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Felipe Balbi550a7372008-07-24 12:27:36 +03001/*
2 * MUSB OTG driver host support
3 *
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
Sergei Shtylyovc7bbc052009-03-26 18:26:40 -07007 * Copyright (C) 2008-2009 MontaVista Software, Inc. <source@mvista.com>
Felipe Balbi550a7372008-07-24 12:27:36 +03008 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
21 * 02110-1301 USA
22 *
23 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
26 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
29 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
30 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 *
34 */
35
36#include <linux/module.h>
37#include <linux/kernel.h>
38#include <linux/delay.h>
39#include <linux/sched.h>
40#include <linux/slab.h>
41#include <linux/errno.h>
42#include <linux/init.h>
43#include <linux/list.h>
Maulik Mankad496dda72010-09-24 13:44:06 +030044#include <linux/dma-mapping.h>
Felipe Balbi550a7372008-07-24 12:27:36 +030045
46#include "musb_core.h"
47#include "musb_host.h"
48
49
50/* MUSB HOST status 22-mar-2006
51 *
52 * - There's still lots of partial code duplication for fault paths, so
53 * they aren't handled as consistently as they need to be.
54 *
55 * - PIO mostly behaved when last tested.
56 * + including ep0, with all usbtest cases 9, 10
57 * + usbtest 14 (ep0out) doesn't seem to run at all
58 * + double buffered OUT/TX endpoints saw stalls(!) with certain usbtest
59 * configurations, but otherwise double buffering passes basic tests.
60 * + for 2.6.N, for N > ~10, needs API changes for hcd framework.
61 *
62 * - DMA (CPPI) ... partially behaves, not currently recommended
63 * + about 1/15 the speed of typical EHCI implementations (PCI)
64 * + RX, all too often reqpkt seems to misbehave after tx
65 * + TX, no known issues (other than evident silicon issue)
66 *
67 * - DMA (Mentor/OMAP) ...has at least toggle update problems
68 *
Ajay Kumar Gupta1e0320f2009-02-24 15:26:13 -080069 * - [23-feb-2009] minimal traffic scheduling to avoid bulk RX packet
70 * starvation ... nothing yet for TX, interrupt, or bulk.
Felipe Balbi550a7372008-07-24 12:27:36 +030071 *
72 * - Not tested with HNP, but some SRP paths seem to behave.
73 *
74 * NOTE 24-August-2006:
75 *
76 * - Bulk traffic finally uses both sides of hardware ep1, freeing up an
77 * extra endpoint for periodic use enabling hub + keybd + mouse. That
78 * mostly works, except that with "usbnet" it's easy to trigger cases
79 * with "ping" where RX loses. (a) ping to davinci, even "ping -f",
80 * fine; but (b) ping _from_ davinci, even "ping -c 1", ICMP RX loses
81 * although ARP RX wins. (That test was done with a full speed link.)
82 */
83
84
85/*
86 * NOTE on endpoint usage:
87 *
88 * CONTROL transfers all go through ep0. BULK ones go through dedicated IN
89 * and OUT endpoints ... hardware is dedicated for those "async" queue(s).
Felipe Balbi550a7372008-07-24 12:27:36 +030090 * (Yes, bulk _could_ use more of the endpoints than that, and would even
Ajay Kumar Gupta1e0320f2009-02-24 15:26:13 -080091 * benefit from it.)
Felipe Balbi550a7372008-07-24 12:27:36 +030092 *
93 * INTERUPPT and ISOCHRONOUS transfers are scheduled to the other endpoints.
94 * So far that scheduling is both dumb and optimistic: the endpoint will be
95 * "claimed" until its software queue is no longer refilled. No multiplexing
96 * of transfers between endpoints, or anything clever.
97 */
98
99
100static void musb_ep_program(struct musb *musb, u8 epnum,
Sergei Shtylyov6b6e9712009-03-26 18:29:19 -0700101 struct urb *urb, int is_out,
102 u8 *buf, u32 offset, u32 len);
Felipe Balbi550a7372008-07-24 12:27:36 +0300103
104/*
105 * Clear TX fifo. Needed to avoid BABBLE errors.
106 */
David Brownellc767c1c2008-09-11 11:53:23 +0300107static void musb_h_tx_flush_fifo(struct musb_hw_ep *ep)
Felipe Balbi550a7372008-07-24 12:27:36 +0300108{
109 void __iomem *epio = ep->regs;
110 u16 csr;
David Brownellbb1c9ef2008-11-24 13:06:50 +0200111 u16 lastcsr = 0;
Felipe Balbi550a7372008-07-24 12:27:36 +0300112 int retries = 1000;
113
114 csr = musb_readw(epio, MUSB_TXCSR);
115 while (csr & MUSB_TXCSR_FIFONOTEMPTY) {
David Brownellbb1c9ef2008-11-24 13:06:50 +0200116 if (csr != lastcsr)
117 DBG(3, "Host TX FIFONOTEMPTY csr: %02x\n", csr);
118 lastcsr = csr;
Felipe Balbi550a7372008-07-24 12:27:36 +0300119 csr |= MUSB_TXCSR_FLUSHFIFO;
120 musb_writew(epio, MUSB_TXCSR, csr);
121 csr = musb_readw(epio, MUSB_TXCSR);
David Brownellbb1c9ef2008-11-24 13:06:50 +0200122 if (WARN(retries-- < 1,
123 "Could not flush host TX%d fifo: csr: %04x\n",
124 ep->epnum, csr))
Felipe Balbi550a7372008-07-24 12:27:36 +0300125 return;
Felipe Balbi550a7372008-07-24 12:27:36 +0300126 mdelay(1);
127 }
128}
129
David Brownell78322c12009-03-26 17:38:30 -0700130static void musb_h_ep0_flush_fifo(struct musb_hw_ep *ep)
131{
132 void __iomem *epio = ep->regs;
133 u16 csr;
134 int retries = 5;
135
136 /* scrub any data left in the fifo */
137 do {
138 csr = musb_readw(epio, MUSB_TXCSR);
139 if (!(csr & (MUSB_CSR0_TXPKTRDY | MUSB_CSR0_RXPKTRDY)))
140 break;
141 musb_writew(epio, MUSB_TXCSR, MUSB_CSR0_FLUSHFIFO);
142 csr = musb_readw(epio, MUSB_TXCSR);
143 udelay(10);
144 } while (--retries);
145
146 WARN(!retries, "Could not flush host TX%d fifo: csr: %04x\n",
147 ep->epnum, csr);
148
149 /* and reset for the next transfer */
150 musb_writew(epio, MUSB_TXCSR, 0);
151}
152
Felipe Balbi550a7372008-07-24 12:27:36 +0300153/*
154 * Start transmit. Caller is responsible for locking shared resources.
155 * musb must be locked.
156 */
157static inline void musb_h_tx_start(struct musb_hw_ep *ep)
158{
159 u16 txcsr;
160
161 /* NOTE: no locks here; caller should lock and select EP */
162 if (ep->epnum) {
163 txcsr = musb_readw(ep->regs, MUSB_TXCSR);
164 txcsr |= MUSB_TXCSR_TXPKTRDY | MUSB_TXCSR_H_WZC_BITS;
165 musb_writew(ep->regs, MUSB_TXCSR, txcsr);
166 } else {
167 txcsr = MUSB_CSR0_H_SETUPPKT | MUSB_CSR0_TXPKTRDY;
168 musb_writew(ep->regs, MUSB_CSR0, txcsr);
169 }
170
171}
172
Sergei Shtylyovc7bbc052009-03-26 18:26:40 -0700173static inline void musb_h_tx_dma_start(struct musb_hw_ep *ep)
Felipe Balbi550a7372008-07-24 12:27:36 +0300174{
175 u16 txcsr;
176
177 /* NOTE: no locks here; caller should lock and select EP */
178 txcsr = musb_readw(ep->regs, MUSB_TXCSR);
179 txcsr |= MUSB_TXCSR_DMAENAB | MUSB_TXCSR_H_WZC_BITS;
Sergei Shtylyovc7bbc052009-03-26 18:26:40 -0700180 if (is_cppi_enabled())
181 txcsr |= MUSB_TXCSR_DMAMODE;
Felipe Balbi550a7372008-07-24 12:27:36 +0300182 musb_writew(ep->regs, MUSB_TXCSR, txcsr);
183}
184
Sergei Shtylyov3e5c6dc2009-03-27 12:55:16 -0700185static void musb_ep_set_qh(struct musb_hw_ep *ep, int is_in, struct musb_qh *qh)
186{
187 if (is_in != 0 || ep->is_shared_fifo)
188 ep->in_qh = qh;
189 if (is_in == 0 || ep->is_shared_fifo)
190 ep->out_qh = qh;
191}
192
193static struct musb_qh *musb_ep_get_qh(struct musb_hw_ep *ep, int is_in)
194{
195 return is_in ? ep->in_qh : ep->out_qh;
196}
197
Felipe Balbi550a7372008-07-24 12:27:36 +0300198/*
199 * Start the URB at the front of an endpoint's queue
200 * end must be claimed from the caller.
201 *
202 * Context: controller locked, irqs blocked
203 */
204static void
205musb_start_urb(struct musb *musb, int is_in, struct musb_qh *qh)
206{
207 u16 frame;
208 u32 len;
Felipe Balbi550a7372008-07-24 12:27:36 +0300209 void __iomem *mbase = musb->mregs;
210 struct urb *urb = next_urb(qh);
Sergei Shtylyov6b6e9712009-03-26 18:29:19 -0700211 void *buf = urb->transfer_buffer;
212 u32 offset = 0;
Felipe Balbi550a7372008-07-24 12:27:36 +0300213 struct musb_hw_ep *hw_ep = qh->hw_ep;
214 unsigned pipe = urb->pipe;
215 u8 address = usb_pipedevice(pipe);
216 int epnum = hw_ep->epnum;
217
218 /* initialize software qh state */
219 qh->offset = 0;
220 qh->segsize = 0;
221
222 /* gather right source of data */
223 switch (qh->type) {
224 case USB_ENDPOINT_XFER_CONTROL:
225 /* control transfers always start with SETUP */
226 is_in = 0;
Felipe Balbi550a7372008-07-24 12:27:36 +0300227 musb->ep0_stage = MUSB_EP0_START;
228 buf = urb->setup_packet;
229 len = 8;
230 break;
231 case USB_ENDPOINT_XFER_ISOC:
232 qh->iso_idx = 0;
233 qh->frame = 0;
Sergei Shtylyov6b6e9712009-03-26 18:29:19 -0700234 offset = urb->iso_frame_desc[0].offset;
Felipe Balbi550a7372008-07-24 12:27:36 +0300235 len = urb->iso_frame_desc[0].length;
236 break;
237 default: /* bulk, interrupt */
Ajay Kumar Gupta1e0320f2009-02-24 15:26:13 -0800238 /* actual_length may be nonzero on retry paths */
239 buf = urb->transfer_buffer + urb->actual_length;
240 len = urb->transfer_buffer_length - urb->actual_length;
Felipe Balbi550a7372008-07-24 12:27:36 +0300241 }
242
243 DBG(4, "qh %p urb %p dev%d ep%d%s%s, hw_ep %d, %p/%d\n",
244 qh, urb, address, qh->epnum,
245 is_in ? "in" : "out",
246 ({char *s; switch (qh->type) {
247 case USB_ENDPOINT_XFER_CONTROL: s = ""; break;
248 case USB_ENDPOINT_XFER_BULK: s = "-bulk"; break;
249 case USB_ENDPOINT_XFER_ISOC: s = "-iso"; break;
250 default: s = "-intr"; break;
251 }; s; }),
Sergei Shtylyov6b6e9712009-03-26 18:29:19 -0700252 epnum, buf + offset, len);
Felipe Balbi550a7372008-07-24 12:27:36 +0300253
254 /* Configure endpoint */
Sergei Shtylyov3e5c6dc2009-03-27 12:55:16 -0700255 musb_ep_set_qh(hw_ep, is_in, qh);
Sergei Shtylyov6b6e9712009-03-26 18:29:19 -0700256 musb_ep_program(musb, epnum, urb, !is_in, buf, offset, len);
Felipe Balbi550a7372008-07-24 12:27:36 +0300257
258 /* transmit may have more work: start it when it is time */
259 if (is_in)
260 return;
261
262 /* determine if the time is right for a periodic transfer */
263 switch (qh->type) {
264 case USB_ENDPOINT_XFER_ISOC:
265 case USB_ENDPOINT_XFER_INT:
266 DBG(3, "check whether there's still time for periodic Tx\n");
Felipe Balbi550a7372008-07-24 12:27:36 +0300267 frame = musb_readw(mbase, MUSB_FRAME);
268 /* FIXME this doesn't implement that scheduling policy ...
269 * or handle framecounter wrapping
270 */
271 if ((urb->transfer_flags & URB_ISO_ASAP)
272 || (frame >= urb->start_frame)) {
273 /* REVISIT the SOF irq handler shouldn't duplicate
274 * this code; and we don't init urb->start_frame...
275 */
276 qh->frame = 0;
277 goto start;
278 } else {
279 qh->frame = urb->start_frame;
280 /* enable SOF interrupt so we can count down */
281 DBG(1, "SOF for %d\n", epnum);
282#if 1 /* ifndef CONFIG_ARCH_DAVINCI */
283 musb_writeb(mbase, MUSB_INTRUSBE, 0xff);
284#endif
285 }
286 break;
287 default:
288start:
289 DBG(4, "Start TX%d %s\n", epnum,
290 hw_ep->tx_channel ? "dma" : "pio");
291
292 if (!hw_ep->tx_channel)
293 musb_h_tx_start(hw_ep);
294 else if (is_cppi_enabled() || tusb_dma_omap())
Sergei Shtylyovc7bbc052009-03-26 18:26:40 -0700295 musb_h_tx_dma_start(hw_ep);
Felipe Balbi550a7372008-07-24 12:27:36 +0300296 }
297}
298
Sergei Shtylyovc9cd06b2009-03-27 12:58:31 -0700299/* Context: caller owns controller lock, IRQs are blocked */
300static void musb_giveback(struct musb *musb, struct urb *urb, int status)
Felipe Balbi550a7372008-07-24 12:27:36 +0300301__releases(musb->lock)
302__acquires(musb->lock)
303{
David Brownellbb1c9ef2008-11-24 13:06:50 +0200304 DBG(({ int level; switch (status) {
Felipe Balbi550a7372008-07-24 12:27:36 +0300305 case 0:
306 level = 4;
307 break;
308 /* common/boring faults */
309 case -EREMOTEIO:
310 case -ESHUTDOWN:
311 case -ECONNRESET:
312 case -EPIPE:
313 level = 3;
314 break;
315 default:
316 level = 2;
317 break;
318 }; level; }),
David Brownellbb1c9ef2008-11-24 13:06:50 +0200319 "complete %p %pF (%d), dev%d ep%d%s, %d/%d\n",
320 urb, urb->complete, status,
Felipe Balbi550a7372008-07-24 12:27:36 +0300321 usb_pipedevice(urb->pipe),
322 usb_pipeendpoint(urb->pipe),
323 usb_pipein(urb->pipe) ? "in" : "out",
324 urb->actual_length, urb->transfer_buffer_length
325 );
326
Ajay Kumar Gupta2492e672008-09-11 11:53:21 +0300327 usb_hcd_unlink_urb_from_ep(musb_to_hcd(musb), urb);
Felipe Balbi550a7372008-07-24 12:27:36 +0300328 spin_unlock(&musb->lock);
329 usb_hcd_giveback_urb(musb_to_hcd(musb), urb, status);
330 spin_lock(&musb->lock);
331}
332
Sergei Shtylyov846099a2009-03-27 12:54:21 -0700333/* For bulk/interrupt endpoints only */
334static inline void musb_save_toggle(struct musb_qh *qh, int is_in,
335 struct urb *urb)
Felipe Balbi550a7372008-07-24 12:27:36 +0300336{
Sergei Shtylyov846099a2009-03-27 12:54:21 -0700337 void __iomem *epio = qh->hw_ep->regs;
Felipe Balbi550a7372008-07-24 12:27:36 +0300338 u16 csr;
Felipe Balbi550a7372008-07-24 12:27:36 +0300339
Sergei Shtylyov846099a2009-03-27 12:54:21 -0700340 /*
341 * FIXME: the current Mentor DMA code seems to have
Felipe Balbi550a7372008-07-24 12:27:36 +0300342 * problems getting toggle correct.
343 */
344
Sergei Shtylyov846099a2009-03-27 12:54:21 -0700345 if (is_in)
346 csr = musb_readw(epio, MUSB_RXCSR) & MUSB_RXCSR_H_DATATOGGLE;
Felipe Balbi550a7372008-07-24 12:27:36 +0300347 else
Sergei Shtylyov846099a2009-03-27 12:54:21 -0700348 csr = musb_readw(epio, MUSB_TXCSR) & MUSB_TXCSR_H_DATATOGGLE;
Felipe Balbi550a7372008-07-24 12:27:36 +0300349
Sergei Shtylyov846099a2009-03-27 12:54:21 -0700350 usb_settoggle(urb->dev, qh->epnum, !is_in, csr ? 1 : 0);
Felipe Balbi550a7372008-07-24 12:27:36 +0300351}
352
Sergei Shtylyovc9cd06b2009-03-27 12:58:31 -0700353/*
354 * Advance this hardware endpoint's queue, completing the specified URB and
355 * advancing to either the next URB queued to that qh, or else invalidating
356 * that qh and advancing to the next qh scheduled after the current one.
357 *
358 * Context: caller owns controller lock, IRQs are blocked
359 */
360static void musb_advance_schedule(struct musb *musb, struct urb *urb,
361 struct musb_hw_ep *hw_ep, int is_in)
Felipe Balbi550a7372008-07-24 12:27:36 +0300362{
Sergei Shtylyovc9cd06b2009-03-27 12:58:31 -0700363 struct musb_qh *qh = musb_ep_get_qh(hw_ep, is_in);
Felipe Balbi550a7372008-07-24 12:27:36 +0300364 struct musb_hw_ep *ep = qh->hw_ep;
Felipe Balbi550a7372008-07-24 12:27:36 +0300365 int ready = qh->is_ready;
Sergei Shtylyovc9cd06b2009-03-27 12:58:31 -0700366 int status;
367
368 status = (urb->status == -EINPROGRESS) ? 0 : urb->status;
Felipe Balbi550a7372008-07-24 12:27:36 +0300369
Felipe Balbi550a7372008-07-24 12:27:36 +0300370 /* save toggle eagerly, for paranoia */
371 switch (qh->type) {
372 case USB_ENDPOINT_XFER_BULK:
373 case USB_ENDPOINT_XFER_INT:
Sergei Shtylyov846099a2009-03-27 12:54:21 -0700374 musb_save_toggle(qh, is_in, urb);
Felipe Balbi550a7372008-07-24 12:27:36 +0300375 break;
376 case USB_ENDPOINT_XFER_ISOC:
Sergei Shtylyov1fe975f2009-07-10 20:02:44 +0300377 if (status == 0 && urb->error_count)
Felipe Balbi550a7372008-07-24 12:27:36 +0300378 status = -EXDEV;
379 break;
380 }
381
Felipe Balbi550a7372008-07-24 12:27:36 +0300382 qh->is_ready = 0;
Sergei Shtylyovc9cd06b2009-03-27 12:58:31 -0700383 musb_giveback(musb, urb, status);
Felipe Balbi550a7372008-07-24 12:27:36 +0300384 qh->is_ready = ready;
385
386 /* reclaim resources (and bandwidth) ASAP; deschedule it, and
387 * invalidate qh as soon as list_empty(&hep->urb_list)
388 */
389 if (list_empty(&qh->hep->urb_list)) {
390 struct list_head *head;
391
392 if (is_in)
393 ep->rx_reinit = 1;
394 else
395 ep->tx_reinit = 1;
396
Sergei Shtylyov3e5c6dc2009-03-27 12:55:16 -0700397 /* Clobber old pointers to this qh */
398 musb_ep_set_qh(ep, is_in, NULL);
Felipe Balbi550a7372008-07-24 12:27:36 +0300399 qh->hep->hcpriv = NULL;
400
401 switch (qh->type) {
402
Ajay Kumar Gupta23d15e02008-10-29 15:10:35 +0200403 case USB_ENDPOINT_XFER_CONTROL:
404 case USB_ENDPOINT_XFER_BULK:
405 /* fifo policy for these lists, except that NAKing
406 * should rotate a qh to the end (for fairness).
407 */
408 if (qh->mux == 1) {
409 head = qh->ring.prev;
410 list_del(&qh->ring);
411 kfree(qh);
412 qh = first_qh(head);
413 break;
414 }
415
Felipe Balbi550a7372008-07-24 12:27:36 +0300416 case USB_ENDPOINT_XFER_ISOC:
417 case USB_ENDPOINT_XFER_INT:
418 /* this is where periodic bandwidth should be
419 * de-allocated if it's tracked and allocated;
420 * and where we'd update the schedule tree...
421 */
Felipe Balbi550a7372008-07-24 12:27:36 +0300422 kfree(qh);
423 qh = NULL;
424 break;
Felipe Balbi550a7372008-07-24 12:27:36 +0300425 }
426 }
Felipe Balbi550a7372008-07-24 12:27:36 +0300427
Sergei Shtylyova2fd8142009-02-21 15:30:45 -0800428 if (qh != NULL && qh->is_ready) {
Felipe Balbi550a7372008-07-24 12:27:36 +0300429 DBG(4, "... next ep%d %cX urb %p\n",
Sergei Shtylyovc9cd06b2009-03-27 12:58:31 -0700430 hw_ep->epnum, is_in ? 'R' : 'T', next_urb(qh));
Felipe Balbi550a7372008-07-24 12:27:36 +0300431 musb_start_urb(musb, is_in, qh);
432 }
433}
434
David Brownellc767c1c2008-09-11 11:53:23 +0300435static u16 musb_h_flush_rxfifo(struct musb_hw_ep *hw_ep, u16 csr)
Felipe Balbi550a7372008-07-24 12:27:36 +0300436{
437 /* we don't want fifo to fill itself again;
438 * ignore dma (various models),
439 * leave toggle alone (may not have been saved yet)
440 */
441 csr |= MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_RXPKTRDY;
442 csr &= ~(MUSB_RXCSR_H_REQPKT
443 | MUSB_RXCSR_H_AUTOREQ
444 | MUSB_RXCSR_AUTOCLEAR);
445
446 /* write 2x to allow double buffering */
447 musb_writew(hw_ep->regs, MUSB_RXCSR, csr);
448 musb_writew(hw_ep->regs, MUSB_RXCSR, csr);
449
450 /* flush writebuffer */
451 return musb_readw(hw_ep->regs, MUSB_RXCSR);
452}
453
454/*
455 * PIO RX for a packet (or part of it).
456 */
457static bool
458musb_host_packet_rx(struct musb *musb, struct urb *urb, u8 epnum, u8 iso_err)
459{
460 u16 rx_count;
461 u8 *buf;
462 u16 csr;
463 bool done = false;
464 u32 length;
465 int do_flush = 0;
466 struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
467 void __iomem *epio = hw_ep->regs;
468 struct musb_qh *qh = hw_ep->in_qh;
469 int pipe = urb->pipe;
470 void *buffer = urb->transfer_buffer;
471
472 /* musb_ep_select(mbase, epnum); */
473 rx_count = musb_readw(epio, MUSB_RXCOUNT);
474 DBG(3, "RX%d count %d, buffer %p len %d/%d\n", epnum, rx_count,
475 urb->transfer_buffer, qh->offset,
476 urb->transfer_buffer_length);
477
478 /* unload FIFO */
479 if (usb_pipeisoc(pipe)) {
480 int status = 0;
481 struct usb_iso_packet_descriptor *d;
482
483 if (iso_err) {
484 status = -EILSEQ;
485 urb->error_count++;
486 }
487
488 d = urb->iso_frame_desc + qh->iso_idx;
489 buf = buffer + d->offset;
490 length = d->length;
491 if (rx_count > length) {
492 if (status == 0) {
493 status = -EOVERFLOW;
494 urb->error_count++;
495 }
496 DBG(2, "** OVERFLOW %d into %d\n", rx_count, length);
497 do_flush = 1;
498 } else
499 length = rx_count;
500 urb->actual_length += length;
501 d->actual_length = length;
502
503 d->status = status;
504
505 /* see if we are done */
506 done = (++qh->iso_idx >= urb->number_of_packets);
507 } else {
508 /* non-isoch */
509 buf = buffer + qh->offset;
510 length = urb->transfer_buffer_length - qh->offset;
511 if (rx_count > length) {
512 if (urb->status == -EINPROGRESS)
513 urb->status = -EOVERFLOW;
514 DBG(2, "** OVERFLOW %d into %d\n", rx_count, length);
515 do_flush = 1;
516 } else
517 length = rx_count;
518 urb->actual_length += length;
519 qh->offset += length;
520
521 /* see if we are done */
522 done = (urb->actual_length == urb->transfer_buffer_length)
523 || (rx_count < qh->maxpacket)
524 || (urb->status != -EINPROGRESS);
525 if (done
526 && (urb->status == -EINPROGRESS)
527 && (urb->transfer_flags & URB_SHORT_NOT_OK)
528 && (urb->actual_length
529 < urb->transfer_buffer_length))
530 urb->status = -EREMOTEIO;
531 }
532
533 musb_read_fifo(hw_ep, length, buf);
534
535 csr = musb_readw(epio, MUSB_RXCSR);
536 csr |= MUSB_RXCSR_H_WZC_BITS;
537 if (unlikely(do_flush))
538 musb_h_flush_rxfifo(hw_ep, csr);
539 else {
540 /* REVISIT this assumes AUTOCLEAR is never set */
541 csr &= ~(MUSB_RXCSR_RXPKTRDY | MUSB_RXCSR_H_REQPKT);
542 if (!done)
543 csr |= MUSB_RXCSR_H_REQPKT;
544 musb_writew(epio, MUSB_RXCSR, csr);
545 }
546
547 return done;
548}
549
550/* we don't always need to reinit a given side of an endpoint...
551 * when we do, use tx/rx reinit routine and then construct a new CSR
552 * to address data toggle, NYET, and DMA or PIO.
553 *
554 * it's possible that driver bugs (especially for DMA) or aborting a
555 * transfer might have left the endpoint busier than it should be.
556 * the busy/not-empty tests are basically paranoia.
557 */
558static void
559musb_rx_reinit(struct musb *musb, struct musb_qh *qh, struct musb_hw_ep *ep)
560{
561 u16 csr;
562
563 /* NOTE: we know the "rx" fifo reinit never triggers for ep0.
564 * That always uses tx_reinit since ep0 repurposes TX register
565 * offsets; the initial SETUP packet is also a kind of OUT.
566 */
567
568 /* if programmed for Tx, put it in RX mode */
569 if (ep->is_shared_fifo) {
570 csr = musb_readw(ep->regs, MUSB_TXCSR);
571 if (csr & MUSB_TXCSR_MODE) {
572 musb_h_tx_flush_fifo(ep);
Sergei Shtylyovb6e434a2009-03-26 18:27:47 -0700573 csr = musb_readw(ep->regs, MUSB_TXCSR);
Felipe Balbi550a7372008-07-24 12:27:36 +0300574 musb_writew(ep->regs, MUSB_TXCSR,
Sergei Shtylyovb6e434a2009-03-26 18:27:47 -0700575 csr | MUSB_TXCSR_FRCDATATOG);
Felipe Balbi550a7372008-07-24 12:27:36 +0300576 }
Sergei Shtylyovb6e434a2009-03-26 18:27:47 -0700577
578 /*
579 * Clear the MODE bit (and everything else) to enable Rx.
580 * NOTE: we mustn't clear the DMAMODE bit before DMAENAB.
581 */
582 if (csr & MUSB_TXCSR_DMAMODE)
583 musb_writew(ep->regs, MUSB_TXCSR, MUSB_TXCSR_DMAMODE);
Felipe Balbi550a7372008-07-24 12:27:36 +0300584 musb_writew(ep->regs, MUSB_TXCSR, 0);
585
586 /* scrub all previous state, clearing toggle */
587 } else {
588 csr = musb_readw(ep->regs, MUSB_RXCSR);
589 if (csr & MUSB_RXCSR_RXPKTRDY)
590 WARNING("rx%d, packet/%d ready?\n", ep->epnum,
591 musb_readw(ep->regs, MUSB_RXCOUNT));
592
593 musb_h_flush_rxfifo(ep, MUSB_RXCSR_CLRDATATOG);
594 }
595
596 /* target addr and (for multipoint) hub addr/port */
597 if (musb->is_multipoint) {
Bryan Wuc6cf8b02008-12-02 21:33:48 +0200598 musb_write_rxfunaddr(ep->target_regs, qh->addr_reg);
599 musb_write_rxhubaddr(ep->target_regs, qh->h_addr_reg);
600 musb_write_rxhubport(ep->target_regs, qh->h_port_reg);
601
Felipe Balbi550a7372008-07-24 12:27:36 +0300602 } else
603 musb_writeb(musb->mregs, MUSB_FADDR, qh->addr_reg);
604
605 /* protocol/endpoint, interval/NAKlimit, i/o size */
606 musb_writeb(ep->regs, MUSB_RXTYPE, qh->type_reg);
607 musb_writeb(ep->regs, MUSB_RXINTERVAL, qh->intv_reg);
608 /* NOTE: bulk combining rewrites high bits of maxpacket */
Cliff Cai9f445cb2010-01-28 20:44:18 -0500609 /* Set RXMAXP with the FIFO size of the endpoint
610 * to disable double buffer mode.
611 */
612 if (musb->hwvers < MUSB_HWVERS_2000)
613 musb_writew(ep->regs, MUSB_RXMAXP, ep->max_packet_sz_rx);
614 else
615 musb_writew(ep->regs, MUSB_RXMAXP,
616 qh->maxpacket | ((qh->hb_mult - 1) << 11));
Felipe Balbi550a7372008-07-24 12:27:36 +0300617
618 ep->rx_reinit = 0;
619}
620
Sergei Shtylyov6b6e9712009-03-26 18:29:19 -0700621static bool musb_tx_dma_program(struct dma_controller *dma,
622 struct musb_hw_ep *hw_ep, struct musb_qh *qh,
623 struct urb *urb, u32 offset, u32 length)
624{
625 struct dma_channel *channel = hw_ep->tx_channel;
626 void __iomem *epio = hw_ep->regs;
627 u16 pkt_size = qh->maxpacket;
628 u16 csr;
629 u8 mode;
630
631#ifdef CONFIG_USB_INVENTRA_DMA
632 if (length > channel->max_len)
633 length = channel->max_len;
634
635 csr = musb_readw(epio, MUSB_TXCSR);
636 if (length > pkt_size) {
637 mode = 1;
Ajay Kumar Guptaa483d702009-04-03 16:16:17 -0700638 csr |= MUSB_TXCSR_DMAMODE | MUSB_TXCSR_DMAENAB;
639 /* autoset shouldn't be set in high bandwidth */
640 if (qh->hb_mult == 1)
641 csr |= MUSB_TXCSR_AUTOSET;
Sergei Shtylyov6b6e9712009-03-26 18:29:19 -0700642 } else {
643 mode = 0;
644 csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAMODE);
645 csr |= MUSB_TXCSR_DMAENAB; /* against programmer's guide */
646 }
647 channel->desired_mode = mode;
648 musb_writew(epio, MUSB_TXCSR, csr);
649#else
650 if (!is_cppi_enabled() && !tusb_dma_omap())
651 return false;
652
653 channel->actual_len = 0;
654
655 /*
656 * TX uses "RNDIS" mode automatically but needs help
657 * to identify the zero-length-final-packet case.
658 */
659 mode = (urb->transfer_flags & URB_ZERO_PACKET) ? 1 : 0;
660#endif
661
662 qh->segsize = length;
663
Santosh Shilimkar4c647332010-09-20 10:32:07 +0300664 /*
665 * Ensure the data reaches to main memory before starting
666 * DMA transfer
667 */
668 wmb();
669
Sergei Shtylyov6b6e9712009-03-26 18:29:19 -0700670 if (!dma->channel_program(channel, pkt_size, mode,
671 urb->transfer_dma + offset, length)) {
672 dma->channel_release(channel);
673 hw_ep->tx_channel = NULL;
674
675 csr = musb_readw(epio, MUSB_TXCSR);
676 csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB);
677 musb_writew(epio, MUSB_TXCSR, csr | MUSB_TXCSR_H_WZC_BITS);
678 return false;
679 }
680 return true;
681}
Felipe Balbi550a7372008-07-24 12:27:36 +0300682
683/*
684 * Program an HDRC endpoint as per the given URB
685 * Context: irqs blocked, controller lock held
686 */
687static void musb_ep_program(struct musb *musb, u8 epnum,
Sergei Shtylyov6b6e9712009-03-26 18:29:19 -0700688 struct urb *urb, int is_out,
689 u8 *buf, u32 offset, u32 len)
Felipe Balbi550a7372008-07-24 12:27:36 +0300690{
691 struct dma_controller *dma_controller;
692 struct dma_channel *dma_channel;
693 u8 dma_ok;
694 void __iomem *mbase = musb->mregs;
695 struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
696 void __iomem *epio = hw_ep->regs;
Sergei Shtylyov3e5c6dc2009-03-27 12:55:16 -0700697 struct musb_qh *qh = musb_ep_get_qh(hw_ep, !is_out);
698 u16 packet_sz = qh->maxpacket;
Felipe Balbi550a7372008-07-24 12:27:36 +0300699
700 DBG(3, "%s hw%d urb %p spd%d dev%d ep%d%s "
701 "h_addr%02x h_port%02x bytes %d\n",
702 is_out ? "-->" : "<--",
703 epnum, urb, urb->dev->speed,
704 qh->addr_reg, qh->epnum, is_out ? "out" : "in",
705 qh->h_addr_reg, qh->h_port_reg,
706 len);
707
708 musb_ep_select(mbase, epnum);
709
710 /* candidate for DMA? */
711 dma_controller = musb->dma_controller;
712 if (is_dma_capable() && epnum && dma_controller) {
713 dma_channel = is_out ? hw_ep->tx_channel : hw_ep->rx_channel;
714 if (!dma_channel) {
715 dma_channel = dma_controller->channel_alloc(
716 dma_controller, hw_ep, is_out);
717 if (is_out)
718 hw_ep->tx_channel = dma_channel;
719 else
720 hw_ep->rx_channel = dma_channel;
721 }
722 } else
723 dma_channel = NULL;
724
725 /* make sure we clear DMAEnab, autoSet bits from previous run */
726
727 /* OUT/transmit/EP0 or IN/receive? */
728 if (is_out) {
729 u16 csr;
730 u16 int_txe;
731 u16 load_count;
732
733 csr = musb_readw(epio, MUSB_TXCSR);
734
735 /* disable interrupt in case we flush */
736 int_txe = musb_readw(mbase, MUSB_INTRTXE);
737 musb_writew(mbase, MUSB_INTRTXE, int_txe & ~(1 << epnum));
738
739 /* general endpoint setup */
740 if (epnum) {
Felipe Balbi550a7372008-07-24 12:27:36 +0300741 /* flush all old state, set default */
742 musb_h_tx_flush_fifo(hw_ep);
Sergei Shtylyovb6e434a2009-03-26 18:27:47 -0700743
744 /*
745 * We must not clear the DMAMODE bit before or in
746 * the same cycle with the DMAENAB bit, so we clear
747 * the latter first...
748 */
Felipe Balbi550a7372008-07-24 12:27:36 +0300749 csr &= ~(MUSB_TXCSR_H_NAKTIMEOUT
Sergei Shtylyovb6e434a2009-03-26 18:27:47 -0700750 | MUSB_TXCSR_AUTOSET
751 | MUSB_TXCSR_DMAENAB
Felipe Balbi550a7372008-07-24 12:27:36 +0300752 | MUSB_TXCSR_FRCDATATOG
753 | MUSB_TXCSR_H_RXSTALL
754 | MUSB_TXCSR_H_ERROR
755 | MUSB_TXCSR_TXPKTRDY
756 );
757 csr |= MUSB_TXCSR_MODE;
758
Sergei Shtylyovb6e434a2009-03-26 18:27:47 -0700759 if (usb_gettoggle(urb->dev, qh->epnum, 1))
Felipe Balbi550a7372008-07-24 12:27:36 +0300760 csr |= MUSB_TXCSR_H_WR_DATATOGGLE
761 | MUSB_TXCSR_H_DATATOGGLE;
762 else
763 csr |= MUSB_TXCSR_CLRDATATOG;
764
Felipe Balbi550a7372008-07-24 12:27:36 +0300765 musb_writew(epio, MUSB_TXCSR, csr);
766 /* REVISIT may need to clear FLUSHFIFO ... */
Sergei Shtylyovb6e434a2009-03-26 18:27:47 -0700767 csr &= ~MUSB_TXCSR_DMAMODE;
Felipe Balbi550a7372008-07-24 12:27:36 +0300768 musb_writew(epio, MUSB_TXCSR, csr);
769 csr = musb_readw(epio, MUSB_TXCSR);
770 } else {
771 /* endpoint 0: just flush */
David Brownell78322c12009-03-26 17:38:30 -0700772 musb_h_ep0_flush_fifo(hw_ep);
Felipe Balbi550a7372008-07-24 12:27:36 +0300773 }
774
775 /* target addr and (for multipoint) hub addr/port */
776 if (musb->is_multipoint) {
Bryan Wuc6cf8b02008-12-02 21:33:48 +0200777 musb_write_txfunaddr(mbase, epnum, qh->addr_reg);
778 musb_write_txhubaddr(mbase, epnum, qh->h_addr_reg);
779 musb_write_txhubport(mbase, epnum, qh->h_port_reg);
Felipe Balbi550a7372008-07-24 12:27:36 +0300780/* FIXME if !epnum, do the same for RX ... */
781 } else
782 musb_writeb(mbase, MUSB_FADDR, qh->addr_reg);
783
784 /* protocol/endpoint/interval/NAKlimit */
785 if (epnum) {
786 musb_writeb(epio, MUSB_TXTYPE, qh->type_reg);
787 if (can_bulk_split(musb, qh->type))
788 musb_writew(epio, MUSB_TXMAXP,
789 packet_sz
790 | ((hw_ep->max_packet_sz_tx /
791 packet_sz) - 1) << 11);
792 else
793 musb_writew(epio, MUSB_TXMAXP,
794 packet_sz);
795 musb_writeb(epio, MUSB_TXINTERVAL, qh->intv_reg);
796 } else {
797 musb_writeb(epio, MUSB_NAKLIMIT0, qh->intv_reg);
798 if (musb->is_multipoint)
799 musb_writeb(epio, MUSB_TYPE0,
800 qh->type_reg);
801 }
802
803 if (can_bulk_split(musb, qh->type))
804 load_count = min((u32) hw_ep->max_packet_sz_tx,
805 len);
806 else
807 load_count = min((u32) packet_sz, len);
808
Sergei Shtylyov6b6e9712009-03-26 18:29:19 -0700809 if (dma_channel && musb_tx_dma_program(dma_controller,
810 hw_ep, qh, urb, offset, len))
811 load_count = 0;
Felipe Balbi550a7372008-07-24 12:27:36 +0300812
813 if (load_count) {
Felipe Balbi550a7372008-07-24 12:27:36 +0300814 /* PIO to load FIFO */
815 qh->segsize = load_count;
816 musb_write_fifo(hw_ep, load_count, buf);
Felipe Balbi550a7372008-07-24 12:27:36 +0300817 }
818
819 /* re-enable interrupt */
820 musb_writew(mbase, MUSB_INTRTXE, int_txe);
821
822 /* IN/receive */
823 } else {
824 u16 csr;
825
826 if (hw_ep->rx_reinit) {
827 musb_rx_reinit(musb, qh, hw_ep);
828
829 /* init new state: toggle and NYET, maybe DMA later */
830 if (usb_gettoggle(urb->dev, qh->epnum, 0))
831 csr = MUSB_RXCSR_H_WR_DATATOGGLE
832 | MUSB_RXCSR_H_DATATOGGLE;
833 else
834 csr = 0;
835 if (qh->type == USB_ENDPOINT_XFER_INT)
836 csr |= MUSB_RXCSR_DISNYET;
837
838 } else {
839 csr = musb_readw(hw_ep->regs, MUSB_RXCSR);
840
841 if (csr & (MUSB_RXCSR_RXPKTRDY
842 | MUSB_RXCSR_DMAENAB
843 | MUSB_RXCSR_H_REQPKT))
844 ERR("broken !rx_reinit, ep%d csr %04x\n",
845 hw_ep->epnum, csr);
846
847 /* scrub any stale state, leaving toggle alone */
848 csr &= MUSB_RXCSR_DISNYET;
849 }
850
851 /* kick things off */
852
853 if ((is_cppi_enabled() || tusb_dma_omap()) && dma_channel) {
854 /* candidate for DMA */
855 if (dma_channel) {
856 dma_channel->actual_len = 0L;
857 qh->segsize = len;
858
859 /* AUTOREQ is in a DMA register */
860 musb_writew(hw_ep->regs, MUSB_RXCSR, csr);
861 csr = musb_readw(hw_ep->regs,
862 MUSB_RXCSR);
863
864 /* unless caller treats short rx transfers as
865 * errors, we dare not queue multiple transfers.
866 */
867 dma_ok = dma_controller->channel_program(
868 dma_channel, packet_sz,
869 !(urb->transfer_flags
870 & URB_SHORT_NOT_OK),
Sergei Shtylyov6b6e9712009-03-26 18:29:19 -0700871 urb->transfer_dma + offset,
Felipe Balbi550a7372008-07-24 12:27:36 +0300872 qh->segsize);
873 if (!dma_ok) {
874 dma_controller->channel_release(
875 dma_channel);
876 hw_ep->rx_channel = NULL;
877 dma_channel = NULL;
878 } else
879 csr |= MUSB_RXCSR_DMAENAB;
880 }
881 }
882
883 csr |= MUSB_RXCSR_H_REQPKT;
884 DBG(7, "RXCSR%d := %04x\n", epnum, csr);
885 musb_writew(hw_ep->regs, MUSB_RXCSR, csr);
886 csr = musb_readw(hw_ep->regs, MUSB_RXCSR);
887 }
888}
889
890
891/*
892 * Service the default endpoint (ep0) as host.
893 * Return true until it's time to start the status stage.
894 */
895static bool musb_h_ep0_continue(struct musb *musb, u16 len, struct urb *urb)
896{
897 bool more = false;
898 u8 *fifo_dest = NULL;
899 u16 fifo_count = 0;
900 struct musb_hw_ep *hw_ep = musb->control_ep;
901 struct musb_qh *qh = hw_ep->in_qh;
902 struct usb_ctrlrequest *request;
903
904 switch (musb->ep0_stage) {
905 case MUSB_EP0_IN:
906 fifo_dest = urb->transfer_buffer + urb->actual_length;
Sergei Shtylyov3ecdb9a2009-02-21 15:31:23 -0800907 fifo_count = min_t(size_t, len, urb->transfer_buffer_length -
908 urb->actual_length);
Felipe Balbi550a7372008-07-24 12:27:36 +0300909 if (fifo_count < len)
910 urb->status = -EOVERFLOW;
911
912 musb_read_fifo(hw_ep, fifo_count, fifo_dest);
913
914 urb->actual_length += fifo_count;
915 if (len < qh->maxpacket) {
916 /* always terminate on short read; it's
917 * rarely reported as an error.
918 */
919 } else if (urb->actual_length <
920 urb->transfer_buffer_length)
921 more = true;
922 break;
923 case MUSB_EP0_START:
924 request = (struct usb_ctrlrequest *) urb->setup_packet;
925
926 if (!request->wLength) {
927 DBG(4, "start no-DATA\n");
928 break;
929 } else if (request->bRequestType & USB_DIR_IN) {
930 DBG(4, "start IN-DATA\n");
931 musb->ep0_stage = MUSB_EP0_IN;
932 more = true;
933 break;
934 } else {
935 DBG(4, "start OUT-DATA\n");
936 musb->ep0_stage = MUSB_EP0_OUT;
937 more = true;
938 }
939 /* FALLTHROUGH */
940 case MUSB_EP0_OUT:
Sergei Shtylyov3ecdb9a2009-02-21 15:31:23 -0800941 fifo_count = min_t(size_t, qh->maxpacket,
942 urb->transfer_buffer_length -
943 urb->actual_length);
Felipe Balbi550a7372008-07-24 12:27:36 +0300944 if (fifo_count) {
945 fifo_dest = (u8 *) (urb->transfer_buffer
946 + urb->actual_length);
David Brownellbb1c9ef2008-11-24 13:06:50 +0200947 DBG(3, "Sending %d byte%s to ep0 fifo %p\n",
948 fifo_count,
949 (fifo_count == 1) ? "" : "s",
950 fifo_dest);
Felipe Balbi550a7372008-07-24 12:27:36 +0300951 musb_write_fifo(hw_ep, fifo_count, fifo_dest);
952
953 urb->actual_length += fifo_count;
954 more = true;
955 }
956 break;
957 default:
958 ERR("bogus ep0 stage %d\n", musb->ep0_stage);
959 break;
960 }
961
962 return more;
963}
964
965/*
966 * Handle default endpoint interrupt as host. Only called in IRQ time
David Brownellc767c1c2008-09-11 11:53:23 +0300967 * from musb_interrupt().
Felipe Balbi550a7372008-07-24 12:27:36 +0300968 *
969 * called with controller irqlocked
970 */
971irqreturn_t musb_h_ep0_irq(struct musb *musb)
972{
973 struct urb *urb;
974 u16 csr, len;
975 int status = 0;
976 void __iomem *mbase = musb->mregs;
977 struct musb_hw_ep *hw_ep = musb->control_ep;
978 void __iomem *epio = hw_ep->regs;
979 struct musb_qh *qh = hw_ep->in_qh;
980 bool complete = false;
981 irqreturn_t retval = IRQ_NONE;
982
983 /* ep0 only has one queue, "in" */
984 urb = next_urb(qh);
985
986 musb_ep_select(mbase, 0);
987 csr = musb_readw(epio, MUSB_CSR0);
988 len = (csr & MUSB_CSR0_RXPKTRDY)
989 ? musb_readb(epio, MUSB_COUNT0)
990 : 0;
991
992 DBG(4, "<== csr0 %04x, qh %p, count %d, urb %p, stage %d\n",
993 csr, qh, len, urb, musb->ep0_stage);
994
995 /* if we just did status stage, we are done */
996 if (MUSB_EP0_STATUS == musb->ep0_stage) {
997 retval = IRQ_HANDLED;
998 complete = true;
999 }
1000
1001 /* prepare status */
1002 if (csr & MUSB_CSR0_H_RXSTALL) {
1003 DBG(6, "STALLING ENDPOINT\n");
1004 status = -EPIPE;
1005
1006 } else if (csr & MUSB_CSR0_H_ERROR) {
1007 DBG(2, "no response, csr0 %04x\n", csr);
1008 status = -EPROTO;
1009
1010 } else if (csr & MUSB_CSR0_H_NAKTIMEOUT) {
1011 DBG(2, "control NAK timeout\n");
1012
1013 /* NOTE: this code path would be a good place to PAUSE a
1014 * control transfer, if another one is queued, so that
Ajay Kumar Gupta1e0320f2009-02-24 15:26:13 -08001015 * ep0 is more likely to stay busy. That's already done
1016 * for bulk RX transfers.
Felipe Balbi550a7372008-07-24 12:27:36 +03001017 *
1018 * if (qh->ring.next != &musb->control), then
1019 * we have a candidate... NAKing is *NOT* an error
1020 */
1021 musb_writew(epio, MUSB_CSR0, 0);
1022 retval = IRQ_HANDLED;
1023 }
1024
1025 if (status) {
1026 DBG(6, "aborting\n");
1027 retval = IRQ_HANDLED;
1028 if (urb)
1029 urb->status = status;
1030 complete = true;
1031
1032 /* use the proper sequence to abort the transfer */
1033 if (csr & MUSB_CSR0_H_REQPKT) {
1034 csr &= ~MUSB_CSR0_H_REQPKT;
1035 musb_writew(epio, MUSB_CSR0, csr);
1036 csr &= ~MUSB_CSR0_H_NAKTIMEOUT;
1037 musb_writew(epio, MUSB_CSR0, csr);
1038 } else {
David Brownell78322c12009-03-26 17:38:30 -07001039 musb_h_ep0_flush_fifo(hw_ep);
Felipe Balbi550a7372008-07-24 12:27:36 +03001040 }
1041
1042 musb_writeb(epio, MUSB_NAKLIMIT0, 0);
1043
1044 /* clear it */
1045 musb_writew(epio, MUSB_CSR0, 0);
1046 }
1047
1048 if (unlikely(!urb)) {
1049 /* stop endpoint since we have no place for its data, this
1050 * SHOULD NEVER HAPPEN! */
1051 ERR("no URB for end 0\n");
1052
David Brownell78322c12009-03-26 17:38:30 -07001053 musb_h_ep0_flush_fifo(hw_ep);
Felipe Balbi550a7372008-07-24 12:27:36 +03001054 goto done;
1055 }
1056
1057 if (!complete) {
1058 /* call common logic and prepare response */
1059 if (musb_h_ep0_continue(musb, len, urb)) {
1060 /* more packets required */
1061 csr = (MUSB_EP0_IN == musb->ep0_stage)
1062 ? MUSB_CSR0_H_REQPKT : MUSB_CSR0_TXPKTRDY;
1063 } else {
1064 /* data transfer complete; perform status phase */
1065 if (usb_pipeout(urb->pipe)
1066 || !urb->transfer_buffer_length)
1067 csr = MUSB_CSR0_H_STATUSPKT
1068 | MUSB_CSR0_H_REQPKT;
1069 else
1070 csr = MUSB_CSR0_H_STATUSPKT
1071 | MUSB_CSR0_TXPKTRDY;
1072
1073 /* flag status stage */
1074 musb->ep0_stage = MUSB_EP0_STATUS;
1075
1076 DBG(5, "ep0 STATUS, csr %04x\n", csr);
1077
1078 }
1079 musb_writew(epio, MUSB_CSR0, csr);
1080 retval = IRQ_HANDLED;
1081 } else
1082 musb->ep0_stage = MUSB_EP0_IDLE;
1083
1084 /* call completion handler if done */
1085 if (complete)
1086 musb_advance_schedule(musb, urb, hw_ep, 1);
1087done:
1088 return retval;
1089}
1090
1091
1092#ifdef CONFIG_USB_INVENTRA_DMA
1093
1094/* Host side TX (OUT) using Mentor DMA works as follows:
1095 submit_urb ->
1096 - if queue was empty, Program Endpoint
1097 - ... which starts DMA to fifo in mode 1 or 0
1098
1099 DMA Isr (transfer complete) -> TxAvail()
1100 - Stop DMA (~DmaEnab) (<--- Alert ... currently happens
1101 only in musb_cleanup_urb)
1102 - TxPktRdy has to be set in mode 0 or for
1103 short packets in mode 1.
1104*/
1105
1106#endif
1107
1108/* Service a Tx-Available or dma completion irq for the endpoint */
1109void musb_host_tx(struct musb *musb, u8 epnum)
1110{
1111 int pipe;
1112 bool done = false;
1113 u16 tx_csr;
Sergei Shtylyov6b6e9712009-03-26 18:29:19 -07001114 size_t length = 0;
1115 size_t offset = 0;
Felipe Balbi550a7372008-07-24 12:27:36 +03001116 struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
1117 void __iomem *epio = hw_ep->regs;
Sergei Shtylyov3e5c6dc2009-03-27 12:55:16 -07001118 struct musb_qh *qh = hw_ep->out_qh;
1119 struct urb *urb = next_urb(qh);
Felipe Balbi550a7372008-07-24 12:27:36 +03001120 u32 status = 0;
1121 void __iomem *mbase = musb->mregs;
1122 struct dma_channel *dma;
1123
Felipe Balbi550a7372008-07-24 12:27:36 +03001124 musb_ep_select(mbase, epnum);
1125 tx_csr = musb_readw(epio, MUSB_TXCSR);
1126
1127 /* with CPPI, DMA sometimes triggers "extra" irqs */
1128 if (!urb) {
1129 DBG(4, "extra TX%d ready, csr %04x\n", epnum, tx_csr);
Sergei Shtylyov6b6e9712009-03-26 18:29:19 -07001130 return;
Felipe Balbi550a7372008-07-24 12:27:36 +03001131 }
1132
1133 pipe = urb->pipe;
1134 dma = is_dma_capable() ? hw_ep->tx_channel : NULL;
1135 DBG(4, "OUT/TX%d end, csr %04x%s\n", epnum, tx_csr,
1136 dma ? ", dma" : "");
1137
1138 /* check for errors */
1139 if (tx_csr & MUSB_TXCSR_H_RXSTALL) {
1140 /* dma was disabled, fifo flushed */
1141 DBG(3, "TX end %d stall\n", epnum);
1142
1143 /* stall; record URB status */
1144 status = -EPIPE;
1145
1146 } else if (tx_csr & MUSB_TXCSR_H_ERROR) {
1147 /* (NON-ISO) dma was disabled, fifo flushed */
1148 DBG(3, "TX 3strikes on ep=%d\n", epnum);
1149
1150 status = -ETIMEDOUT;
1151
1152 } else if (tx_csr & MUSB_TXCSR_H_NAKTIMEOUT) {
1153 DBG(6, "TX end=%d device not responding\n", epnum);
1154
1155 /* NOTE: this code path would be a good place to PAUSE a
1156 * transfer, if there's some other (nonperiodic) tx urb
1157 * that could use this fifo. (dma complicates it...)
Ajay Kumar Gupta1e0320f2009-02-24 15:26:13 -08001158 * That's already done for bulk RX transfers.
Felipe Balbi550a7372008-07-24 12:27:36 +03001159 *
1160 * if (bulk && qh->ring.next != &musb->out_bulk), then
1161 * we have a candidate... NAKing is *NOT* an error
1162 */
1163 musb_ep_select(mbase, epnum);
1164 musb_writew(epio, MUSB_TXCSR,
1165 MUSB_TXCSR_H_WZC_BITS
1166 | MUSB_TXCSR_TXPKTRDY);
Sergei Shtylyov6b6e9712009-03-26 18:29:19 -07001167 return;
Felipe Balbi550a7372008-07-24 12:27:36 +03001168 }
1169
1170 if (status) {
1171 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
1172 dma->status = MUSB_DMA_STATUS_CORE_ABORT;
1173 (void) musb->dma_controller->channel_abort(dma);
1174 }
1175
1176 /* do the proper sequence to abort the transfer in the
1177 * usb core; the dma engine should already be stopped.
1178 */
1179 musb_h_tx_flush_fifo(hw_ep);
1180 tx_csr &= ~(MUSB_TXCSR_AUTOSET
1181 | MUSB_TXCSR_DMAENAB
1182 | MUSB_TXCSR_H_ERROR
1183 | MUSB_TXCSR_H_RXSTALL
1184 | MUSB_TXCSR_H_NAKTIMEOUT
1185 );
1186
1187 musb_ep_select(mbase, epnum);
1188 musb_writew(epio, MUSB_TXCSR, tx_csr);
1189 /* REVISIT may need to clear FLUSHFIFO ... */
1190 musb_writew(epio, MUSB_TXCSR, tx_csr);
1191 musb_writeb(epio, MUSB_TXINTERVAL, 0);
1192
1193 done = true;
1194 }
1195
1196 /* second cppi case */
1197 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
1198 DBG(4, "extra TX%d ready, csr %04x\n", epnum, tx_csr);
Sergei Shtylyov6b6e9712009-03-26 18:29:19 -07001199 return;
Felipe Balbi550a7372008-07-24 12:27:36 +03001200 }
1201
Sergei Shtylyovc7bbc052009-03-26 18:26:40 -07001202 if (is_dma_capable() && dma && !status) {
1203 /*
1204 * DMA has completed. But if we're using DMA mode 1 (multi
1205 * packet DMA), we need a terminal TXPKTRDY interrupt before
1206 * we can consider this transfer completed, lest we trash
1207 * its last packet when writing the next URB's data. So we
1208 * switch back to mode 0 to get that interrupt; we'll come
1209 * back here once it happens.
1210 */
1211 if (tx_csr & MUSB_TXCSR_DMAMODE) {
1212 /*
1213 * We shouldn't clear DMAMODE with DMAENAB set; so
1214 * clear them in a safe order. That should be OK
1215 * once TXPKTRDY has been set (and I've never seen
1216 * it being 0 at this moment -- DMA interrupt latency
1217 * is significant) but if it hasn't been then we have
1218 * no choice but to stop being polite and ignore the
1219 * programmer's guide... :-)
1220 *
1221 * Note that we must write TXCSR with TXPKTRDY cleared
1222 * in order not to re-trigger the packet send (this bit
1223 * can't be cleared by CPU), and there's another caveat:
1224 * TXPKTRDY may be set shortly and then cleared in the
1225 * double-buffered FIFO mode, so we do an extra TXCSR
1226 * read for debouncing...
1227 */
1228 tx_csr &= musb_readw(epio, MUSB_TXCSR);
1229 if (tx_csr & MUSB_TXCSR_TXPKTRDY) {
1230 tx_csr &= ~(MUSB_TXCSR_DMAENAB |
1231 MUSB_TXCSR_TXPKTRDY);
1232 musb_writew(epio, MUSB_TXCSR,
1233 tx_csr | MUSB_TXCSR_H_WZC_BITS);
1234 }
1235 tx_csr &= ~(MUSB_TXCSR_DMAMODE |
1236 MUSB_TXCSR_TXPKTRDY);
1237 musb_writew(epio, MUSB_TXCSR,
1238 tx_csr | MUSB_TXCSR_H_WZC_BITS);
1239
1240 /*
1241 * There is no guarantee that we'll get an interrupt
1242 * after clearing DMAMODE as we might have done this
1243 * too late (after TXPKTRDY was cleared by controller).
1244 * Re-read TXCSR as we have spoiled its previous value.
1245 */
1246 tx_csr = musb_readw(epio, MUSB_TXCSR);
1247 }
1248
1249 /*
1250 * We may get here from a DMA completion or TXPKTRDY interrupt.
1251 * In any case, we must check the FIFO status here and bail out
1252 * only if the FIFO still has data -- that should prevent the
1253 * "missed" TXPKTRDY interrupts and deal with double-buffered
1254 * FIFO mode too...
1255 */
1256 if (tx_csr & (MUSB_TXCSR_FIFONOTEMPTY | MUSB_TXCSR_TXPKTRDY)) {
1257 DBG(2, "DMA complete but packet still in FIFO, "
1258 "CSR %04x\n", tx_csr);
1259 return;
1260 }
1261 }
1262
Felipe Balbi550a7372008-07-24 12:27:36 +03001263 if (!status || dma || usb_pipeisoc(pipe)) {
1264 if (dma)
Sergei Shtylyov6b6e9712009-03-26 18:29:19 -07001265 length = dma->actual_len;
Felipe Balbi550a7372008-07-24 12:27:36 +03001266 else
Sergei Shtylyov6b6e9712009-03-26 18:29:19 -07001267 length = qh->segsize;
1268 qh->offset += length;
Felipe Balbi550a7372008-07-24 12:27:36 +03001269
1270 if (usb_pipeisoc(pipe)) {
1271 struct usb_iso_packet_descriptor *d;
1272
1273 d = urb->iso_frame_desc + qh->iso_idx;
Sergei Shtylyov6b6e9712009-03-26 18:29:19 -07001274 d->actual_length = length;
1275 d->status = status;
Felipe Balbi550a7372008-07-24 12:27:36 +03001276 if (++qh->iso_idx >= urb->number_of_packets) {
1277 done = true;
1278 } else {
1279 d++;
Sergei Shtylyov6b6e9712009-03-26 18:29:19 -07001280 offset = d->offset;
1281 length = d->length;
Felipe Balbi550a7372008-07-24 12:27:36 +03001282 }
1283 } else if (dma) {
1284 done = true;
1285 } else {
1286 /* see if we need to send more data, or ZLP */
1287 if (qh->segsize < qh->maxpacket)
1288 done = true;
1289 else if (qh->offset == urb->transfer_buffer_length
1290 && !(urb->transfer_flags
1291 & URB_ZERO_PACKET))
1292 done = true;
1293 if (!done) {
Sergei Shtylyov6b6e9712009-03-26 18:29:19 -07001294 offset = qh->offset;
1295 length = urb->transfer_buffer_length - offset;
Felipe Balbi550a7372008-07-24 12:27:36 +03001296 }
1297 }
1298 }
1299
1300 /* urb->status != -EINPROGRESS means request has been faulted,
1301 * so we must abort this transfer after cleanup
1302 */
1303 if (urb->status != -EINPROGRESS) {
1304 done = true;
1305 if (status == 0)
1306 status = urb->status;
1307 }
1308
1309 if (done) {
1310 /* set status */
1311 urb->status = status;
1312 urb->actual_length = qh->offset;
1313 musb_advance_schedule(musb, urb, hw_ep, USB_DIR_OUT);
Sergei Shtylyov6b6e9712009-03-26 18:29:19 -07001314 return;
1315 } else if (usb_pipeisoc(pipe) && dma) {
1316 if (musb_tx_dma_program(musb->dma_controller, hw_ep, qh, urb,
Ajay Kumar Guptadfeffa52009-11-17 15:22:55 +05301317 offset, length)) {
1318 if (is_cppi_enabled() || tusb_dma_omap())
1319 musb_h_tx_dma_start(hw_ep);
Sergei Shtylyov6b6e9712009-03-26 18:29:19 -07001320 return;
Ajay Kumar Guptadfeffa52009-11-17 15:22:55 +05301321 }
Sergei Shtylyov6b6e9712009-03-26 18:29:19 -07001322 } else if (tx_csr & MUSB_TXCSR_DMAENAB) {
1323 DBG(1, "not complete, but DMA enabled?\n");
1324 return;
1325 }
Felipe Balbi550a7372008-07-24 12:27:36 +03001326
Sergei Shtylyov6b6e9712009-03-26 18:29:19 -07001327 /*
1328 * PIO: start next packet in this URB.
1329 *
1330 * REVISIT: some docs say that when hw_ep->tx_double_buffered,
1331 * (and presumably, FIFO is not half-full) we should write *two*
1332 * packets before updating TXCSR; other docs disagree...
1333 */
1334 if (length > qh->maxpacket)
1335 length = qh->maxpacket;
Maulik Mankad496dda72010-09-24 13:44:06 +03001336 /* Unmap the buffer so that CPU can use it */
1337 unmap_urb_for_dma(musb_to_hcd(musb), urb);
Sergei Shtylyov6b6e9712009-03-26 18:29:19 -07001338 musb_write_fifo(hw_ep, length, urb->transfer_buffer + offset);
1339 qh->segsize = length;
Felipe Balbi550a7372008-07-24 12:27:36 +03001340
Sergei Shtylyov6b6e9712009-03-26 18:29:19 -07001341 musb_ep_select(mbase, epnum);
1342 musb_writew(epio, MUSB_TXCSR,
1343 MUSB_TXCSR_H_WZC_BITS | MUSB_TXCSR_TXPKTRDY);
Felipe Balbi550a7372008-07-24 12:27:36 +03001344}
1345
1346
1347#ifdef CONFIG_USB_INVENTRA_DMA
1348
1349/* Host side RX (IN) using Mentor DMA works as follows:
1350 submit_urb ->
1351 - if queue was empty, ProgramEndpoint
1352 - first IN token is sent out (by setting ReqPkt)
1353 LinuxIsr -> RxReady()
1354 /\ => first packet is received
1355 | - Set in mode 0 (DmaEnab, ~ReqPkt)
1356 | -> DMA Isr (transfer complete) -> RxReady()
1357 | - Ack receive (~RxPktRdy), turn off DMA (~DmaEnab)
1358 | - if urb not complete, send next IN token (ReqPkt)
1359 | | else complete urb.
1360 | |
1361 ---------------------------
1362 *
1363 * Nuances of mode 1:
1364 * For short packets, no ack (+RxPktRdy) is sent automatically
1365 * (even if AutoClear is ON)
1366 * For full packets, ack (~RxPktRdy) and next IN token (+ReqPkt) is sent
1367 * automatically => major problem, as collecting the next packet becomes
1368 * difficult. Hence mode 1 is not used.
1369 *
1370 * REVISIT
1371 * All we care about at this driver level is that
1372 * (a) all URBs terminate with REQPKT cleared and fifo(s) empty;
1373 * (b) termination conditions are: short RX, or buffer full;
1374 * (c) fault modes include
1375 * - iff URB_SHORT_NOT_OK, short RX status is -EREMOTEIO.
1376 * (and that endpoint's dma queue stops immediately)
1377 * - overflow (full, PLUS more bytes in the terminal packet)
1378 *
1379 * So for example, usb-storage sets URB_SHORT_NOT_OK, and would
1380 * thus be a great candidate for using mode 1 ... for all but the
1381 * last packet of one URB's transfer.
1382 */
1383
1384#endif
1385
Ajay Kumar Gupta1e0320f2009-02-24 15:26:13 -08001386/* Schedule next QH from musb->in_bulk and move the current qh to
1387 * the end; avoids starvation for other endpoints.
1388 */
1389static void musb_bulk_rx_nak_timeout(struct musb *musb, struct musb_hw_ep *ep)
1390{
1391 struct dma_channel *dma;
1392 struct urb *urb;
1393 void __iomem *mbase = musb->mregs;
1394 void __iomem *epio = ep->regs;
1395 struct musb_qh *cur_qh, *next_qh;
1396 u16 rx_csr;
1397
1398 musb_ep_select(mbase, ep->epnum);
1399 dma = is_dma_capable() ? ep->rx_channel : NULL;
1400
1401 /* clear nak timeout bit */
1402 rx_csr = musb_readw(epio, MUSB_RXCSR);
1403 rx_csr |= MUSB_RXCSR_H_WZC_BITS;
1404 rx_csr &= ~MUSB_RXCSR_DATAERROR;
1405 musb_writew(epio, MUSB_RXCSR, rx_csr);
1406
1407 cur_qh = first_qh(&musb->in_bulk);
1408 if (cur_qh) {
1409 urb = next_urb(cur_qh);
1410 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
1411 dma->status = MUSB_DMA_STATUS_CORE_ABORT;
1412 musb->dma_controller->channel_abort(dma);
1413 urb->actual_length += dma->actual_len;
1414 dma->actual_len = 0L;
1415 }
Sergei Shtylyov846099a2009-03-27 12:54:21 -07001416 musb_save_toggle(cur_qh, 1, urb);
Ajay Kumar Gupta1e0320f2009-02-24 15:26:13 -08001417
1418 /* move cur_qh to end of queue */
1419 list_move_tail(&cur_qh->ring, &musb->in_bulk);
1420
1421 /* get the next qh from musb->in_bulk */
1422 next_qh = first_qh(&musb->in_bulk);
1423
1424 /* set rx_reinit and schedule the next qh */
1425 ep->rx_reinit = 1;
1426 musb_start_urb(musb, 1, next_qh);
1427 }
1428}
1429
Felipe Balbi550a7372008-07-24 12:27:36 +03001430/*
1431 * Service an RX interrupt for the given IN endpoint; docs cover bulk, iso,
1432 * and high-bandwidth IN transfer cases.
1433 */
1434void musb_host_rx(struct musb *musb, u8 epnum)
1435{
1436 struct urb *urb;
1437 struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
1438 void __iomem *epio = hw_ep->regs;
1439 struct musb_qh *qh = hw_ep->in_qh;
1440 size_t xfer_len;
1441 void __iomem *mbase = musb->mregs;
1442 int pipe;
1443 u16 rx_csr, val;
1444 bool iso_err = false;
1445 bool done = false;
1446 u32 status;
1447 struct dma_channel *dma;
1448
1449 musb_ep_select(mbase, epnum);
1450
1451 urb = next_urb(qh);
1452 dma = is_dma_capable() ? hw_ep->rx_channel : NULL;
1453 status = 0;
1454 xfer_len = 0;
1455
1456 rx_csr = musb_readw(epio, MUSB_RXCSR);
1457 val = rx_csr;
1458
1459 if (unlikely(!urb)) {
1460 /* REVISIT -- THIS SHOULD NEVER HAPPEN ... but, at least
1461 * usbtest #11 (unlinks) triggers it regularly, sometimes
1462 * with fifo full. (Only with DMA??)
1463 */
1464 DBG(3, "BOGUS RX%d ready, csr %04x, count %d\n", epnum, val,
1465 musb_readw(epio, MUSB_RXCOUNT));
1466 musb_h_flush_rxfifo(hw_ep, MUSB_RXCSR_CLRDATATOG);
1467 return;
1468 }
1469
1470 pipe = urb->pipe;
1471
1472 DBG(5, "<== hw %d rxcsr %04x, urb actual %d (+dma %zu)\n",
1473 epnum, rx_csr, urb->actual_length,
1474 dma ? dma->actual_len : 0);
1475
1476 /* check for errors, concurrent stall & unlink is not really
1477 * handled yet! */
1478 if (rx_csr & MUSB_RXCSR_H_RXSTALL) {
1479 DBG(3, "RX end %d STALL\n", epnum);
1480
1481 /* stall; record URB status */
1482 status = -EPIPE;
1483
1484 } else if (rx_csr & MUSB_RXCSR_H_ERROR) {
1485 DBG(3, "end %d RX proto error\n", epnum);
1486
1487 status = -EPROTO;
1488 musb_writeb(epio, MUSB_RXINTERVAL, 0);
1489
1490 } else if (rx_csr & MUSB_RXCSR_DATAERROR) {
1491
1492 if (USB_ENDPOINT_XFER_ISOC != qh->type) {
Felipe Balbi550a7372008-07-24 12:27:36 +03001493 DBG(6, "RX end %d NAK timeout\n", epnum);
Ajay Kumar Gupta1e0320f2009-02-24 15:26:13 -08001494
1495 /* NOTE: NAKing is *NOT* an error, so we want to
1496 * continue. Except ... if there's a request for
1497 * another QH, use that instead of starving it.
1498 *
1499 * Devices like Ethernet and serial adapters keep
1500 * reads posted at all times, which will starve
1501 * other devices without this logic.
1502 */
1503 if (usb_pipebulk(urb->pipe)
1504 && qh->mux == 1
1505 && !list_is_singular(&musb->in_bulk)) {
1506 musb_bulk_rx_nak_timeout(musb, hw_ep);
1507 return;
1508 }
Felipe Balbi550a7372008-07-24 12:27:36 +03001509 musb_ep_select(mbase, epnum);
Ajay Kumar Gupta1e0320f2009-02-24 15:26:13 -08001510 rx_csr |= MUSB_RXCSR_H_WZC_BITS;
1511 rx_csr &= ~MUSB_RXCSR_DATAERROR;
1512 musb_writew(epio, MUSB_RXCSR, rx_csr);
Felipe Balbi550a7372008-07-24 12:27:36 +03001513
1514 goto finish;
1515 } else {
1516 DBG(4, "RX end %d ISO data error\n", epnum);
1517 /* packet error reported later */
1518 iso_err = true;
1519 }
Ajay Kumar Guptaa483d702009-04-03 16:16:17 -07001520 } else if (rx_csr & MUSB_RXCSR_INCOMPRX) {
1521 DBG(3, "end %d high bandwidth incomplete ISO packet RX\n",
1522 epnum);
1523 status = -EPROTO;
Felipe Balbi550a7372008-07-24 12:27:36 +03001524 }
1525
1526 /* faults abort the transfer */
1527 if (status) {
1528 /* clean up dma and collect transfer count */
1529 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
1530 dma->status = MUSB_DMA_STATUS_CORE_ABORT;
1531 (void) musb->dma_controller->channel_abort(dma);
1532 xfer_len = dma->actual_len;
1533 }
1534 musb_h_flush_rxfifo(hw_ep, MUSB_RXCSR_CLRDATATOG);
1535 musb_writeb(epio, MUSB_RXINTERVAL, 0);
1536 done = true;
1537 goto finish;
1538 }
1539
1540 if (unlikely(dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY)) {
1541 /* SHOULD NEVER HAPPEN ... but at least DaVinci has done it */
1542 ERR("RX%d dma busy, csr %04x\n", epnum, rx_csr);
1543 goto finish;
1544 }
1545
1546 /* thorough shutdown for now ... given more precise fault handling
1547 * and better queueing support, we might keep a DMA pipeline going
1548 * while processing this irq for earlier completions.
1549 */
1550
1551 /* FIXME this is _way_ too much in-line logic for Mentor DMA */
1552
1553#ifndef CONFIG_USB_INVENTRA_DMA
1554 if (rx_csr & MUSB_RXCSR_H_REQPKT) {
1555 /* REVISIT this happened for a while on some short reads...
1556 * the cleanup still needs investigation... looks bad...
1557 * and also duplicates dma cleanup code above ... plus,
1558 * shouldn't this be the "half full" double buffer case?
1559 */
1560 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
1561 dma->status = MUSB_DMA_STATUS_CORE_ABORT;
1562 (void) musb->dma_controller->channel_abort(dma);
1563 xfer_len = dma->actual_len;
1564 done = true;
1565 }
1566
1567 DBG(2, "RXCSR%d %04x, reqpkt, len %zu%s\n", epnum, rx_csr,
1568 xfer_len, dma ? ", dma" : "");
1569 rx_csr &= ~MUSB_RXCSR_H_REQPKT;
1570
1571 musb_ep_select(mbase, epnum);
1572 musb_writew(epio, MUSB_RXCSR,
1573 MUSB_RXCSR_H_WZC_BITS | rx_csr);
1574 }
1575#endif
1576 if (dma && (rx_csr & MUSB_RXCSR_DMAENAB)) {
1577 xfer_len = dma->actual_len;
1578
1579 val &= ~(MUSB_RXCSR_DMAENAB
1580 | MUSB_RXCSR_H_AUTOREQ
1581 | MUSB_RXCSR_AUTOCLEAR
1582 | MUSB_RXCSR_RXPKTRDY);
1583 musb_writew(hw_ep->regs, MUSB_RXCSR, val);
1584
1585#ifdef CONFIG_USB_INVENTRA_DMA
Ajay Kumar Guptaf82a6892008-10-29 15:10:31 +02001586 if (usb_pipeisoc(pipe)) {
1587 struct usb_iso_packet_descriptor *d;
1588
1589 d = urb->iso_frame_desc + qh->iso_idx;
1590 d->actual_length = xfer_len;
1591
1592 /* even if there was an error, we did the dma
1593 * for iso_frame_desc->length
1594 */
1595 if (d->status != EILSEQ && d->status != -EOVERFLOW)
1596 d->status = 0;
1597
1598 if (++qh->iso_idx >= urb->number_of_packets)
1599 done = true;
1600 else
1601 done = false;
1602
1603 } else {
Felipe Balbi550a7372008-07-24 12:27:36 +03001604 /* done if urb buffer is full or short packet is recd */
1605 done = (urb->actual_length + xfer_len >=
1606 urb->transfer_buffer_length
1607 || dma->actual_len < qh->maxpacket);
Ajay Kumar Guptaf82a6892008-10-29 15:10:31 +02001608 }
Felipe Balbi550a7372008-07-24 12:27:36 +03001609
1610 /* send IN token for next packet, without AUTOREQ */
1611 if (!done) {
1612 val |= MUSB_RXCSR_H_REQPKT;
1613 musb_writew(epio, MUSB_RXCSR,
1614 MUSB_RXCSR_H_WZC_BITS | val);
1615 }
1616
1617 DBG(4, "ep %d dma %s, rxcsr %04x, rxcount %d\n", epnum,
1618 done ? "off" : "reset",
1619 musb_readw(epio, MUSB_RXCSR),
1620 musb_readw(epio, MUSB_RXCOUNT));
1621#else
1622 done = true;
1623#endif
1624 } else if (urb->status == -EINPROGRESS) {
1625 /* if no errors, be sure a packet is ready for unloading */
1626 if (unlikely(!(rx_csr & MUSB_RXCSR_RXPKTRDY))) {
1627 status = -EPROTO;
1628 ERR("Rx interrupt with no errors or packet!\n");
1629
1630 /* FIXME this is another "SHOULD NEVER HAPPEN" */
1631
1632/* SCRUB (RX) */
1633 /* do the proper sequence to abort the transfer */
1634 musb_ep_select(mbase, epnum);
1635 val &= ~MUSB_RXCSR_H_REQPKT;
1636 musb_writew(epio, MUSB_RXCSR, val);
1637 goto finish;
1638 }
1639
1640 /* we are expecting IN packets */
1641#ifdef CONFIG_USB_INVENTRA_DMA
1642 if (dma) {
1643 struct dma_controller *c;
1644 u16 rx_count;
Ajay Kumar Guptaf82a6892008-10-29 15:10:31 +02001645 int ret, length;
1646 dma_addr_t buf;
Felipe Balbi550a7372008-07-24 12:27:36 +03001647
1648 rx_count = musb_readw(epio, MUSB_RXCOUNT);
1649
1650 DBG(2, "RX%d count %d, buffer 0x%x len %d/%d\n",
1651 epnum, rx_count,
1652 urb->transfer_dma
1653 + urb->actual_length,
1654 qh->offset,
1655 urb->transfer_buffer_length);
1656
1657 c = musb->dma_controller;
1658
Ajay Kumar Guptaf82a6892008-10-29 15:10:31 +02001659 if (usb_pipeisoc(pipe)) {
Felipe Balbi8b4959d2009-12-04 15:47:47 +02001660 int d_status = 0;
Ajay Kumar Guptaf82a6892008-10-29 15:10:31 +02001661 struct usb_iso_packet_descriptor *d;
1662
1663 d = urb->iso_frame_desc + qh->iso_idx;
1664
1665 if (iso_err) {
Felipe Balbi8b4959d2009-12-04 15:47:47 +02001666 d_status = -EILSEQ;
Ajay Kumar Guptaf82a6892008-10-29 15:10:31 +02001667 urb->error_count++;
1668 }
1669 if (rx_count > d->length) {
Felipe Balbi8b4959d2009-12-04 15:47:47 +02001670 if (d_status == 0) {
1671 d_status = -EOVERFLOW;
Ajay Kumar Guptaf82a6892008-10-29 15:10:31 +02001672 urb->error_count++;
1673 }
1674 DBG(2, "** OVERFLOW %d into %d\n",\
1675 rx_count, d->length);
1676
1677 length = d->length;
1678 } else
1679 length = rx_count;
Felipe Balbi8b4959d2009-12-04 15:47:47 +02001680 d->status = d_status;
Ajay Kumar Guptaf82a6892008-10-29 15:10:31 +02001681 buf = urb->transfer_dma + d->offset;
1682 } else {
1683 length = rx_count;
1684 buf = urb->transfer_dma +
1685 urb->actual_length;
1686 }
1687
Felipe Balbi550a7372008-07-24 12:27:36 +03001688 dma->desired_mode = 0;
1689#ifdef USE_MODE1
1690 /* because of the issue below, mode 1 will
1691 * only rarely behave with correct semantics.
1692 */
1693 if ((urb->transfer_flags &
1694 URB_SHORT_NOT_OK)
1695 && (urb->transfer_buffer_length -
1696 urb->actual_length)
1697 > qh->maxpacket)
1698 dma->desired_mode = 1;
Ajay Kumar Guptaf82a6892008-10-29 15:10:31 +02001699 if (rx_count < hw_ep->max_packet_sz_rx) {
1700 length = rx_count;
Sonic Zhangae926972010-03-08 11:26:01 -05001701 dma->desired_mode = 0;
Ajay Kumar Guptaf82a6892008-10-29 15:10:31 +02001702 } else {
1703 length = urb->transfer_buffer_length;
1704 }
Felipe Balbi550a7372008-07-24 12:27:36 +03001705#endif
1706
1707/* Disadvantage of using mode 1:
1708 * It's basically usable only for mass storage class; essentially all
1709 * other protocols also terminate transfers on short packets.
1710 *
1711 * Details:
1712 * An extra IN token is sent at the end of the transfer (due to AUTOREQ)
1713 * If you try to use mode 1 for (transfer_buffer_length - 512), and try
1714 * to use the extra IN token to grab the last packet using mode 0, then
1715 * the problem is that you cannot be sure when the device will send the
1716 * last packet and RxPktRdy set. Sometimes the packet is recd too soon
1717 * such that it gets lost when RxCSR is re-set at the end of the mode 1
1718 * transfer, while sometimes it is recd just a little late so that if you
1719 * try to configure for mode 0 soon after the mode 1 transfer is
1720 * completed, you will find rxcount 0. Okay, so you might think why not
1721 * wait for an interrupt when the pkt is recd. Well, you won't get any!
1722 */
1723
1724 val = musb_readw(epio, MUSB_RXCSR);
1725 val &= ~MUSB_RXCSR_H_REQPKT;
1726
1727 if (dma->desired_mode == 0)
1728 val &= ~MUSB_RXCSR_H_AUTOREQ;
1729 else
1730 val |= MUSB_RXCSR_H_AUTOREQ;
Ajay Kumar Guptaa483d702009-04-03 16:16:17 -07001731 val |= MUSB_RXCSR_DMAENAB;
1732
1733 /* autoclear shouldn't be set in high bandwidth */
1734 if (qh->hb_mult == 1)
1735 val |= MUSB_RXCSR_AUTOCLEAR;
Felipe Balbi550a7372008-07-24 12:27:36 +03001736
1737 musb_writew(epio, MUSB_RXCSR,
1738 MUSB_RXCSR_H_WZC_BITS | val);
1739
1740 /* REVISIT if when actual_length != 0,
1741 * transfer_buffer_length needs to be
1742 * adjusted first...
1743 */
1744 ret = c->channel_program(
1745 dma, qh->maxpacket,
Ajay Kumar Guptaf82a6892008-10-29 15:10:31 +02001746 dma->desired_mode, buf, length);
Felipe Balbi550a7372008-07-24 12:27:36 +03001747
1748 if (!ret) {
1749 c->channel_release(dma);
1750 hw_ep->rx_channel = NULL;
1751 dma = NULL;
1752 /* REVISIT reset CSR */
1753 }
1754 }
1755#endif /* Mentor DMA */
1756
1757 if (!dma) {
Maulik Mankad496dda72010-09-24 13:44:06 +03001758 /* Unmap the buffer so that CPU can use it */
1759 unmap_urb_for_dma(musb_to_hcd(musb), urb);
Felipe Balbi550a7372008-07-24 12:27:36 +03001760 done = musb_host_packet_rx(musb, urb,
1761 epnum, iso_err);
1762 DBG(6, "read %spacket\n", done ? "last " : "");
1763 }
1764 }
1765
Felipe Balbi550a7372008-07-24 12:27:36 +03001766finish:
1767 urb->actual_length += xfer_len;
1768 qh->offset += xfer_len;
1769 if (done) {
1770 if (urb->status == -EINPROGRESS)
1771 urb->status = status;
1772 musb_advance_schedule(musb, urb, hw_ep, USB_DIR_IN);
1773 }
1774}
1775
1776/* schedule nodes correspond to peripheral endpoints, like an OHCI QH.
1777 * the software schedule associates multiple such nodes with a given
1778 * host side hardware endpoint + direction; scheduling may activate
1779 * that hardware endpoint.
1780 */
1781static int musb_schedule(
1782 struct musb *musb,
1783 struct musb_qh *qh,
1784 int is_in)
1785{
1786 int idle;
1787 int best_diff;
1788 int best_end, epnum;
1789 struct musb_hw_ep *hw_ep = NULL;
1790 struct list_head *head = NULL;
Swaminathan S5274dab2009-12-28 13:40:37 +02001791 u8 toggle;
1792 u8 txtype;
1793 struct urb *urb = next_urb(qh);
Felipe Balbi550a7372008-07-24 12:27:36 +03001794
1795 /* use fixed hardware for control and bulk */
Ajay Kumar Gupta23d15e02008-10-29 15:10:35 +02001796 if (qh->type == USB_ENDPOINT_XFER_CONTROL) {
Felipe Balbi550a7372008-07-24 12:27:36 +03001797 head = &musb->control;
1798 hw_ep = musb->control_ep;
Felipe Balbi550a7372008-07-24 12:27:36 +03001799 goto success;
1800 }
1801
1802 /* else, periodic transfers get muxed to other endpoints */
1803
Sergei Shtylyov5d67a852009-02-24 15:23:34 -08001804 /*
1805 * We know this qh hasn't been scheduled, so all we need to do
Felipe Balbi550a7372008-07-24 12:27:36 +03001806 * is choose which hardware endpoint to put it on ...
1807 *
1808 * REVISIT what we really want here is a regular schedule tree
Sergei Shtylyov5d67a852009-02-24 15:23:34 -08001809 * like e.g. OHCI uses.
Felipe Balbi550a7372008-07-24 12:27:36 +03001810 */
1811 best_diff = 4096;
1812 best_end = -1;
1813
Sergei Shtylyov5d67a852009-02-24 15:23:34 -08001814 for (epnum = 1, hw_ep = musb->endpoints + 1;
1815 epnum < musb->nr_endpoints;
1816 epnum++, hw_ep++) {
Felipe Balbi550a7372008-07-24 12:27:36 +03001817 int diff;
1818
Sergei Shtylyov3e5c6dc2009-03-27 12:55:16 -07001819 if (musb_ep_get_qh(hw_ep, is_in) != NULL)
Felipe Balbi550a7372008-07-24 12:27:36 +03001820 continue;
Sergei Shtylyov5d67a852009-02-24 15:23:34 -08001821
Felipe Balbi550a7372008-07-24 12:27:36 +03001822 if (hw_ep == musb->bulk_ep)
1823 continue;
1824
1825 if (is_in)
Ajay Kumar Guptaa483d702009-04-03 16:16:17 -07001826 diff = hw_ep->max_packet_sz_rx;
Felipe Balbi550a7372008-07-24 12:27:36 +03001827 else
Ajay Kumar Guptaa483d702009-04-03 16:16:17 -07001828 diff = hw_ep->max_packet_sz_tx;
1829 diff -= (qh->maxpacket * qh->hb_mult);
Felipe Balbi550a7372008-07-24 12:27:36 +03001830
Ajay Kumar Gupta23d15e02008-10-29 15:10:35 +02001831 if (diff >= 0 && best_diff > diff) {
Swaminathan S5274dab2009-12-28 13:40:37 +02001832
1833 /*
1834 * Mentor controller has a bug in that if we schedule
1835 * a BULK Tx transfer on an endpoint that had earlier
1836 * handled ISOC then the BULK transfer has to start on
1837 * a zero toggle. If the BULK transfer starts on a 1
1838 * toggle then this transfer will fail as the mentor
1839 * controller starts the Bulk transfer on a 0 toggle
1840 * irrespective of the programming of the toggle bits
1841 * in the TXCSR register. Check for this condition
1842 * while allocating the EP for a Tx Bulk transfer. If
1843 * so skip this EP.
1844 */
1845 hw_ep = musb->endpoints + epnum;
1846 toggle = usb_gettoggle(urb->dev, qh->epnum, !is_in);
1847 txtype = (musb_readb(hw_ep->regs, MUSB_TXTYPE)
1848 >> 4) & 0x3;
1849 if (!is_in && (qh->type == USB_ENDPOINT_XFER_BULK) &&
1850 toggle && (txtype == USB_ENDPOINT_XFER_ISOC))
1851 continue;
1852
Felipe Balbi550a7372008-07-24 12:27:36 +03001853 best_diff = diff;
1854 best_end = epnum;
1855 }
1856 }
Ajay Kumar Gupta23d15e02008-10-29 15:10:35 +02001857 /* use bulk reserved ep1 if no other ep is free */
Felipe Balbiaa5cbbe2008-11-17 09:08:16 +02001858 if (best_end < 0 && qh->type == USB_ENDPOINT_XFER_BULK) {
Ajay Kumar Gupta23d15e02008-10-29 15:10:35 +02001859 hw_ep = musb->bulk_ep;
1860 if (is_in)
1861 head = &musb->in_bulk;
1862 else
1863 head = &musb->out_bulk;
Ajay Kumar Gupta1e0320f2009-02-24 15:26:13 -08001864
1865 /* Enable bulk RX NAK timeout scheme when bulk requests are
1866 * multiplexed. This scheme doen't work in high speed to full
1867 * speed scenario as NAK interrupts are not coming from a
1868 * full speed device connected to a high speed device.
1869 * NAK timeout interval is 8 (128 uframe or 16ms) for HS and
1870 * 4 (8 frame or 8ms) for FS device.
1871 */
1872 if (is_in && qh->dev)
1873 qh->intv_reg =
1874 (USB_SPEED_HIGH == qh->dev->speed) ? 8 : 4;
Ajay Kumar Gupta23d15e02008-10-29 15:10:35 +02001875 goto success;
1876 } else if (best_end < 0) {
Felipe Balbi550a7372008-07-24 12:27:36 +03001877 return -ENOSPC;
Ajay Kumar Gupta23d15e02008-10-29 15:10:35 +02001878 }
Felipe Balbi550a7372008-07-24 12:27:36 +03001879
1880 idle = 1;
Ajay Kumar Gupta23d15e02008-10-29 15:10:35 +02001881 qh->mux = 0;
Felipe Balbi550a7372008-07-24 12:27:36 +03001882 hw_ep = musb->endpoints + best_end;
Felipe Balbi550a7372008-07-24 12:27:36 +03001883 DBG(4, "qh %p periodic slot %d\n", qh, best_end);
1884success:
Ajay Kumar Gupta23d15e02008-10-29 15:10:35 +02001885 if (head) {
1886 idle = list_empty(head);
1887 list_add_tail(&qh->ring, head);
1888 qh->mux = 1;
1889 }
Felipe Balbi550a7372008-07-24 12:27:36 +03001890 qh->hw_ep = hw_ep;
1891 qh->hep->hcpriv = qh;
1892 if (idle)
1893 musb_start_urb(musb, is_in, qh);
1894 return 0;
1895}
1896
1897static int musb_urb_enqueue(
1898 struct usb_hcd *hcd,
1899 struct urb *urb,
1900 gfp_t mem_flags)
1901{
1902 unsigned long flags;
1903 struct musb *musb = hcd_to_musb(hcd);
1904 struct usb_host_endpoint *hep = urb->ep;
David Brownell74bb3502009-03-26 17:36:57 -07001905 struct musb_qh *qh;
Felipe Balbi550a7372008-07-24 12:27:36 +03001906 struct usb_endpoint_descriptor *epd = &hep->desc;
1907 int ret;
1908 unsigned type_reg;
1909 unsigned interval;
1910
1911 /* host role must be active */
1912 if (!is_host_active(musb) || !musb->is_active)
1913 return -ENODEV;
1914
1915 spin_lock_irqsave(&musb->lock, flags);
1916 ret = usb_hcd_link_urb_to_ep(hcd, urb);
David Brownell74bb3502009-03-26 17:36:57 -07001917 qh = ret ? NULL : hep->hcpriv;
1918 if (qh)
1919 urb->hcpriv = qh;
Felipe Balbi550a7372008-07-24 12:27:36 +03001920 spin_unlock_irqrestore(&musb->lock, flags);
Felipe Balbi550a7372008-07-24 12:27:36 +03001921
1922 /* DMA mapping was already done, if needed, and this urb is on
David Brownell74bb3502009-03-26 17:36:57 -07001923 * hep->urb_list now ... so we're done, unless hep wasn't yet
1924 * scheduled onto a live qh.
Felipe Balbi550a7372008-07-24 12:27:36 +03001925 *
1926 * REVISIT best to keep hep->hcpriv valid until the endpoint gets
1927 * disabled, testing for empty qh->ring and avoiding qh setup costs
1928 * except for the first urb queued after a config change.
1929 */
David Brownell74bb3502009-03-26 17:36:57 -07001930 if (qh || ret)
1931 return ret;
Felipe Balbi550a7372008-07-24 12:27:36 +03001932
1933 /* Allocate and initialize qh, minimizing the work done each time
1934 * hw_ep gets reprogrammed, or with irqs blocked. Then schedule it.
1935 *
1936 * REVISIT consider a dedicated qh kmem_cache, so it's harder
1937 * for bugs in other kernel code to break this driver...
1938 */
1939 qh = kzalloc(sizeof *qh, mem_flags);
1940 if (!qh) {
Ajay Kumar Gupta2492e672008-09-11 11:53:21 +03001941 spin_lock_irqsave(&musb->lock, flags);
Felipe Balbi550a7372008-07-24 12:27:36 +03001942 usb_hcd_unlink_urb_from_ep(hcd, urb);
Ajay Kumar Gupta2492e672008-09-11 11:53:21 +03001943 spin_unlock_irqrestore(&musb->lock, flags);
Felipe Balbi550a7372008-07-24 12:27:36 +03001944 return -ENOMEM;
1945 }
1946
1947 qh->hep = hep;
1948 qh->dev = urb->dev;
1949 INIT_LIST_HEAD(&qh->ring);
1950 qh->is_ready = 1;
1951
1952 qh->maxpacket = le16_to_cpu(epd->wMaxPacketSize);
Ajay Kumar Guptaa483d702009-04-03 16:16:17 -07001953 qh->type = usb_endpoint_type(epd);
Felipe Balbi550a7372008-07-24 12:27:36 +03001954
Ajay Kumar Guptaa483d702009-04-03 16:16:17 -07001955 /* Bits 11 & 12 of wMaxPacketSize encode high bandwidth multiplier.
1956 * Some musb cores don't support high bandwidth ISO transfers; and
1957 * we don't (yet!) support high bandwidth interrupt transfers.
1958 */
1959 qh->hb_mult = 1 + ((qh->maxpacket >> 11) & 0x03);
1960 if (qh->hb_mult > 1) {
1961 int ok = (qh->type == USB_ENDPOINT_XFER_ISOC);
1962
1963 if (ok)
1964 ok = (usb_pipein(urb->pipe) && musb->hb_iso_rx)
1965 || (usb_pipeout(urb->pipe) && musb->hb_iso_tx);
1966 if (!ok) {
1967 ret = -EMSGSIZE;
1968 goto done;
1969 }
1970 qh->maxpacket &= 0x7ff;
Felipe Balbi550a7372008-07-24 12:27:36 +03001971 }
1972
Julia Lawall96bcd092009-01-24 17:57:24 -08001973 qh->epnum = usb_endpoint_num(epd);
Felipe Balbi550a7372008-07-24 12:27:36 +03001974
1975 /* NOTE: urb->dev->devnum is wrong during SET_ADDRESS */
1976 qh->addr_reg = (u8) usb_pipedevice(urb->pipe);
1977
1978 /* precompute rxtype/txtype/type0 register */
1979 type_reg = (qh->type << 4) | qh->epnum;
1980 switch (urb->dev->speed) {
1981 case USB_SPEED_LOW:
1982 type_reg |= 0xc0;
1983 break;
1984 case USB_SPEED_FULL:
1985 type_reg |= 0x80;
1986 break;
1987 default:
1988 type_reg |= 0x40;
1989 }
1990 qh->type_reg = type_reg;
1991
Sergei Shtylyov136733d2009-02-21 15:31:35 -08001992 /* Precompute RXINTERVAL/TXINTERVAL register */
Felipe Balbi550a7372008-07-24 12:27:36 +03001993 switch (qh->type) {
1994 case USB_ENDPOINT_XFER_INT:
Sergei Shtylyov136733d2009-02-21 15:31:35 -08001995 /*
1996 * Full/low speeds use the linear encoding,
1997 * high speed uses the logarithmic encoding.
1998 */
1999 if (urb->dev->speed <= USB_SPEED_FULL) {
2000 interval = max_t(u8, epd->bInterval, 1);
2001 break;
Felipe Balbi550a7372008-07-24 12:27:36 +03002002 }
2003 /* FALLTHROUGH */
2004 case USB_ENDPOINT_XFER_ISOC:
Sergei Shtylyov136733d2009-02-21 15:31:35 -08002005 /* ISO always uses logarithmic encoding */
2006 interval = min_t(u8, epd->bInterval, 16);
Felipe Balbi550a7372008-07-24 12:27:36 +03002007 break;
2008 default:
2009 /* REVISIT we actually want to use NAK limits, hinting to the
2010 * transfer scheduling logic to try some other qh, e.g. try
2011 * for 2 msec first:
2012 *
2013 * interval = (USB_SPEED_HIGH == urb->dev->speed) ? 16 : 2;
2014 *
2015 * The downside of disabling this is that transfer scheduling
2016 * gets VERY unfair for nonperiodic transfers; a misbehaving
Ajay Kumar Gupta1e0320f2009-02-24 15:26:13 -08002017 * peripheral could make that hurt. That's perfectly normal
2018 * for reads from network or serial adapters ... so we have
2019 * partial NAKlimit support for bulk RX.
Felipe Balbi550a7372008-07-24 12:27:36 +03002020 *
Ajay Kumar Gupta1e0320f2009-02-24 15:26:13 -08002021 * The upside of disabling it is simpler transfer scheduling.
Felipe Balbi550a7372008-07-24 12:27:36 +03002022 */
2023 interval = 0;
2024 }
2025 qh->intv_reg = interval;
2026
2027 /* precompute addressing for external hub/tt ports */
2028 if (musb->is_multipoint) {
2029 struct usb_device *parent = urb->dev->parent;
2030
2031 if (parent != hcd->self.root_hub) {
2032 qh->h_addr_reg = (u8) parent->devnum;
2033
2034 /* set up tt info if needed */
2035 if (urb->dev->tt) {
2036 qh->h_port_reg = (u8) urb->dev->ttport;
Ajay Kumar Guptaae5ad292008-09-11 11:53:20 +03002037 if (urb->dev->tt->hub)
2038 qh->h_addr_reg =
2039 (u8) urb->dev->tt->hub->devnum;
2040 if (urb->dev->tt->multi)
2041 qh->h_addr_reg |= 0x80;
Felipe Balbi550a7372008-07-24 12:27:36 +03002042 }
2043 }
2044 }
2045
2046 /* invariant: hep->hcpriv is null OR the qh that's already scheduled.
2047 * until we get real dma queues (with an entry for each urb/buffer),
2048 * we only have work to do in the former case.
2049 */
2050 spin_lock_irqsave(&musb->lock, flags);
2051 if (hep->hcpriv) {
2052 /* some concurrent activity submitted another urb to hep...
2053 * odd, rare, error prone, but legal.
2054 */
2055 kfree(qh);
Dan Carpenter714bc5e2010-03-25 13:14:27 +02002056 qh = NULL;
Felipe Balbi550a7372008-07-24 12:27:36 +03002057 ret = 0;
2058 } else
2059 ret = musb_schedule(musb, qh,
2060 epd->bEndpointAddress & USB_ENDPOINT_DIR_MASK);
2061
2062 if (ret == 0) {
2063 urb->hcpriv = qh;
2064 /* FIXME set urb->start_frame for iso/intr, it's tested in
2065 * musb_start_urb(), but otherwise only konicawc cares ...
2066 */
2067 }
2068 spin_unlock_irqrestore(&musb->lock, flags);
2069
2070done:
2071 if (ret != 0) {
Ajay Kumar Gupta2492e672008-09-11 11:53:21 +03002072 spin_lock_irqsave(&musb->lock, flags);
Felipe Balbi550a7372008-07-24 12:27:36 +03002073 usb_hcd_unlink_urb_from_ep(hcd, urb);
Ajay Kumar Gupta2492e672008-09-11 11:53:21 +03002074 spin_unlock_irqrestore(&musb->lock, flags);
Felipe Balbi550a7372008-07-24 12:27:36 +03002075 kfree(qh);
2076 }
2077 return ret;
2078}
2079
2080
2081/*
2082 * abort a transfer that's at the head of a hardware queue.
2083 * called with controller locked, irqs blocked
2084 * that hardware queue advances to the next transfer, unless prevented
2085 */
Sergei Shtylyov81ec4e42009-03-27 12:57:50 -07002086static int musb_cleanup_urb(struct urb *urb, struct musb_qh *qh)
Felipe Balbi550a7372008-07-24 12:27:36 +03002087{
2088 struct musb_hw_ep *ep = qh->hw_ep;
2089 void __iomem *epio = ep->regs;
2090 unsigned hw_end = ep->epnum;
2091 void __iomem *regs = ep->musb->mregs;
Sergei Shtylyov81ec4e42009-03-27 12:57:50 -07002092 int is_in = usb_pipein(urb->pipe);
Felipe Balbi550a7372008-07-24 12:27:36 +03002093 int status = 0;
Sergei Shtylyov81ec4e42009-03-27 12:57:50 -07002094 u16 csr;
Felipe Balbi550a7372008-07-24 12:27:36 +03002095
2096 musb_ep_select(regs, hw_end);
2097
2098 if (is_dma_capable()) {
2099 struct dma_channel *dma;
2100
2101 dma = is_in ? ep->rx_channel : ep->tx_channel;
2102 if (dma) {
2103 status = ep->musb->dma_controller->channel_abort(dma);
2104 DBG(status ? 1 : 3,
2105 "abort %cX%d DMA for urb %p --> %d\n",
2106 is_in ? 'R' : 'T', ep->epnum,
2107 urb, status);
2108 urb->actual_length += dma->actual_len;
2109 }
2110 }
2111
2112 /* turn off DMA requests, discard state, stop polling ... */
2113 if (is_in) {
2114 /* giveback saves bulk toggle */
2115 csr = musb_h_flush_rxfifo(ep, 0);
2116
2117 /* REVISIT we still get an irq; should likely clear the
2118 * endpoint's irq status here to avoid bogus irqs.
2119 * clearing that status is platform-specific...
2120 */
David Brownell78322c12009-03-26 17:38:30 -07002121 } else if (ep->epnum) {
Felipe Balbi550a7372008-07-24 12:27:36 +03002122 musb_h_tx_flush_fifo(ep);
2123 csr = musb_readw(epio, MUSB_TXCSR);
2124 csr &= ~(MUSB_TXCSR_AUTOSET
2125 | MUSB_TXCSR_DMAENAB
2126 | MUSB_TXCSR_H_RXSTALL
2127 | MUSB_TXCSR_H_NAKTIMEOUT
2128 | MUSB_TXCSR_H_ERROR
2129 | MUSB_TXCSR_TXPKTRDY);
2130 musb_writew(epio, MUSB_TXCSR, csr);
2131 /* REVISIT may need to clear FLUSHFIFO ... */
2132 musb_writew(epio, MUSB_TXCSR, csr);
2133 /* flush cpu writebuffer */
2134 csr = musb_readw(epio, MUSB_TXCSR);
David Brownell78322c12009-03-26 17:38:30 -07002135 } else {
2136 musb_h_ep0_flush_fifo(ep);
Felipe Balbi550a7372008-07-24 12:27:36 +03002137 }
2138 if (status == 0)
2139 musb_advance_schedule(ep->musb, urb, ep, is_in);
2140 return status;
2141}
2142
2143static int musb_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
2144{
2145 struct musb *musb = hcd_to_musb(hcd);
2146 struct musb_qh *qh;
Felipe Balbi550a7372008-07-24 12:27:36 +03002147 unsigned long flags;
Sergei Shtylyov22a0d6f2009-03-27 12:56:26 -07002148 int is_in = usb_pipein(urb->pipe);
Felipe Balbi550a7372008-07-24 12:27:36 +03002149 int ret;
2150
2151 DBG(4, "urb=%p, dev%d ep%d%s\n", urb,
2152 usb_pipedevice(urb->pipe),
2153 usb_pipeendpoint(urb->pipe),
Sergei Shtylyov22a0d6f2009-03-27 12:56:26 -07002154 is_in ? "in" : "out");
Felipe Balbi550a7372008-07-24 12:27:36 +03002155
2156 spin_lock_irqsave(&musb->lock, flags);
2157 ret = usb_hcd_check_unlink_urb(hcd, urb, status);
2158 if (ret)
2159 goto done;
2160
2161 qh = urb->hcpriv;
2162 if (!qh)
2163 goto done;
2164
Sergei Shtylyov22a0d6f2009-03-27 12:56:26 -07002165 /*
2166 * Any URB not actively programmed into endpoint hardware can be
Sergei Shtylyova2fd8142009-02-21 15:30:45 -08002167 * immediately given back; that's any URB not at the head of an
Felipe Balbi550a7372008-07-24 12:27:36 +03002168 * endpoint queue, unless someday we get real DMA queues. And even
Sergei Shtylyova2fd8142009-02-21 15:30:45 -08002169 * if it's at the head, it might not be known to the hardware...
Felipe Balbi550a7372008-07-24 12:27:36 +03002170 *
Sergei Shtylyov22a0d6f2009-03-27 12:56:26 -07002171 * Otherwise abort current transfer, pending DMA, etc.; urb->status
Felipe Balbi550a7372008-07-24 12:27:36 +03002172 * has already been updated. This is a synchronous abort; it'd be
2173 * OK to hold off until after some IRQ, though.
Sergei Shtylyov22a0d6f2009-03-27 12:56:26 -07002174 *
2175 * NOTE: qh is invalid unless !list_empty(&hep->urb_list)
Felipe Balbi550a7372008-07-24 12:27:36 +03002176 */
Sergei Shtylyov22a0d6f2009-03-27 12:56:26 -07002177 if (!qh->is_ready
2178 || urb->urb_list.prev != &qh->hep->urb_list
2179 || musb_ep_get_qh(qh->hw_ep, is_in) != qh) {
Felipe Balbi550a7372008-07-24 12:27:36 +03002180 int ready = qh->is_ready;
2181
Felipe Balbi550a7372008-07-24 12:27:36 +03002182 qh->is_ready = 0;
Sergei Shtylyovc9cd06b2009-03-27 12:58:31 -07002183 musb_giveback(musb, urb, 0);
Felipe Balbi550a7372008-07-24 12:27:36 +03002184 qh->is_ready = ready;
Sergei Shtylyova2fd8142009-02-21 15:30:45 -08002185
2186 /* If nothing else (usually musb_giveback) is using it
2187 * and its URB list has emptied, recycle this qh.
2188 */
2189 if (ready && list_empty(&qh->hep->urb_list)) {
2190 qh->hep->hcpriv = NULL;
2191 list_del(&qh->ring);
2192 kfree(qh);
2193 }
Felipe Balbi550a7372008-07-24 12:27:36 +03002194 } else
Sergei Shtylyov81ec4e42009-03-27 12:57:50 -07002195 ret = musb_cleanup_urb(urb, qh);
Felipe Balbi550a7372008-07-24 12:27:36 +03002196done:
2197 spin_unlock_irqrestore(&musb->lock, flags);
2198 return ret;
2199}
2200
2201/* disable an endpoint */
2202static void
2203musb_h_disable(struct usb_hcd *hcd, struct usb_host_endpoint *hep)
2204{
Sergei Shtylyov22a0d6f2009-03-27 12:56:26 -07002205 u8 is_in = hep->desc.bEndpointAddress & USB_DIR_IN;
Felipe Balbi550a7372008-07-24 12:27:36 +03002206 unsigned long flags;
2207 struct musb *musb = hcd_to_musb(hcd);
Sergei Shtylyovdc61d232009-02-21 15:31:01 -08002208 struct musb_qh *qh;
2209 struct urb *urb;
Felipe Balbi550a7372008-07-24 12:27:36 +03002210
Felipe Balbi550a7372008-07-24 12:27:36 +03002211 spin_lock_irqsave(&musb->lock, flags);
2212
Sergei Shtylyovdc61d232009-02-21 15:31:01 -08002213 qh = hep->hcpriv;
2214 if (qh == NULL)
2215 goto exit;
2216
Sergei Shtylyov22a0d6f2009-03-27 12:56:26 -07002217 /* NOTE: qh is invalid unless !list_empty(&hep->urb_list) */
Felipe Balbi550a7372008-07-24 12:27:36 +03002218
Sergei Shtylyov22a0d6f2009-03-27 12:56:26 -07002219 /* Kick the first URB off the hardware, if needed */
Felipe Balbi550a7372008-07-24 12:27:36 +03002220 qh->is_ready = 0;
Sergei Shtylyov22a0d6f2009-03-27 12:56:26 -07002221 if (musb_ep_get_qh(qh->hw_ep, is_in) == qh) {
Felipe Balbi550a7372008-07-24 12:27:36 +03002222 urb = next_urb(qh);
2223
2224 /* make software (then hardware) stop ASAP */
2225 if (!urb->unlinked)
2226 urb->status = -ESHUTDOWN;
2227
2228 /* cleanup */
Sergei Shtylyov81ec4e42009-03-27 12:57:50 -07002229 musb_cleanup_urb(urb, qh);
Felipe Balbi550a7372008-07-24 12:27:36 +03002230
Sergei Shtylyovdc61d232009-02-21 15:31:01 -08002231 /* Then nuke all the others ... and advance the
2232 * queue on hw_ep (e.g. bulk ring) when we're done.
2233 */
2234 while (!list_empty(&hep->urb_list)) {
2235 urb = next_urb(qh);
2236 urb->status = -ESHUTDOWN;
2237 musb_advance_schedule(musb, urb, qh->hw_ep, is_in);
2238 }
2239 } else {
2240 /* Just empty the queue; the hardware is busy with
2241 * other transfers, and since !qh->is_ready nothing
2242 * will activate any of these as it advances.
2243 */
2244 while (!list_empty(&hep->urb_list))
Sergei Shtylyovc9cd06b2009-03-27 12:58:31 -07002245 musb_giveback(musb, next_urb(qh), -ESHUTDOWN);
Felipe Balbi550a7372008-07-24 12:27:36 +03002246
Sergei Shtylyovdc61d232009-02-21 15:31:01 -08002247 hep->hcpriv = NULL;
2248 list_del(&qh->ring);
2249 kfree(qh);
2250 }
2251exit:
Felipe Balbi550a7372008-07-24 12:27:36 +03002252 spin_unlock_irqrestore(&musb->lock, flags);
2253}
2254
2255static int musb_h_get_frame_number(struct usb_hcd *hcd)
2256{
2257 struct musb *musb = hcd_to_musb(hcd);
2258
2259 return musb_readw(musb->mregs, MUSB_FRAME);
2260}
2261
2262static int musb_h_start(struct usb_hcd *hcd)
2263{
2264 struct musb *musb = hcd_to_musb(hcd);
2265
2266 /* NOTE: musb_start() is called when the hub driver turns
2267 * on port power, or when (OTG) peripheral starts.
2268 */
2269 hcd->state = HC_STATE_RUNNING;
2270 musb->port1_status = 0;
2271 return 0;
2272}
2273
2274static void musb_h_stop(struct usb_hcd *hcd)
2275{
2276 musb_stop(hcd_to_musb(hcd));
2277 hcd->state = HC_STATE_HALT;
2278}
2279
2280static int musb_bus_suspend(struct usb_hcd *hcd)
2281{
2282 struct musb *musb = hcd_to_musb(hcd);
David Brownell89368d32009-07-01 03:36:16 -07002283 u8 devctl;
Felipe Balbi550a7372008-07-24 12:27:36 +03002284
David Brownell89368d32009-07-01 03:36:16 -07002285 if (!is_host_active(musb))
Felipe Balbi550a7372008-07-24 12:27:36 +03002286 return 0;
2287
David Brownell89368d32009-07-01 03:36:16 -07002288 switch (musb->xceiv->state) {
2289 case OTG_STATE_A_SUSPEND:
2290 return 0;
2291 case OTG_STATE_A_WAIT_VRISE:
2292 /* ID could be grounded even if there's no device
2293 * on the other end of the cable. NOTE that the
2294 * A_WAIT_VRISE timers are messy with MUSB...
2295 */
2296 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
2297 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
2298 musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
2299 break;
2300 default:
2301 break;
2302 }
2303
2304 if (musb->is_active) {
2305 WARNING("trying to suspend as %s while active\n",
2306 otg_state_string(musb));
Felipe Balbi550a7372008-07-24 12:27:36 +03002307 return -EBUSY;
2308 } else
2309 return 0;
2310}
2311
2312static int musb_bus_resume(struct usb_hcd *hcd)
2313{
2314 /* resuming child port does the work */
2315 return 0;
2316}
2317
2318const struct hc_driver musb_hc_driver = {
2319 .description = "musb-hcd",
2320 .product_desc = "MUSB HDRC host driver",
2321 .hcd_priv_size = sizeof(struct musb),
2322 .flags = HCD_USB2 | HCD_MEMORY,
2323
2324 /* not using irq handler or reset hooks from usbcore, since
2325 * those must be shared with peripheral code for OTG configs
2326 */
2327
2328 .start = musb_h_start,
2329 .stop = musb_h_stop,
2330
2331 .get_frame_number = musb_h_get_frame_number,
2332
2333 .urb_enqueue = musb_urb_enqueue,
2334 .urb_dequeue = musb_urb_dequeue,
2335 .endpoint_disable = musb_h_disable,
2336
2337 .hub_status_data = musb_hub_status_data,
2338 .hub_control = musb_hub_control,
2339 .bus_suspend = musb_bus_suspend,
2340 .bus_resume = musb_bus_resume,
2341 /* .start_port_reset = NULL, */
2342 /* .hub_irq_enable = NULL, */
2343};