Mike Rapoport | a7f3f03 | 2008-10-05 10:26:55 +0100 | [diff] [blame] | 1 | /* |
| 2 | * linux/arch/arm/mach-pxa/cm-x255.c |
| 3 | * |
| 4 | * Copyright (C) 2007, 2008 CompuLab, Ltd. |
| 5 | * Mike Rapoport <mike@compulab.co.il> |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License version 2 as |
| 9 | * published by the Free Software Foundation. |
| 10 | */ |
| 11 | |
| 12 | #include <linux/platform_device.h> |
| 13 | #include <linux/irq.h> |
| 14 | #include <linux/gpio.h> |
Mike Rapoport | 49a7061 | 2008-10-05 10:29:59 +0100 | [diff] [blame^] | 15 | #include <linux/mtd/partitions.h> |
| 16 | #include <linux/mtd/physmap.h> |
| 17 | #include <linux/mtd/nand-gpio.h> |
Mike Rapoport | a7f3f03 | 2008-10-05 10:26:55 +0100 | [diff] [blame] | 18 | |
| 19 | #include <linux/spi/spi.h> |
| 20 | |
| 21 | #include <asm/mach/arch.h> |
| 22 | #include <asm/mach-types.h> |
| 23 | #include <asm/mach/map.h> |
| 24 | |
| 25 | #include <mach/pxa2xx-regs.h> |
| 26 | #include <mach/mfp-pxa25x.h> |
| 27 | #include <mach/pxa2xx_spi.h> |
| 28 | #include <mach/bitfield.h> |
| 29 | |
| 30 | #include "generic.h" |
| 31 | |
Mike Rapoport | 49a7061 | 2008-10-05 10:29:59 +0100 | [diff] [blame^] | 32 | #define GPIO_NAND_CS (5) |
| 33 | #define GPIO_NAND_ALE (4) |
| 34 | #define GPIO_NAND_CLE (3) |
| 35 | #define GPIO_NAND_RB (10) |
| 36 | |
Mike Rapoport | a7f3f03 | 2008-10-05 10:26:55 +0100 | [diff] [blame] | 37 | static unsigned long cmx255_pin_config[] = { |
| 38 | /* AC'97 */ |
| 39 | GPIO28_AC97_BITCLK, |
| 40 | GPIO29_AC97_SDATA_IN_0, |
| 41 | GPIO30_AC97_SDATA_OUT, |
| 42 | GPIO31_AC97_SYNC, |
| 43 | |
| 44 | /* BTUART */ |
| 45 | GPIO42_BTUART_RXD, |
| 46 | GPIO43_BTUART_TXD, |
| 47 | GPIO44_BTUART_CTS, |
| 48 | GPIO45_BTUART_RTS, |
| 49 | |
| 50 | /* STUART */ |
| 51 | GPIO46_STUART_RXD, |
| 52 | GPIO47_STUART_TXD, |
| 53 | |
| 54 | /* LCD */ |
| 55 | GPIO58_LCD_LDD_0, |
| 56 | GPIO59_LCD_LDD_1, |
| 57 | GPIO60_LCD_LDD_2, |
| 58 | GPIO61_LCD_LDD_3, |
| 59 | GPIO62_LCD_LDD_4, |
| 60 | GPIO63_LCD_LDD_5, |
| 61 | GPIO64_LCD_LDD_6, |
| 62 | GPIO65_LCD_LDD_7, |
| 63 | GPIO66_LCD_LDD_8, |
| 64 | GPIO67_LCD_LDD_9, |
| 65 | GPIO68_LCD_LDD_10, |
| 66 | GPIO69_LCD_LDD_11, |
| 67 | GPIO70_LCD_LDD_12, |
| 68 | GPIO71_LCD_LDD_13, |
| 69 | GPIO72_LCD_LDD_14, |
| 70 | GPIO73_LCD_LDD_15, |
| 71 | GPIO74_LCD_FCLK, |
| 72 | GPIO75_LCD_LCLK, |
| 73 | GPIO76_LCD_PCLK, |
| 74 | GPIO77_LCD_BIAS, |
| 75 | |
| 76 | /* SSP1 */ |
| 77 | GPIO23_SSP1_SCLK, |
| 78 | GPIO24_SSP1_SFRM, |
| 79 | GPIO25_SSP1_TXD, |
| 80 | GPIO26_SSP1_RXD, |
| 81 | |
| 82 | /* SSP2 */ |
| 83 | GPIO81_SSP2_CLK_OUT, |
| 84 | GPIO82_SSP2_FRM_OUT, |
| 85 | GPIO83_SSP2_TXD, |
| 86 | GPIO84_SSP2_RXD, |
| 87 | |
| 88 | /* PC Card */ |
| 89 | GPIO48_nPOE, |
| 90 | GPIO49_nPWE, |
| 91 | GPIO50_nPIOR, |
| 92 | GPIO51_nPIOW, |
| 93 | GPIO52_nPCE_1, |
| 94 | GPIO53_nPCE_2, |
| 95 | GPIO54_nPSKTSEL, |
| 96 | GPIO55_nPREG, |
| 97 | GPIO56_nPWAIT, |
| 98 | GPIO57_nIOIS16, |
| 99 | |
| 100 | /* SDRAM and local bus */ |
| 101 | GPIO15_nCS_1, |
| 102 | GPIO78_nCS_2, |
| 103 | GPIO79_nCS_3, |
| 104 | GPIO80_nCS_4, |
| 105 | GPIO33_nCS_5, |
| 106 | GPIO18_RDY, |
| 107 | |
| 108 | /* GPIO */ |
| 109 | GPIO0_GPIO | WAKEUP_ON_EDGE_BOTH, |
| 110 | GPIO9_GPIO, /* PC card reset */ |
| 111 | |
| 112 | /* NAND controls */ |
| 113 | GPIO5_GPIO | MFP_LPM_DRIVE_HIGH, /* NAND CE# */ |
| 114 | GPIO4_GPIO | MFP_LPM_DRIVE_LOW, /* NAND ALE */ |
| 115 | GPIO3_GPIO | MFP_LPM_DRIVE_LOW, /* NAND CLE */ |
| 116 | GPIO10_GPIO, /* NAND Ready/Busy */ |
| 117 | |
| 118 | /* interrupts */ |
| 119 | GPIO22_GPIO, /* DM9000 interrupt */ |
| 120 | }; |
| 121 | |
| 122 | #if defined(CONFIG_SPI_PXA2XX) |
| 123 | static struct pxa2xx_spi_master pxa_ssp_master_info = { |
| 124 | .num_chipselect = 1, |
| 125 | }; |
| 126 | |
| 127 | static struct spi_board_info spi_board_info[] __initdata = { |
| 128 | [0] = { |
| 129 | .modalias = "rtc-max6902", |
| 130 | .max_speed_hz = 1000000, |
| 131 | .bus_num = 1, |
| 132 | .chip_select = 0, |
| 133 | }, |
| 134 | }; |
| 135 | |
| 136 | static void __init cmx255_init_rtc(void) |
| 137 | { |
| 138 | pxa2xx_set_spi_info(1, &pxa_ssp_master_info); |
| 139 | spi_register_board_info(ARRAY_AND_SIZE(spi_board_info)); |
| 140 | } |
| 141 | #else |
| 142 | static inline void cmx255_init_rtc(void) {} |
| 143 | #endif |
| 144 | |
Mike Rapoport | 49a7061 | 2008-10-05 10:29:59 +0100 | [diff] [blame^] | 145 | #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE) |
| 146 | static struct mtd_partition cmx255_nor_partitions[] = { |
| 147 | { |
| 148 | .name = "ARMmon", |
| 149 | .size = 0x00030000, |
| 150 | .offset = 0, |
| 151 | .mask_flags = MTD_WRITEABLE /* force read-only */ |
| 152 | } , { |
| 153 | .name = "ARMmon setup block", |
| 154 | .size = 0x00010000, |
| 155 | .offset = MTDPART_OFS_APPEND, |
| 156 | .mask_flags = MTD_WRITEABLE /* force read-only */ |
| 157 | } , { |
| 158 | .name = "kernel", |
| 159 | .size = 0x00160000, |
| 160 | .offset = MTDPART_OFS_APPEND, |
| 161 | } , { |
| 162 | .name = "ramdisk", |
| 163 | .size = MTDPART_SIZ_FULL, |
| 164 | .offset = MTDPART_OFS_APPEND |
| 165 | } |
| 166 | }; |
| 167 | |
| 168 | static struct physmap_flash_data cmx255_nor_flash_data[] = { |
| 169 | { |
| 170 | .width = 2, /* bankwidth in bytes */ |
| 171 | .parts = cmx255_nor_partitions, |
| 172 | .nr_parts = ARRAY_SIZE(cmx255_nor_partitions) |
| 173 | } |
| 174 | }; |
| 175 | |
| 176 | static struct resource cmx255_nor_resource = { |
| 177 | .start = PXA_CS0_PHYS, |
| 178 | .end = PXA_CS0_PHYS + SZ_8M - 1, |
| 179 | .flags = IORESOURCE_MEM, |
| 180 | }; |
| 181 | |
| 182 | static struct platform_device cmx255_nor = { |
| 183 | .name = "physmap-flash", |
| 184 | .id = -1, |
| 185 | .dev = { |
| 186 | .platform_data = cmx255_nor_flash_data, |
| 187 | }, |
| 188 | .resource = &cmx255_nor_resource, |
| 189 | .num_resources = 1, |
| 190 | }; |
| 191 | |
| 192 | static void __init cmx255_init_nor(void) |
| 193 | { |
| 194 | platform_device_register(&cmx255_nor); |
| 195 | } |
| 196 | #else |
| 197 | static inline void cmx255_init_nor(void) {} |
| 198 | #endif |
| 199 | |
| 200 | #if defined(CONFIG_MTD_NAND_GPIO) || defined(CONFIG_MTD_NAND_GPIO_MODULE) |
| 201 | static struct resource cmx255_nand_resource[] = { |
| 202 | [0] = { |
| 203 | .start = PXA_CS1_PHYS, |
| 204 | .end = PXA_CS1_PHYS + 11, |
| 205 | .flags = IORESOURCE_MEM, |
| 206 | }, |
| 207 | [1] = { |
| 208 | .start = PXA_CS5_PHYS, |
| 209 | .end = PXA_CS5_PHYS + 3, |
| 210 | .flags = IORESOURCE_MEM, |
| 211 | }, |
| 212 | }; |
| 213 | |
| 214 | static struct mtd_partition cmx255_nand_parts[] = { |
| 215 | [0] = { |
| 216 | .name = "cmx255-nand", |
| 217 | .size = MTDPART_SIZ_FULL, |
| 218 | .offset = 0, |
| 219 | }, |
| 220 | }; |
| 221 | |
| 222 | static struct gpio_nand_platdata cmx255_nand_platdata = { |
| 223 | .gpio_nce = GPIO_NAND_CS, |
| 224 | .gpio_cle = GPIO_NAND_CLE, |
| 225 | .gpio_ale = GPIO_NAND_ALE, |
| 226 | .gpio_rdy = GPIO_NAND_RB, |
| 227 | .gpio_nwp = -1, |
| 228 | .parts = cmx255_nand_parts, |
| 229 | .num_parts = ARRAY_SIZE(cmx255_nand_parts), |
| 230 | .chip_delay = 25, |
| 231 | }; |
| 232 | |
| 233 | static struct platform_device cmx255_nand = { |
| 234 | .name = "gpio-nand", |
| 235 | .num_resources = ARRAY_SIZE(cmx255_nand_resource), |
| 236 | .resource = cmx255_nand_resource, |
| 237 | .id = -1, |
| 238 | .dev = { |
| 239 | .platform_data = &cmx255_nand_platdata, |
| 240 | } |
| 241 | }; |
| 242 | |
| 243 | static void __init cmx255_init_nand(void) |
| 244 | { |
| 245 | platform_device_register(&cmx255_nand); |
| 246 | } |
| 247 | #else |
| 248 | static inline void cmx255_init_nand(void) {} |
| 249 | #endif |
| 250 | |
Mike Rapoport | a7f3f03 | 2008-10-05 10:26:55 +0100 | [diff] [blame] | 251 | void __init cmx255_init(void) |
| 252 | { |
| 253 | pxa2xx_mfp_config(ARRAY_AND_SIZE(cmx255_pin_config)); |
| 254 | |
| 255 | cmx255_init_rtc(); |
Mike Rapoport | 49a7061 | 2008-10-05 10:29:59 +0100 | [diff] [blame^] | 256 | cmx255_init_nor(); |
| 257 | cmx255_init_nand(); |
Mike Rapoport | a7f3f03 | 2008-10-05 10:26:55 +0100 | [diff] [blame] | 258 | } |