Giuseppe CAVALLARO | a1d6f3f | 2010-03-31 21:44:04 +0000 | [diff] [blame] | 1 | STMicroelectronics 10/100/1000 Synopsys Ethernet driver |
| 2 | |
| 3 | Copyright (C) 2007-2010 STMicroelectronics Ltd |
| 4 | Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> |
| 5 | |
| 6 | This is the driver for the MAC 10/100/1000 on-chip Ethernet controllers |
Giuseppe CAVALLARO | 5b99326 | 2011-12-21 03:58:20 +0000 | [diff] [blame] | 7 | (Synopsys IP blocks). |
Giuseppe CAVALLARO | a1d6f3f | 2010-03-31 21:44:04 +0000 | [diff] [blame] | 8 | |
| 9 | Currently this network device driver is for all STM embedded MAC/GMAC |
Giuseppe CAVALLARO | 5b99326 | 2011-12-21 03:58:20 +0000 | [diff] [blame] | 10 | (i.e. 7xxx/5xxx SoCs), SPEAr (arm), Loongson1B (mips) and XLINX XC2V3000 |
| 11 | FF1152AMT0221 D1215994A VIRTEX FPGA board. |
Giuseppe CAVALLARO | a1d6f3f | 2010-03-31 21:44:04 +0000 | [diff] [blame] | 12 | |
Giuseppe CAVALLARO | 3d23771 | 2012-06-04 19:22:56 +0000 | [diff] [blame] | 13 | DWC Ether MAC 10/100/1000 Universal version 3.60a (and older) and DWC Ether |
| 14 | MAC 10/100 Universal version 4.0 have been used for developing this driver. |
Giuseppe CAVALLARO | 5b99326 | 2011-12-21 03:58:20 +0000 | [diff] [blame] | 15 | |
| 16 | This driver supports both the platform bus and PCI. |
Giuseppe CAVALLARO | a1d6f3f | 2010-03-31 21:44:04 +0000 | [diff] [blame] | 17 | |
| 18 | Please, for more information also visit: www.stlinux.com |
| 19 | |
| 20 | 1) Kernel Configuration |
| 21 | The kernel configuration option is STMMAC_ETH: |
| 22 | Device Drivers ---> Network device support ---> Ethernet (1000 Mbit) ---> |
| 23 | STMicroelectronics 10/100/1000 Ethernet driver (STMMAC_ETH) |
| 24 | |
| 25 | 2) Driver parameters list: |
| 26 | debug: message level (0: no output, 16: all); |
| 27 | phyaddr: to manually provide the physical address to the PHY device; |
| 28 | dma_rxsize: DMA rx ring size; |
| 29 | dma_txsize: DMA tx ring size; |
| 30 | buf_sz: DMA buffer size; |
| 31 | tc: control the HW FIFO threshold; |
Giuseppe CAVALLARO | a1d6f3f | 2010-03-31 21:44:04 +0000 | [diff] [blame] | 32 | watchdog: transmit timeout (in milliseconds); |
| 33 | flow_ctrl: Flow control ability [on/off]; |
| 34 | pause: Flow Control Pause Time; |
Giuseppe CAVALLARO | a1d6f3f | 2010-03-31 21:44:04 +0000 | [diff] [blame] | 35 | |
| 36 | 3) Command line options |
| 37 | Driver parameters can be also passed in command line by using: |
| 38 | stmmaceth=dma_rxsize:128,dma_txsize:512 |
| 39 | |
| 40 | 4) Driver information and notes |
| 41 | |
| 42 | 4.1) Transmit process |
| 43 | The xmit method is invoked when the kernel needs to transmit a packet; it sets |
| 44 | the descriptors in the ring and informs the DMA engine that there is a packet |
| 45 | ready to be transmitted. |
| 46 | Once the controller has finished transmitting the packet, an interrupt is |
| 47 | triggered; So the driver will be able to release the socket buffers. |
| 48 | By default, the driver sets the NETIF_F_SG bit in the features field of the |
| 49 | net_device structure enabling the scatter/gather feature. |
| 50 | |
| 51 | 4.2) Receive process |
| 52 | When one or more packets are received, an interrupt happens. The interrupts |
| 53 | are not queued so the driver has to scan all the descriptors in the ring during |
| 54 | the receive process. |
Giuseppe CAVALLARO | 3d23771 | 2012-06-04 19:22:56 +0000 | [diff] [blame] | 55 | This is based on NAPI so the interrupt handler signals only if there is work |
| 56 | to be done, and it exits. |
Giuseppe CAVALLARO | a1d6f3f | 2010-03-31 21:44:04 +0000 | [diff] [blame] | 57 | Then the poll method will be scheduled at some future point. |
| 58 | The incoming packets are stored, by the DMA, in a list of pre-allocated socket |
| 59 | buffers in order to avoid the memcpy (Zero-copy). |
| 60 | |
Giuseppe CAVALLARO | f9e01b5 | 2012-11-25 23:10:45 +0000 | [diff] [blame] | 61 | 4.3) Interrupt Mitigation |
| 62 | The driver is able to mitigate the number of its DMA interrupts |
| 63 | using NAPI for the reception on chips older than the 3.50. |
| 64 | New chips have an HW RX-Watchdog used for this mitigation. |
| 65 | |
| 66 | On Tx-side, the mitigation schema is based on a SW timer that calls the |
| 67 | tx function (stmmac_tx) to reclaim the resource after transmitting the |
| 68 | frames. |
| 69 | Also there is another parameter (like a threshold) used to program |
| 70 | the descriptors avoiding to set the interrupt on completion bit in |
| 71 | when the frame is sent (xmit). |
| 72 | |
| 73 | Mitigation parameters can be tuned by ethtool. |
Giuseppe CAVALLARO | a1d6f3f | 2010-03-31 21:44:04 +0000 | [diff] [blame] | 74 | |
| 75 | 4.4) WOL |
Giuseppe CAVALLARO | 3d23771 | 2012-06-04 19:22:56 +0000 | [diff] [blame] | 76 | Wake up on Lan feature through Magic and Unicast frames are supported for the |
| 77 | GMAC core. |
Giuseppe CAVALLARO | a1d6f3f | 2010-03-31 21:44:04 +0000 | [diff] [blame] | 78 | |
| 79 | 4.5) DMA descriptors |
| 80 | Driver handles both normal and enhanced descriptors. The latter has been only |
Giuseppe CAVALLARO | 51e3137 | 2011-10-18 00:01:20 +0000 | [diff] [blame] | 81 | tested on DWC Ether MAC 10/100/1000 Universal version 3.41a and later. |
| 82 | |
| 83 | STMMAC supports DMA descriptor to operate both in dual buffer (RING) |
| 84 | and linked-list(CHAINED) mode. In RING each descriptor points to two |
| 85 | data buffer pointers whereas in CHAINED mode they point to only one data |
| 86 | buffer pointer. RING mode is the default. |
| 87 | |
| 88 | In CHAINED mode each descriptor will have pointer to next descriptor in |
| 89 | the list, hence creating the explicit chaining in the descriptor itself, |
| 90 | whereas such explicit chaining is not possible in RING mode. |
Giuseppe CAVALLARO | a1d6f3f | 2010-03-31 21:44:04 +0000 | [diff] [blame] | 91 | |
| 92 | 4.6) Ethtool support |
| 93 | Ethtool is supported. Driver statistics and internal errors can be taken using: |
| 94 | ethtool -S ethX command. It is possible to dump registers etc. |
| 95 | |
| 96 | 4.7) Jumbo and Segmentation Offloading |
| 97 | Jumbo frames are supported and tested for the GMAC. |
| 98 | The GSO has been also added but it's performed in software. |
| 99 | LRO is not supported. |
| 100 | |
| 101 | 4.8) Physical |
| 102 | The driver is compatible with PAL to work with PHY and GPHY devices. |
| 103 | |
| 104 | 4.9) Platform information |
Giuseppe CAVALLARO | 557e2a3 | 2011-07-20 00:05:24 +0000 | [diff] [blame] | 105 | Several driver's information can be passed through the platform |
| 106 | These are included in the include/linux/stmmac.h header file |
| 107 | and detailed below as well: |
Giuseppe CAVALLARO | a1d6f3f | 2010-03-31 21:44:04 +0000 | [diff] [blame] | 108 | |
Giuseppe CAVALLARO | 3d23771 | 2012-06-04 19:22:56 +0000 | [diff] [blame] | 109 | struct plat_stmmacenet_data { |
| 110 | char *phy_bus_name; |
Giuseppe Cavallaro | f5539b5 | 2010-11-12 12:43:34 -0800 | [diff] [blame] | 111 | int bus_id; |
Giuseppe CAVALLARO | 557e2a3 | 2011-07-20 00:05:24 +0000 | [diff] [blame] | 112 | int phy_addr; |
| 113 | int interface; |
| 114 | struct stmmac_mdio_bus_data *mdio_bus_data; |
Deepak SIKRI | 8327eb6 | 2012-04-04 04:33:23 +0000 | [diff] [blame] | 115 | struct stmmac_dma_cfg *dma_cfg; |
Giuseppe Cavallaro | f5539b5 | 2010-11-12 12:43:34 -0800 | [diff] [blame] | 116 | int clk_csr; |
| 117 | int has_gmac; |
| 118 | int enh_desc; |
| 119 | int tx_coe; |
Deepak SIKRI | 55f9a4d | 2012-04-04 04:33:20 +0000 | [diff] [blame] | 120 | int rx_coe; |
Giuseppe Cavallaro | f5539b5 | 2010-11-12 12:43:34 -0800 | [diff] [blame] | 121 | int bugged_jumbo; |
| 122 | int pmt; |
Giuseppe CAVALLARO | 557e2a3 | 2011-07-20 00:05:24 +0000 | [diff] [blame] | 123 | int force_sf_dma_mode; |
Giuseppe CAVALLARO | f9e01b5 | 2012-11-25 23:10:45 +0000 | [diff] [blame] | 124 | int riwt_off; |
Giuseppe CAVALLARO | 557e2a3 | 2011-07-20 00:05:24 +0000 | [diff] [blame] | 125 | void (*fix_mac_speed)(void *priv, unsigned int speed); |
| 126 | void (*bus_setup)(void __iomem *ioaddr); |
| 127 | int (*init)(struct platform_device *pdev); |
| 128 | void (*exit)(struct platform_device *pdev); |
Giuseppe CAVALLARO | 3d23771 | 2012-06-04 19:22:56 +0000 | [diff] [blame] | 129 | void *custom_cfg; |
| 130 | void *custom_data; |
Giuseppe CAVALLARO | 557e2a3 | 2011-07-20 00:05:24 +0000 | [diff] [blame] | 131 | void *bsp_priv; |
| 132 | }; |
Giuseppe CAVALLARO | a1d6f3f | 2010-03-31 21:44:04 +0000 | [diff] [blame] | 133 | |
| 134 | Where: |
Giuseppe CAVALLARO | 3d23771 | 2012-06-04 19:22:56 +0000 | [diff] [blame] | 135 | o phy_bus_name: phy bus name to attach to the stmmac. |
Giuseppe CAVALLARO | 557e2a3 | 2011-07-20 00:05:24 +0000 | [diff] [blame] | 136 | o bus_id: bus identifier. |
| 137 | o phy_addr: the physical address can be passed from the platform. |
| 138 | If it is set to -1 the driver will automatically |
| 139 | detect it at run-time by probing all the 32 addresses. |
| 140 | o interface: PHY device's interface. |
| 141 | o mdio_bus_data: specific platform fields for the MDIO bus. |
Giuseppe CAVALLARO | 3d23771 | 2012-06-04 19:22:56 +0000 | [diff] [blame] | 142 | o dma_cfg: internal DMA parameters |
| 143 | o pbl: the Programmable Burst Length is maximum number of beats to |
Giuseppe CAVALLARO | 557e2a3 | 2011-07-20 00:05:24 +0000 | [diff] [blame] | 144 | be transferred in one DMA transaction. |
| 145 | GMAC also enables the 4xPBL by default. |
Giuseppe CAVALLARO | 3d23771 | 2012-06-04 19:22:56 +0000 | [diff] [blame] | 146 | o fixed_burst/mixed_burst/burst_len |
Giuseppe CAVALLARO | cd7201f | 2012-04-04 04:33:27 +0000 | [diff] [blame] | 147 | o clk_csr: fixed CSR Clock range selection. |
Giuseppe CAVALLARO | 557e2a3 | 2011-07-20 00:05:24 +0000 | [diff] [blame] | 148 | o has_gmac: uses the GMAC core. |
| 149 | o enh_desc: if sets the MAC will use the enhanced descriptor structure. |
| 150 | o tx_coe: core is able to perform the tx csum in HW. |
Deepak SIKRI | 55f9a4d | 2012-04-04 04:33:20 +0000 | [diff] [blame] | 151 | o rx_coe: the supports three check sum offloading engine types: |
| 152 | type_1, type_2 (full csum) and no RX coe. |
Giuseppe CAVALLARO | 557e2a3 | 2011-07-20 00:05:24 +0000 | [diff] [blame] | 153 | o bugged_jumbo: some HWs are not able to perform the csum in HW for |
| 154 | over-sized frames due to limited buffer sizes. |
| 155 | Setting this flag the csum will be done in SW on |
| 156 | JUMBO frames. |
| 157 | o pmt: core has the embedded power module (optional). |
| 158 | o force_sf_dma_mode: force DMA to use the Store and Forward mode |
| 159 | instead of the Threshold. |
Giuseppe CAVALLARO | f9e01b5 | 2012-11-25 23:10:45 +0000 | [diff] [blame] | 160 | o riwt_off: force to disable the RX watchdog feature and switch to NAPI mode. |
Giuseppe CAVALLARO | 557e2a3 | 2011-07-20 00:05:24 +0000 | [diff] [blame] | 161 | o fix_mac_speed: this callback is used for modifying some syscfg registers |
| 162 | (on ST SoCs) according to the link speed negotiated by the |
| 163 | physical layer . |
| 164 | o bus_setup: perform HW setup of the bus. For example, on some ST platforms |
| 165 | this field is used to configure the AMBA bridge to generate more |
| 166 | efficient STBus traffic. |
| 167 | o init/exit: callbacks used for calling a custom initialisation; |
| 168 | this is sometime necessary on some platforms (e.g. ST boxes) |
| 169 | where the HW needs to have set some PIO lines or system cfg |
| 170 | registers. |
Giuseppe CAVALLARO | 3d23771 | 2012-06-04 19:22:56 +0000 | [diff] [blame] | 171 | o custom_cfg/custom_data: this is a custom configuration that can be passed |
| 172 | while initialising the resources. |
| 173 | o bsp_priv: another private poiter. |
Giuseppe CAVALLARO | a1d6f3f | 2010-03-31 21:44:04 +0000 | [diff] [blame] | 174 | |
Deepak SIKRI | 8327eb6 | 2012-04-04 04:33:23 +0000 | [diff] [blame] | 175 | For MDIO bus The we have: |
Giuseppe CAVALLARO | 557e2a3 | 2011-07-20 00:05:24 +0000 | [diff] [blame] | 176 | |
| 177 | struct stmmac_mdio_bus_data { |
Giuseppe CAVALLARO | 557e2a3 | 2011-07-20 00:05:24 +0000 | [diff] [blame] | 178 | int (*phy_reset)(void *priv); |
| 179 | unsigned int phy_mask; |
| 180 | int *irqs; |
| 181 | int probed_phy_irq; |
| 182 | }; |
Giuseppe CAVALLARO | a1d6f3f | 2010-03-31 21:44:04 +0000 | [diff] [blame] | 183 | |
| 184 | Where: |
Giuseppe CAVALLARO | 557e2a3 | 2011-07-20 00:05:24 +0000 | [diff] [blame] | 185 | o phy_reset: hook to reset the phy device attached to the bus. |
| 186 | o phy_mask: phy mask passed when register the MDIO bus within the driver. |
| 187 | o irqs: list of IRQs, one per PHY. |
| 188 | o probed_phy_irq: if irqs is NULL, use this for probed PHY. |
Giuseppe CAVALLARO | a1d6f3f | 2010-03-31 21:44:04 +0000 | [diff] [blame] | 189 | |
Deepak SIKRI | 8327eb6 | 2012-04-04 04:33:23 +0000 | [diff] [blame] | 190 | For DMA engine we have the following internal fields that should be |
| 191 | tuned according to the HW capabilities. |
| 192 | |
| 193 | struct stmmac_dma_cfg { |
| 194 | int pbl; |
| 195 | int fixed_burst; |
| 196 | int burst_len_supported; |
| 197 | }; |
| 198 | |
| 199 | Where: |
| 200 | o pbl: Programmable Burst Length |
| 201 | o fixed_burst: program the DMA to use the fixed burst mode |
| 202 | o burst_len: this is the value we put in the register |
| 203 | supported values are provided as macros in |
| 204 | linux/stmmac.h header file. |
| 205 | |
| 206 | --- |
| 207 | |
Giuseppe CAVALLARO | 557e2a3 | 2011-07-20 00:05:24 +0000 | [diff] [blame] | 208 | Below an example how the structures above are using on ST platforms. |
Giuseppe Cavallaro | f5539b5 | 2010-11-12 12:43:34 -0800 | [diff] [blame] | 209 | |
Giuseppe CAVALLARO | 557e2a3 | 2011-07-20 00:05:24 +0000 | [diff] [blame] | 210 | static struct plat_stmmacenet_data stxYYY_ethernet_platform_data = { |
Giuseppe CAVALLARO | 557e2a3 | 2011-07-20 00:05:24 +0000 | [diff] [blame] | 211 | .has_gmac = 0, |
| 212 | .enh_desc = 0, |
| 213 | .fix_mac_speed = stxYYY_ethernet_fix_mac_speed, |
| 214 | | |
| 215 | |-> to write an internal syscfg |
| 216 | | on this platform when the |
| 217 | | link speed changes from 10 to |
| 218 | | 100 and viceversa |
| 219 | .init = &stmmac_claim_resource, |
| 220 | | |
| 221 | |-> On ST SoC this calls own "PAD" |
| 222 | | manager framework to claim |
| 223 | | all the resources necessary |
| 224 | | (GPIO ...). The .custom_cfg field |
| 225 | | is used to pass a custom config. |
| 226 | }; |
| 227 | |
| 228 | Below the usage of the stmmac_mdio_bus_data: on this SoC, in fact, |
| 229 | there are two MAC cores: one MAC is for MDIO Bus/PHY emulation |
| 230 | with fixed_link support. |
| 231 | |
| 232 | static struct stmmac_mdio_bus_data stmmac1_mdio_bus = { |
Giuseppe CAVALLARO | 557e2a3 | 2011-07-20 00:05:24 +0000 | [diff] [blame] | 233 | .phy_reset = phy_reset; |
| 234 | | |
| 235 | |-> function to provide the phy_reset on this board |
| 236 | .phy_mask = 0, |
| 237 | }; |
| 238 | |
| 239 | static struct fixed_phy_status stmmac0_fixed_phy_status = { |
| 240 | .link = 1, |
| 241 | .speed = 100, |
| 242 | .duplex = 1, |
| 243 | }; |
| 244 | |
| 245 | During the board's device_init we can configure the first |
| 246 | MAC for fixed_link by calling: |
| 247 | fixed_phy_add(PHY_POLL, 1, &stmmac0_fixed_phy_status));) |
| 248 | and the second one, with a real PHY device attached to the bus, |
| 249 | by using the stmmac_mdio_bus_data structure (to provide the id, the |
| 250 | reset procedure etc). |
| 251 | |
| 252 | 4.10) List of source files: |
| 253 | o Kconfig |
| 254 | o Makefile |
| 255 | o stmmac_main.c: main network device driver; |
| 256 | o stmmac_mdio.c: mdio functions; |
Giuseppe CAVALLARO | 0ec2ccd | 2012-06-27 21:14:36 +0000 | [diff] [blame] | 257 | o stmmac_pci: PCI driver; |
| 258 | o stmmac_platform.c: platform driver |
Giuseppe CAVALLARO | 557e2a3 | 2011-07-20 00:05:24 +0000 | [diff] [blame] | 259 | o stmmac_ethtool.c: ethtool support; |
| 260 | o stmmac_timer.[ch]: timer code used for mitigating the driver dma interrupts |
Giuseppe CAVALLARO | 0ec2ccd | 2012-06-27 21:14:36 +0000 | [diff] [blame] | 261 | (only tested on ST40 platforms based); |
Giuseppe CAVALLARO | 557e2a3 | 2011-07-20 00:05:24 +0000 | [diff] [blame] | 262 | o stmmac.h: private driver structure; |
| 263 | o common.h: common definitions and VFTs; |
| 264 | o descs.h: descriptor structure definitions; |
| 265 | o dwmac1000_core.c: GMAC core functions; |
| 266 | o dwmac1000_dma.c: dma functions for the GMAC chip; |
| 267 | o dwmac1000.h: specific header file for the GMAC; |
| 268 | o dwmac100_core: MAC 100 core and dma code; |
| 269 | o dwmac100_dma.c: dma funtions for the MAC chip; |
| 270 | o dwmac1000.h: specific header file for the MAC; |
Giuseppe CAVALLARO | 0ec2ccd | 2012-06-27 21:14:36 +0000 | [diff] [blame] | 271 | o dwmac_lib.c: generic DMA functions shared among chips; |
| 272 | o enh_desc.c: functions for handling enhanced descriptors; |
| 273 | o norm_desc.c: functions for handling normal descriptors; |
| 274 | o chain_mode.c/ring_mode.c:: functions to manage RING/CHAINED modes; |
| 275 | o mmc_core.c/mmc.h: Management MAC Counters; |
Giuseppe CAVALLARO | 557e2a3 | 2011-07-20 00:05:24 +0000 | [diff] [blame] | 276 | |
Giuseppe CAVALLARO | 4f2f25f | 2011-09-01 21:51:42 +0000 | [diff] [blame] | 277 | 5) Debug Information |
| 278 | |
| 279 | The driver exports many information i.e. internal statistics, |
| 280 | debug information, MAC and DMA registers etc. |
| 281 | |
| 282 | These can be read in several ways depending on the |
| 283 | type of the information actually needed. |
| 284 | |
| 285 | For example a user can be use the ethtool support |
| 286 | to get statistics: e.g. using: ethtool -S ethX |
| 287 | (that shows the Management counters (MMC) if supported) |
| 288 | or sees the MAC/DMA registers: e.g. using: ethtool -d ethX |
| 289 | |
| 290 | Compiling the Kernel with CONFIG_DEBUG_FS and enabling the |
| 291 | STMMAC_DEBUG_FS option the driver will export the following |
| 292 | debugfs entries: |
| 293 | |
| 294 | /sys/kernel/debug/stmmaceth/descriptors_status |
| 295 | To show the DMA TX/RX descriptor rings |
| 296 | |
| 297 | Developer can also use the "debug" module parameter to get |
| 298 | further debug information. |
| 299 | |
| 300 | In the end, there are other macros (that cannot be enabled |
| 301 | via menuconfig) to turn-on the RX/TX DMA debugging, |
| 302 | specific MAC core debug printk etc. Others to enable the |
| 303 | debug in the TX and RX processes. |
| 304 | All these are only useful during the developing stage |
| 305 | and should never enabled inside the code for general usage. |
| 306 | In fact, these can generate an huge amount of debug messages. |
| 307 | |
Giuseppe CAVALLARO | 0ec2ccd | 2012-06-27 21:14:36 +0000 | [diff] [blame] | 308 | 6) Energy Efficient Ethernet |
| 309 | |
| 310 | Energy Efficient Ethernet(EEE) enables IEEE 802.3 MAC sublayer along |
| 311 | with a family of Physical layer to operate in the Low power Idle(LPI) |
| 312 | mode. The EEE mode supports the IEEE 802.3 MAC operation at 100Mbps, |
| 313 | 1000Mbps & 10Gbps. |
| 314 | |
| 315 | The LPI mode allows power saving by switching off parts of the |
| 316 | communication device functionality when there is no data to be |
| 317 | transmitted & received. The system on both the side of the link can |
| 318 | disable some functionalities & save power during the period of low-link |
| 319 | utilization. The MAC controls whether the system should enter or exit |
| 320 | the LPI mode & communicate this to PHY. |
| 321 | |
| 322 | As soon as the interface is opened, the driver verifies if the EEE can |
| 323 | be supported. This is done by looking at both the DMA HW capability |
| 324 | register and the PHY devices MCD registers. |
| 325 | To enter in Tx LPI mode the driver needs to have a software timer |
| 326 | that enable and disable the LPI mode when there is nothing to be |
| 327 | transmitted. |
| 328 | |
Giuseppe CAVALLARO | 94fbbbf | 2013-03-26 04:43:12 +0000 | [diff] [blame] | 329 | 7) Extended descriptors |
| 330 | The extended descriptors give us information about the receive Ethernet payload |
| 331 | when it is carrying PTP packets or TCP/UDP/ICMP over IP. |
| 332 | These are not available on GMAC Synopsys chips older than the 3.50. |
| 333 | At probe time the driver will decide if these can be actually used. |
| 334 | This support also is mandatory for PTPv2 because the extra descriptors 6 and 7 |
| 335 | are used for saving the hardware timestamps. |
| 336 | |
| 337 | 8) Precision Time Protocol (PTP) |
| 338 | The driver supports the IEEE 1588-2002, Precision Time Protocol (PTP), |
| 339 | which enables precise synchronization of clocks in measurement and |
| 340 | control systems implemented with technologies such as network |
| 341 | communication. |
| 342 | |
| 343 | In addition to the basic timestamp features mentioned in IEEE 1588-2002 |
| 344 | Timestamps, new GMAC cores support the advanced timestamp features. |
| 345 | IEEE 1588-2008 that can be enabled when configure the Kernel. |
| 346 | |
| 347 | 9) SGMII/RGMII supports |
| 348 | New GMAC devices provide own way to manage RGMII/SGMII. |
| 349 | This information is available at run-time by looking at the |
| 350 | HW capability register. This means that the stmmac can manage |
| 351 | auto-negotiation and link status w/o using the PHYLIB stuff |
| 352 | In fact, the HW provides a subset of extended registers to |
| 353 | restart the ANE, verify Full/Half duplex mode and Speed. |
| 354 | Also thanks to these registers it is possible to look at the |
| 355 | Auto-negotiated Link Parter Ability. |
| 356 | |
| 357 | 10) TODO: |
Giuseppe CAVALLARO | 557e2a3 | 2011-07-20 00:05:24 +0000 | [diff] [blame] | 358 | o XGMAC is not supported. |
Giuseppe CAVALLARO | 94fbbbf | 2013-03-26 04:43:12 +0000 | [diff] [blame] | 359 | o Complete the TBI & RTBI support. |
| 360 | o extened VLAN support for 3.70a SYNP GMAC. |