Sascha Hauer | e038ed5 | 2012-03-09 09:11:46 +0100 | [diff] [blame] | 1 | #include <linux/clk.h> |
Alexander Shiyan | c349add | 2014-06-07 20:09:26 +0400 | [diff] [blame] | 2 | #include <linux/clk-provider.h> |
Sascha Hauer | e038ed5 | 2012-03-09 09:11:46 +0100 | [diff] [blame] | 3 | #include <linux/clkdev.h> |
| 4 | #include <linux/err.h> |
Sascha Hauer | e038ed5 | 2012-03-09 09:11:46 +0100 | [diff] [blame] | 5 | #include <linux/of.h> |
Alexander Shiyan | c349add | 2014-06-07 20:09:26 +0400 | [diff] [blame] | 6 | #include <linux/of_address.h> |
Alexander Shiyan | e8e3faa | 2014-07-05 09:36:06 +0400 | [diff] [blame] | 7 | #include <dt-bindings/clock/imx27-clock.h> |
Shawn Guo | 0c83131 | 2015-04-25 18:43:45 +0800 | [diff] [blame] | 8 | #include <soc/imx/revision.h> |
Shawn Guo | 0931aff | 2015-05-15 11:41:39 +0800 | [diff] [blame] | 9 | #include <soc/imx/timer.h> |
Shawn Guo | 0c83131 | 2015-04-25 18:43:45 +0800 | [diff] [blame] | 10 | #include <asm/irq.h> |
Sascha Hauer | e038ed5 | 2012-03-09 09:11:46 +0100 | [diff] [blame] | 11 | |
Sascha Hauer | e038ed5 | 2012-03-09 09:11:46 +0100 | [diff] [blame] | 12 | #include "clk.h" |
Shawn Guo | 0c83131 | 2015-04-25 18:43:45 +0800 | [diff] [blame] | 13 | |
| 14 | #define MX27_CCM_BASE_ADDR 0x10027000 |
| 15 | #define MX27_GPT1_BASE_ADDR 0x10003000 |
| 16 | #define MX27_INT_GPT1 (NR_IRQS_LEGACY + 26) |
Sascha Hauer | e038ed5 | 2012-03-09 09:11:46 +0100 | [diff] [blame] | 17 | |
Alexander Shiyan | c349add | 2014-06-07 20:09:26 +0400 | [diff] [blame] | 18 | static void __iomem *ccm __initdata; |
Sascha Hauer | e038ed5 | 2012-03-09 09:11:46 +0100 | [diff] [blame] | 19 | |
| 20 | /* Register offsets */ |
Alexander Shiyan | c349add | 2014-06-07 20:09:26 +0400 | [diff] [blame] | 21 | #define CCM_CSCR (ccm + 0x00) |
| 22 | #define CCM_MPCTL0 (ccm + 0x04) |
| 23 | #define CCM_MPCTL1 (ccm + 0x08) |
| 24 | #define CCM_SPCTL0 (ccm + 0x0c) |
| 25 | #define CCM_SPCTL1 (ccm + 0x10) |
Alexander Shiyan | c349add | 2014-06-07 20:09:26 +0400 | [diff] [blame] | 26 | #define CCM_PCDR0 (ccm + 0x18) |
| 27 | #define CCM_PCDR1 (ccm + 0x1c) |
| 28 | #define CCM_PCCR0 (ccm + 0x20) |
| 29 | #define CCM_PCCR1 (ccm + 0x24) |
| 30 | #define CCM_CCSR (ccm + 0x28) |
Sascha Hauer | e038ed5 | 2012-03-09 09:11:46 +0100 | [diff] [blame] | 31 | |
| 32 | static const char *vpu_sel_clks[] = { "spll", "mpll_main2", }; |
| 33 | static const char *cpu_sel_clks[] = { "mpll_main2", "mpll", }; |
Sascha Hauer | 4ea9e85 | 2012-10-31 08:25:08 +0100 | [diff] [blame] | 34 | static const char *mpll_sel_clks[] = { "fpm", "mpll_osc_sel", }; |
Alexander Shiyan | b4de531 | 2014-07-05 09:36:09 +0400 | [diff] [blame] | 35 | static const char *mpll_osc_sel_clks[] = { "ckih_gate", "ckih_div1p5", }; |
Sascha Hauer | e038ed5 | 2012-03-09 09:11:46 +0100 | [diff] [blame] | 36 | static const char *clko_sel_clks[] = { |
Alexander Shiyan | b4de531 | 2014-07-05 09:36:09 +0400 | [diff] [blame] | 37 | "ckil", "fpm", "ckih_gate", "ckih_gate", |
| 38 | "ckih_gate", "mpll", "spll", "cpu_div", |
Sascha Hauer | e038ed5 | 2012-03-09 09:11:46 +0100 | [diff] [blame] | 39 | "ahb", "ipg", "per1_div", "per2_div", |
| 40 | "per3_div", "per4_div", "ssi1_div", "ssi2_div", |
| 41 | "nfc_div", "mshc_div", "vpu_div", "60m", |
| 42 | "32k", "usb_div", "dptc", |
| 43 | }; |
| 44 | |
Gwenhael Goavec-Merou | b7eed20 | 2013-01-13 15:15:01 +0100 | [diff] [blame] | 45 | static const char *ssi_sel_clks[] = { "spll_gate", "mpll", }; |
Sascha Hauer | e038ed5 | 2012-03-09 09:11:46 +0100 | [diff] [blame] | 46 | |
Alexander Shiyan | e8e3faa | 2014-07-05 09:36:06 +0400 | [diff] [blame] | 47 | static struct clk *clk[IMX27_CLK_MAX]; |
Fabio Estevam | c20736f | 2012-11-28 15:55:30 -0200 | [diff] [blame] | 48 | static struct clk_onecell_data clk_data; |
Sascha Hauer | e038ed5 | 2012-03-09 09:11:46 +0100 | [diff] [blame] | 49 | |
Alexander Shiyan | bb9c339 | 2014-06-07 20:09:25 +0400 | [diff] [blame] | 50 | static void __init _mx27_clocks_init(unsigned long fref) |
Sascha Hauer | e038ed5 | 2012-03-09 09:11:46 +0100 | [diff] [blame] | 51 | { |
Alexander Shiyan | c349add | 2014-06-07 20:09:26 +0400 | [diff] [blame] | 52 | BUG_ON(!ccm); |
| 53 | |
Alexander Shiyan | e8e3faa | 2014-07-05 09:36:06 +0400 | [diff] [blame] | 54 | clk[IMX27_CLK_DUMMY] = imx_clk_fixed("dummy", 0); |
| 55 | clk[IMX27_CLK_CKIH] = imx_clk_fixed("ckih", fref); |
| 56 | clk[IMX27_CLK_CKIL] = imx_clk_fixed("ckil", 32768); |
| 57 | clk[IMX27_CLK_FPM] = imx_clk_fixed_factor("fpm", "ckil", 1024, 1); |
Alexander Shiyan | b4de531 | 2014-07-05 09:36:09 +0400 | [diff] [blame] | 58 | clk[IMX27_CLK_CKIH_DIV1P5] = imx_clk_fixed_factor("ckih_div1p5", "ckih_gate", 2, 3); |
| 59 | clk[IMX27_CLK_CKIH_GATE] = imx_clk_gate_dis("ckih_gate", "ckih", CCM_CSCR, 3); |
Alexander Shiyan | e8e3faa | 2014-07-05 09:36:06 +0400 | [diff] [blame] | 60 | clk[IMX27_CLK_MPLL_OSC_SEL] = imx_clk_mux("mpll_osc_sel", CCM_CSCR, 4, 1, mpll_osc_sel_clks, ARRAY_SIZE(mpll_osc_sel_clks)); |
| 61 | clk[IMX27_CLK_MPLL_SEL] = imx_clk_mux("mpll_sel", CCM_CSCR, 16, 1, mpll_sel_clks, ARRAY_SIZE(mpll_sel_clks)); |
Shawn Guo | 3bec5f8 | 2015-04-26 13:33:39 +0800 | [diff] [blame] | 62 | clk[IMX27_CLK_MPLL] = imx_clk_pllv1(IMX_PLLV1_IMX27, "mpll", "mpll_sel", CCM_MPCTL0); |
| 63 | clk[IMX27_CLK_SPLL] = imx_clk_pllv1(IMX_PLLV1_IMX27, "spll", "ckih_gate", CCM_SPCTL0); |
Alexander Shiyan | e8e3faa | 2014-07-05 09:36:06 +0400 | [diff] [blame] | 64 | clk[IMX27_CLK_SPLL_GATE] = imx_clk_gate("spll_gate", "spll", CCM_CSCR, 1); |
| 65 | clk[IMX27_CLK_MPLL_MAIN2] = imx_clk_fixed_factor("mpll_main2", "mpll", 2, 3); |
Sascha Hauer | e038ed5 | 2012-03-09 09:11:46 +0100 | [diff] [blame] | 66 | |
| 67 | if (mx27_revision() >= IMX_CHIP_REVISION_2_0) { |
Alexander Shiyan | e8e3faa | 2014-07-05 09:36:06 +0400 | [diff] [blame] | 68 | clk[IMX27_CLK_AHB] = imx_clk_divider("ahb", "mpll_main2", CCM_CSCR, 8, 2); |
| 69 | clk[IMX27_CLK_IPG] = imx_clk_fixed_factor("ipg", "ahb", 1, 2); |
Sascha Hauer | e038ed5 | 2012-03-09 09:11:46 +0100 | [diff] [blame] | 70 | } else { |
Alexander Shiyan | e8e3faa | 2014-07-05 09:36:06 +0400 | [diff] [blame] | 71 | clk[IMX27_CLK_AHB] = imx_clk_divider("ahb", "mpll_main2", CCM_CSCR, 9, 4); |
| 72 | clk[IMX27_CLK_IPG] = imx_clk_divider("ipg", "ahb", CCM_CSCR, 8, 1); |
Sascha Hauer | e038ed5 | 2012-03-09 09:11:46 +0100 | [diff] [blame] | 73 | } |
| 74 | |
Alexander Shiyan | e8e3faa | 2014-07-05 09:36:06 +0400 | [diff] [blame] | 75 | clk[IMX27_CLK_MSHC_DIV] = imx_clk_divider("mshc_div", "ahb", CCM_PCDR0, 0, 6); |
| 76 | clk[IMX27_CLK_NFC_DIV] = imx_clk_divider("nfc_div", "ahb", CCM_PCDR0, 6, 4); |
| 77 | clk[IMX27_CLK_PER1_DIV] = imx_clk_divider("per1_div", "mpll_main2", CCM_PCDR1, 0, 6); |
| 78 | clk[IMX27_CLK_PER2_DIV] = imx_clk_divider("per2_div", "mpll_main2", CCM_PCDR1, 8, 6); |
| 79 | clk[IMX27_CLK_PER3_DIV] = imx_clk_divider("per3_div", "mpll_main2", CCM_PCDR1, 16, 6); |
| 80 | clk[IMX27_CLK_PER4_DIV] = imx_clk_divider("per4_div", "mpll_main2", CCM_PCDR1, 24, 6); |
| 81 | clk[IMX27_CLK_VPU_SEL] = imx_clk_mux("vpu_sel", CCM_CSCR, 21, 1, vpu_sel_clks, ARRAY_SIZE(vpu_sel_clks)); |
| 82 | clk[IMX27_CLK_VPU_DIV] = imx_clk_divider("vpu_div", "vpu_sel", CCM_PCDR0, 10, 6); |
| 83 | clk[IMX27_CLK_USB_DIV] = imx_clk_divider("usb_div", "spll_gate", CCM_CSCR, 28, 3); |
| 84 | clk[IMX27_CLK_CPU_SEL] = imx_clk_mux("cpu_sel", CCM_CSCR, 15, 1, cpu_sel_clks, ARRAY_SIZE(cpu_sel_clks)); |
| 85 | clk[IMX27_CLK_CLKO_SEL] = imx_clk_mux("clko_sel", CCM_CCSR, 0, 5, clko_sel_clks, ARRAY_SIZE(clko_sel_clks)); |
| 86 | |
Sascha Hauer | e038ed5 | 2012-03-09 09:11:46 +0100 | [diff] [blame] | 87 | if (mx27_revision() >= IMX_CHIP_REVISION_2_0) |
Alexander Shiyan | e8e3faa | 2014-07-05 09:36:06 +0400 | [diff] [blame] | 88 | clk[IMX27_CLK_CPU_DIV] = imx_clk_divider("cpu_div", "cpu_sel", CCM_CSCR, 12, 2); |
Sascha Hauer | e038ed5 | 2012-03-09 09:11:46 +0100 | [diff] [blame] | 89 | else |
Alexander Shiyan | e8e3faa | 2014-07-05 09:36:06 +0400 | [diff] [blame] | 90 | clk[IMX27_CLK_CPU_DIV] = imx_clk_divider("cpu_div", "cpu_sel", CCM_CSCR, 13, 3); |
| 91 | |
| 92 | clk[IMX27_CLK_CLKO_DIV] = imx_clk_divider("clko_div", "clko_sel", CCM_PCDR0, 22, 3); |
| 93 | clk[IMX27_CLK_SSI1_SEL] = imx_clk_mux("ssi1_sel", CCM_CSCR, 22, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks)); |
| 94 | clk[IMX27_CLK_SSI2_SEL] = imx_clk_mux("ssi2_sel", CCM_CSCR, 23, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks)); |
| 95 | clk[IMX27_CLK_SSI1_DIV] = imx_clk_divider("ssi1_div", "ssi1_sel", CCM_PCDR0, 16, 6); |
| 96 | clk[IMX27_CLK_SSI2_DIV] = imx_clk_divider("ssi2_div", "ssi2_sel", CCM_PCDR0, 26, 6); |
| 97 | clk[IMX27_CLK_CLKO_EN] = imx_clk_gate("clko_en", "clko_div", CCM_PCCR0, 0); |
| 98 | clk[IMX27_CLK_SSI2_IPG_GATE] = imx_clk_gate("ssi2_ipg_gate", "ipg", CCM_PCCR0, 0); |
| 99 | clk[IMX27_CLK_SSI1_IPG_GATE] = imx_clk_gate("ssi1_ipg_gate", "ipg", CCM_PCCR0, 1); |
| 100 | clk[IMX27_CLK_SLCDC_IPG_GATE] = imx_clk_gate("slcdc_ipg_gate", "ipg", CCM_PCCR0, 2); |
| 101 | clk[IMX27_CLK_SDHC3_IPG_GATE] = imx_clk_gate("sdhc3_ipg_gate", "ipg", CCM_PCCR0, 3); |
| 102 | clk[IMX27_CLK_SDHC2_IPG_GATE] = imx_clk_gate("sdhc2_ipg_gate", "ipg", CCM_PCCR0, 4); |
| 103 | clk[IMX27_CLK_SDHC1_IPG_GATE] = imx_clk_gate("sdhc1_ipg_gate", "ipg", CCM_PCCR0, 5); |
| 104 | clk[IMX27_CLK_SCC_IPG_GATE] = imx_clk_gate("scc_ipg_gate", "ipg", CCM_PCCR0, 6); |
| 105 | clk[IMX27_CLK_SAHARA_IPG_GATE] = imx_clk_gate("sahara_ipg_gate", "ipg", CCM_PCCR0, 7); |
| 106 | clk[IMX27_CLK_RTIC_IPG_GATE] = imx_clk_gate("rtic_ipg_gate", "ipg", CCM_PCCR0, 8); |
| 107 | clk[IMX27_CLK_RTC_IPG_GATE] = imx_clk_gate("rtc_ipg_gate", "ipg", CCM_PCCR0, 9); |
| 108 | clk[IMX27_CLK_PWM_IPG_GATE] = imx_clk_gate("pwm_ipg_gate", "ipg", CCM_PCCR0, 11); |
| 109 | clk[IMX27_CLK_OWIRE_IPG_GATE] = imx_clk_gate("owire_ipg_gate", "ipg", CCM_PCCR0, 12); |
| 110 | clk[IMX27_CLK_MSHC_IPG_GATE] = imx_clk_gate("mshc_ipg_gate", "ipg", CCM_PCCR0, 13); |
| 111 | clk[IMX27_CLK_LCDC_IPG_GATE] = imx_clk_gate("lcdc_ipg_gate", "ipg", CCM_PCCR0, 14); |
| 112 | clk[IMX27_CLK_KPP_IPG_GATE] = imx_clk_gate("kpp_ipg_gate", "ipg", CCM_PCCR0, 15); |
| 113 | clk[IMX27_CLK_IIM_IPG_GATE] = imx_clk_gate("iim_ipg_gate", "ipg", CCM_PCCR0, 16); |
| 114 | clk[IMX27_CLK_I2C2_IPG_GATE] = imx_clk_gate("i2c2_ipg_gate", "ipg", CCM_PCCR0, 17); |
| 115 | clk[IMX27_CLK_I2C1_IPG_GATE] = imx_clk_gate("i2c1_ipg_gate", "ipg", CCM_PCCR0, 18); |
| 116 | clk[IMX27_CLK_GPT6_IPG_GATE] = imx_clk_gate("gpt6_ipg_gate", "ipg", CCM_PCCR0, 19); |
| 117 | clk[IMX27_CLK_GPT5_IPG_GATE] = imx_clk_gate("gpt5_ipg_gate", "ipg", CCM_PCCR0, 20); |
| 118 | clk[IMX27_CLK_GPT4_IPG_GATE] = imx_clk_gate("gpt4_ipg_gate", "ipg", CCM_PCCR0, 21); |
| 119 | clk[IMX27_CLK_GPT3_IPG_GATE] = imx_clk_gate("gpt3_ipg_gate", "ipg", CCM_PCCR0, 22); |
| 120 | clk[IMX27_CLK_GPT2_IPG_GATE] = imx_clk_gate("gpt2_ipg_gate", "ipg", CCM_PCCR0, 23); |
| 121 | clk[IMX27_CLK_GPT1_IPG_GATE] = imx_clk_gate("gpt1_ipg_gate", "ipg", CCM_PCCR0, 24); |
| 122 | clk[IMX27_CLK_GPIO_IPG_GATE] = imx_clk_gate("gpio_ipg_gate", "ipg", CCM_PCCR0, 25); |
| 123 | clk[IMX27_CLK_FEC_IPG_GATE] = imx_clk_gate("fec_ipg_gate", "ipg", CCM_PCCR0, 26); |
| 124 | clk[IMX27_CLK_EMMA_IPG_GATE] = imx_clk_gate("emma_ipg_gate", "ipg", CCM_PCCR0, 27); |
| 125 | clk[IMX27_CLK_DMA_IPG_GATE] = imx_clk_gate("dma_ipg_gate", "ipg", CCM_PCCR0, 28); |
| 126 | clk[IMX27_CLK_CSPI3_IPG_GATE] = imx_clk_gate("cspi3_ipg_gate", "ipg", CCM_PCCR0, 29); |
| 127 | clk[IMX27_CLK_CSPI2_IPG_GATE] = imx_clk_gate("cspi2_ipg_gate", "ipg", CCM_PCCR0, 30); |
| 128 | clk[IMX27_CLK_CSPI1_IPG_GATE] = imx_clk_gate("cspi1_ipg_gate", "ipg", CCM_PCCR0, 31); |
| 129 | clk[IMX27_CLK_MSHC_BAUD_GATE] = imx_clk_gate("mshc_baud_gate", "mshc_div", CCM_PCCR1, 2); |
| 130 | clk[IMX27_CLK_NFC_BAUD_GATE] = imx_clk_gate("nfc_baud_gate", "nfc_div", CCM_PCCR1, 3); |
| 131 | clk[IMX27_CLK_SSI2_BAUD_GATE] = imx_clk_gate("ssi2_baud_gate", "ssi2_div", CCM_PCCR1, 4); |
| 132 | clk[IMX27_CLK_SSI1_BAUD_GATE] = imx_clk_gate("ssi1_baud_gate", "ssi1_div", CCM_PCCR1, 5); |
| 133 | clk[IMX27_CLK_VPU_BAUD_GATE] = imx_clk_gate("vpu_baud_gate", "vpu_div", CCM_PCCR1, 6); |
| 134 | clk[IMX27_CLK_PER4_GATE] = imx_clk_gate("per4_gate", "per4_div", CCM_PCCR1, 7); |
| 135 | clk[IMX27_CLK_PER3_GATE] = imx_clk_gate("per3_gate", "per3_div", CCM_PCCR1, 8); |
| 136 | clk[IMX27_CLK_PER2_GATE] = imx_clk_gate("per2_gate", "per2_div", CCM_PCCR1, 9); |
| 137 | clk[IMX27_CLK_PER1_GATE] = imx_clk_gate("per1_gate", "per1_div", CCM_PCCR1, 10); |
| 138 | clk[IMX27_CLK_USB_AHB_GATE] = imx_clk_gate("usb_ahb_gate", "ahb", CCM_PCCR1, 11); |
| 139 | clk[IMX27_CLK_SLCDC_AHB_GATE] = imx_clk_gate("slcdc_ahb_gate", "ahb", CCM_PCCR1, 12); |
| 140 | clk[IMX27_CLK_SAHARA_AHB_GATE] = imx_clk_gate("sahara_ahb_gate", "ahb", CCM_PCCR1, 13); |
| 141 | clk[IMX27_CLK_RTIC_AHB_GATE] = imx_clk_gate("rtic_ahb_gate", "ahb", CCM_PCCR1, 14); |
| 142 | clk[IMX27_CLK_LCDC_AHB_GATE] = imx_clk_gate("lcdc_ahb_gate", "ahb", CCM_PCCR1, 15); |
| 143 | clk[IMX27_CLK_VPU_AHB_GATE] = imx_clk_gate("vpu_ahb_gate", "ahb", CCM_PCCR1, 16); |
| 144 | clk[IMX27_CLK_FEC_AHB_GATE] = imx_clk_gate("fec_ahb_gate", "ahb", CCM_PCCR1, 17); |
| 145 | clk[IMX27_CLK_EMMA_AHB_GATE] = imx_clk_gate("emma_ahb_gate", "ahb", CCM_PCCR1, 18); |
| 146 | clk[IMX27_CLK_EMI_AHB_GATE] = imx_clk_gate("emi_ahb_gate", "ahb", CCM_PCCR1, 19); |
| 147 | clk[IMX27_CLK_DMA_AHB_GATE] = imx_clk_gate("dma_ahb_gate", "ahb", CCM_PCCR1, 20); |
| 148 | clk[IMX27_CLK_CSI_AHB_GATE] = imx_clk_gate("csi_ahb_gate", "ahb", CCM_PCCR1, 21); |
| 149 | clk[IMX27_CLK_BROM_AHB_GATE] = imx_clk_gate("brom_ahb_gate", "ahb", CCM_PCCR1, 22); |
| 150 | clk[IMX27_CLK_ATA_AHB_GATE] = imx_clk_gate("ata_ahb_gate", "ahb", CCM_PCCR1, 23); |
| 151 | clk[IMX27_CLK_WDOG_IPG_GATE] = imx_clk_gate("wdog_ipg_gate", "ipg", CCM_PCCR1, 24); |
| 152 | clk[IMX27_CLK_USB_IPG_GATE] = imx_clk_gate("usb_ipg_gate", "ipg", CCM_PCCR1, 25); |
| 153 | clk[IMX27_CLK_UART6_IPG_GATE] = imx_clk_gate("uart6_ipg_gate", "ipg", CCM_PCCR1, 26); |
| 154 | clk[IMX27_CLK_UART5_IPG_GATE] = imx_clk_gate("uart5_ipg_gate", "ipg", CCM_PCCR1, 27); |
| 155 | clk[IMX27_CLK_UART4_IPG_GATE] = imx_clk_gate("uart4_ipg_gate", "ipg", CCM_PCCR1, 28); |
| 156 | clk[IMX27_CLK_UART3_IPG_GATE] = imx_clk_gate("uart3_ipg_gate", "ipg", CCM_PCCR1, 29); |
| 157 | clk[IMX27_CLK_UART2_IPG_GATE] = imx_clk_gate("uart2_ipg_gate", "ipg", CCM_PCCR1, 30); |
| 158 | clk[IMX27_CLK_UART1_IPG_GATE] = imx_clk_gate("uart1_ipg_gate", "ipg", CCM_PCCR1, 31); |
Sascha Hauer | e038ed5 | 2012-03-09 09:11:46 +0100 | [diff] [blame] | 159 | |
Alexander Shiyan | 229be9c | 2014-06-10 19:40:26 +0400 | [diff] [blame] | 160 | imx_check_clocks(clk, ARRAY_SIZE(clk)); |
Sascha Hauer | e038ed5 | 2012-03-09 09:11:46 +0100 | [diff] [blame] | 161 | |
Alexander Shiyan | e8e3faa | 2014-07-05 09:36:06 +0400 | [diff] [blame] | 162 | clk_register_clkdev(clk[IMX27_CLK_CPU_DIV], NULL, "cpu0"); |
Alexander Shiyan | bb9c339 | 2014-06-07 20:09:25 +0400 | [diff] [blame] | 163 | |
Alexander Shiyan | e8e3faa | 2014-07-05 09:36:06 +0400 | [diff] [blame] | 164 | clk_prepare_enable(clk[IMX27_CLK_EMI_AHB_GATE]); |
Alexander Shiyan | bb9c339 | 2014-06-07 20:09:25 +0400 | [diff] [blame] | 165 | |
| 166 | imx_print_silicon_rev("i.MX27", mx27_revision()); |
| 167 | } |
| 168 | |
| 169 | int __init mx27_clocks_init(unsigned long fref) |
| 170 | { |
Alexander Shiyan | c349add | 2014-06-07 20:09:26 +0400 | [diff] [blame] | 171 | ccm = ioremap(MX27_CCM_BASE_ADDR, SZ_4K); |
| 172 | |
Alexander Shiyan | bb9c339 | 2014-06-07 20:09:25 +0400 | [diff] [blame] | 173 | _mx27_clocks_init(fref); |
Fabio Estevam | c20736f | 2012-11-28 15:55:30 -0200 | [diff] [blame] | 174 | |
Alexander Shiyan | e8e3faa | 2014-07-05 09:36:06 +0400 | [diff] [blame] | 175 | clk_register_clkdev(clk[IMX27_CLK_UART1_IPG_GATE], "ipg", "imx21-uart.0"); |
| 176 | clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx21-uart.0"); |
| 177 | clk_register_clkdev(clk[IMX27_CLK_UART2_IPG_GATE], "ipg", "imx21-uart.1"); |
| 178 | clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx21-uart.1"); |
| 179 | clk_register_clkdev(clk[IMX27_CLK_UART3_IPG_GATE], "ipg", "imx21-uart.2"); |
| 180 | clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx21-uart.2"); |
| 181 | clk_register_clkdev(clk[IMX27_CLK_UART4_IPG_GATE], "ipg", "imx21-uart.3"); |
| 182 | clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx21-uart.3"); |
| 183 | clk_register_clkdev(clk[IMX27_CLK_UART5_IPG_GATE], "ipg", "imx21-uart.4"); |
| 184 | clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx21-uart.4"); |
| 185 | clk_register_clkdev(clk[IMX27_CLK_UART6_IPG_GATE], "ipg", "imx21-uart.5"); |
| 186 | clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx21-uart.5"); |
| 187 | clk_register_clkdev(clk[IMX27_CLK_GPT1_IPG_GATE], "ipg", "imx-gpt.0"); |
| 188 | clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx-gpt.0"); |
| 189 | clk_register_clkdev(clk[IMX27_CLK_PER2_GATE], "per", "imx21-mmc.0"); |
| 190 | clk_register_clkdev(clk[IMX27_CLK_SDHC1_IPG_GATE], "ipg", "imx21-mmc.0"); |
| 191 | clk_register_clkdev(clk[IMX27_CLK_PER2_GATE], "per", "imx21-mmc.1"); |
| 192 | clk_register_clkdev(clk[IMX27_CLK_SDHC2_IPG_GATE], "ipg", "imx21-mmc.1"); |
| 193 | clk_register_clkdev(clk[IMX27_CLK_PER2_GATE], "per", "imx21-mmc.2"); |
| 194 | clk_register_clkdev(clk[IMX27_CLK_SDHC2_IPG_GATE], "ipg", "imx21-mmc.2"); |
| 195 | clk_register_clkdev(clk[IMX27_CLK_PER2_GATE], "per", "imx27-cspi.0"); |
| 196 | clk_register_clkdev(clk[IMX27_CLK_CSPI1_IPG_GATE], "ipg", "imx27-cspi.0"); |
| 197 | clk_register_clkdev(clk[IMX27_CLK_PER2_GATE], "per", "imx27-cspi.1"); |
| 198 | clk_register_clkdev(clk[IMX27_CLK_CSPI2_IPG_GATE], "ipg", "imx27-cspi.1"); |
| 199 | clk_register_clkdev(clk[IMX27_CLK_PER2_GATE], "per", "imx27-cspi.2"); |
| 200 | clk_register_clkdev(clk[IMX27_CLK_CSPI3_IPG_GATE], "ipg", "imx27-cspi.2"); |
| 201 | clk_register_clkdev(clk[IMX27_CLK_PER3_GATE], "per", "imx21-fb.0"); |
| 202 | clk_register_clkdev(clk[IMX27_CLK_LCDC_IPG_GATE], "ipg", "imx21-fb.0"); |
| 203 | clk_register_clkdev(clk[IMX27_CLK_LCDC_AHB_GATE], "ahb", "imx21-fb.0"); |
| 204 | clk_register_clkdev(clk[IMX27_CLK_CSI_AHB_GATE], "ahb", "imx27-camera.0"); |
| 205 | clk_register_clkdev(clk[IMX27_CLK_PER4_GATE], "per", "imx27-camera.0"); |
| 206 | clk_register_clkdev(clk[IMX27_CLK_USB_DIV], "per", "imx-udc-mx27"); |
| 207 | clk_register_clkdev(clk[IMX27_CLK_USB_IPG_GATE], "ipg", "imx-udc-mx27"); |
| 208 | clk_register_clkdev(clk[IMX27_CLK_USB_AHB_GATE], "ahb", "imx-udc-mx27"); |
| 209 | clk_register_clkdev(clk[IMX27_CLK_USB_DIV], "per", "mxc-ehci.0"); |
| 210 | clk_register_clkdev(clk[IMX27_CLK_USB_IPG_GATE], "ipg", "mxc-ehci.0"); |
| 211 | clk_register_clkdev(clk[IMX27_CLK_USB_AHB_GATE], "ahb", "mxc-ehci.0"); |
| 212 | clk_register_clkdev(clk[IMX27_CLK_USB_DIV], "per", "mxc-ehci.1"); |
| 213 | clk_register_clkdev(clk[IMX27_CLK_USB_IPG_GATE], "ipg", "mxc-ehci.1"); |
| 214 | clk_register_clkdev(clk[IMX27_CLK_USB_AHB_GATE], "ahb", "mxc-ehci.1"); |
| 215 | clk_register_clkdev(clk[IMX27_CLK_USB_DIV], "per", "mxc-ehci.2"); |
| 216 | clk_register_clkdev(clk[IMX27_CLK_USB_IPG_GATE], "ipg", "mxc-ehci.2"); |
| 217 | clk_register_clkdev(clk[IMX27_CLK_USB_AHB_GATE], "ahb", "mxc-ehci.2"); |
| 218 | clk_register_clkdev(clk[IMX27_CLK_SSI1_IPG_GATE], NULL, "imx-ssi.0"); |
| 219 | clk_register_clkdev(clk[IMX27_CLK_SSI2_IPG_GATE], NULL, "imx-ssi.1"); |
| 220 | clk_register_clkdev(clk[IMX27_CLK_NFC_BAUD_GATE], NULL, "imx27-nand.0"); |
| 221 | clk_register_clkdev(clk[IMX27_CLK_VPU_BAUD_GATE], "per", "coda-imx27.0"); |
| 222 | clk_register_clkdev(clk[IMX27_CLK_VPU_AHB_GATE], "ahb", "coda-imx27.0"); |
| 223 | clk_register_clkdev(clk[IMX27_CLK_DMA_AHB_GATE], "ahb", "imx27-dma"); |
| 224 | clk_register_clkdev(clk[IMX27_CLK_DMA_IPG_GATE], "ipg", "imx27-dma"); |
| 225 | clk_register_clkdev(clk[IMX27_CLK_FEC_IPG_GATE], "ipg", "imx27-fec.0"); |
| 226 | clk_register_clkdev(clk[IMX27_CLK_FEC_AHB_GATE], "ahb", "imx27-fec.0"); |
| 227 | clk_register_clkdev(clk[IMX27_CLK_WDOG_IPG_GATE], NULL, "imx2-wdt.0"); |
| 228 | clk_register_clkdev(clk[IMX27_CLK_I2C1_IPG_GATE], NULL, "imx21-i2c.0"); |
| 229 | clk_register_clkdev(clk[IMX27_CLK_I2C2_IPG_GATE], NULL, "imx21-i2c.1"); |
| 230 | clk_register_clkdev(clk[IMX27_CLK_OWIRE_IPG_GATE], NULL, "mxc_w1.0"); |
| 231 | clk_register_clkdev(clk[IMX27_CLK_KPP_IPG_GATE], NULL, "imx-keypad"); |
| 232 | clk_register_clkdev(clk[IMX27_CLK_EMMA_AHB_GATE], "emma-ahb", "imx27-camera.0"); |
| 233 | clk_register_clkdev(clk[IMX27_CLK_EMMA_IPG_GATE], "emma-ipg", "imx27-camera.0"); |
| 234 | clk_register_clkdev(clk[IMX27_CLK_EMMA_AHB_GATE], "ahb", "m2m-emmaprp.0"); |
| 235 | clk_register_clkdev(clk[IMX27_CLK_EMMA_IPG_GATE], "ipg", "m2m-emmaprp.0"); |
Sascha Hauer | e038ed5 | 2012-03-09 09:11:46 +0100 | [diff] [blame] | 236 | |
Shawn Guo | 0931aff | 2015-05-15 11:41:39 +0800 | [diff] [blame] | 237 | mxc_timer_init(MX27_GPT1_BASE_ADDR, MX27_INT_GPT1, GPT_TYPE_IMX21); |
Sascha Hauer | e038ed5 | 2012-03-09 09:11:46 +0100 | [diff] [blame] | 238 | |
Sascha Hauer | e038ed5 | 2012-03-09 09:11:46 +0100 | [diff] [blame] | 239 | return 0; |
| 240 | } |
| 241 | |
Alexander Shiyan | c349add | 2014-06-07 20:09:26 +0400 | [diff] [blame] | 242 | static void __init mx27_clocks_init_dt(struct device_node *np) |
Sascha Hauer | e038ed5 | 2012-03-09 09:11:46 +0100 | [diff] [blame] | 243 | { |
Alexander Shiyan | c349add | 2014-06-07 20:09:26 +0400 | [diff] [blame] | 244 | struct device_node *refnp; |
Sascha Hauer | e038ed5 | 2012-03-09 09:11:46 +0100 | [diff] [blame] | 245 | u32 fref = 26000000; /* default */ |
| 246 | |
Alexander Shiyan | c349add | 2014-06-07 20:09:26 +0400 | [diff] [blame] | 247 | for_each_compatible_node(refnp, NULL, "fixed-clock") { |
| 248 | if (!of_device_is_compatible(refnp, "fsl,imx-osc26m")) |
Sascha Hauer | e038ed5 | 2012-03-09 09:11:46 +0100 | [diff] [blame] | 249 | continue; |
| 250 | |
Alexander Shiyan | c349add | 2014-06-07 20:09:26 +0400 | [diff] [blame] | 251 | if (!of_property_read_u32(refnp, "clock-frequency", &fref)) |
Sascha Hauer | e038ed5 | 2012-03-09 09:11:46 +0100 | [diff] [blame] | 252 | break; |
| 253 | } |
| 254 | |
Alexander Shiyan | c349add | 2014-06-07 20:09:26 +0400 | [diff] [blame] | 255 | ccm = of_iomap(np, 0); |
Alexander Shiyan | bb9c339 | 2014-06-07 20:09:25 +0400 | [diff] [blame] | 256 | |
Alexander Shiyan | c349add | 2014-06-07 20:09:26 +0400 | [diff] [blame] | 257 | _mx27_clocks_init(fref); |
Alexander Shiyan | bb9c339 | 2014-06-07 20:09:25 +0400 | [diff] [blame] | 258 | |
| 259 | clk_data.clks = clk; |
| 260 | clk_data.clk_num = ARRAY_SIZE(clk); |
| 261 | of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); |
Sascha Hauer | e038ed5 | 2012-03-09 09:11:46 +0100 | [diff] [blame] | 262 | } |
Alexander Shiyan | c349add | 2014-06-07 20:09:26 +0400 | [diff] [blame] | 263 | CLK_OF_DECLARE(imx27_ccm, "fsl,imx27-ccm", mx27_clocks_init_dt); |