Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 1 | /* bnx2x.h: Broadcom Everest network driver. |
| 2 | * |
Eliezer Tamir | 49d6677 | 2008-02-28 11:53:13 -0800 | [diff] [blame^] | 3 | * Copyright (c) 2007-2008 Broadcom Corporation |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify |
| 6 | * it under the terms of the GNU General Public License as published by |
| 7 | * the Free Software Foundation. |
| 8 | * |
| 9 | * Written by: Eliezer Tamir <eliezert@broadcom.com> |
| 10 | * Based on code from Michael Chan's bnx2 driver |
| 11 | */ |
| 12 | |
| 13 | #ifndef BNX2X_H |
| 14 | #define BNX2X_H |
| 15 | |
| 16 | /* error/debug prints */ |
| 17 | |
| 18 | #define DRV_MODULE_NAME "bnx2x" |
| 19 | #define PFX DRV_MODULE_NAME ": " |
| 20 | |
| 21 | /* for messages that are currently off */ |
| 22 | #define BNX2X_MSG_OFF 0 |
| 23 | #define BNX2X_MSG_MCP 0x10000 /* was: NETIF_MSG_HW */ |
| 24 | #define BNX2X_MSG_STATS 0x20000 /* was: NETIF_MSG_TIMER */ |
| 25 | #define NETIF_MSG_NVM 0x40000 /* was: NETIF_MSG_HW */ |
| 26 | #define NETIF_MSG_DMAE 0x80000 /* was: NETIF_MSG_HW */ |
Eliezer Tamir | f141064 | 2008-02-28 11:51:50 -0800 | [diff] [blame] | 27 | #define BNX2X_MSG_SP 0x100000 /* was: NETIF_MSG_INTR */ |
| 28 | #define BNX2X_MSG_FP 0x200000 /* was: NETIF_MSG_INTR */ |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 29 | |
| 30 | #define DP_LEVEL KERN_NOTICE /* was: KERN_DEBUG */ |
| 31 | |
| 32 | /* regular debug print */ |
| 33 | #define DP(__mask, __fmt, __args...) do { \ |
| 34 | if (bp->msglevel & (__mask)) \ |
| 35 | printk(DP_LEVEL "[%s:%d(%s)]" __fmt, __FUNCTION__, \ |
| 36 | __LINE__, bp->dev?(bp->dev->name):"?", ##__args); \ |
| 37 | } while (0) |
| 38 | |
| 39 | /* for errors (never masked) */ |
| 40 | #define BNX2X_ERR(__fmt, __args...) do { \ |
| 41 | printk(KERN_ERR "[%s:%d(%s)]" __fmt, __FUNCTION__, \ |
| 42 | __LINE__, bp->dev?(bp->dev->name):"?", ##__args); \ |
| 43 | } while (0) |
| 44 | |
Eliezer Tamir | f141064 | 2008-02-28 11:51:50 -0800 | [diff] [blame] | 45 | /* for logging (never masked) */ |
| 46 | #define BNX2X_LOG(__fmt, __args...) do { \ |
| 47 | printk(KERN_NOTICE "[%s:%d(%s)]" __fmt, __FUNCTION__, \ |
| 48 | __LINE__, bp->dev?(bp->dev->name):"?", ##__args); \ |
| 49 | } while (0) |
| 50 | |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 51 | /* before we have a dev->name use dev_info() */ |
| 52 | #define BNX2X_DEV_INFO(__fmt, __args...) do { \ |
| 53 | if (bp->msglevel & NETIF_MSG_PROBE) \ |
| 54 | dev_info(&bp->pdev->dev, __fmt, ##__args); \ |
| 55 | } while (0) |
| 56 | |
| 57 | |
| 58 | #ifdef BNX2X_STOP_ON_ERROR |
| 59 | #define bnx2x_panic() do { \ |
| 60 | bp->panic = 1; \ |
| 61 | BNX2X_ERR("driver assert\n"); \ |
| 62 | bnx2x_disable_int(bp); \ |
| 63 | bnx2x_panic_dump(bp); \ |
| 64 | } while (0) |
| 65 | #else |
| 66 | #define bnx2x_panic() do { \ |
| 67 | BNX2X_ERR("driver assert\n"); \ |
| 68 | bnx2x_panic_dump(bp); \ |
| 69 | } while (0) |
| 70 | #endif |
| 71 | |
| 72 | |
| 73 | #define U64_LO(x) (((u64)x) & 0xffffffff) |
| 74 | #define U64_HI(x) (((u64)x) >> 32) |
| 75 | #define HILO_U64(hi, lo) (((u64)hi << 32) + lo) |
| 76 | |
| 77 | |
| 78 | #define REG_ADDR(bp, offset) (bp->regview + offset) |
| 79 | |
| 80 | #define REG_RD(bp, offset) readl(REG_ADDR(bp, offset)) |
| 81 | #define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset)) |
| 82 | #define REG_RD64(bp, offset) readq(REG_ADDR(bp, offset)) |
| 83 | |
| 84 | #define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset)) |
| 85 | #define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset)) |
| 86 | #define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset)) |
| 87 | #define REG_WR32(bp, offset, val) REG_WR(bp, offset, val) |
| 88 | |
| 89 | #define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset) |
| 90 | #define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val) |
| 91 | |
| 92 | #define REG_WR_DMAE(bp, offset, val, len32) \ |
| 93 | do { \ |
| 94 | memcpy(bnx2x_sp(bp, wb_data[0]), val, len32 * 4); \ |
| 95 | bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \ |
| 96 | offset, len32); \ |
| 97 | } while (0) |
| 98 | |
| 99 | #define SHMEM_RD(bp, type) \ |
| 100 | REG_RD(bp, bp->shmem_base + offsetof(struct shmem_region, type)) |
| 101 | #define SHMEM_WR(bp, type, val) \ |
| 102 | REG_WR(bp, bp->shmem_base + offsetof(struct shmem_region, type), val) |
| 103 | |
| 104 | #define NIG_WR(reg, val) REG_WR(bp, reg, val) |
| 105 | #define EMAC_WR(reg, val) REG_WR(bp, emac_base + reg, val) |
| 106 | #define BMAC_WR(reg, val) REG_WR(bp, GRCBASE_NIG + bmac_addr + reg, val) |
| 107 | |
| 108 | |
| 109 | #define for_each_queue(bp, var) for (var = 0; var < bp->num_queues; var++) |
| 110 | |
| 111 | #define for_each_nondefault_queue(bp, var) \ |
| 112 | for (var = 1; var < bp->num_queues; var++) |
| 113 | #define is_multi(bp) (bp->num_queues > 1) |
| 114 | |
| 115 | |
| 116 | struct regp { |
| 117 | u32 lo; |
| 118 | u32 hi; |
| 119 | }; |
| 120 | |
| 121 | struct bmac_stats { |
| 122 | struct regp tx_gtpkt; |
| 123 | struct regp tx_gtxpf; |
| 124 | struct regp tx_gtfcs; |
| 125 | struct regp tx_gtmca; |
| 126 | struct regp tx_gtgca; |
| 127 | struct regp tx_gtfrg; |
| 128 | struct regp tx_gtovr; |
| 129 | struct regp tx_gt64; |
| 130 | struct regp tx_gt127; |
| 131 | struct regp tx_gt255; /* 10 */ |
| 132 | struct regp tx_gt511; |
| 133 | struct regp tx_gt1023; |
| 134 | struct regp tx_gt1518; |
| 135 | struct regp tx_gt2047; |
| 136 | struct regp tx_gt4095; |
| 137 | struct regp tx_gt9216; |
| 138 | struct regp tx_gt16383; |
| 139 | struct regp tx_gtmax; |
| 140 | struct regp tx_gtufl; |
| 141 | struct regp tx_gterr; /* 20 */ |
| 142 | struct regp tx_gtbyt; |
| 143 | |
| 144 | struct regp rx_gr64; |
| 145 | struct regp rx_gr127; |
| 146 | struct regp rx_gr255; |
| 147 | struct regp rx_gr511; |
| 148 | struct regp rx_gr1023; |
| 149 | struct regp rx_gr1518; |
| 150 | struct regp rx_gr2047; |
| 151 | struct regp rx_gr4095; |
| 152 | struct regp rx_gr9216; /* 30 */ |
| 153 | struct regp rx_gr16383; |
| 154 | struct regp rx_grmax; |
| 155 | struct regp rx_grpkt; |
| 156 | struct regp rx_grfcs; |
| 157 | struct regp rx_grmca; |
| 158 | struct regp rx_grbca; |
| 159 | struct regp rx_grxcf; |
| 160 | struct regp rx_grxpf; |
| 161 | struct regp rx_grxuo; |
| 162 | struct regp rx_grjbr; /* 40 */ |
| 163 | struct regp rx_grovr; |
| 164 | struct regp rx_grflr; |
| 165 | struct regp rx_grmeg; |
| 166 | struct regp rx_grmeb; |
| 167 | struct regp rx_grbyt; |
| 168 | struct regp rx_grund; |
| 169 | struct regp rx_grfrg; |
| 170 | struct regp rx_grerb; |
| 171 | struct regp rx_grfre; |
| 172 | struct regp rx_gripj; /* 50 */ |
| 173 | }; |
| 174 | |
| 175 | struct emac_stats { |
| 176 | u32 rx_ifhcinoctets ; |
| 177 | u32 rx_ifhcinbadoctets ; |
| 178 | u32 rx_etherstatsfragments ; |
| 179 | u32 rx_ifhcinucastpkts ; |
| 180 | u32 rx_ifhcinmulticastpkts ; |
| 181 | u32 rx_ifhcinbroadcastpkts ; |
| 182 | u32 rx_dot3statsfcserrors ; |
| 183 | u32 rx_dot3statsalignmenterrors ; |
| 184 | u32 rx_dot3statscarriersenseerrors ; |
| 185 | u32 rx_xonpauseframesreceived ; /* 10 */ |
| 186 | u32 rx_xoffpauseframesreceived ; |
| 187 | u32 rx_maccontrolframesreceived ; |
| 188 | u32 rx_xoffstateentered ; |
| 189 | u32 rx_dot3statsframestoolong ; |
| 190 | u32 rx_etherstatsjabbers ; |
| 191 | u32 rx_etherstatsundersizepkts ; |
| 192 | u32 rx_etherstatspkts64octets ; |
| 193 | u32 rx_etherstatspkts65octetsto127octets ; |
| 194 | u32 rx_etherstatspkts128octetsto255octets ; |
| 195 | u32 rx_etherstatspkts256octetsto511octets ; /* 20 */ |
| 196 | u32 rx_etherstatspkts512octetsto1023octets ; |
| 197 | u32 rx_etherstatspkts1024octetsto1522octets; |
| 198 | u32 rx_etherstatspktsover1522octets ; |
| 199 | |
| 200 | u32 rx_falsecarriererrors ; |
| 201 | |
| 202 | u32 tx_ifhcoutoctets ; |
| 203 | u32 tx_ifhcoutbadoctets ; |
| 204 | u32 tx_etherstatscollisions ; |
| 205 | u32 tx_outxonsent ; |
| 206 | u32 tx_outxoffsent ; |
| 207 | u32 tx_flowcontroldone ; /* 30 */ |
| 208 | u32 tx_dot3statssinglecollisionframes ; |
| 209 | u32 tx_dot3statsmultiplecollisionframes ; |
| 210 | u32 tx_dot3statsdeferredtransmissions ; |
| 211 | u32 tx_dot3statsexcessivecollisions ; |
| 212 | u32 tx_dot3statslatecollisions ; |
| 213 | u32 tx_ifhcoutucastpkts ; |
| 214 | u32 tx_ifhcoutmulticastpkts ; |
| 215 | u32 tx_ifhcoutbroadcastpkts ; |
| 216 | u32 tx_etherstatspkts64octets ; |
| 217 | u32 tx_etherstatspkts65octetsto127octets ; /* 40 */ |
| 218 | u32 tx_etherstatspkts128octetsto255octets ; |
| 219 | u32 tx_etherstatspkts256octetsto511octets ; |
| 220 | u32 tx_etherstatspkts512octetsto1023octets ; |
| 221 | u32 tx_etherstatspkts1024octetsto1522octet ; |
| 222 | u32 tx_etherstatspktsover1522octets ; |
| 223 | u32 tx_dot3statsinternalmactransmiterrors ; /* 46 */ |
| 224 | }; |
| 225 | |
| 226 | union mac_stats { |
| 227 | struct emac_stats emac; |
| 228 | struct bmac_stats bmac; |
| 229 | }; |
| 230 | |
| 231 | struct nig_stats { |
| 232 | u32 brb_discard; |
| 233 | u32 brb_packet; |
| 234 | u32 brb_truncate; |
| 235 | u32 flow_ctrl_discard; |
| 236 | u32 flow_ctrl_octets; |
| 237 | u32 flow_ctrl_packet; |
| 238 | u32 mng_discard; |
| 239 | u32 mng_octet_inp; |
| 240 | u32 mng_octet_out; |
| 241 | u32 mng_packet_inp; |
| 242 | u32 mng_packet_out; |
| 243 | u32 pbf_octets; |
| 244 | u32 pbf_packet; |
| 245 | u32 safc_inp; |
| 246 | u32 done; |
| 247 | u32 pad; |
| 248 | }; |
| 249 | |
| 250 | struct bnx2x_eth_stats { |
| 251 | u32 pad; /* to make long counters u64 aligned */ |
| 252 | u32 mac_stx_start; |
| 253 | u32 total_bytes_received_hi; |
| 254 | u32 total_bytes_received_lo; |
| 255 | u32 total_bytes_transmitted_hi; |
| 256 | u32 total_bytes_transmitted_lo; |
| 257 | u32 total_unicast_packets_received_hi; |
| 258 | u32 total_unicast_packets_received_lo; |
| 259 | u32 total_multicast_packets_received_hi; |
| 260 | u32 total_multicast_packets_received_lo; |
| 261 | u32 total_broadcast_packets_received_hi; |
| 262 | u32 total_broadcast_packets_received_lo; |
| 263 | u32 total_unicast_packets_transmitted_hi; |
| 264 | u32 total_unicast_packets_transmitted_lo; |
| 265 | u32 total_multicast_packets_transmitted_hi; |
| 266 | u32 total_multicast_packets_transmitted_lo; |
| 267 | u32 total_broadcast_packets_transmitted_hi; |
| 268 | u32 total_broadcast_packets_transmitted_lo; |
| 269 | u32 crc_receive_errors; |
| 270 | u32 alignment_errors; |
| 271 | u32 false_carrier_detections; |
| 272 | u32 runt_packets_received; |
| 273 | u32 jabber_packets_received; |
| 274 | u32 pause_xon_frames_received; |
| 275 | u32 pause_xoff_frames_received; |
| 276 | u32 pause_xon_frames_transmitted; |
| 277 | u32 pause_xoff_frames_transmitted; |
| 278 | u32 single_collision_transmit_frames; |
| 279 | u32 multiple_collision_transmit_frames; |
| 280 | u32 late_collision_frames; |
| 281 | u32 excessive_collision_frames; |
| 282 | u32 control_frames_received; |
| 283 | u32 frames_received_64_bytes; |
| 284 | u32 frames_received_65_127_bytes; |
| 285 | u32 frames_received_128_255_bytes; |
| 286 | u32 frames_received_256_511_bytes; |
| 287 | u32 frames_received_512_1023_bytes; |
| 288 | u32 frames_received_1024_1522_bytes; |
| 289 | u32 frames_received_1523_9022_bytes; |
| 290 | u32 frames_transmitted_64_bytes; |
| 291 | u32 frames_transmitted_65_127_bytes; |
| 292 | u32 frames_transmitted_128_255_bytes; |
| 293 | u32 frames_transmitted_256_511_bytes; |
| 294 | u32 frames_transmitted_512_1023_bytes; |
| 295 | u32 frames_transmitted_1024_1522_bytes; |
| 296 | u32 frames_transmitted_1523_9022_bytes; |
| 297 | u32 valid_bytes_received_hi; |
| 298 | u32 valid_bytes_received_lo; |
| 299 | u32 error_runt_packets_received; |
| 300 | u32 error_jabber_packets_received; |
| 301 | u32 mac_stx_end; |
| 302 | |
| 303 | u32 pad2; |
| 304 | u32 stat_IfHCInBadOctets_hi; |
| 305 | u32 stat_IfHCInBadOctets_lo; |
| 306 | u32 stat_IfHCOutBadOctets_hi; |
| 307 | u32 stat_IfHCOutBadOctets_lo; |
| 308 | u32 stat_Dot3statsFramesTooLong; |
| 309 | u32 stat_Dot3statsInternalMacTransmitErrors; |
| 310 | u32 stat_Dot3StatsCarrierSenseErrors; |
| 311 | u32 stat_Dot3StatsDeferredTransmissions; |
| 312 | u32 stat_FlowControlDone; |
| 313 | u32 stat_XoffStateEntered; |
| 314 | |
| 315 | u32 x_total_sent_bytes_hi; |
| 316 | u32 x_total_sent_bytes_lo; |
| 317 | u32 x_total_sent_pkts; |
| 318 | |
| 319 | u32 t_rcv_unicast_bytes_hi; |
| 320 | u32 t_rcv_unicast_bytes_lo; |
| 321 | u32 t_rcv_broadcast_bytes_hi; |
| 322 | u32 t_rcv_broadcast_bytes_lo; |
| 323 | u32 t_rcv_multicast_bytes_hi; |
| 324 | u32 t_rcv_multicast_bytes_lo; |
| 325 | u32 t_total_rcv_pkt; |
| 326 | |
| 327 | u32 checksum_discard; |
| 328 | u32 packets_too_big_discard; |
| 329 | u32 no_buff_discard; |
| 330 | u32 ttl0_discard; |
| 331 | u32 mac_discard; |
| 332 | u32 mac_filter_discard; |
| 333 | u32 xxoverflow_discard; |
| 334 | u32 brb_truncate_discard; |
| 335 | |
| 336 | u32 brb_discard; |
| 337 | u32 brb_packet; |
| 338 | u32 brb_truncate; |
| 339 | u32 flow_ctrl_discard; |
| 340 | u32 flow_ctrl_octets; |
| 341 | u32 flow_ctrl_packet; |
| 342 | u32 mng_discard; |
| 343 | u32 mng_octet_inp; |
| 344 | u32 mng_octet_out; |
| 345 | u32 mng_packet_inp; |
| 346 | u32 mng_packet_out; |
| 347 | u32 pbf_octets; |
| 348 | u32 pbf_packet; |
| 349 | u32 safc_inp; |
| 350 | u32 driver_xoff; |
| 351 | u32 number_of_bugs_found_in_stats_spec; /* just kidding */ |
| 352 | }; |
| 353 | |
| 354 | #define MAC_STX_NA 0xffffffff |
| 355 | |
| 356 | #ifdef BNX2X_MULTI |
| 357 | #define MAX_CONTEXT 16 |
| 358 | #else |
| 359 | #define MAX_CONTEXT 1 |
| 360 | #endif |
| 361 | |
| 362 | union cdu_context { |
| 363 | struct eth_context eth; |
| 364 | char pad[1024]; |
| 365 | }; |
| 366 | |
| 367 | #define MAX_DMAE_C 5 |
| 368 | |
| 369 | /* DMA memory not used in fastpath */ |
| 370 | struct bnx2x_slowpath { |
| 371 | union cdu_context context[MAX_CONTEXT]; |
| 372 | struct eth_stats_query fw_stats; |
| 373 | struct mac_configuration_cmd mac_config; |
| 374 | struct mac_configuration_cmd mcast_config; |
| 375 | |
| 376 | /* used by dmae command executer */ |
| 377 | struct dmae_command dmae[MAX_DMAE_C]; |
| 378 | |
| 379 | union mac_stats mac_stats; |
| 380 | struct nig_stats nig; |
| 381 | struct bnx2x_eth_stats eth_stats; |
| 382 | |
| 383 | u32 wb_comp; |
| 384 | #define BNX2X_WB_COMP_VAL 0xe0d0d0ae |
| 385 | u32 wb_data[4]; |
| 386 | }; |
| 387 | |
| 388 | #define bnx2x_sp(bp, var) (&bp->slowpath->var) |
| 389 | #define bnx2x_sp_check(bp, var) ((bp->slowpath) ? (&bp->slowpath->var) : NULL) |
| 390 | #define bnx2x_sp_mapping(bp, var) \ |
| 391 | (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var)) |
| 392 | |
| 393 | |
| 394 | struct sw_rx_bd { |
| 395 | struct sk_buff *skb; |
| 396 | DECLARE_PCI_UNMAP_ADDR(mapping) |
| 397 | }; |
| 398 | |
| 399 | struct sw_tx_bd { |
| 400 | struct sk_buff *skb; |
| 401 | u16 first_bd; |
| 402 | }; |
| 403 | |
| 404 | struct bnx2x_fastpath { |
| 405 | |
| 406 | struct napi_struct napi; |
| 407 | |
| 408 | struct host_status_block *status_blk; |
| 409 | dma_addr_t status_blk_mapping; |
| 410 | |
| 411 | struct eth_tx_db_data *hw_tx_prods; |
| 412 | dma_addr_t tx_prods_mapping; |
| 413 | |
| 414 | struct sw_tx_bd *tx_buf_ring; |
| 415 | |
| 416 | struct eth_tx_bd *tx_desc_ring; |
| 417 | dma_addr_t tx_desc_mapping; |
| 418 | |
| 419 | struct sw_rx_bd *rx_buf_ring; |
| 420 | |
| 421 | struct eth_rx_bd *rx_desc_ring; |
| 422 | dma_addr_t rx_desc_mapping; |
| 423 | |
| 424 | union eth_rx_cqe *rx_comp_ring; |
| 425 | dma_addr_t rx_comp_mapping; |
| 426 | |
| 427 | int state; |
| 428 | #define BNX2X_FP_STATE_CLOSED 0 |
| 429 | #define BNX2X_FP_STATE_IRQ 0x80000 |
| 430 | #define BNX2X_FP_STATE_OPENING 0x90000 |
| 431 | #define BNX2X_FP_STATE_OPEN 0xa0000 |
| 432 | #define BNX2X_FP_STATE_HALTING 0xb0000 |
| 433 | #define BNX2X_FP_STATE_HALTED 0xc0000 |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 434 | |
| 435 | int index; |
| 436 | |
| 437 | u16 tx_pkt_prod; |
| 438 | u16 tx_pkt_cons; |
| 439 | u16 tx_bd_prod; |
| 440 | u16 tx_bd_cons; |
| 441 | u16 *tx_cons_sb; |
| 442 | |
| 443 | u16 fp_c_idx; |
| 444 | u16 fp_u_idx; |
| 445 | |
| 446 | u16 rx_bd_prod; |
| 447 | u16 rx_bd_cons; |
| 448 | u16 rx_comp_prod; |
| 449 | u16 rx_comp_cons; |
| 450 | u16 *rx_cons_sb; |
| 451 | |
| 452 | unsigned long tx_pkt, |
| 453 | rx_pkt, |
| 454 | rx_calls; |
| 455 | |
| 456 | struct bnx2x *bp; /* parent */ |
| 457 | }; |
| 458 | |
| 459 | #define bnx2x_fp(bp, nr, var) (bp->fp[nr].var) |
| 460 | |
| 461 | |
| 462 | /* attn group wiring */ |
| 463 | #define MAX_DYNAMIC_ATTN_GRPS 8 |
| 464 | |
| 465 | struct attn_route { |
| 466 | u32 sig[4]; |
| 467 | }; |
| 468 | |
| 469 | struct bnx2x { |
| 470 | /* Fields used in the tx and intr/napi performance paths |
| 471 | * are grouped together in the beginning of the structure |
| 472 | */ |
| 473 | struct bnx2x_fastpath *fp; |
| 474 | void __iomem *regview; |
| 475 | void __iomem *doorbells; |
| 476 | |
| 477 | struct net_device *dev; |
| 478 | struct pci_dev *pdev; |
| 479 | |
| 480 | atomic_t intr_sem; |
| 481 | struct msix_entry msix_table[MAX_CONTEXT+1]; |
| 482 | |
| 483 | int tx_ring_size; |
| 484 | |
| 485 | #ifdef BCM_VLAN |
| 486 | struct vlan_group *vlgrp; |
| 487 | #endif |
| 488 | |
| 489 | u32 rx_csum; |
| 490 | u32 rx_offset; |
| 491 | u32 rx_buf_use_size; /* useable size */ |
| 492 | u32 rx_buf_size; /* with alignment */ |
| 493 | #define ETH_OVREHEAD (ETH_HLEN + 8) /* 8 for CRC + VLAN */ |
| 494 | #define ETH_MIN_PACKET_SIZE 60 |
| 495 | #define ETH_MAX_PACKET_SIZE 1500 |
| 496 | #define ETH_MAX_JUMBO_PACKET_SIZE 9600 |
| 497 | |
| 498 | struct host_def_status_block *def_status_blk; |
| 499 | #define DEF_SB_ID 16 |
| 500 | u16 def_c_idx; |
| 501 | u16 def_u_idx; |
| 502 | u16 def_t_idx; |
| 503 | u16 def_x_idx; |
| 504 | u16 def_att_idx; |
| 505 | u32 attn_state; |
| 506 | struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS]; |
| 507 | u32 aeu_mask; |
| 508 | u32 nig_mask; |
| 509 | |
| 510 | /* slow path ring */ |
| 511 | struct eth_spe *spq; |
| 512 | dma_addr_t spq_mapping; |
| 513 | u16 spq_prod_idx; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 514 | struct eth_spe *spq_prod_bd; |
| 515 | struct eth_spe *spq_last_bd; |
| 516 | u16 *dsb_sp_prod; |
| 517 | u16 spq_left; /* serialize spq */ |
| 518 | spinlock_t spq_lock; |
| 519 | |
| 520 | /* Flag for marking that there is either |
| 521 | * STAT_QUERY or CFC DELETE ramrod pending |
| 522 | */ |
| 523 | u8 stat_pending; |
| 524 | |
Eliezer Tamir | c14423f | 2008-02-28 11:49:42 -0800 | [diff] [blame] | 525 | /* End of fields used in the performance code paths */ |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 526 | |
| 527 | int panic; |
| 528 | int msglevel; |
| 529 | |
| 530 | u32 flags; |
| 531 | #define PCIX_FLAG 1 |
| 532 | #define PCI_32BIT_FLAG 2 |
| 533 | #define ONE_TDMA_FLAG 4 /* no longer used */ |
| 534 | #define NO_WOL_FLAG 8 |
| 535 | #define USING_DAC_FLAG 0x10 |
| 536 | #define USING_MSIX_FLAG 0x20 |
| 537 | #define ASF_ENABLE_FLAG 0x40 |
| 538 | |
| 539 | int port; |
| 540 | |
| 541 | int pm_cap; |
| 542 | int pcie_cap; |
| 543 | |
| 544 | /* Used to synchronize phy accesses */ |
| 545 | spinlock_t phy_lock; |
| 546 | |
| 547 | struct work_struct reset_task; |
| 548 | u16 in_reset_task; |
| 549 | |
| 550 | struct work_struct sp_task; |
| 551 | |
| 552 | struct timer_list timer; |
| 553 | int timer_interval; |
| 554 | int current_interval; |
| 555 | |
| 556 | u32 shmem_base; |
| 557 | |
| 558 | u32 chip_id; |
| 559 | /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ |
| 560 | #define CHIP_ID(bp) (((bp)->chip_id) & 0xfffffff0) |
| 561 | |
| 562 | #define CHIP_NUM(bp) (((bp)->chip_id) & 0xffff0000) |
| 563 | #define CHIP_NUM_5710 0x57100000 |
| 564 | |
| 565 | #define CHIP_REV(bp) (((bp)->chip_id) & 0x0000f000) |
| 566 | #define CHIP_REV_Ax 0x00000000 |
| 567 | #define CHIP_REV_Bx 0x00001000 |
| 568 | #define CHIP_REV_Cx 0x00002000 |
| 569 | #define CHIP_REV_EMUL 0x0000e000 |
| 570 | #define CHIP_REV_FPGA 0x0000f000 |
| 571 | #define CHIP_REV_IS_SLOW(bp) ((CHIP_REV(bp) == CHIP_REV_EMUL) || \ |
| 572 | (CHIP_REV(bp) == CHIP_REV_FPGA)) |
| 573 | |
| 574 | #define CHIP_METAL(bp) (((bp)->chip_id) & 0x00000ff0) |
| 575 | #define CHIP_BOND_ID(bp) (((bp)->chip_id) & 0x0000000f) |
| 576 | |
| 577 | u16 fw_seq; |
| 578 | u16 fw_drv_pulse_wr_seq; |
| 579 | u32 fw_mb; |
| 580 | |
| 581 | u32 hw_config; |
Eliezer Tamir | f141064 | 2008-02-28 11:51:50 -0800 | [diff] [blame] | 582 | u32 board; |
| 583 | u32 serdes_config; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 584 | u32 lane_config; |
| 585 | u32 ext_phy_config; |
| 586 | #define XGXS_EXT_PHY_TYPE(bp) (bp->ext_phy_config & \ |
| 587 | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK) |
| 588 | #define SERDES_EXT_PHY_TYPE(bp) (bp->ext_phy_config & \ |
| 589 | PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK) |
| 590 | |
| 591 | u32 speed_cap_mask; |
| 592 | u32 link_config; |
| 593 | #define SWITCH_CFG_1G PORT_FEATURE_CON_SWITCH_1G_SWITCH |
| 594 | #define SWITCH_CFG_10G PORT_FEATURE_CON_SWITCH_10G_SWITCH |
| 595 | #define SWITCH_CFG_AUTO_DETECT PORT_FEATURE_CON_SWITCH_AUTO_DETECT |
| 596 | #define SWITCH_CFG_ONE_TIME_DETECT \ |
| 597 | PORT_FEATURE_CON_SWITCH_ONE_TIME_DETECT |
| 598 | |
| 599 | u8 ser_lane; |
| 600 | u8 rx_lane_swap; |
| 601 | u8 tx_lane_swap; |
| 602 | |
| 603 | u8 link_up; |
Eliezer Tamir | f141064 | 2008-02-28 11:51:50 -0800 | [diff] [blame] | 604 | u8 phy_link_up; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 605 | |
| 606 | u32 supported; |
| 607 | /* link settings - missing defines */ |
| 608 | #define SUPPORTED_2500baseT_Full (1 << 15) |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 609 | |
| 610 | u32 phy_flags; |
| 611 | /*#define PHY_SERDES_FLAG 0x1*/ |
| 612 | #define PHY_BMAC_FLAG 0x2 |
| 613 | #define PHY_EMAC_FLAG 0x4 |
| 614 | #define PHY_XGXS_FLAG 0x8 |
| 615 | #define PHY_SGMII_FLAG 0x10 |
| 616 | #define PHY_INT_MODE_MASK_FLAG 0x300 |
| 617 | #define PHY_INT_MODE_AUTO_POLLING_FLAG 0x100 |
| 618 | #define PHY_INT_MODE_LINK_READY_FLAG 0x200 |
| 619 | |
| 620 | u32 phy_addr; |
| 621 | u32 phy_id; |
| 622 | |
| 623 | u32 autoneg; |
| 624 | #define AUTONEG_CL37 SHARED_HW_CFG_AN_ENABLE_CL37 |
| 625 | #define AUTONEG_CL73 SHARED_HW_CFG_AN_ENABLE_CL73 |
| 626 | #define AUTONEG_BAM SHARED_HW_CFG_AN_ENABLE_BAM |
| 627 | #define AUTONEG_PARALLEL \ |
| 628 | SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION |
| 629 | #define AUTONEG_SGMII_FIBER_AUTODET \ |
| 630 | SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT |
| 631 | #define AUTONEG_REMOTE_PHY SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY |
| 632 | |
| 633 | u32 req_autoneg; |
| 634 | #define AUTONEG_SPEED 0x1 |
| 635 | #define AUTONEG_FLOW_CTRL 0x2 |
| 636 | |
| 637 | u32 req_line_speed; |
| 638 | /* link settings - missing defines */ |
| 639 | #define SPEED_12000 12000 |
| 640 | #define SPEED_12500 12500 |
| 641 | #define SPEED_13000 13000 |
| 642 | #define SPEED_15000 15000 |
| 643 | #define SPEED_16000 16000 |
| 644 | |
| 645 | u32 req_duplex; |
| 646 | u32 req_flow_ctrl; |
| 647 | #define FLOW_CTRL_AUTO PORT_FEATURE_FLOW_CONTROL_AUTO |
| 648 | #define FLOW_CTRL_TX PORT_FEATURE_FLOW_CONTROL_TX |
| 649 | #define FLOW_CTRL_RX PORT_FEATURE_FLOW_CONTROL_RX |
| 650 | #define FLOW_CTRL_BOTH PORT_FEATURE_FLOW_CONTROL_BOTH |
| 651 | #define FLOW_CTRL_NONE PORT_FEATURE_FLOW_CONTROL_NONE |
| 652 | |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 653 | u32 advertising; |
| 654 | /* link settings - missing defines */ |
| 655 | #define ADVERTISED_2500baseT_Full (1 << 15) |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 656 | |
| 657 | u32 link_status; |
| 658 | u32 line_speed; |
| 659 | u32 duplex; |
| 660 | u32 flow_ctrl; |
| 661 | |
| 662 | u32 bc_ver; |
| 663 | |
| 664 | int flash_size; |
| 665 | #define NVRAM_1MB_SIZE 0x20000 /* 1M bit in bytes */ |
| 666 | #define NVRAM_TIMEOUT_COUNT 30000 |
| 667 | #define NVRAM_PAGE_SIZE 256 |
| 668 | |
Eliezer Tamir | f141064 | 2008-02-28 11:51:50 -0800 | [diff] [blame] | 669 | u8 wol; |
| 670 | |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 671 | int rx_ring_size; |
| 672 | |
| 673 | u16 tx_quick_cons_trip_int; |
| 674 | u16 tx_quick_cons_trip; |
| 675 | u16 tx_ticks_int; |
| 676 | u16 tx_ticks; |
| 677 | |
| 678 | u16 rx_quick_cons_trip_int; |
| 679 | u16 rx_quick_cons_trip; |
| 680 | u16 rx_ticks_int; |
| 681 | u16 rx_ticks; |
| 682 | |
| 683 | u32 stats_ticks; |
| 684 | |
| 685 | int state; |
| 686 | #define BNX2X_STATE_CLOSED 0x0 |
| 687 | #define BNX2X_STATE_OPENING_WAIT4_LOAD 0x1000 |
| 688 | #define BNX2X_STATE_OPENING_WAIT4_PORT 0x2000 |
| 689 | #define BNX2X_STATE_OPEN 0x3000 |
| 690 | #define BNX2X_STATE_CLOSING_WAIT4_HALT 0x4000 |
| 691 | #define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000 |
| 692 | #define BNX2X_STATE_CLOSING_WAIT4_UNLOAD 0x6000 |
| 693 | #define BNX2X_STATE_ERROR 0xF000 |
| 694 | |
| 695 | int num_queues; |
| 696 | |
| 697 | u32 rx_mode; |
| 698 | #define BNX2X_RX_MODE_NONE 0 |
| 699 | #define BNX2X_RX_MODE_NORMAL 1 |
| 700 | #define BNX2X_RX_MODE_ALLMULTI 2 |
| 701 | #define BNX2X_RX_MODE_PROMISC 3 |
| 702 | #define BNX2X_MAX_MULTICAST 64 |
| 703 | #define BNX2X_MAX_EMUL_MULTI 16 |
| 704 | |
| 705 | dma_addr_t def_status_blk_mapping; |
| 706 | |
| 707 | struct bnx2x_slowpath *slowpath; |
| 708 | dma_addr_t slowpath_mapping; |
| 709 | |
| 710 | #ifdef BCM_ISCSI |
| 711 | void *t1; |
| 712 | dma_addr_t t1_mapping; |
| 713 | void *t2; |
| 714 | dma_addr_t t2_mapping; |
| 715 | void *timers; |
| 716 | dma_addr_t timers_mapping; |
| 717 | void *qm; |
| 718 | dma_addr_t qm_mapping; |
| 719 | #endif |
| 720 | |
| 721 | char *name; |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 722 | |
| 723 | /* used to synchronize stats collecting */ |
| 724 | int stats_state; |
| 725 | #define STATS_STATE_DISABLE 0 |
| 726 | #define STATS_STATE_ENABLE 1 |
| 727 | #define STATS_STATE_STOP 2 /* stop stats on next iteration */ |
| 728 | |
| 729 | /* used by dmae command loader */ |
| 730 | struct dmae_command dmae; |
| 731 | int executer_idx; |
| 732 | |
| 733 | u32 old_brb_discard; |
| 734 | struct bmac_stats old_bmac; |
| 735 | struct tstorm_per_client_stats old_tclient; |
| 736 | struct z_stream_s *strm; |
| 737 | void *gunzip_buf; |
| 738 | dma_addr_t gunzip_mapping; |
| 739 | int gunzip_outlen; |
| 740 | #define FW_BUF_SIZE 0x8000 |
| 741 | |
| 742 | }; |
| 743 | |
| 744 | |
| 745 | /* DMAE command defines */ |
| 746 | #define DMAE_CMD_SRC_PCI 0 |
| 747 | #define DMAE_CMD_SRC_GRC DMAE_COMMAND_SRC |
| 748 | |
| 749 | #define DMAE_CMD_DST_PCI (1 << DMAE_COMMAND_DST_SHIFT) |
| 750 | #define DMAE_CMD_DST_GRC (2 << DMAE_COMMAND_DST_SHIFT) |
| 751 | |
| 752 | #define DMAE_CMD_C_DST_PCI 0 |
| 753 | #define DMAE_CMD_C_DST_GRC (1 << DMAE_COMMAND_C_DST_SHIFT) |
| 754 | |
| 755 | #define DMAE_CMD_C_ENABLE DMAE_COMMAND_C_TYPE_ENABLE |
| 756 | |
| 757 | #define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT) |
| 758 | #define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT) |
| 759 | #define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT) |
| 760 | #define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT) |
| 761 | |
| 762 | #define DMAE_CMD_PORT_0 0 |
| 763 | #define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT |
| 764 | |
| 765 | #define DMAE_CMD_SRC_RESET DMAE_COMMAND_SRC_RESET |
| 766 | #define DMAE_CMD_DST_RESET DMAE_COMMAND_DST_RESET |
| 767 | |
| 768 | #define DMAE_LEN32_MAX 0x400 |
| 769 | |
| 770 | |
| 771 | /* MC hsi */ |
| 772 | #define RX_COPY_THRESH 92 |
| 773 | #define BCM_PAGE_BITS 12 |
| 774 | #define BCM_PAGE_SIZE (1 << BCM_PAGE_BITS) |
| 775 | |
| 776 | #define NUM_TX_RINGS 16 |
| 777 | #define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_tx_bd)) |
| 778 | #define MAX_TX_DESC_CNT (TX_DESC_CNT - 1) |
| 779 | #define NUM_TX_BD (TX_DESC_CNT * NUM_TX_RINGS) |
| 780 | #define MAX_TX_BD (NUM_TX_BD - 1) |
| 781 | #define MAX_TX_AVAIL (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2) |
| 782 | #define NEXT_TX_IDX(x) ((((x) & MAX_TX_DESC_CNT) == \ |
| 783 | (MAX_TX_DESC_CNT - 1)) ? (x) + 2 : (x) + 1) |
| 784 | #define TX_BD(x) ((x) & MAX_TX_BD) |
| 785 | #define TX_BD_POFF(x) ((x) & MAX_TX_DESC_CNT) |
| 786 | |
| 787 | /* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */ |
| 788 | #define NUM_RX_RINGS 8 |
| 789 | #define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd)) |
| 790 | #define MAX_RX_DESC_CNT (RX_DESC_CNT - 2) |
| 791 | #define RX_DESC_MASK (RX_DESC_CNT - 1) |
| 792 | #define NUM_RX_BD (RX_DESC_CNT * NUM_RX_RINGS) |
| 793 | #define MAX_RX_BD (NUM_RX_BD - 1) |
| 794 | #define MAX_RX_AVAIL (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2) |
| 795 | #define NEXT_RX_IDX(x) ((((x) & RX_DESC_MASK) == \ |
| 796 | (MAX_RX_DESC_CNT - 1)) ? (x) + 3 : (x) + 1) |
| 797 | #define RX_BD(x) ((x) & MAX_RX_BD) |
| 798 | |
| 799 | #define NUM_RCQ_RINGS (NUM_RX_RINGS * 2) |
| 800 | #define RCQ_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe)) |
| 801 | #define MAX_RCQ_DESC_CNT (RCQ_DESC_CNT - 1) |
| 802 | #define NUM_RCQ_BD (RCQ_DESC_CNT * NUM_RCQ_RINGS) |
| 803 | #define MAX_RCQ_BD (NUM_RCQ_BD - 1) |
| 804 | #define MAX_RCQ_AVAIL (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2) |
| 805 | #define NEXT_RCQ_IDX(x) ((((x) & MAX_RCQ_DESC_CNT) == \ |
| 806 | (MAX_RCQ_DESC_CNT - 1)) ? (x) + 2 : (x) + 1) |
| 807 | #define RCQ_BD(x) ((x) & MAX_RCQ_BD) |
| 808 | |
| 809 | |
| 810 | /* used on a CID received from the HW */ |
| 811 | #define SW_CID(x) (le32_to_cpu(x) & \ |
| 812 | (COMMON_RAMROD_ETH_RX_CQE_CID >> 1)) |
| 813 | #define CQE_CMD(x) (le32_to_cpu(x) >> \ |
| 814 | COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT) |
| 815 | |
| 816 | #define BD_UNMAP_ADDR(bd) HILO_U64(le32_to_cpu((bd)->addr_hi), \ |
| 817 | le32_to_cpu((bd)->addr_lo)) |
| 818 | #define BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes)) |
| 819 | |
| 820 | |
| 821 | #define STROM_ASSERT_ARRAY_SIZE 50 |
| 822 | |
| 823 | |
| 824 | #define MDIO_INDIRECT_REG_ADDR 0x1f |
| 825 | #define MDIO_SET_REG_BANK(bp, reg_bank) \ |
| 826 | bnx2x_mdio22_write(bp, MDIO_INDIRECT_REG_ADDR, reg_bank) |
| 827 | |
| 828 | #define MDIO_ACCESS_TIMEOUT 1000 |
| 829 | |
| 830 | |
| 831 | /* must be used on a CID before placing it on a HW ring */ |
| 832 | #define HW_CID(bp, x) (x | (bp->port << 23)) |
| 833 | |
| 834 | #define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe)) |
| 835 | #define MAX_SP_DESC_CNT (SP_DESC_CNT - 1) |
| 836 | |
| 837 | #define ATTN_NIG_FOR_FUNC (1L << 8) |
| 838 | #define ATTN_SW_TIMER_4_FUNC (1L << 9) |
| 839 | #define GPIO_2_FUNC (1L << 10) |
| 840 | #define GPIO_3_FUNC (1L << 11) |
| 841 | #define GPIO_4_FUNC (1L << 12) |
| 842 | #define ATTN_GENERAL_ATTN_1 (1L << 13) |
| 843 | #define ATTN_GENERAL_ATTN_2 (1L << 14) |
| 844 | #define ATTN_GENERAL_ATTN_3 (1L << 15) |
| 845 | #define ATTN_GENERAL_ATTN_4 (1L << 13) |
| 846 | #define ATTN_GENERAL_ATTN_5 (1L << 14) |
| 847 | #define ATTN_GENERAL_ATTN_6 (1L << 15) |
| 848 | |
| 849 | #define ATTN_HARD_WIRED_MASK 0xff00 |
| 850 | #define ATTENTION_ID 4 |
| 851 | |
| 852 | |
| 853 | #define BNX2X_BTR 3 |
| 854 | #define MAX_SPQ_PENDING 8 |
| 855 | |
| 856 | |
| 857 | #define BNX2X_NUM_STATS 31 |
| 858 | #define BNX2X_NUM_TESTS 2 |
| 859 | |
| 860 | |
| 861 | #define DPM_TRIGER_TYPE 0x40 |
| 862 | #define DOORBELL(bp, cid, val) \ |
| 863 | do { \ |
| 864 | writel((u32)val, (bp)->doorbells + (BCM_PAGE_SIZE * cid) + \ |
| 865 | DPM_TRIGER_TYPE); \ |
| 866 | } while (0) |
| 867 | |
Eliezer Tamir | 2504795 | 2008-02-28 11:50:16 -0800 | [diff] [blame] | 868 | /* PCIE link and speed */ |
| 869 | #define PCICFG_LINK_WIDTH 0x1f00000 |
| 870 | #define PCICFG_LINK_WIDTH_SHIFT 20 |
| 871 | #define PCICFG_LINK_SPEED 0xf0000 |
| 872 | #define PCICFG_LINK_SPEED_SHIFT 16 |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 873 | |
Eliezer Tamir | f141064 | 2008-02-28 11:51:50 -0800 | [diff] [blame] | 874 | #define BMAC_CONTROL_RX_ENABLE 2 |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 875 | /* stuff added to make the code fit 80Col */ |
| 876 | |
| 877 | #define TPA_TYPE_START ETH_FAST_PATH_RX_CQE_START_FLG |
| 878 | #define TPA_TYPE_END ETH_FAST_PATH_RX_CQE_END_FLG |
| 879 | #define TPA_TYPE(cqe) (cqe->fast_path_cqe.error_type_flags & \ |
| 880 | (TPA_TYPE_START | TPA_TYPE_END)) |
| 881 | #define BNX2X_RX_SUM_OK(cqe) \ |
| 882 | (!(cqe->fast_path_cqe.status_flags & \ |
| 883 | (ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG | \ |
| 884 | ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG))) |
| 885 | |
| 886 | #define BNX2X_RX_SUM_FIX(cqe) \ |
| 887 | ((le16_to_cpu(cqe->fast_path_cqe.pars_flags.flags) & \ |
| 888 | PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) == \ |
| 889 | (1 << PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT)) |
| 890 | |
| 891 | |
| 892 | #define MDIO_AN_CL73_OR_37_COMPLETE \ |
| 893 | (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \ |
| 894 | MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE) |
| 895 | |
| 896 | #define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \ |
| 897 | MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE |
| 898 | #define GP_STATUS_PAUSE_RSOLUTION_RXSIDE \ |
| 899 | MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE |
| 900 | #define GP_STATUS_SPEED_MASK \ |
| 901 | MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK |
| 902 | #define GP_STATUS_10M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M |
| 903 | #define GP_STATUS_100M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M |
| 904 | #define GP_STATUS_1G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G |
| 905 | #define GP_STATUS_2_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G |
| 906 | #define GP_STATUS_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G |
| 907 | #define GP_STATUS_6G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G |
| 908 | #define GP_STATUS_10G_HIG \ |
| 909 | MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG |
| 910 | #define GP_STATUS_10G_CX4 \ |
| 911 | MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4 |
| 912 | #define GP_STATUS_12G_HIG \ |
| 913 | MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG |
| 914 | #define GP_STATUS_12_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G |
| 915 | #define GP_STATUS_13G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G |
| 916 | #define GP_STATUS_15G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G |
| 917 | #define GP_STATUS_16G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G |
| 918 | #define GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX |
| 919 | #define GP_STATUS_10G_KX4 \ |
| 920 | MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4 |
| 921 | |
| 922 | #define LINK_10THD LINK_STATUS_SPEED_AND_DUPLEX_10THD |
| 923 | #define LINK_10TFD LINK_STATUS_SPEED_AND_DUPLEX_10TFD |
| 924 | #define LINK_100TXHD LINK_STATUS_SPEED_AND_DUPLEX_100TXHD |
| 925 | #define LINK_100T4 LINK_STATUS_SPEED_AND_DUPLEX_100T4 |
| 926 | #define LINK_100TXFD LINK_STATUS_SPEED_AND_DUPLEX_100TXFD |
| 927 | #define LINK_1000THD LINK_STATUS_SPEED_AND_DUPLEX_1000THD |
| 928 | #define LINK_1000TFD LINK_STATUS_SPEED_AND_DUPLEX_1000TFD |
| 929 | #define LINK_1000XFD LINK_STATUS_SPEED_AND_DUPLEX_1000XFD |
| 930 | #define LINK_2500THD LINK_STATUS_SPEED_AND_DUPLEX_2500THD |
| 931 | #define LINK_2500TFD LINK_STATUS_SPEED_AND_DUPLEX_2500TFD |
| 932 | #define LINK_2500XFD LINK_STATUS_SPEED_AND_DUPLEX_2500XFD |
| 933 | #define LINK_10GTFD LINK_STATUS_SPEED_AND_DUPLEX_10GTFD |
| 934 | #define LINK_10GXFD LINK_STATUS_SPEED_AND_DUPLEX_10GXFD |
| 935 | #define LINK_12GTFD LINK_STATUS_SPEED_AND_DUPLEX_12GTFD |
| 936 | #define LINK_12GXFD LINK_STATUS_SPEED_AND_DUPLEX_12GXFD |
| 937 | #define LINK_12_5GTFD LINK_STATUS_SPEED_AND_DUPLEX_12_5GTFD |
| 938 | #define LINK_12_5GXFD LINK_STATUS_SPEED_AND_DUPLEX_12_5GXFD |
| 939 | #define LINK_13GTFD LINK_STATUS_SPEED_AND_DUPLEX_13GTFD |
| 940 | #define LINK_13GXFD LINK_STATUS_SPEED_AND_DUPLEX_13GXFD |
| 941 | #define LINK_15GTFD LINK_STATUS_SPEED_AND_DUPLEX_15GTFD |
| 942 | #define LINK_15GXFD LINK_STATUS_SPEED_AND_DUPLEX_15GXFD |
| 943 | #define LINK_16GTFD LINK_STATUS_SPEED_AND_DUPLEX_16GTFD |
| 944 | #define LINK_16GXFD LINK_STATUS_SPEED_AND_DUPLEX_16GXFD |
| 945 | |
Eliezer Tamir | f141064 | 2008-02-28 11:51:50 -0800 | [diff] [blame] | 946 | #define NIG_STATUS_XGXS0_LINK10G \ |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 947 | NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G |
Eliezer Tamir | f141064 | 2008-02-28 11:51:50 -0800 | [diff] [blame] | 948 | #define NIG_STATUS_XGXS0_LINK_STATUS \ |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 949 | NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS |
Eliezer Tamir | f141064 | 2008-02-28 11:51:50 -0800 | [diff] [blame] | 950 | #define NIG_STATUS_XGXS0_LINK_STATUS_SIZE \ |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 951 | NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE |
Eliezer Tamir | f141064 | 2008-02-28 11:51:50 -0800 | [diff] [blame] | 952 | #define NIG_STATUS_SERDES0_LINK_STATUS \ |
Eliezer Tamir | a2fbb9e | 2007-11-15 20:09:02 +0200 | [diff] [blame] | 953 | NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS |
| 954 | #define NIG_MASK_MI_INT \ |
| 955 | NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT |
| 956 | #define NIG_MASK_XGXS0_LINK10G \ |
| 957 | NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G |
| 958 | #define NIG_MASK_XGXS0_LINK_STATUS \ |
| 959 | NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS |
| 960 | #define NIG_MASK_SERDES0_LINK_STATUS \ |
| 961 | NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS |
| 962 | |
| 963 | #define XGXS_RESET_BITS \ |
| 964 | (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW | \ |
| 965 | MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ | \ |
| 966 | MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN | \ |
| 967 | MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \ |
| 968 | MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB) |
| 969 | |
| 970 | #define SERDES_RESET_BITS \ |
| 971 | (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \ |
| 972 | MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ | \ |
| 973 | MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN | \ |
| 974 | MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD) |
| 975 | |
| 976 | |
| 977 | #define BNX2X_MC_ASSERT_BITS \ |
| 978 | (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ |
| 979 | GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \ |
| 980 | GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ |
| 981 | GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT)) |
| 982 | |
| 983 | #define BNX2X_MCP_ASSERT \ |
| 984 | GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT) |
| 985 | |
| 986 | #define BNX2X_DOORQ_ASSERT \ |
| 987 | AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT |
| 988 | |
| 989 | #define HW_INTERRUT_ASSERT_SET_0 \ |
| 990 | (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \ |
| 991 | AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \ |
| 992 | AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \ |
| 993 | AEU_INPUTS_ATTN_BITS_PBF_HW_INTERRUPT) |
| 994 | #define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \ |
| 995 | AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \ |
| 996 | AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \ |
| 997 | AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\ |
| 998 | AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR) |
| 999 | #define HW_INTERRUT_ASSERT_SET_1 \ |
| 1000 | (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \ |
| 1001 | AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \ |
| 1002 | AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \ |
| 1003 | AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \ |
| 1004 | AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \ |
| 1005 | AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \ |
| 1006 | AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \ |
| 1007 | AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \ |
| 1008 | AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \ |
| 1009 | AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \ |
| 1010 | AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT) |
| 1011 | #define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR |\ |
| 1012 | AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \ |
| 1013 | AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \ |
| 1014 | AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \ |
| 1015 | AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\ |
| 1016 | AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\ |
| 1017 | AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \ |
| 1018 | AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \ |
| 1019 | AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \ |
| 1020 | AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \ |
| 1021 | AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR) |
| 1022 | #define HW_INTERRUT_ASSERT_SET_2 \ |
| 1023 | (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \ |
| 1024 | AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \ |
| 1025 | AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \ |
| 1026 | AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\ |
| 1027 | AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT) |
| 1028 | #define HW_PRTY_ASSERT_SET_2 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \ |
| 1029 | AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \ |
| 1030 | AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\ |
| 1031 | AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \ |
| 1032 | AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \ |
| 1033 | AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \ |
| 1034 | AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR) |
| 1035 | |
| 1036 | |
| 1037 | #define ETH_RX_ERROR_FALGS (ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG | \ |
| 1038 | ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG | \ |
| 1039 | ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG) |
| 1040 | |
| 1041 | |
| 1042 | #define MULTI_FLAGS \ |
| 1043 | (TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY | \ |
| 1044 | TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY | \ |
| 1045 | TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY | \ |
| 1046 | TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY | \ |
| 1047 | TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_ENABLE) |
| 1048 | |
| 1049 | #define MULTI_MASK 0x7f |
| 1050 | |
| 1051 | |
| 1052 | #define U_SB_ETH_RX_CQ_INDEX HC_INDEX_U_ETH_RX_CQ_CONS |
| 1053 | #define C_SB_ETH_TX_CQ_INDEX HC_INDEX_C_ETH_TX_CQ_CONS |
| 1054 | #define C_DEF_SB_SP_INDEX HC_INDEX_DEF_C_ETH_SLOW_PATH |
| 1055 | |
| 1056 | #define BNX2X_RX_SB_INDEX \ |
| 1057 | &fp->status_blk->u_status_block.index_values[U_SB_ETH_RX_CQ_INDEX] |
| 1058 | |
| 1059 | #define BNX2X_TX_SB_INDEX \ |
| 1060 | &fp->status_blk->c_status_block.index_values[C_SB_ETH_TX_CQ_INDEX] |
| 1061 | |
| 1062 | #define BNX2X_SP_DSB_INDEX \ |
| 1063 | &bp->def_status_blk->c_def_status_block.index_values[C_DEF_SB_SP_INDEX] |
| 1064 | |
| 1065 | |
| 1066 | #define CAM_IS_INVALID(x) \ |
| 1067 | (x.target_table_entry.flags == TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE) |
| 1068 | |
| 1069 | #define CAM_INVALIDATE(x) \ |
| 1070 | x.target_table_entry.flags = TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE |
| 1071 | |
| 1072 | |
| 1073 | /* MISC_REG_RESET_REG - this is here for the hsi to work don't touch */ |
| 1074 | |
| 1075 | #endif /* bnx2x.h */ |