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Xiubo Lib5051832014-02-27 17:39:49 +08001/*
2 * Freescale FlexTimer Module (FTM) PWM Driver
3 *
4 * Copyright 2012-2013 Freescale Semiconductor, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12#include <linux/clk.h>
13#include <linux/err.h>
14#include <linux/io.h>
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/mutex.h>
18#include <linux/of_address.h>
19#include <linux/platform_device.h>
20#include <linux/pwm.h>
Xiubo Li42fa98a2014-08-19 12:38:02 +080021#include <linux/regmap.h>
Xiubo Lib5051832014-02-27 17:39:49 +080022#include <linux/slab.h>
23
24#define FTM_SC 0x00
Xiubo Licd6d92d2014-08-19 12:38:01 +080025#define FTM_SC_CLK_MASK_SHIFT 3
26#define FTM_SC_CLK_MASK (3 << FTM_SC_CLK_MASK_SHIFT)
27#define FTM_SC_CLK(c) (((c) + 1) << FTM_SC_CLK_MASK_SHIFT)
Xiubo Lib5051832014-02-27 17:39:49 +080028#define FTM_SC_PS_MASK 0x7
Xiubo Lib5051832014-02-27 17:39:49 +080029
30#define FTM_CNT 0x04
31#define FTM_MOD 0x08
32
33#define FTM_CSC_BASE 0x0C
34#define FTM_CSC_MSB BIT(5)
35#define FTM_CSC_MSA BIT(4)
36#define FTM_CSC_ELSB BIT(3)
37#define FTM_CSC_ELSA BIT(2)
38#define FTM_CSC(_channel) (FTM_CSC_BASE + ((_channel) * 8))
39
40#define FTM_CV_BASE 0x10
41#define FTM_CV(_channel) (FTM_CV_BASE + ((_channel) * 8))
42
43#define FTM_CNTIN 0x4C
44#define FTM_STATUS 0x50
45
46#define FTM_MODE 0x54
47#define FTM_MODE_FTMEN BIT(0)
48#define FTM_MODE_INIT BIT(2)
49#define FTM_MODE_PWMSYNC BIT(3)
50
51#define FTM_SYNC 0x58
52#define FTM_OUTINIT 0x5C
53#define FTM_OUTMASK 0x60
54#define FTM_COMBINE 0x64
55#define FTM_DEADTIME 0x68
56#define FTM_EXTTRIG 0x6C
57#define FTM_POL 0x70
58#define FTM_FMS 0x74
59#define FTM_FILTER 0x78
60#define FTM_FLTCTRL 0x7C
61#define FTM_QDCTRL 0x80
62#define FTM_CONF 0x84
63#define FTM_FLTPOL 0x88
64#define FTM_SYNCONF 0x8C
65#define FTM_INVCTRL 0x90
66#define FTM_SWOCTRL 0x94
67#define FTM_PWMLOAD 0x98
68
69enum fsl_pwm_clk {
70 FSL_PWM_CLK_SYS,
71 FSL_PWM_CLK_FIX,
72 FSL_PWM_CLK_EXT,
73 FSL_PWM_CLK_CNTEN,
74 FSL_PWM_CLK_MAX
75};
76
77struct fsl_pwm_chip {
78 struct pwm_chip chip;
79
80 struct mutex lock;
81
82 unsigned int use_count;
83 unsigned int cnt_select;
84 unsigned int clk_ps;
85
Xiubo Li42fa98a2014-08-19 12:38:02 +080086 struct regmap *regmap;
Xiubo Lib5051832014-02-27 17:39:49 +080087
88 int period_ns;
89
90 struct clk *clk[FSL_PWM_CLK_MAX];
91};
92
93static inline struct fsl_pwm_chip *to_fsl_chip(struct pwm_chip *chip)
94{
95 return container_of(chip, struct fsl_pwm_chip, chip);
96}
97
98static int fsl_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
99{
100 struct fsl_pwm_chip *fpc = to_fsl_chip(chip);
101
102 return clk_prepare_enable(fpc->clk[FSL_PWM_CLK_SYS]);
103}
104
105static void fsl_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
106{
107 struct fsl_pwm_chip *fpc = to_fsl_chip(chip);
108
109 clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_SYS]);
110}
111
112static int fsl_pwm_calculate_default_ps(struct fsl_pwm_chip *fpc,
113 enum fsl_pwm_clk index)
114{
115 unsigned long sys_rate, cnt_rate;
116 unsigned long long ratio;
117
118 sys_rate = clk_get_rate(fpc->clk[FSL_PWM_CLK_SYS]);
119 if (!sys_rate)
120 return -EINVAL;
121
122 cnt_rate = clk_get_rate(fpc->clk[fpc->cnt_select]);
123 if (!cnt_rate)
124 return -EINVAL;
125
126 switch (index) {
127 case FSL_PWM_CLK_SYS:
128 fpc->clk_ps = 1;
129 break;
130 case FSL_PWM_CLK_FIX:
131 ratio = 2 * cnt_rate - 1;
132 do_div(ratio, sys_rate);
133 fpc->clk_ps = ratio;
134 break;
135 case FSL_PWM_CLK_EXT:
136 ratio = 4 * cnt_rate - 1;
137 do_div(ratio, sys_rate);
138 fpc->clk_ps = ratio;
139 break;
140 default:
141 return -EINVAL;
142 }
143
144 return 0;
145}
146
147static unsigned long fsl_pwm_calculate_cycles(struct fsl_pwm_chip *fpc,
148 unsigned long period_ns)
149{
150 unsigned long long c, c0;
151
152 c = clk_get_rate(fpc->clk[fpc->cnt_select]);
153 c = c * period_ns;
154 do_div(c, 1000000000UL);
155
156 do {
157 c0 = c;
158 do_div(c0, (1 << fpc->clk_ps));
159 if (c0 <= 0xFFFF)
160 return (unsigned long)c0;
161 } while (++fpc->clk_ps < 8);
162
163 return 0;
164}
165
166static unsigned long fsl_pwm_calculate_period_cycles(struct fsl_pwm_chip *fpc,
167 unsigned long period_ns,
168 enum fsl_pwm_clk index)
169{
170 int ret;
171
172 ret = fsl_pwm_calculate_default_ps(fpc, index);
173 if (ret) {
174 dev_err(fpc->chip.dev,
175 "failed to calculate default prescaler: %d\n",
176 ret);
177 return 0;
178 }
179
180 return fsl_pwm_calculate_cycles(fpc, period_ns);
181}
182
183static unsigned long fsl_pwm_calculate_period(struct fsl_pwm_chip *fpc,
184 unsigned long period_ns)
185{
186 enum fsl_pwm_clk m0, m1;
187 unsigned long fix_rate, ext_rate, cycles;
188
189 cycles = fsl_pwm_calculate_period_cycles(fpc, period_ns,
190 FSL_PWM_CLK_SYS);
191 if (cycles) {
192 fpc->cnt_select = FSL_PWM_CLK_SYS;
193 return cycles;
194 }
195
196 fix_rate = clk_get_rate(fpc->clk[FSL_PWM_CLK_FIX]);
197 ext_rate = clk_get_rate(fpc->clk[FSL_PWM_CLK_EXT]);
198
199 if (fix_rate > ext_rate) {
200 m0 = FSL_PWM_CLK_FIX;
201 m1 = FSL_PWM_CLK_EXT;
202 } else {
203 m0 = FSL_PWM_CLK_EXT;
204 m1 = FSL_PWM_CLK_FIX;
205 }
206
207 cycles = fsl_pwm_calculate_period_cycles(fpc, period_ns, m0);
208 if (cycles) {
209 fpc->cnt_select = m0;
210 return cycles;
211 }
212
213 fpc->cnt_select = m1;
214
215 return fsl_pwm_calculate_period_cycles(fpc, period_ns, m1);
216}
217
218static unsigned long fsl_pwm_calculate_duty(struct fsl_pwm_chip *fpc,
219 unsigned long period_ns,
220 unsigned long duty_ns)
221{
Xiubo Li42fa98a2014-08-19 12:38:02 +0800222 unsigned long long duty;
223 u32 val;
Xiubo Lib5051832014-02-27 17:39:49 +0800224
Xiubo Li42fa98a2014-08-19 12:38:02 +0800225 regmap_read(fpc->regmap, FTM_MOD, &val);
226 duty = (unsigned long long)duty_ns * (val + 1);
Xiubo Lib5051832014-02-27 17:39:49 +0800227 do_div(duty, period_ns);
228
229 return (unsigned long)duty;
230}
231
232static int fsl_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
233 int duty_ns, int period_ns)
234{
235 struct fsl_pwm_chip *fpc = to_fsl_chip(chip);
Xiubo Li42fa98a2014-08-19 12:38:02 +0800236 u32 period, duty;
Xiubo Lib5051832014-02-27 17:39:49 +0800237
238 mutex_lock(&fpc->lock);
239
240 /*
241 * The Freescale FTM controller supports only a single period for
242 * all PWM channels, therefore incompatible changes need to be
243 * refused.
244 */
245 if (fpc->period_ns && fpc->period_ns != period_ns) {
246 dev_err(fpc->chip.dev,
247 "conflicting period requested for PWM %u\n",
248 pwm->hwpwm);
249 mutex_unlock(&fpc->lock);
250 return -EBUSY;
251 }
252
253 if (!fpc->period_ns && duty_ns) {
254 period = fsl_pwm_calculate_period(fpc, period_ns);
255 if (!period) {
256 dev_err(fpc->chip.dev, "failed to calculate period\n");
257 mutex_unlock(&fpc->lock);
258 return -EINVAL;
259 }
260
Xiubo Li42fa98a2014-08-19 12:38:02 +0800261 regmap_update_bits(fpc->regmap, FTM_SC, FTM_SC_PS_MASK,
262 fpc->clk_ps);
263 regmap_write(fpc->regmap, FTM_MOD, period - 1);
Xiubo Lib5051832014-02-27 17:39:49 +0800264
265 fpc->period_ns = period_ns;
266 }
267
268 mutex_unlock(&fpc->lock);
269
270 duty = fsl_pwm_calculate_duty(fpc, period_ns, duty_ns);
271
Xiubo Li42fa98a2014-08-19 12:38:02 +0800272 regmap_write(fpc->regmap, FTM_CSC(pwm->hwpwm),
273 FTM_CSC_MSB | FTM_CSC_ELSB);
274 regmap_write(fpc->regmap, FTM_CV(pwm->hwpwm), duty);
Xiubo Lib5051832014-02-27 17:39:49 +0800275
276 return 0;
277}
278
279static int fsl_pwm_set_polarity(struct pwm_chip *chip,
280 struct pwm_device *pwm,
281 enum pwm_polarity polarity)
282{
283 struct fsl_pwm_chip *fpc = to_fsl_chip(chip);
284 u32 val;
285
Xiubo Li42fa98a2014-08-19 12:38:02 +0800286 regmap_read(fpc->regmap, FTM_POL, &val);
Xiubo Lib5051832014-02-27 17:39:49 +0800287
288 if (polarity == PWM_POLARITY_INVERSED)
289 val |= BIT(pwm->hwpwm);
290 else
291 val &= ~BIT(pwm->hwpwm);
292
Xiubo Li42fa98a2014-08-19 12:38:02 +0800293 regmap_write(fpc->regmap, FTM_POL, val);
Xiubo Lib5051832014-02-27 17:39:49 +0800294
295 return 0;
296}
297
298static int fsl_counter_clock_enable(struct fsl_pwm_chip *fpc)
299{
Xiubo Lib5051832014-02-27 17:39:49 +0800300 int ret;
301
302 if (fpc->use_count != 0)
303 return 0;
304
305 /* select counter clock source */
Xiubo Li42fa98a2014-08-19 12:38:02 +0800306 regmap_update_bits(fpc->regmap, FTM_SC, FTM_SC_CLK_MASK,
307 FTM_SC_CLK(fpc->cnt_select));
Xiubo Lib5051832014-02-27 17:39:49 +0800308
309 ret = clk_prepare_enable(fpc->clk[fpc->cnt_select]);
310 if (ret)
311 return ret;
312
313 ret = clk_prepare_enable(fpc->clk[FSL_PWM_CLK_CNTEN]);
314 if (ret) {
315 clk_disable_unprepare(fpc->clk[fpc->cnt_select]);
316 return ret;
317 }
318
319 fpc->use_count++;
320
321 return 0;
322}
323
324static int fsl_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
325{
326 struct fsl_pwm_chip *fpc = to_fsl_chip(chip);
Xiubo Lib5051832014-02-27 17:39:49 +0800327 int ret;
328
329 mutex_lock(&fpc->lock);
Xiubo Li42fa98a2014-08-19 12:38:02 +0800330 regmap_update_bits(fpc->regmap, FTM_OUTMASK, BIT(pwm->hwpwm), 0);
Xiubo Lib5051832014-02-27 17:39:49 +0800331
332 ret = fsl_counter_clock_enable(fpc);
333 mutex_unlock(&fpc->lock);
334
335 return ret;
336}
337
338static void fsl_counter_clock_disable(struct fsl_pwm_chip *fpc)
339{
Xiubo Lib5051832014-02-27 17:39:49 +0800340 /*
341 * already disabled, do nothing
342 */
343 if (fpc->use_count == 0)
344 return;
345
346 /* there are still users, so can't disable yet */
347 if (--fpc->use_count > 0)
348 return;
349
350 /* no users left, disable PWM counter clock */
Xiubo Li42fa98a2014-08-19 12:38:02 +0800351 regmap_update_bits(fpc->regmap, FTM_SC, FTM_SC_CLK_MASK, 0);
Xiubo Lib5051832014-02-27 17:39:49 +0800352
353 clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_CNTEN]);
354 clk_disable_unprepare(fpc->clk[fpc->cnt_select]);
355}
356
357static void fsl_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
358{
359 struct fsl_pwm_chip *fpc = to_fsl_chip(chip);
360 u32 val;
361
362 mutex_lock(&fpc->lock);
Xiubo Li42fa98a2014-08-19 12:38:02 +0800363 regmap_update_bits(fpc->regmap, FTM_OUTMASK, BIT(pwm->hwpwm),
364 BIT(pwm->hwpwm));
Xiubo Lib5051832014-02-27 17:39:49 +0800365
366 fsl_counter_clock_disable(fpc);
367
Xiubo Li42fa98a2014-08-19 12:38:02 +0800368 regmap_read(fpc->regmap, FTM_OUTMASK, &val);
Xiubo Lib5051832014-02-27 17:39:49 +0800369 if ((val & 0xFF) == 0xFF)
370 fpc->period_ns = 0;
371
372 mutex_unlock(&fpc->lock);
373}
374
375static const struct pwm_ops fsl_pwm_ops = {
376 .request = fsl_pwm_request,
377 .free = fsl_pwm_free,
378 .config = fsl_pwm_config,
379 .set_polarity = fsl_pwm_set_polarity,
380 .enable = fsl_pwm_enable,
381 .disable = fsl_pwm_disable,
382 .owner = THIS_MODULE,
383};
384
385static int fsl_pwm_init(struct fsl_pwm_chip *fpc)
386{
387 int ret;
388
389 ret = clk_prepare_enable(fpc->clk[FSL_PWM_CLK_SYS]);
390 if (ret)
391 return ret;
392
Xiubo Li42fa98a2014-08-19 12:38:02 +0800393 regmap_write(fpc->regmap, FTM_CNTIN, 0x00);
394 regmap_write(fpc->regmap, FTM_OUTINIT, 0x00);
395 regmap_write(fpc->regmap, FTM_OUTMASK, 0xFF);
Xiubo Lib5051832014-02-27 17:39:49 +0800396
397 clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_SYS]);
398
399 return 0;
400}
401
Xiubo Li42fa98a2014-08-19 12:38:02 +0800402static const struct regmap_config fsl_pwm_regmap_config = {
403 .reg_bits = 32,
404 .reg_stride = 4,
405 .val_bits = 32,
406
407 .max_register = FTM_PWMLOAD,
408};
409
Xiubo Lib5051832014-02-27 17:39:49 +0800410static int fsl_pwm_probe(struct platform_device *pdev)
411{
412 struct fsl_pwm_chip *fpc;
413 struct resource *res;
Xiubo Li42fa98a2014-08-19 12:38:02 +0800414 void __iomem *base;
Xiubo Lib5051832014-02-27 17:39:49 +0800415 int ret;
416
417 fpc = devm_kzalloc(&pdev->dev, sizeof(*fpc), GFP_KERNEL);
418 if (!fpc)
419 return -ENOMEM;
420
421 mutex_init(&fpc->lock);
422
423 fpc->chip.dev = &pdev->dev;
424
425 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
Xiubo Li42fa98a2014-08-19 12:38:02 +0800426 base = devm_ioremap_resource(&pdev->dev, res);
427 if (IS_ERR(base))
428 return PTR_ERR(base);
429
430 fpc->regmap = devm_regmap_init_mmio_clk(&pdev->dev, NULL, base,
431 &fsl_pwm_regmap_config);
432 if (IS_ERR(fpc->regmap)) {
433 dev_err(&pdev->dev, "regmap init failed\n");
434 return PTR_ERR(fpc->regmap);
435 }
Xiubo Lib5051832014-02-27 17:39:49 +0800436
437 fpc->clk[FSL_PWM_CLK_SYS] = devm_clk_get(&pdev->dev, "ftm_sys");
438 if (IS_ERR(fpc->clk[FSL_PWM_CLK_SYS])) {
439 dev_err(&pdev->dev, "failed to get \"ftm_sys\" clock\n");
440 return PTR_ERR(fpc->clk[FSL_PWM_CLK_SYS]);
441 }
442
443 fpc->clk[FSL_PWM_CLK_FIX] = devm_clk_get(fpc->chip.dev, "ftm_fix");
444 if (IS_ERR(fpc->clk[FSL_PWM_CLK_FIX]))
445 return PTR_ERR(fpc->clk[FSL_PWM_CLK_FIX]);
446
447 fpc->clk[FSL_PWM_CLK_EXT] = devm_clk_get(fpc->chip.dev, "ftm_ext");
448 if (IS_ERR(fpc->clk[FSL_PWM_CLK_EXT]))
449 return PTR_ERR(fpc->clk[FSL_PWM_CLK_EXT]);
450
451 fpc->clk[FSL_PWM_CLK_CNTEN] =
452 devm_clk_get(fpc->chip.dev, "ftm_cnt_clk_en");
453 if (IS_ERR(fpc->clk[FSL_PWM_CLK_CNTEN]))
454 return PTR_ERR(fpc->clk[FSL_PWM_CLK_CNTEN]);
455
456 fpc->chip.ops = &fsl_pwm_ops;
457 fpc->chip.of_xlate = of_pwm_xlate_with_flags;
458 fpc->chip.of_pwm_n_cells = 3;
459 fpc->chip.base = -1;
460 fpc->chip.npwm = 8;
Axel Lin39fd3f92014-05-22 08:05:20 +0800461 fpc->chip.can_sleep = true;
Xiubo Lib5051832014-02-27 17:39:49 +0800462
463 ret = pwmchip_add(&fpc->chip);
464 if (ret < 0) {
465 dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret);
466 return ret;
467 }
468
469 platform_set_drvdata(pdev, fpc);
470
471 return fsl_pwm_init(fpc);
472}
473
474static int fsl_pwm_remove(struct platform_device *pdev)
475{
476 struct fsl_pwm_chip *fpc = platform_get_drvdata(pdev);
477
478 return pwmchip_remove(&fpc->chip);
479}
480
481static const struct of_device_id fsl_pwm_dt_ids[] = {
482 { .compatible = "fsl,vf610-ftm-pwm", },
483 { /* sentinel */ }
484};
485MODULE_DEVICE_TABLE(of, fsl_pwm_dt_ids);
486
487static struct platform_driver fsl_pwm_driver = {
488 .driver = {
489 .name = "fsl-ftm-pwm",
490 .of_match_table = fsl_pwm_dt_ids,
491 },
492 .probe = fsl_pwm_probe,
493 .remove = fsl_pwm_remove,
494};
495module_platform_driver(fsl_pwm_driver);
496
497MODULE_DESCRIPTION("Freescale FlexTimer Module PWM Driver");
498MODULE_AUTHOR("Xiubo Li <Li.Xiubo@freescale.com>");
499MODULE_ALIAS("platform:fsl-ftm-pwm");
500MODULE_LICENSE("GPL");