Krzysztof Hałasa | 11c7974 | 2009-05-23 23:58:30 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Goramo MultiLink router platform code |
| 3 | * Copyright (C) 2006-2009 Krzysztof Halasa <khc@pm.waw.pl> |
| 4 | */ |
| 5 | |
| 6 | #include <linux/delay.h> |
| 7 | #include <linux/hdlc.h> |
| 8 | #include <linux/i2c-gpio.h> |
| 9 | #include <linux/io.h> |
| 10 | #include <linux/irq.h> |
| 11 | #include <linux/kernel.h> |
| 12 | #include <linux/pci.h> |
| 13 | #include <linux/serial_8250.h> |
| 14 | #include <asm/mach-types.h> |
| 15 | #include <asm/system.h> |
| 16 | #include <asm/mach/arch.h> |
| 17 | #include <asm/mach/flash.h> |
| 18 | #include <asm/mach/pci.h> |
| 19 | |
Krzysztof Hałasa | 11c7974 | 2009-05-23 23:58:30 +0200 | [diff] [blame] | 20 | #define SLOT_ETHA 0x0B /* IDSEL = AD21 */ |
| 21 | #define SLOT_ETHB 0x0C /* IDSEL = AD20 */ |
| 22 | #define SLOT_MPCI 0x0D /* IDSEL = AD19 */ |
| 23 | #define SLOT_NEC 0x0E /* IDSEL = AD18 */ |
| 24 | |
Krzysztof Hałasa | 11c7974 | 2009-05-23 23:58:30 +0200 | [diff] [blame] | 25 | /* GPIO lines */ |
| 26 | #define GPIO_SCL 0 |
| 27 | #define GPIO_SDA 1 |
| 28 | #define GPIO_STR 2 |
Krzysztof Hałasa | 8d3fdf3 | 2009-11-17 18:48:23 +0100 | [diff] [blame] | 29 | #define GPIO_IRQ_NEC 3 |
| 30 | #define GPIO_IRQ_ETHA 4 |
| 31 | #define GPIO_IRQ_ETHB 5 |
Krzysztof Hałasa | 11c7974 | 2009-05-23 23:58:30 +0200 | [diff] [blame] | 32 | #define GPIO_HSS0_DCD_N 6 |
| 33 | #define GPIO_HSS1_DCD_N 7 |
Krzysztof Hałasa | 8d3fdf3 | 2009-11-17 18:48:23 +0100 | [diff] [blame] | 34 | #define GPIO_UART0_DCD 8 |
| 35 | #define GPIO_UART1_DCD 9 |
Krzysztof Hałasa | 11c7974 | 2009-05-23 23:58:30 +0200 | [diff] [blame] | 36 | #define GPIO_HSS0_CTS_N 10 |
| 37 | #define GPIO_HSS1_CTS_N 11 |
Krzysztof Hałasa | 8d3fdf3 | 2009-11-17 18:48:23 +0100 | [diff] [blame] | 38 | #define GPIO_IRQ_MPCI 12 |
Krzysztof Hałasa | 11c7974 | 2009-05-23 23:58:30 +0200 | [diff] [blame] | 39 | #define GPIO_HSS1_RTS_N 13 |
| 40 | #define GPIO_HSS0_RTS_N 14 |
Krzysztof Hałasa | 8d3fdf3 | 2009-11-17 18:48:23 +0100 | [diff] [blame] | 41 | /* GPIO15 is not connected */ |
Krzysztof Hałasa | 11c7974 | 2009-05-23 23:58:30 +0200 | [diff] [blame] | 42 | |
| 43 | /* Control outputs from 74HC4094 */ |
| 44 | #define CONTROL_HSS0_CLK_INT 0 |
| 45 | #define CONTROL_HSS1_CLK_INT 1 |
| 46 | #define CONTROL_HSS0_DTR_N 2 |
| 47 | #define CONTROL_HSS1_DTR_N 3 |
| 48 | #define CONTROL_EXT 4 |
| 49 | #define CONTROL_AUTO_RESET 5 |
| 50 | #define CONTROL_PCI_RESET_N 6 |
| 51 | #define CONTROL_EEPROM_WC_N 7 |
| 52 | |
| 53 | /* offsets from start of flash ROM = 0x50000000 */ |
| 54 | #define CFG_ETH0_ADDRESS 0x40 /* 6 bytes */ |
| 55 | #define CFG_ETH1_ADDRESS 0x46 /* 6 bytes */ |
| 56 | #define CFG_REV 0x4C /* u32 */ |
| 57 | #define CFG_SDRAM_SIZE 0x50 /* u32 */ |
| 58 | #define CFG_SDRAM_CONF 0x54 /* u32 */ |
| 59 | #define CFG_SDRAM_MODE 0x58 /* u32 */ |
| 60 | #define CFG_SDRAM_REFRESH 0x5C /* u32 */ |
| 61 | |
| 62 | #define CFG_HW_BITS 0x60 /* u32 */ |
| 63 | #define CFG_HW_USB_PORTS 0x00000007 /* 0 = no NEC chip, 1-5 = ports # */ |
| 64 | #define CFG_HW_HAS_PCI_SLOT 0x00000008 |
| 65 | #define CFG_HW_HAS_ETH0 0x00000010 |
| 66 | #define CFG_HW_HAS_ETH1 0x00000020 |
| 67 | #define CFG_HW_HAS_HSS0 0x00000040 |
| 68 | #define CFG_HW_HAS_HSS1 0x00000080 |
| 69 | #define CFG_HW_HAS_UART0 0x00000100 |
| 70 | #define CFG_HW_HAS_UART1 0x00000200 |
| 71 | #define CFG_HW_HAS_EEPROM 0x00000400 |
| 72 | |
| 73 | #define FLASH_CMD_READ_ARRAY 0xFF |
| 74 | #define FLASH_CMD_READ_ID 0x90 |
| 75 | #define FLASH_SER_OFF 0x102 /* 0x81 in 16-bit mode */ |
| 76 | |
| 77 | static u32 hw_bits = 0xFFFFFFFD; /* assume all hardware present */; |
| 78 | static u8 control_value; |
| 79 | |
| 80 | static void set_scl(u8 value) |
| 81 | { |
| 82 | gpio_line_set(GPIO_SCL, !!value); |
| 83 | udelay(3); |
| 84 | } |
| 85 | |
| 86 | static void set_sda(u8 value) |
| 87 | { |
| 88 | gpio_line_set(GPIO_SDA, !!value); |
| 89 | udelay(3); |
| 90 | } |
| 91 | |
| 92 | static void set_str(u8 value) |
| 93 | { |
| 94 | gpio_line_set(GPIO_STR, !!value); |
| 95 | udelay(3); |
| 96 | } |
| 97 | |
| 98 | static inline void set_control(int line, int value) |
| 99 | { |
| 100 | if (value) |
| 101 | control_value |= (1 << line); |
| 102 | else |
| 103 | control_value &= ~(1 << line); |
| 104 | } |
| 105 | |
| 106 | |
| 107 | static void output_control(void) |
| 108 | { |
| 109 | int i; |
| 110 | |
| 111 | gpio_line_config(GPIO_SCL, IXP4XX_GPIO_OUT); |
| 112 | gpio_line_config(GPIO_SDA, IXP4XX_GPIO_OUT); |
| 113 | |
| 114 | for (i = 0; i < 8; i++) { |
| 115 | set_scl(0); |
| 116 | set_sda(control_value & (0x80 >> i)); /* MSB first */ |
| 117 | set_scl(1); /* active edge */ |
| 118 | } |
| 119 | |
| 120 | set_str(1); |
| 121 | set_str(0); |
| 122 | |
| 123 | set_scl(0); |
| 124 | set_sda(1); /* Be ready for START */ |
| 125 | set_scl(1); |
| 126 | } |
| 127 | |
| 128 | |
| 129 | static void (*set_carrier_cb_tab[2])(void *pdev, int carrier); |
| 130 | |
| 131 | static int hss_set_clock(int port, unsigned int clock_type) |
| 132 | { |
| 133 | int ctrl_int = port ? CONTROL_HSS1_CLK_INT : CONTROL_HSS0_CLK_INT; |
| 134 | |
| 135 | switch (clock_type) { |
| 136 | case CLOCK_DEFAULT: |
| 137 | case CLOCK_EXT: |
| 138 | set_control(ctrl_int, 0); |
| 139 | output_control(); |
| 140 | return CLOCK_EXT; |
| 141 | |
| 142 | case CLOCK_INT: |
| 143 | set_control(ctrl_int, 1); |
| 144 | output_control(); |
| 145 | return CLOCK_INT; |
| 146 | |
| 147 | default: |
| 148 | return -EINVAL; |
| 149 | } |
| 150 | } |
| 151 | |
| 152 | static irqreturn_t hss_dcd_irq(int irq, void *pdev) |
| 153 | { |
Krzysztof Hałasa | 8d3fdf3 | 2009-11-17 18:48:23 +0100 | [diff] [blame] | 154 | int i, port = (irq == IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N)); |
Krzysztof Hałasa | 11c7974 | 2009-05-23 23:58:30 +0200 | [diff] [blame] | 155 | gpio_line_get(port ? GPIO_HSS1_DCD_N : GPIO_HSS0_DCD_N, &i); |
| 156 | set_carrier_cb_tab[port](pdev, !i); |
| 157 | return IRQ_HANDLED; |
| 158 | } |
| 159 | |
| 160 | |
| 161 | static int hss_open(int port, void *pdev, |
| 162 | void (*set_carrier_cb)(void *pdev, int carrier)) |
| 163 | { |
| 164 | int i, irq; |
| 165 | |
| 166 | if (!port) |
Krzysztof Hałasa | 8d3fdf3 | 2009-11-17 18:48:23 +0100 | [diff] [blame] | 167 | irq = IXP4XX_GPIO_IRQ(GPIO_HSS0_DCD_N); |
Krzysztof Hałasa | 11c7974 | 2009-05-23 23:58:30 +0200 | [diff] [blame] | 168 | else |
Krzysztof Hałasa | 8d3fdf3 | 2009-11-17 18:48:23 +0100 | [diff] [blame] | 169 | irq = IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N); |
Krzysztof Hałasa | 11c7974 | 2009-05-23 23:58:30 +0200 | [diff] [blame] | 170 | |
| 171 | gpio_line_get(port ? GPIO_HSS1_DCD_N : GPIO_HSS0_DCD_N, &i); |
| 172 | set_carrier_cb(pdev, !i); |
| 173 | |
| 174 | set_carrier_cb_tab[!!port] = set_carrier_cb; |
| 175 | |
| 176 | if ((i = request_irq(irq, hss_dcd_irq, 0, "IXP4xx HSS", pdev)) != 0) { |
| 177 | printk(KERN_ERR "ixp4xx_hss: failed to request IRQ%i (%i)\n", |
| 178 | irq, i); |
| 179 | return i; |
| 180 | } |
| 181 | |
| 182 | set_control(port ? CONTROL_HSS1_DTR_N : CONTROL_HSS0_DTR_N, 0); |
| 183 | output_control(); |
| 184 | gpio_line_set(port ? GPIO_HSS1_RTS_N : GPIO_HSS0_RTS_N, 0); |
| 185 | return 0; |
| 186 | } |
| 187 | |
| 188 | static void hss_close(int port, void *pdev) |
| 189 | { |
Krzysztof Hałasa | 8d3fdf3 | 2009-11-17 18:48:23 +0100 | [diff] [blame] | 190 | free_irq(port ? IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N) : |
| 191 | IXP4XX_GPIO_IRQ(GPIO_HSS0_DCD_N), pdev); |
Krzysztof Hałasa | 11c7974 | 2009-05-23 23:58:30 +0200 | [diff] [blame] | 192 | set_carrier_cb_tab[!!port] = NULL; /* catch bugs */ |
| 193 | |
| 194 | set_control(port ? CONTROL_HSS1_DTR_N : CONTROL_HSS0_DTR_N, 1); |
| 195 | output_control(); |
| 196 | gpio_line_set(port ? GPIO_HSS1_RTS_N : GPIO_HSS0_RTS_N, 1); |
| 197 | } |
| 198 | |
| 199 | |
| 200 | /* Flash memory */ |
| 201 | static struct flash_platform_data flash_data = { |
| 202 | .map_name = "cfi_probe", |
| 203 | .width = 2, |
| 204 | }; |
| 205 | |
| 206 | static struct resource flash_resource = { |
| 207 | .flags = IORESOURCE_MEM, |
| 208 | }; |
| 209 | |
| 210 | static struct platform_device device_flash = { |
| 211 | .name = "IXP4XX-Flash", |
| 212 | .id = 0, |
| 213 | .dev = { .platform_data = &flash_data }, |
| 214 | .num_resources = 1, |
| 215 | .resource = &flash_resource, |
| 216 | }; |
| 217 | |
| 218 | |
| 219 | /* I^2C interface */ |
| 220 | static struct i2c_gpio_platform_data i2c_data = { |
| 221 | .sda_pin = GPIO_SDA, |
| 222 | .scl_pin = GPIO_SCL, |
| 223 | }; |
| 224 | |
| 225 | static struct platform_device device_i2c = { |
| 226 | .name = "i2c-gpio", |
| 227 | .id = 0, |
| 228 | .dev = { .platform_data = &i2c_data }, |
| 229 | }; |
| 230 | |
| 231 | |
| 232 | /* IXP425 2 UART ports */ |
| 233 | static struct resource uart_resources[] = { |
| 234 | { |
| 235 | .start = IXP4XX_UART1_BASE_PHYS, |
| 236 | .end = IXP4XX_UART1_BASE_PHYS + 0x0fff, |
| 237 | .flags = IORESOURCE_MEM, |
| 238 | }, |
| 239 | { |
| 240 | .start = IXP4XX_UART2_BASE_PHYS, |
| 241 | .end = IXP4XX_UART2_BASE_PHYS + 0x0fff, |
| 242 | .flags = IORESOURCE_MEM, |
| 243 | } |
| 244 | }; |
| 245 | |
| 246 | static struct plat_serial8250_port uart_data[] = { |
| 247 | { |
| 248 | .mapbase = IXP4XX_UART1_BASE_PHYS, |
| 249 | .membase = (char __iomem *)IXP4XX_UART1_BASE_VIRT + |
| 250 | REG_OFFSET, |
| 251 | .irq = IRQ_IXP4XX_UART1, |
| 252 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, |
| 253 | .iotype = UPIO_MEM, |
| 254 | .regshift = 2, |
| 255 | .uartclk = IXP4XX_UART_XTAL, |
| 256 | }, |
| 257 | { |
| 258 | .mapbase = IXP4XX_UART2_BASE_PHYS, |
| 259 | .membase = (char __iomem *)IXP4XX_UART2_BASE_VIRT + |
| 260 | REG_OFFSET, |
| 261 | .irq = IRQ_IXP4XX_UART2, |
| 262 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, |
| 263 | .iotype = UPIO_MEM, |
| 264 | .regshift = 2, |
| 265 | .uartclk = IXP4XX_UART_XTAL, |
| 266 | }, |
| 267 | { }, |
| 268 | }; |
| 269 | |
| 270 | static struct platform_device device_uarts = { |
| 271 | .name = "serial8250", |
| 272 | .id = PLAT8250_DEV_PLATFORM, |
| 273 | .dev.platform_data = uart_data, |
| 274 | .num_resources = 2, |
| 275 | .resource = uart_resources, |
| 276 | }; |
| 277 | |
| 278 | |
| 279 | /* Built-in 10/100 Ethernet MAC interfaces */ |
| 280 | static struct eth_plat_info eth_plat[] = { |
| 281 | { |
| 282 | .phy = 0, |
| 283 | .rxq = 3, |
| 284 | .txreadyq = 32, |
| 285 | }, { |
| 286 | .phy = 1, |
| 287 | .rxq = 4, |
| 288 | .txreadyq = 33, |
| 289 | } |
| 290 | }; |
| 291 | |
| 292 | static struct platform_device device_eth_tab[] = { |
| 293 | { |
| 294 | .name = "ixp4xx_eth", |
| 295 | .id = IXP4XX_ETH_NPEB, |
| 296 | .dev.platform_data = eth_plat, |
| 297 | }, { |
| 298 | .name = "ixp4xx_eth", |
| 299 | .id = IXP4XX_ETH_NPEC, |
| 300 | .dev.platform_data = eth_plat + 1, |
| 301 | } |
| 302 | }; |
| 303 | |
| 304 | |
| 305 | /* IXP425 2 synchronous serial ports */ |
| 306 | static struct hss_plat_info hss_plat[] = { |
| 307 | { |
| 308 | .set_clock = hss_set_clock, |
| 309 | .open = hss_open, |
| 310 | .close = hss_close, |
| 311 | .txreadyq = 34, |
| 312 | }, { |
| 313 | .set_clock = hss_set_clock, |
| 314 | .open = hss_open, |
| 315 | .close = hss_close, |
| 316 | .txreadyq = 35, |
| 317 | } |
| 318 | }; |
| 319 | |
| 320 | static struct platform_device device_hss_tab[] = { |
| 321 | { |
| 322 | .name = "ixp4xx_hss", |
| 323 | .id = 0, |
| 324 | .dev.platform_data = hss_plat, |
| 325 | }, { |
| 326 | .name = "ixp4xx_hss", |
| 327 | .id = 1, |
| 328 | .dev.platform_data = hss_plat + 1, |
| 329 | } |
| 330 | }; |
| 331 | |
| 332 | |
| 333 | static struct platform_device *device_tab[6] __initdata = { |
| 334 | &device_flash, /* index 0 */ |
| 335 | }; |
| 336 | |
| 337 | static inline u8 __init flash_readb(u8 __iomem *flash, u32 addr) |
| 338 | { |
| 339 | #ifdef __ARMEB__ |
| 340 | return __raw_readb(flash + addr); |
| 341 | #else |
| 342 | return __raw_readb(flash + (addr ^ 3)); |
| 343 | #endif |
| 344 | } |
| 345 | |
| 346 | static inline u16 __init flash_readw(u8 __iomem *flash, u32 addr) |
| 347 | { |
| 348 | #ifdef __ARMEB__ |
| 349 | return __raw_readw(flash + addr); |
| 350 | #else |
| 351 | return __raw_readw(flash + (addr ^ 2)); |
| 352 | #endif |
| 353 | } |
| 354 | |
| 355 | static void __init gmlr_init(void) |
| 356 | { |
| 357 | u8 __iomem *flash; |
| 358 | int i, devices = 1; /* flash */ |
| 359 | |
| 360 | ixp4xx_sys_init(); |
| 361 | |
| 362 | if ((flash = ioremap(IXP4XX_EXP_BUS_BASE_PHYS, 0x80)) == NULL) |
| 363 | printk(KERN_ERR "goramo-mlr: unable to access system" |
| 364 | " configuration data\n"); |
| 365 | else { |
| 366 | system_rev = __raw_readl(flash + CFG_REV); |
| 367 | hw_bits = __raw_readl(flash + CFG_HW_BITS); |
| 368 | |
| 369 | for (i = 0; i < ETH_ALEN; i++) { |
| 370 | eth_plat[0].hwaddr[i] = |
| 371 | flash_readb(flash, CFG_ETH0_ADDRESS + i); |
| 372 | eth_plat[1].hwaddr[i] = |
| 373 | flash_readb(flash, CFG_ETH1_ADDRESS + i); |
| 374 | } |
| 375 | |
| 376 | __raw_writew(FLASH_CMD_READ_ID, flash); |
| 377 | system_serial_high = flash_readw(flash, FLASH_SER_OFF); |
| 378 | system_serial_high <<= 16; |
| 379 | system_serial_high |= flash_readw(flash, FLASH_SER_OFF + 2); |
| 380 | system_serial_low = flash_readw(flash, FLASH_SER_OFF + 4); |
| 381 | system_serial_low <<= 16; |
| 382 | system_serial_low |= flash_readw(flash, FLASH_SER_OFF + 6); |
| 383 | __raw_writew(FLASH_CMD_READ_ARRAY, flash); |
| 384 | |
| 385 | iounmap(flash); |
| 386 | } |
| 387 | |
| 388 | switch (hw_bits & (CFG_HW_HAS_UART0 | CFG_HW_HAS_UART1)) { |
| 389 | case CFG_HW_HAS_UART0: |
| 390 | memset(&uart_data[1], 0, sizeof(uart_data[1])); |
| 391 | device_uarts.num_resources = 1; |
| 392 | break; |
| 393 | |
| 394 | case CFG_HW_HAS_UART1: |
| 395 | device_uarts.dev.platform_data = &uart_data[1]; |
| 396 | device_uarts.resource = &uart_resources[1]; |
| 397 | device_uarts.num_resources = 1; |
| 398 | break; |
| 399 | } |
| 400 | if (hw_bits & (CFG_HW_HAS_UART0 | CFG_HW_HAS_UART1)) |
| 401 | device_tab[devices++] = &device_uarts; /* max index 1 */ |
| 402 | |
| 403 | if (hw_bits & CFG_HW_HAS_ETH0) |
| 404 | device_tab[devices++] = &device_eth_tab[0]; /* max index 2 */ |
| 405 | if (hw_bits & CFG_HW_HAS_ETH1) |
| 406 | device_tab[devices++] = &device_eth_tab[1]; /* max index 3 */ |
| 407 | |
| 408 | if (hw_bits & CFG_HW_HAS_HSS0) |
| 409 | device_tab[devices++] = &device_hss_tab[0]; /* max index 4 */ |
| 410 | if (hw_bits & CFG_HW_HAS_HSS1) |
| 411 | device_tab[devices++] = &device_hss_tab[1]; /* max index 5 */ |
| 412 | |
| 413 | if (hw_bits & CFG_HW_HAS_EEPROM) |
| 414 | device_tab[devices++] = &device_i2c; /* max index 6 */ |
| 415 | |
| 416 | gpio_line_config(GPIO_SCL, IXP4XX_GPIO_OUT); |
| 417 | gpio_line_config(GPIO_SDA, IXP4XX_GPIO_OUT); |
| 418 | gpio_line_config(GPIO_STR, IXP4XX_GPIO_OUT); |
| 419 | gpio_line_config(GPIO_HSS0_RTS_N, IXP4XX_GPIO_OUT); |
| 420 | gpio_line_config(GPIO_HSS1_RTS_N, IXP4XX_GPIO_OUT); |
| 421 | gpio_line_config(GPIO_HSS0_DCD_N, IXP4XX_GPIO_IN); |
| 422 | gpio_line_config(GPIO_HSS1_DCD_N, IXP4XX_GPIO_IN); |
Thomas Gleixner | 6845664a | 2011-03-24 13:25:22 +0100 | [diff] [blame] | 423 | irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_HSS0_DCD_N), IRQ_TYPE_EDGE_BOTH); |
| 424 | irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N), IRQ_TYPE_EDGE_BOTH); |
Krzysztof Hałasa | 11c7974 | 2009-05-23 23:58:30 +0200 | [diff] [blame] | 425 | |
| 426 | set_control(CONTROL_HSS0_DTR_N, 1); |
| 427 | set_control(CONTROL_HSS1_DTR_N, 1); |
| 428 | set_control(CONTROL_EEPROM_WC_N, 1); |
| 429 | set_control(CONTROL_PCI_RESET_N, 1); |
| 430 | output_control(); |
| 431 | |
| 432 | msleep(1); /* Wait for PCI devices to initialize */ |
| 433 | |
| 434 | flash_resource.start = IXP4XX_EXP_BUS_BASE(0); |
| 435 | flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + ixp4xx_exp_bus_size - 1; |
| 436 | |
| 437 | platform_add_devices(device_tab, devices); |
| 438 | } |
| 439 | |
| 440 | |
| 441 | #ifdef CONFIG_PCI |
| 442 | static void __init gmlr_pci_preinit(void) |
| 443 | { |
Thomas Gleixner | 6845664a | 2011-03-24 13:25:22 +0100 | [diff] [blame] | 444 | irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHA), IRQ_TYPE_LEVEL_LOW); |
| 445 | irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHB), IRQ_TYPE_LEVEL_LOW); |
| 446 | irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_NEC), IRQ_TYPE_LEVEL_LOW); |
| 447 | irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_MPCI), IRQ_TYPE_LEVEL_LOW); |
Krzysztof Hałasa | 11c7974 | 2009-05-23 23:58:30 +0200 | [diff] [blame] | 448 | ixp4xx_pci_preinit(); |
| 449 | } |
| 450 | |
| 451 | static void __init gmlr_pci_postinit(void) |
| 452 | { |
| 453 | if ((hw_bits & CFG_HW_USB_PORTS) >= 2 && |
| 454 | (hw_bits & CFG_HW_USB_PORTS) < 5) { |
| 455 | /* need to adjust number of USB ports on NEC chip */ |
| 456 | u32 value, addr = BIT(32 - SLOT_NEC) | 0xE0; |
| 457 | if (!ixp4xx_pci_read(addr, NP_CMD_CONFIGREAD, &value)) { |
| 458 | value &= ~7; |
| 459 | value |= (hw_bits & CFG_HW_USB_PORTS); |
| 460 | ixp4xx_pci_write(addr, NP_CMD_CONFIGWRITE, value); |
| 461 | } |
| 462 | } |
| 463 | } |
| 464 | |
Ralf Baechle | d534194 | 2011-06-10 15:30:21 +0100 | [diff] [blame] | 465 | static int __init gmlr_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) |
Krzysztof Hałasa | 11c7974 | 2009-05-23 23:58:30 +0200 | [diff] [blame] | 466 | { |
| 467 | switch(slot) { |
Krzysztof Hałasa | 8d3fdf3 | 2009-11-17 18:48:23 +0100 | [diff] [blame] | 468 | case SLOT_ETHA: return IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHA); |
| 469 | case SLOT_ETHB: return IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHB); |
| 470 | case SLOT_NEC: return IXP4XX_GPIO_IRQ(GPIO_IRQ_NEC); |
| 471 | default: return IXP4XX_GPIO_IRQ(GPIO_IRQ_MPCI); |
Krzysztof Hałasa | 11c7974 | 2009-05-23 23:58:30 +0200 | [diff] [blame] | 472 | } |
| 473 | } |
| 474 | |
| 475 | static struct hw_pci gmlr_hw_pci __initdata = { |
| 476 | .nr_controllers = 1, |
| 477 | .preinit = gmlr_pci_preinit, |
| 478 | .postinit = gmlr_pci_postinit, |
| 479 | .swizzle = pci_std_swizzle, |
| 480 | .setup = ixp4xx_setup, |
| 481 | .scan = ixp4xx_scan_bus, |
| 482 | .map_irq = gmlr_map_irq, |
| 483 | }; |
| 484 | |
| 485 | static int __init gmlr_pci_init(void) |
| 486 | { |
| 487 | if (machine_is_goramo_mlr() && |
| 488 | (hw_bits & (CFG_HW_USB_PORTS | CFG_HW_HAS_PCI_SLOT))) |
| 489 | pci_common_init(&gmlr_hw_pci); |
| 490 | return 0; |
| 491 | } |
| 492 | |
| 493 | subsys_initcall(gmlr_pci_init); |
| 494 | #endif /* CONFIG_PCI */ |
| 495 | |
| 496 | |
| 497 | MACHINE_START(GORAMO_MLR, "MultiLink") |
| 498 | /* Maintainer: Krzysztof Halasa */ |
Krzysztof Hałasa | 11c7974 | 2009-05-23 23:58:30 +0200 | [diff] [blame] | 499 | .map_io = ixp4xx_map_io, |
| 500 | .init_irq = ixp4xx_init_irq, |
| 501 | .timer = &ixp4xx_timer, |
Nicolas Pitre | e022c72 | 2011-07-05 22:38:13 -0400 | [diff] [blame] | 502 | .atag_offset = 0x100, |
Krzysztof Hałasa | 11c7974 | 2009-05-23 23:58:30 +0200 | [diff] [blame] | 503 | .init_machine = gmlr_init, |
Nicolas Pitre | 7553ee7 | 2011-07-05 22:28:09 -0400 | [diff] [blame] | 504 | #if defined(CONFIG_PCI) |
| 505 | .dma_zone_size = SZ_64M, |
| 506 | #endif |
Russell King | d1b860f | 2011-11-05 12:10:55 +0000 | [diff] [blame] | 507 | .restart = ixp4xx_restart, |
Krzysztof Hałasa | 11c7974 | 2009-05-23 23:58:30 +0200 | [diff] [blame] | 508 | MACHINE_END |