Ben Dooks | a21765a | 2007-02-11 18:31:01 +0100 | [diff] [blame] | 1 | /* linux/arch/arm/mach-s3c2440/clock.c |
Ben Dooks | a8d11e3 | 2005-07-26 22:39:14 +0100 | [diff] [blame] | 2 | * |
| 3 | * Copyright (c) 2004-2005 Simtec Electronics |
| 4 | * http://armlinux.simtec.co.uk/ |
| 5 | * Ben Dooks <ben@simtec.co.uk> |
| 6 | * |
| 7 | * S3C2440 Clock support |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License as published by |
| 11 | * the Free Software Foundation; either version 2 of the License, or |
| 12 | * (at your option) any later version. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 22 | */ |
| 23 | |
| 24 | #include <linux/init.h> |
| 25 | #include <linux/module.h> |
| 26 | #include <linux/kernel.h> |
| 27 | #include <linux/list.h> |
| 28 | #include <linux/errno.h> |
| 29 | #include <linux/err.h> |
| 30 | #include <linux/device.h> |
Ben Dooks | a8d11e3 | 2005-07-26 22:39:14 +0100 | [diff] [blame] | 31 | #include <linux/interrupt.h> |
| 32 | #include <linux/ioport.h> |
Ben Dooks | 36c64af | 2006-03-20 21:00:48 +0000 | [diff] [blame] | 33 | #include <linux/mutex.h> |
Russell King | f8ce254 | 2006-01-07 16:15:52 +0000 | [diff] [blame] | 34 | #include <linux/clk.h> |
Russell King | fced80c | 2008-09-06 12:10:45 +0100 | [diff] [blame] | 35 | #include <linux/io.h> |
Thomas Abraham | 046c217 | 2011-10-24 11:47:40 +0200 | [diff] [blame] | 36 | #include <linux/serial_core.h> |
Ben Dooks | a8d11e3 | 2005-07-26 22:39:14 +0100 | [diff] [blame] | 37 | |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 38 | #include <mach/hardware.h> |
Arun Sharma | 60063497 | 2011-07-26 16:09:06 -0700 | [diff] [blame] | 39 | #include <linux/atomic.h> |
Ben Dooks | a8d11e3 | 2005-07-26 22:39:14 +0100 | [diff] [blame] | 40 | #include <asm/irq.h> |
Ben Dooks | a8d11e3 | 2005-07-26 22:39:14 +0100 | [diff] [blame] | 41 | |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 42 | #include <mach/regs-clock.h> |
Ben Dooks | a8d11e3 | 2005-07-26 22:39:14 +0100 | [diff] [blame] | 43 | |
Ben Dooks | d5120ae | 2008-10-07 23:09:51 +0100 | [diff] [blame] | 44 | #include <plat/clock.h> |
Ben Dooks | a2b7ba9 | 2008-10-07 22:26:09 +0100 | [diff] [blame] | 45 | #include <plat/cpu.h> |
Thomas Abraham | 046c217 | 2011-10-24 11:47:40 +0200 | [diff] [blame] | 46 | #include <plat/regs-serial.h> |
Ben Dooks | a8d11e3 | 2005-07-26 22:39:14 +0100 | [diff] [blame] | 47 | |
| 48 | /* S3C2440 extended clock support */ |
| 49 | |
Ben Dooks | e44c039 | 2006-03-20 21:00:12 +0000 | [diff] [blame] | 50 | static unsigned long s3c2440_camif_upll_round(struct clk *clk, |
| 51 | unsigned long rate) |
| 52 | { |
| 53 | unsigned long parent_rate = clk_get_rate(clk->parent); |
| 54 | int div; |
| 55 | |
| 56 | if (rate > parent_rate) |
| 57 | return parent_rate; |
| 58 | |
| 59 | /* note, we remove the +/- 1 calculations for the divisor */ |
| 60 | |
| 61 | div = (parent_rate / rate) / 2; |
| 62 | |
| 63 | if (div < 1) |
| 64 | div = 1; |
| 65 | else if (div > 16) |
| 66 | div = 16; |
| 67 | |
| 68 | return parent_rate / (div * 2); |
| 69 | } |
| 70 | |
| 71 | static int s3c2440_camif_upll_setrate(struct clk *clk, unsigned long rate) |
| 72 | { |
| 73 | unsigned long parent_rate = clk_get_rate(clk->parent); |
| 74 | unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN); |
| 75 | |
| 76 | rate = s3c2440_camif_upll_round(clk, rate); |
| 77 | |
| 78 | camdivn &= ~(S3C2440_CAMDIVN_CAMCLK_SEL | S3C2440_CAMDIVN_CAMCLK_MASK); |
| 79 | |
| 80 | if (rate != parent_rate) { |
| 81 | camdivn |= S3C2440_CAMDIVN_CAMCLK_SEL; |
| 82 | camdivn |= (((parent_rate / rate) / 2) - 1); |
| 83 | } |
| 84 | |
| 85 | __raw_writel(camdivn, S3C2440_CAMDIVN); |
| 86 | |
| 87 | return 0; |
| 88 | } |
| 89 | |
| 90 | /* Extra S3C2440 clocks */ |
| 91 | |
Ben Dooks | a8d11e3 | 2005-07-26 22:39:14 +0100 | [diff] [blame] | 92 | static struct clk s3c2440_clk_cam = { |
| 93 | .name = "camif", |
Ben Dooks | 99c1385 | 2006-06-22 22:18:20 +0100 | [diff] [blame] | 94 | .enable = s3c2410_clkcon_enable, |
Ben Dooks | a8d11e3 | 2005-07-26 22:39:14 +0100 | [diff] [blame] | 95 | .ctrlbit = S3C2440_CLKCON_CAMERA, |
| 96 | }; |
| 97 | |
Ben Dooks | e44c039 | 2006-03-20 21:00:12 +0000 | [diff] [blame] | 98 | static struct clk s3c2440_clk_cam_upll = { |
| 99 | .name = "camif-upll", |
Ben Dooks | b3bf41b | 2009-12-01 01:24:37 +0000 | [diff] [blame] | 100 | .ops = &(struct clk_ops) { |
| 101 | .set_rate = s3c2440_camif_upll_setrate, |
| 102 | .round_rate = s3c2440_camif_upll_round, |
| 103 | }, |
Ben Dooks | e44c039 | 2006-03-20 21:00:12 +0000 | [diff] [blame] | 104 | }; |
| 105 | |
Ben Dooks | a8d11e3 | 2005-07-26 22:39:14 +0100 | [diff] [blame] | 106 | static struct clk s3c2440_clk_ac97 = { |
| 107 | .name = "ac97", |
Ben Dooks | 99c1385 | 2006-06-22 22:18:20 +0100 | [diff] [blame] | 108 | .enable = s3c2410_clkcon_enable, |
Ben Dooks | a8d11e3 | 2005-07-26 22:39:14 +0100 | [diff] [blame] | 109 | .ctrlbit = S3C2440_CLKCON_CAMERA, |
| 110 | }; |
| 111 | |
Thomas Abraham | 046c217 | 2011-10-24 11:47:40 +0200 | [diff] [blame] | 112 | static unsigned long s3c2440_fclk_n_getrate(struct clk *clk) |
| 113 | { |
| 114 | unsigned long ucon0, ucon1, ucon2, divisor; |
| 115 | |
| 116 | /* the fun of calculating the uart divisors on the s3c2440 */ |
| 117 | ucon0 = __raw_readl(S3C24XX_VA_UART0 + S3C2410_UCON); |
| 118 | ucon1 = __raw_readl(S3C24XX_VA_UART1 + S3C2410_UCON); |
| 119 | ucon2 = __raw_readl(S3C24XX_VA_UART2 + S3C2410_UCON); |
| 120 | |
| 121 | ucon0 &= S3C2440_UCON0_DIVMASK; |
| 122 | ucon1 &= S3C2440_UCON1_DIVMASK; |
| 123 | ucon2 &= S3C2440_UCON2_DIVMASK; |
| 124 | |
| 125 | if (ucon0 != 0) |
| 126 | divisor = (ucon0 >> S3C2440_UCON_DIVSHIFT) + 6; |
| 127 | else if (ucon1 != 0) |
| 128 | divisor = (ucon1 >> S3C2440_UCON_DIVSHIFT) + 21; |
| 129 | else if (ucon2 != 0) |
| 130 | divisor = (ucon2 >> S3C2440_UCON_DIVSHIFT) + 36; |
| 131 | else |
| 132 | /* manual calims 44, seems to be 9 */ |
| 133 | divisor = 9; |
| 134 | |
| 135 | return clk_get_rate(clk->parent) / divisor; |
| 136 | } |
| 137 | |
| 138 | static struct clk s3c2440_clk_fclk_n = { |
| 139 | .name = "fclk_n", |
| 140 | .parent = &clk_f, |
| 141 | .ops = &(struct clk_ops) { |
| 142 | .get_rate = s3c2440_fclk_n_getrate, |
| 143 | }, |
| 144 | }; |
| 145 | |
Thomas Abraham | 0cfb26e | 2011-10-24 12:08:42 +0200 | [diff] [blame] | 146 | static struct clk_lookup s3c2440_clk_lookup[] = { |
| 147 | CLKDEV_INIT(NULL, "clk_uart_baud1", &s3c24xx_uclk), |
| 148 | CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p), |
| 149 | CLKDEV_INIT(NULL, "clk_uart_baud3", &s3c2440_clk_fclk_n), |
| 150 | }; |
| 151 | |
Kay Sievers | 4a858cf | 2011-12-21 16:01:38 -0800 | [diff] [blame] | 152 | static int s3c2440_clk_add(struct device *dev) |
Ben Dooks | a8d11e3 | 2005-07-26 22:39:14 +0100 | [diff] [blame] | 153 | { |
Ben Dooks | 3a38e4b | 2008-01-28 13:01:34 +0100 | [diff] [blame] | 154 | struct clk *clock_upll; |
Ben Dooks | e546e8a | 2006-12-17 20:38:14 +0100 | [diff] [blame] | 155 | struct clk *clock_h; |
| 156 | struct clk *clock_p; |
Ben Dooks | a8d11e3 | 2005-07-26 22:39:14 +0100 | [diff] [blame] | 157 | |
Ben Dooks | e546e8a | 2006-12-17 20:38:14 +0100 | [diff] [blame] | 158 | clock_p = clk_get(NULL, "pclk"); |
| 159 | clock_h = clk_get(NULL, "hclk"); |
| 160 | clock_upll = clk_get(NULL, "upll"); |
Ben Dooks | a8d11e3 | 2005-07-26 22:39:14 +0100 | [diff] [blame] | 161 | |
Ben Dooks | e546e8a | 2006-12-17 20:38:14 +0100 | [diff] [blame] | 162 | if (IS_ERR(clock_p) || IS_ERR(clock_h) || IS_ERR(clock_upll)) { |
Ben Dooks | a8d11e3 | 2005-07-26 22:39:14 +0100 | [diff] [blame] | 163 | printk(KERN_ERR "S3C2440: Failed to get parent clocks\n"); |
| 164 | return -EINVAL; |
| 165 | } |
| 166 | |
Ben Dooks | e546e8a | 2006-12-17 20:38:14 +0100 | [diff] [blame] | 167 | s3c2440_clk_cam.parent = clock_h; |
| 168 | s3c2440_clk_ac97.parent = clock_p; |
| 169 | s3c2440_clk_cam_upll.parent = clock_upll; |
Thomas Abraham | 046c217 | 2011-10-24 11:47:40 +0200 | [diff] [blame] | 170 | s3c24xx_register_clock(&s3c2440_clk_fclk_n); |
Ben Dooks | a8d11e3 | 2005-07-26 22:39:14 +0100 | [diff] [blame] | 171 | |
| 172 | s3c24xx_register_clock(&s3c2440_clk_ac97); |
| 173 | s3c24xx_register_clock(&s3c2440_clk_cam); |
Ben Dooks | e44c039 | 2006-03-20 21:00:12 +0000 | [diff] [blame] | 174 | s3c24xx_register_clock(&s3c2440_clk_cam_upll); |
Thomas Abraham | 0cfb26e | 2011-10-24 12:08:42 +0200 | [diff] [blame] | 175 | clkdev_add_table(s3c2440_clk_lookup, ARRAY_SIZE(s3c2440_clk_lookup)); |
Ben Dooks | a8d11e3 | 2005-07-26 22:39:14 +0100 | [diff] [blame] | 176 | |
| 177 | clk_disable(&s3c2440_clk_ac97); |
| 178 | clk_disable(&s3c2440_clk_cam); |
| 179 | |
| 180 | return 0; |
| 181 | } |
| 182 | |
Kay Sievers | 4a858cf | 2011-12-21 16:01:38 -0800 | [diff] [blame] | 183 | static struct subsys_interface s3c2440_clk_interface = { |
| 184 | .name = "s3c2440_clk", |
| 185 | .subsys = &s3c2440_subsys, |
| 186 | .add_dev = s3c2440_clk_add, |
Ben Dooks | a8d11e3 | 2005-07-26 22:39:14 +0100 | [diff] [blame] | 187 | }; |
| 188 | |
Kay Sievers | 4a858cf | 2011-12-21 16:01:38 -0800 | [diff] [blame] | 189 | static __init int s3c24xx_clk_init(void) |
Ben Dooks | a8d11e3 | 2005-07-26 22:39:14 +0100 | [diff] [blame] | 190 | { |
Kay Sievers | 4a858cf | 2011-12-21 16:01:38 -0800 | [diff] [blame] | 191 | return subsys_interface_register(&s3c2440_clk_interface); |
Ben Dooks | a8d11e3 | 2005-07-26 22:39:14 +0100 | [diff] [blame] | 192 | } |
| 193 | |
Kay Sievers | 4a858cf | 2011-12-21 16:01:38 -0800 | [diff] [blame] | 194 | arch_initcall(s3c24xx_clk_init); |