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Catalin Marinas4f04d8f2012-03-05 11:49:27 +00001/*
2 * Copyright (C) 2012 ARM Ltd.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16#ifndef __ASM_PGTABLE_H
17#define __ASM_PGTABLE_H
18
19#include <asm/proc-fns.h>
20
21#include <asm/memory.h>
22#include <asm/pgtable-hwdef.h>
23
24/*
25 * Software defined PTE bits definition.
26 */
Will Deacona6fadf72012-12-18 14:15:15 +000027#define PTE_VALID (_AT(pteval_t, 1) << 0)
Catalin Marinas3676f9e2013-11-27 16:59:27 +000028#define PTE_FILE (_AT(pteval_t, 1) << 2) /* only when !pte_present() */
Catalin Marinas4f04d8f2012-03-05 11:49:27 +000029#define PTE_DIRTY (_AT(pteval_t, 1) << 55)
30#define PTE_SPECIAL (_AT(pteval_t, 1) << 56)
Steve Capperc2c93e52014-01-15 14:07:13 +000031#define PTE_WRITE (_AT(pteval_t, 1) << 57)
Catalin Marinas3676f9e2013-11-27 16:59:27 +000032#define PTE_PROT_NONE (_AT(pteval_t, 1) << 58) /* only when !PTE_VALID */
Catalin Marinas4f04d8f2012-03-05 11:49:27 +000033
34/*
35 * VMALLOC and SPARSEMEM_VMEMMAP ranges.
Catalin Marinas08375192014-07-16 17:42:43 +010036 *
37 * VMEMAP_SIZE: allows the whole VA space to be covered by a struct page array
38 * (rounded up to PUD_SIZE).
39 * VMALLOC_START: beginning of the kernel VA space
40 * VMALLOC_END: extends to the available space below vmmemmap, PCI I/O space,
41 * fixed mappings and modules
Catalin Marinas4f04d8f2012-03-05 11:49:27 +000042 */
Catalin Marinas08375192014-07-16 17:42:43 +010043#define VMEMMAP_SIZE ALIGN((1UL << (VA_BITS - PAGE_SHIFT)) * sizeof(struct page), PUD_SIZE)
Catalin Marinas847264fb2013-10-23 16:50:07 +010044#define VMALLOC_START (UL(0xffffffffffffffff) << VA_BITS)
Catalin Marinas08375192014-07-16 17:42:43 +010045#define VMALLOC_END (PAGE_OFFSET - PUD_SIZE - VMEMMAP_SIZE - SZ_64K)
Catalin Marinas4f04d8f2012-03-05 11:49:27 +000046
47#define vmemmap ((struct page *)(VMALLOC_END + SZ_64K))
48
49#define FIRST_USER_ADDRESS 0
50
51#ifndef __ASSEMBLY__
52extern void __pte_error(const char *file, int line, unsigned long val);
53extern void __pmd_error(const char *file, int line, unsigned long val);
Jungseok Leec79b9542014-05-12 18:40:51 +090054extern void __pud_error(const char *file, int line, unsigned long val);
Catalin Marinas4f04d8f2012-03-05 11:49:27 +000055extern void __pgd_error(const char *file, int line, unsigned long val);
56
Catalin Marinasa501e322014-04-03 15:57:15 +010057#ifdef CONFIG_SMP
58#define PROT_DEFAULT (PTE_TYPE_PAGE | PTE_AF | PTE_SHARED)
59#define PROT_SECT_DEFAULT (PMD_TYPE_SECT | PMD_SECT_AF | PMD_SECT_S)
60#else
61#define PROT_DEFAULT (PTE_TYPE_PAGE | PTE_AF)
62#define PROT_SECT_DEFAULT (PMD_TYPE_SECT | PMD_SECT_AF)
63#endif
Catalin Marinas4f04d8f2012-03-05 11:49:27 +000064
Catalin Marinasa501e322014-04-03 15:57:15 +010065#define PROT_DEVICE_nGnRE (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_ATTRINDX(MT_DEVICE_nGnRE))
66#define PROT_NORMAL_NC (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_ATTRINDX(MT_NORMAL_NC))
67#define PROT_NORMAL (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_ATTRINDX(MT_NORMAL))
Catalin Marinas4f04d8f2012-03-05 11:49:27 +000068
Catalin Marinasa501e322014-04-03 15:57:15 +010069#define PROT_SECT_DEVICE_nGnRE (PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PMD_ATTRINDX(MT_DEVICE_nGnRE))
70#define PROT_SECT_NORMAL (PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PMD_ATTRINDX(MT_NORMAL))
71#define PROT_SECT_NORMAL_EXEC (PROT_SECT_DEFAULT | PMD_SECT_UXN | PMD_ATTRINDX(MT_NORMAL))
Catalin Marinas4f04d8f2012-03-05 11:49:27 +000072
Catalin Marinasa501e322014-04-03 15:57:15 +010073#define _PAGE_DEFAULT (PROT_DEFAULT | PTE_ATTRINDX(MT_NORMAL))
Will Deacona6fadf72012-12-18 14:15:15 +000074
Catalin Marinasa501e322014-04-03 15:57:15 +010075#define PAGE_KERNEL __pgprot(_PAGE_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE)
76#define PAGE_KERNEL_EXEC __pgprot(_PAGE_DEFAULT | PTE_UXN | PTE_DIRTY | PTE_WRITE)
Catalin Marinas4f04d8f2012-03-05 11:49:27 +000077
Catalin Marinasa501e322014-04-03 15:57:15 +010078#define PAGE_HYP __pgprot(_PAGE_DEFAULT | PTE_HYP)
Marc Zyngier36311602012-12-07 18:35:41 +000079#define PAGE_HYP_DEVICE __pgprot(PROT_DEVICE_nGnRE | PTE_HYP)
80
Catalin Marinasa501e322014-04-03 15:57:15 +010081#define PAGE_S2 __pgprot(PROT_DEFAULT | PTE_S2_MEMATTR(MT_S2_NORMAL) | PTE_S2_RDONLY)
Ard Biesheuvel4a513fb2014-09-17 14:56:20 -070082#define PAGE_S2_DEVICE __pgprot(PROT_DEFAULT | PTE_S2_MEMATTR(MT_S2_DEVICE_nGnRE) | PTE_S2_RDONLY | PTE_UXN)
Marc Zyngier36311602012-12-07 18:35:41 +000083
Catalin Marinasa501e322014-04-03 15:57:15 +010084#define PAGE_NONE __pgprot(((_PAGE_DEFAULT) & ~PTE_TYPE_MASK) | PTE_PROT_NONE | PTE_PXN | PTE_UXN)
85#define PAGE_SHARED __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_UXN | PTE_WRITE)
86#define PAGE_SHARED_EXEC __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_WRITE)
87#define PAGE_COPY __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_UXN)
88#define PAGE_COPY_EXEC __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN)
89#define PAGE_READONLY __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_UXN)
90#define PAGE_READONLY_EXEC __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN)
Catalin Marinas4f04d8f2012-03-05 11:49:27 +000091
Catalin Marinasa501e322014-04-03 15:57:15 +010092#define __P000 PAGE_NONE
93#define __P001 PAGE_READONLY
94#define __P010 PAGE_COPY
95#define __P011 PAGE_COPY
Catalin Marinas5a0fdfa2014-05-16 16:44:32 +010096#define __P100 PAGE_READONLY_EXEC
Catalin Marinasa501e322014-04-03 15:57:15 +010097#define __P101 PAGE_READONLY_EXEC
98#define __P110 PAGE_COPY_EXEC
99#define __P111 PAGE_COPY_EXEC
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000100
Catalin Marinasa501e322014-04-03 15:57:15 +0100101#define __S000 PAGE_NONE
102#define __S001 PAGE_READONLY
103#define __S010 PAGE_SHARED
104#define __S011 PAGE_SHARED
Catalin Marinas5a0fdfa2014-05-16 16:44:32 +0100105#define __S100 PAGE_READONLY_EXEC
Catalin Marinasa501e322014-04-03 15:57:15 +0100106#define __S101 PAGE_READONLY_EXEC
107#define __S110 PAGE_SHARED_EXEC
108#define __S111 PAGE_SHARED_EXEC
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000109
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000110/*
111 * ZERO_PAGE is a global shared page that is always zero: used
112 * for zero-mapped memory areas etc..
113 */
114extern struct page *empty_zero_page;
115#define ZERO_PAGE(vaddr) (empty_zero_page)
116
Catalin Marinas7078db42014-07-21 14:52:49 +0100117#define pte_ERROR(pte) __pte_error(__FILE__, __LINE__, pte_val(pte))
118
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000119#define pte_pfn(pte) ((pte_val(pte) & PHYS_MASK) >> PAGE_SHIFT)
120
121#define pfn_pte(pfn,prot) (__pte(((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)))
122
123#define pte_none(pte) (!pte_val(pte))
124#define pte_clear(mm,addr,ptep) set_pte(ptep, __pte(0))
125#define pte_page(pte) (pfn_to_page(pte_pfn(pte)))
Catalin Marinas7078db42014-07-21 14:52:49 +0100126
127/* Find an entry in the third-level page table. */
128#define pte_index(addr) (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
129
Will Deacon9ab6d022013-06-10 19:34:41 +0100130#define pte_offset_kernel(dir,addr) (pmd_page_vaddr(*(dir)) + pte_index(addr))
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000131
132#define pte_offset_map(dir,addr) pte_offset_kernel((dir), (addr))
133#define pte_offset_map_nested(dir,addr) pte_offset_kernel((dir), (addr))
134#define pte_unmap(pte) do { } while (0)
135#define pte_unmap_nested(pte) do { } while (0)
136
137/*
138 * The following only work if pte_present(). Undefined behaviour otherwise.
139 */
Steve Capper84fe6822014-02-25 11:38:53 +0000140#define pte_present(pte) (!!(pte_val(pte) & (PTE_VALID | PTE_PROT_NONE)))
141#define pte_dirty(pte) (!!(pte_val(pte) & PTE_DIRTY))
142#define pte_young(pte) (!!(pte_val(pte) & PTE_AF))
143#define pte_special(pte) (!!(pte_val(pte) & PTE_SPECIAL))
144#define pte_write(pte) (!!(pte_val(pte) & PTE_WRITE))
Catalin Marinas8e620b02012-11-15 17:21:16 +0000145#define pte_exec(pte) (!(pte_val(pte) & PTE_UXN))
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000146
Will Deacona6fadf72012-12-18 14:15:15 +0000147#define pte_valid_user(pte) \
Will Deacon02522462013-01-09 11:08:10 +0000148 ((pte_val(pte) & (PTE_VALID | PTE_USER)) == (PTE_VALID | PTE_USER))
Catalin Marinas7f0b1bf2014-06-09 11:55:03 +0100149#define pte_valid_not_user(pte) \
150 ((pte_val(pte) & (PTE_VALID | PTE_USER)) == PTE_VALID)
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000151
Steve Capper44b6dfc2014-01-15 14:07:12 +0000152static inline pte_t pte_wrprotect(pte_t pte)
153{
Steve Capperc2c93e52014-01-15 14:07:13 +0000154 pte_val(pte) &= ~PTE_WRITE;
Steve Capper44b6dfc2014-01-15 14:07:12 +0000155 return pte;
156}
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000157
Steve Capper44b6dfc2014-01-15 14:07:12 +0000158static inline pte_t pte_mkwrite(pte_t pte)
159{
Steve Capperc2c93e52014-01-15 14:07:13 +0000160 pte_val(pte) |= PTE_WRITE;
Steve Capper44b6dfc2014-01-15 14:07:12 +0000161 return pte;
162}
163
164static inline pte_t pte_mkclean(pte_t pte)
165{
166 pte_val(pte) &= ~PTE_DIRTY;
167 return pte;
168}
169
170static inline pte_t pte_mkdirty(pte_t pte)
171{
172 pte_val(pte) |= PTE_DIRTY;
173 return pte;
174}
175
176static inline pte_t pte_mkold(pte_t pte)
177{
178 pte_val(pte) &= ~PTE_AF;
179 return pte;
180}
181
182static inline pte_t pte_mkyoung(pte_t pte)
183{
184 pte_val(pte) |= PTE_AF;
185 return pte;
186}
187
188static inline pte_t pte_mkspecial(pte_t pte)
189{
190 pte_val(pte) |= PTE_SPECIAL;
191 return pte;
192}
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000193
194static inline void set_pte(pte_t *ptep, pte_t pte)
195{
196 *ptep = pte;
Catalin Marinas7f0b1bf2014-06-09 11:55:03 +0100197
198 /*
199 * Only if the new pte is valid and kernel, otherwise TLB maintenance
200 * or update_mmu_cache() have the necessary barriers.
201 */
202 if (pte_valid_not_user(pte)) {
203 dsb(ishst);
204 isb();
205 }
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000206}
207
208extern void __sync_icache_dcache(pte_t pteval, unsigned long addr);
209
210static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
211 pte_t *ptep, pte_t pte)
212{
Will Deacona6fadf72012-12-18 14:15:15 +0000213 if (pte_valid_user(pte)) {
Catalin Marinas71fdb6b2014-03-12 16:28:09 +0000214 if (!pte_special(pte) && pte_exec(pte))
Will Deacon02522462013-01-09 11:08:10 +0000215 __sync_icache_dcache(pte, addr);
Steve Capperc2c93e52014-01-15 14:07:13 +0000216 if (pte_dirty(pte) && pte_write(pte))
217 pte_val(pte) &= ~PTE_RDONLY;
218 else
219 pte_val(pte) |= PTE_RDONLY;
Will Deacon02522462013-01-09 11:08:10 +0000220 }
221
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000222 set_pte(ptep, pte);
223}
224
225/*
226 * Huge pte definitions.
227 */
Steve Capper084bd292013-04-10 13:48:00 +0100228#define pte_huge(pte) (!(pte_val(pte) & PTE_TABLE_BIT))
229#define pte_mkhuge(pte) (__pte(pte_val(pte) & ~PTE_TABLE_BIT))
230
231/*
232 * Hugetlb definitions.
233 */
234#define HUGE_MAX_HSTATE 2
235#define HPAGE_SHIFT PMD_SHIFT
236#define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT)
237#define HPAGE_MASK (~(HPAGE_SIZE - 1))
238#define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT)
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000239
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000240#define __HAVE_ARCH_PTE_SPECIAL
241
Steve Capper9c7e5352014-02-25 10:02:13 +0000242static inline pte_t pmd_pte(pmd_t pmd)
243{
244 return __pte(pmd_val(pmd));
245}
Steve Capperaf074842013-04-19 16:23:57 +0100246
Steve Capper9c7e5352014-02-25 10:02:13 +0000247static inline pmd_t pte_pmd(pte_t pte)
248{
249 return __pmd(pte_val(pte));
250}
Steve Capperaf074842013-04-19 16:23:57 +0100251
252/*
253 * THP definitions.
254 */
Steve Capperaf074842013-04-19 16:23:57 +0100255
256#ifdef CONFIG_TRANSPARENT_HUGEPAGE
257#define pmd_trans_huge(pmd) (pmd_val(pmd) && !(pmd_val(pmd) & PMD_TABLE_BIT))
Steve Capper9c7e5352014-02-25 10:02:13 +0000258#define pmd_trans_splitting(pmd) pte_special(pmd_pte(pmd))
Steve Capperaf074842013-04-19 16:23:57 +0100259#endif
260
Steve Capper9c7e5352014-02-25 10:02:13 +0000261#define pmd_young(pmd) pte_young(pmd_pte(pmd))
262#define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd)))
263#define pmd_mksplitting(pmd) pte_pmd(pte_mkspecial(pmd_pte(pmd)))
264#define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd)))
265#define pmd_mkwrite(pmd) pte_pmd(pte_mkwrite(pmd_pte(pmd)))
266#define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd)))
267#define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd)))
Will Deacone3a920a2014-06-18 14:06:27 +0100268#define pmd_mknotpresent(pmd) (__pmd(pmd_val(pmd) & ~PMD_TYPE_MASK))
Steve Capperaf074842013-04-19 16:23:57 +0100269
Steve Capper9c7e5352014-02-25 10:02:13 +0000270#define __HAVE_ARCH_PMD_WRITE
271#define pmd_write(pmd) pte_write(pmd_pte(pmd))
Steve Capperaf074842013-04-19 16:23:57 +0100272
273#define pmd_mkhuge(pmd) (__pmd(pmd_val(pmd) & ~PMD_TABLE_BIT))
274
275#define pmd_pfn(pmd) (((pmd_val(pmd) & PMD_MASK) & PHYS_MASK) >> PAGE_SHIFT)
276#define pfn_pmd(pfn,prot) (__pmd(((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)))
277#define mk_pmd(page,prot) pfn_pmd(page_to_pfn(page),prot)
278
279#define pmd_page(pmd) pfn_to_page(__phys_to_pfn(pmd_val(pmd) & PHYS_MASK))
Steve Capper206a2a72014-05-06 14:02:27 +0100280#define pud_pfn(pud) (((pud_val(pud) & PUD_MASK) & PHYS_MASK) >> PAGE_SHIFT)
Steve Capperaf074842013-04-19 16:23:57 +0100281
Will Deaconceb21832014-05-27 19:11:58 +0100282#define set_pmd_at(mm, addr, pmdp, pmd) set_pte_at(mm, addr, (pte_t *)pmdp, pmd_pte(pmd))
Steve Capperaf074842013-04-19 16:23:57 +0100283
284static inline int has_transparent_hugepage(void)
285{
286 return 1;
287}
288
Catalin Marinasa501e322014-04-03 15:57:15 +0100289#define __pgprot_modify(prot,mask,bits) \
290 __pgprot((pgprot_val(prot) & ~(mask)) | (bits))
291
Steve Capperaf074842013-04-19 16:23:57 +0100292/*
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000293 * Mark the prot value as uncacheable and unbufferable.
294 */
295#define pgprot_noncached(prot) \
Catalin Marinasde2db742014-03-12 16:07:06 +0000296 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN)
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000297#define pgprot_writecombine(prot) \
Catalin Marinasde2db742014-03-12 16:07:06 +0000298 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN)
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000299#define __HAVE_PHYS_MEM_ACCESS_PROT
300struct file;
301extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
302 unsigned long size, pgprot_t vma_prot);
303
304#define pmd_none(pmd) (!pmd_val(pmd))
305#define pmd_present(pmd) (pmd_val(pmd))
306
307#define pmd_bad(pmd) (!(pmd_val(pmd) & 2))
308
Marc Zyngier36311602012-12-07 18:35:41 +0000309#define pmd_table(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \
310 PMD_TYPE_TABLE)
311#define pmd_sect(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \
312 PMD_TYPE_SECT)
313
Steve Capperf3b766a2014-06-25 08:41:45 +0100314#ifdef CONFIG_ARM64_64K_PAGES
Steve Capper206a2a72014-05-06 14:02:27 +0100315#define pud_sect(pud) (0)
316#else
317#define pud_sect(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \
318 PUD_TYPE_SECT)
319#endif
Marc Zyngier36311602012-12-07 18:35:41 +0000320
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000321static inline void set_pmd(pmd_t *pmdp, pmd_t pmd)
322{
323 *pmdp = pmd;
Will Deacon98f76852014-05-02 16:24:10 +0100324 dsb(ishst);
Catalin Marinas7f0b1bf2014-06-09 11:55:03 +0100325 isb();
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000326}
327
328static inline void pmd_clear(pmd_t *pmdp)
329{
330 set_pmd(pmdp, __pmd(0));
331}
332
333static inline pte_t *pmd_page_vaddr(pmd_t pmd)
334{
335 return __va(pmd_val(pmd) & PHYS_MASK & (s32)PAGE_MASK);
336}
337
338#define pmd_page(pmd) pfn_to_page(__phys_to_pfn(pmd_val(pmd) & PHYS_MASK))
339
340/*
341 * Conversion functions: convert a page and protection to a page entry,
342 * and a page entry and page directory to the page they refer to.
343 */
344#define mk_pte(page,prot) pfn_pte(page_to_pfn(page),prot)
345
Catalin Marinasabe669d2014-07-15 15:37:21 +0100346#if CONFIG_ARM64_PGTABLE_LEVELS > 2
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000347
Catalin Marinas7078db42014-07-21 14:52:49 +0100348#define pmd_ERROR(pmd) __pmd_error(__FILE__, __LINE__, pmd_val(pmd))
349
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000350#define pud_none(pud) (!pud_val(pud))
351#define pud_bad(pud) (!(pud_val(pud) & 2))
352#define pud_present(pud) (pud_val(pud))
353
354static inline void set_pud(pud_t *pudp, pud_t pud)
355{
356 *pudp = pud;
Will Deacon98f76852014-05-02 16:24:10 +0100357 dsb(ishst);
Catalin Marinas7f0b1bf2014-06-09 11:55:03 +0100358 isb();
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000359}
360
361static inline void pud_clear(pud_t *pudp)
362{
363 set_pud(pudp, __pud(0));
364}
365
366static inline pmd_t *pud_page_vaddr(pud_t pud)
367{
368 return __va(pud_val(pud) & PHYS_MASK & (s32)PAGE_MASK);
369}
370
Catalin Marinas7078db42014-07-21 14:52:49 +0100371/* Find an entry in the second-level page table. */
372#define pmd_index(addr) (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1))
373
374static inline pmd_t *pmd_offset(pud_t *pud, unsigned long addr)
375{
376 return (pmd_t *)pud_page_vaddr(*pud) + pmd_index(addr);
377}
378
Catalin Marinasabe669d2014-07-15 15:37:21 +0100379#endif /* CONFIG_ARM64_PGTABLE_LEVELS > 2 */
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000380
Catalin Marinasabe669d2014-07-15 15:37:21 +0100381#if CONFIG_ARM64_PGTABLE_LEVELS > 3
Jungseok Leec79b9542014-05-12 18:40:51 +0900382
Catalin Marinas7078db42014-07-21 14:52:49 +0100383#define pud_ERROR(pud) __pud_error(__FILE__, __LINE__, pud_val(pud))
384
Jungseok Leec79b9542014-05-12 18:40:51 +0900385#define pgd_none(pgd) (!pgd_val(pgd))
386#define pgd_bad(pgd) (!(pgd_val(pgd) & 2))
387#define pgd_present(pgd) (pgd_val(pgd))
388
389static inline void set_pgd(pgd_t *pgdp, pgd_t pgd)
390{
391 *pgdp = pgd;
392 dsb(ishst);
393}
394
395static inline void pgd_clear(pgd_t *pgdp)
396{
397 set_pgd(pgdp, __pgd(0));
398}
399
400static inline pud_t *pgd_page_vaddr(pgd_t pgd)
401{
402 return __va(pgd_val(pgd) & PHYS_MASK & (s32)PAGE_MASK);
403}
404
Catalin Marinas7078db42014-07-21 14:52:49 +0100405/* Find an entry in the frst-level page table. */
406#define pud_index(addr) (((addr) >> PUD_SHIFT) & (PTRS_PER_PUD - 1))
407
408static inline pud_t *pud_offset(pgd_t *pgd, unsigned long addr)
409{
410 return (pud_t *)pgd_page_vaddr(*pgd) + pud_index(addr);
411}
412
Catalin Marinasabe669d2014-07-15 15:37:21 +0100413#endif /* CONFIG_ARM64_PGTABLE_LEVELS > 3 */
Jungseok Leec79b9542014-05-12 18:40:51 +0900414
Catalin Marinas7078db42014-07-21 14:52:49 +0100415#define pgd_ERROR(pgd) __pgd_error(__FILE__, __LINE__, pgd_val(pgd))
416
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000417/* to find an entry in a page-table-directory */
418#define pgd_index(addr) (((addr) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1))
419
420#define pgd_offset(mm, addr) ((mm)->pgd+pgd_index(addr))
421
422/* to find an entry in a kernel page-table-directory */
423#define pgd_offset_k(addr) pgd_offset(&init_mm, addr)
424
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000425static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
426{
Will Deacona6fadf72012-12-18 14:15:15 +0000427 const pteval_t mask = PTE_USER | PTE_PXN | PTE_UXN | PTE_RDONLY |
Steve Capperc2c93e52014-01-15 14:07:13 +0000428 PTE_PROT_NONE | PTE_VALID | PTE_WRITE;
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000429 pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask);
430 return pte;
431}
432
Steve Capper9c7e5352014-02-25 10:02:13 +0000433static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot)
434{
435 return pte_pmd(pte_modify(pmd_pte(pmd), newprot));
436}
437
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000438extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
439extern pgd_t idmap_pg_dir[PTRS_PER_PGD];
440
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000441/*
442 * Encode and decode a swap entry:
Catalin Marinas3676f9e2013-11-27 16:59:27 +0000443 * bits 0-1: present (must be zero)
444 * bit 2: PTE_FILE
445 * bits 3-8: swap type
446 * bits 9-57: swap offset
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000447 */
Catalin Marinas3676f9e2013-11-27 16:59:27 +0000448#define __SWP_TYPE_SHIFT 3
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000449#define __SWP_TYPE_BITS 6
Catalin Marinas3676f9e2013-11-27 16:59:27 +0000450#define __SWP_OFFSET_BITS 49
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000451#define __SWP_TYPE_MASK ((1 << __SWP_TYPE_BITS) - 1)
452#define __SWP_OFFSET_SHIFT (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT)
Catalin Marinas3676f9e2013-11-27 16:59:27 +0000453#define __SWP_OFFSET_MASK ((1UL << __SWP_OFFSET_BITS) - 1)
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000454
455#define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK)
Catalin Marinas3676f9e2013-11-27 16:59:27 +0000456#define __swp_offset(x) (((x).val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK)
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000457#define __swp_entry(type,offset) ((swp_entry_t) { ((type) << __SWP_TYPE_SHIFT) | ((offset) << __SWP_OFFSET_SHIFT) })
458
459#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
460#define __swp_entry_to_pte(swp) ((pte_t) { (swp).val })
461
462/*
463 * Ensure that there are not more swap files than can be encoded in the kernel
Geert Uytterhoevenaad90612014-03-11 11:23:39 +0100464 * PTEs.
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000465 */
466#define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS)
467
468/*
469 * Encode and decode a file entry:
Catalin Marinas3676f9e2013-11-27 16:59:27 +0000470 * bits 0-1: present (must be zero)
471 * bit 2: PTE_FILE
472 * bits 3-57: file offset / PAGE_SIZE
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000473 */
474#define pte_file(pte) (pte_val(pte) & PTE_FILE)
Catalin Marinas3676f9e2013-11-27 16:59:27 +0000475#define pte_to_pgoff(x) (pte_val(x) >> 3)
476#define pgoff_to_pte(x) __pte(((x) << 3) | PTE_FILE)
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000477
Catalin Marinas3676f9e2013-11-27 16:59:27 +0000478#define PTE_FILE_MAX_BITS 55
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000479
480extern int kern_addr_valid(unsigned long addr);
481
482#include <asm-generic/pgtable.h>
483
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000484#define pgtable_cache_init() do { } while (0)
485
486#endif /* !__ASSEMBLY__ */
487
488#endif /* __ASM_PGTABLE_H */