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Hans Verkuil54450f52012-07-18 05:45:16 -03001/*
2 * adv7604 - Analog Devices ADV7604 video decoder driver
3 *
4 * Copyright 2012 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
5 *
6 * This program is free software; you may redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
11 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
12 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
13 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
14 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
15 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
16 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
17 * SOFTWARE.
18 *
19 */
20
21#ifndef _ADV7604_
22#define _ADV7604_
23
Lars-Peter Clausene5e749d2013-11-21 11:23:45 -030024#include <linux/types.h>
25
Hans Verkuil54450f52012-07-18 05:45:16 -030026/* Analog input muxing modes (AFE register 0x02, [2:0]) */
27enum adv7604_ain_sel {
28 ADV7604_AIN1_2_3_NC_SYNC_1_2 = 0,
29 ADV7604_AIN4_5_6_NC_SYNC_2_1 = 1,
30 ADV7604_AIN7_8_9_NC_SYNC_3_1 = 2,
31 ADV7604_AIN10_11_12_NC_SYNC_4_1 = 3,
32 ADV7604_AIN9_4_5_6_SYNC_2_1 = 4,
33};
34
Laurent Pinchart539b33b2014-01-26 18:42:37 -030035/*
36 * Bus rotation and reordering. This is used to specify component reordering on
37 * the board and describes the components order on the bus when the ADV7604
38 * outputs RGB.
39 */
40enum adv7604_bus_order {
41 ADV7604_BUS_ORDER_RGB, /* No operation */
42 ADV7604_BUS_ORDER_GRB, /* Swap 1-2 */
43 ADV7604_BUS_ORDER_RBG, /* Swap 2-3 */
44 ADV7604_BUS_ORDER_BGR, /* Swap 1-3 */
45 ADV7604_BUS_ORDER_BRG, /* Rotate right */
46 ADV7604_BUS_ORDER_GBR, /* Rotate left */
Hans Verkuil54450f52012-07-18 05:45:16 -030047};
48
Hans Verkuil54450f52012-07-18 05:45:16 -030049/* Input Color Space (IO register 0x02, [7:4]) */
Pablo Antonb44b2e02015-02-03 14:13:18 -030050enum adv76xx_inp_color_space {
51 ADV76XX_INP_COLOR_SPACE_LIM_RGB = 0,
52 ADV76XX_INP_COLOR_SPACE_FULL_RGB = 1,
53 ADV76XX_INP_COLOR_SPACE_LIM_YCbCr_601 = 2,
54 ADV76XX_INP_COLOR_SPACE_LIM_YCbCr_709 = 3,
55 ADV76XX_INP_COLOR_SPACE_XVYCC_601 = 4,
56 ADV76XX_INP_COLOR_SPACE_XVYCC_709 = 5,
57 ADV76XX_INP_COLOR_SPACE_FULL_YCbCr_601 = 6,
58 ADV76XX_INP_COLOR_SPACE_FULL_YCbCr_709 = 7,
59 ADV76XX_INP_COLOR_SPACE_AUTO = 0xf,
Hans Verkuil54450f52012-07-18 05:45:16 -030060};
61
Laurent Pinchart539b33b2014-01-26 18:42:37 -030062/* Select output format (IO register 0x03, [4:2]) */
63enum adv7604_op_format_mode_sel {
64 ADV7604_OP_FORMAT_MODE0 = 0x00,
65 ADV7604_OP_FORMAT_MODE1 = 0x04,
66 ADV7604_OP_FORMAT_MODE2 = 0x08,
Hans Verkuil54450f52012-07-18 05:45:16 -030067};
68
Pablo Antonb44b2e02015-02-03 14:13:18 -030069enum adv76xx_drive_strength {
70 ADV76XX_DR_STR_MEDIUM_LOW = 1,
71 ADV76XX_DR_STR_MEDIUM_HIGH = 2,
72 ADV76XX_DR_STR_HIGH = 3,
Mikhail Khelikf31b62e2013-12-20 05:12:00 -030073};
74
Pablo Antonb44b2e02015-02-03 14:13:18 -030075/* INT1 Configuration (IO register 0x40, [1:0]) */
76enum adv76xx_int1_config {
77 ADV76XX_INT1_CONFIG_OPEN_DRAIN,
78 ADV76XX_INT1_CONFIG_ACTIVE_LOW,
79 ADV76XX_INT1_CONFIG_ACTIVE_HIGH,
80 ADV76XX_INT1_CONFIG_DISABLED,
Lars-Peter Clausend42010a2013-11-25 15:45:07 -030081};
82
Pablo Antonb44b2e02015-02-03 14:13:18 -030083enum adv76xx_page {
84 ADV76XX_PAGE_IO,
Laurent Pinchart05cacb12014-01-30 16:32:21 -030085 ADV7604_PAGE_AVLINK,
Pablo Antonb44b2e02015-02-03 14:13:18 -030086 ADV76XX_PAGE_CEC,
87 ADV76XX_PAGE_INFOFRAME,
Laurent Pinchart05cacb12014-01-30 16:32:21 -030088 ADV7604_PAGE_ESDP,
89 ADV7604_PAGE_DPP,
Pablo Antonb44b2e02015-02-03 14:13:18 -030090 ADV76XX_PAGE_AFE,
91 ADV76XX_PAGE_REP,
92 ADV76XX_PAGE_EDID,
93 ADV76XX_PAGE_HDMI,
94 ADV76XX_PAGE_TEST,
95 ADV76XX_PAGE_CP,
Laurent Pinchart05cacb12014-01-30 16:32:21 -030096 ADV7604_PAGE_VDP,
Pablo Antonb44b2e02015-02-03 14:13:18 -030097 ADV76XX_PAGE_MAX,
Laurent Pinchart05cacb12014-01-30 16:32:21 -030098};
99
Hans Verkuil54450f52012-07-18 05:45:16 -0300100/* Platform dependent definition */
Pablo Antonb44b2e02015-02-03 14:13:18 -0300101struct adv76xx_platform_data {
Hans Verkuil54450f52012-07-18 05:45:16 -0300102 /* DIS_PWRDNB: 1 if the PWRDNB pin is unused and unconnected */
103 unsigned disable_pwrdnb:1;
104
105 /* DIS_CABLE_DET_RST: 1 if the 5V pins are unused and unconnected */
106 unsigned disable_cable_det_rst:1;
107
Laurent Pinchart5ef54b52014-01-31 10:57:27 -0300108 int default_input;
109
Hans Verkuil54450f52012-07-18 05:45:16 -0300110 /* Analog input muxing mode */
111 enum adv7604_ain_sel ain_sel;
112
113 /* Bus rotation and reordering */
Laurent Pinchart539b33b2014-01-26 18:42:37 -0300114 enum adv7604_bus_order bus_order;
Hans Verkuil54450f52012-07-18 05:45:16 -0300115
Laurent Pinchart539b33b2014-01-26 18:42:37 -0300116 /* Select output format mode */
117 enum adv7604_op_format_mode_sel op_format_mode_sel;
Hans Verkuil54450f52012-07-18 05:45:16 -0300118
Lars-Peter Clausend42010a2013-11-25 15:45:07 -0300119 /* Configuration of the INT1 pin */
Pablo Antonb44b2e02015-02-03 14:13:18 -0300120 enum adv76xx_int1_config int1_config;
Lars-Peter Clausend42010a2013-11-25 15:45:07 -0300121
Hans Verkuil54450f52012-07-18 05:45:16 -0300122 /* IO register 0x02 */
123 unsigned alt_gamma:1;
124 unsigned op_656_range:1;
Hans Verkuil54450f52012-07-18 05:45:16 -0300125 unsigned alt_data_sat:1;
126
127 /* IO register 0x05 */
128 unsigned blank_data:1;
129 unsigned insert_av_codes:1;
130 unsigned replicate_av_codes:1;
Hans Verkuil54450f52012-07-18 05:45:16 -0300131
Martin Bugge98908692013-12-20 05:14:57 -0300132 /* IO register 0x06 */
133 unsigned inv_vs_pol:1;
134 unsigned inv_hs_pol:1;
Laurent Pinchart1b5ab872014-02-04 19:57:56 -0300135 unsigned inv_llc_pol:1;
Martin Bugge98908692013-12-20 05:14:57 -0300136
Mikhail Khelikf31b62e2013-12-20 05:12:00 -0300137 /* IO register 0x14 */
Pablo Antonb44b2e02015-02-03 14:13:18 -0300138 enum adv76xx_drive_strength dr_str_data;
139 enum adv76xx_drive_strength dr_str_clk;
140 enum adv76xx_drive_strength dr_str_sync;
Mikhail Khelikf31b62e2013-12-20 05:12:00 -0300141
Hans Verkuil54450f52012-07-18 05:45:16 -0300142 /* IO register 0x30 */
143 unsigned output_bus_lsb_to_msb:1;
144
145 /* Free run */
146 unsigned hdmi_free_run_mode;
147
148 /* i2c addresses: 0 == use default */
Pablo Antonb44b2e02015-02-03 14:13:18 -0300149 u8 i2c_addresses[ADV76XX_PAGE_MAX];
Hans Verkuil54450f52012-07-18 05:45:16 -0300150};
151
Pablo Antonb44b2e02015-02-03 14:13:18 -0300152enum adv76xx_pad {
153 ADV76XX_PAD_HDMI_PORT_A = 0,
Laurent Pinchartc784b1e2014-01-29 10:08:58 -0300154 ADV7604_PAD_HDMI_PORT_B = 1,
155 ADV7604_PAD_HDMI_PORT_C = 2,
156 ADV7604_PAD_HDMI_PORT_D = 3,
157 ADV7604_PAD_VGA_RGB = 4,
158 ADV7604_PAD_VGA_COMP = 5,
159 /* The source pad is either 1 (ADV7611) or 6 (ADV7604) */
160 ADV7604_PAD_SOURCE = 6,
161 ADV7611_PAD_SOURCE = 1,
Pablo Antonb44b2e02015-02-03 14:13:18 -0300162 ADV76XX_PAD_MAX = 7,
Hans Verkuil6b0d5d32012-10-16 06:40:45 -0300163};
164
Hans Verkuil54450f52012-07-18 05:45:16 -0300165#define V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE (V4L2_CID_DV_CLASS_BASE + 0x1000)
166#define V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL (V4L2_CID_DV_CLASS_BASE + 0x1001)
167#define V4L2_CID_ADV_RX_FREE_RUN_COLOR (V4L2_CID_DV_CLASS_BASE + 0x1002)
168
169/* notify events */
Pablo Antonb44b2e02015-02-03 14:13:18 -0300170#define ADV76XX_HOTPLUG 1
171#define ADV76XX_FMT_CHANGE 2
Hans Verkuil54450f52012-07-18 05:45:16 -0300172
173#endif