Marc Zyngier | 359b706 | 2015-03-27 13:09:23 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Contains CPU feature definitions |
| 3 | * |
| 4 | * Copyright (C) 2015 ARM Ltd. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 as |
| 8 | * published by the Free Software Foundation. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
| 17 | */ |
| 18 | |
Suzuki K. Poulose | 9cdf8ec | 2015-10-19 14:24:41 +0100 | [diff] [blame] | 19 | #define pr_fmt(fmt) "CPU features: " fmt |
Marc Zyngier | 359b706 | 2015-03-27 13:09:23 +0000 | [diff] [blame] | 20 | |
Suzuki K. Poulose | 3c739b5 | 2015-10-19 14:24:45 +0100 | [diff] [blame] | 21 | #include <linux/bsearch.h> |
James Morse | 2a6dcb2 | 2016-10-18 11:27:46 +0100 | [diff] [blame] | 22 | #include <linux/cpumask.h> |
Suzuki K. Poulose | 3c739b5 | 2015-10-19 14:24:45 +0100 | [diff] [blame] | 23 | #include <linux/sort.h> |
James Morse | 2a6dcb2 | 2016-10-18 11:27:46 +0100 | [diff] [blame] | 24 | #include <linux/stop_machine.h> |
Marc Zyngier | 359b706 | 2015-03-27 13:09:23 +0000 | [diff] [blame] | 25 | #include <linux/types.h> |
Laura Abbott | f8fee94e | 2017-01-10 13:35:49 -0800 | [diff] [blame] | 26 | #include <linux/mm.h> |
Marc Zyngier | 359b706 | 2015-03-27 13:09:23 +0000 | [diff] [blame] | 27 | #include <asm/cpu.h> |
| 28 | #include <asm/cpufeature.h> |
Suzuki K. Poulose | dbb4e15 | 2015-10-19 14:24:50 +0100 | [diff] [blame] | 29 | #include <asm/cpu_ops.h> |
Suzuki K Poulose | 13f417f | 2016-02-23 10:31:45 +0000 | [diff] [blame] | 30 | #include <asm/mmu_context.h> |
James Morse | 338d4f4 | 2015-07-22 19:05:54 +0100 | [diff] [blame] | 31 | #include <asm/processor.h> |
Suzuki K. Poulose | cdcf817 | 2015-10-19 14:24:42 +0100 | [diff] [blame] | 32 | #include <asm/sysreg.h> |
Marc Zyngier | d88701b | 2015-01-29 11:24:05 +0000 | [diff] [blame] | 33 | #include <asm/virt.h> |
Marc Zyngier | 359b706 | 2015-03-27 13:09:23 +0000 | [diff] [blame] | 34 | |
Suzuki K. Poulose | 9cdf8ec | 2015-10-19 14:24:41 +0100 | [diff] [blame] | 35 | unsigned long elf_hwcap __read_mostly; |
| 36 | EXPORT_SYMBOL_GPL(elf_hwcap); |
| 37 | |
| 38 | #ifdef CONFIG_COMPAT |
| 39 | #define COMPAT_ELF_HWCAP_DEFAULT \ |
| 40 | (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\ |
| 41 | COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\ |
| 42 | COMPAT_HWCAP_TLS|COMPAT_HWCAP_VFP|\ |
| 43 | COMPAT_HWCAP_VFPv3|COMPAT_HWCAP_VFPv4|\ |
| 44 | COMPAT_HWCAP_NEON|COMPAT_HWCAP_IDIV|\ |
| 45 | COMPAT_HWCAP_LPAE) |
| 46 | unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT; |
| 47 | unsigned int compat_elf_hwcap2 __read_mostly; |
| 48 | #endif |
| 49 | |
| 50 | DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS); |
Catalin Marinas | 005bf1a | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 51 | EXPORT_SYMBOL(cpu_hwcaps); |
Suzuki K. Poulose | 9cdf8ec | 2015-10-19 14:24:41 +0100 | [diff] [blame] | 52 | |
Catalin Marinas | efd9e03 | 2016-09-05 18:25:48 +0100 | [diff] [blame] | 53 | DEFINE_STATIC_KEY_ARRAY_FALSE(cpu_hwcap_keys, ARM64_NCAPS); |
| 54 | EXPORT_SYMBOL(cpu_hwcap_keys); |
| 55 | |
Suzuki K. Poulose | 4f0a606 | 2015-11-18 17:08:57 +0000 | [diff] [blame] | 56 | #define __ARM64_FTR_BITS(SIGNED, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ |
Suzuki K. Poulose | 3c739b5 | 2015-10-19 14:24:45 +0100 | [diff] [blame] | 57 | { \ |
Suzuki K. Poulose | 4f0a606 | 2015-11-18 17:08:57 +0000 | [diff] [blame] | 58 | .sign = SIGNED, \ |
Suzuki K. Poulose | 3c739b5 | 2015-10-19 14:24:45 +0100 | [diff] [blame] | 59 | .strict = STRICT, \ |
| 60 | .type = TYPE, \ |
| 61 | .shift = SHIFT, \ |
| 62 | .width = WIDTH, \ |
| 63 | .safe_val = SAFE_VAL, \ |
| 64 | } |
| 65 | |
Suzuki K Poulose | 0710cfd | 2016-01-26 10:58:14 +0000 | [diff] [blame] | 66 | /* Define a feature with unsigned values */ |
Suzuki K. Poulose | 4f0a606 | 2015-11-18 17:08:57 +0000 | [diff] [blame] | 67 | #define ARM64_FTR_BITS(STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ |
Suzuki K. Poulose | 4f0a606 | 2015-11-18 17:08:57 +0000 | [diff] [blame] | 68 | __ARM64_FTR_BITS(FTR_UNSIGNED, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) |
| 69 | |
Suzuki K Poulose | 0710cfd | 2016-01-26 10:58:14 +0000 | [diff] [blame] | 70 | /* Define a feature with a signed value */ |
| 71 | #define S_ARM64_FTR_BITS(STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ |
| 72 | __ARM64_FTR_BITS(FTR_SIGNED, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) |
| 73 | |
Suzuki K. Poulose | 3c739b5 | 2015-10-19 14:24:45 +0100 | [diff] [blame] | 74 | #define ARM64_FTR_END \ |
| 75 | { \ |
| 76 | .width = 0, \ |
| 77 | } |
| 78 | |
James Morse | 7054419 | 2016-02-05 14:58:50 +0000 | [diff] [blame] | 79 | /* meta feature for alternatives */ |
| 80 | static bool __maybe_unused |
Suzuki K Poulose | 92406f0 | 2016-04-22 12:25:31 +0100 | [diff] [blame] | 81 | cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused); |
| 82 | |
James Morse | 7054419 | 2016-02-05 14:58:50 +0000 | [diff] [blame] | 83 | |
Ard Biesheuvel | 5e49d73 | 2016-08-31 11:31:08 +0100 | [diff] [blame] | 84 | static const struct arm64_ftr_bits ftr_id_aa64isar0[] = { |
Suzuki K Poulose | ba62b30 | 2017-10-11 14:01:02 +0100 | [diff] [blame] | 85 | ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64ISAR0_DP_SHIFT, 4, 0), |
| 86 | ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64ISAR0_SM4_SHIFT, 4, 0), |
| 87 | ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64ISAR0_SM3_SHIFT, 4, 0), |
| 88 | ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64ISAR0_SHA3_SHIFT, 4, 0), |
Suzuki K. Poulose | 3c739b5 | 2015-10-19 14:24:45 +0100 | [diff] [blame] | 89 | ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64ISAR0_RDM_SHIFT, 4, 0), |
| 90 | ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 24, 4, 0), |
| 91 | ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0), |
| 92 | ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0), |
| 93 | ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0), |
| 94 | ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0), |
| 95 | ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0), |
| 96 | ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0), /* RAZ */ |
| 97 | ARM64_FTR_END, |
| 98 | }; |
| 99 | |
Ard Biesheuvel | 5e49d73 | 2016-08-31 11:31:08 +0100 | [diff] [blame] | 100 | static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = { |
Will Deacon | 7354772 | 2018-04-03 12:09:14 +0100 | [diff] [blame] | 101 | ARM64_FTR_BITS(FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV3_SHIFT, 4, 0), |
Mark Rutland | 4732001 | 2018-04-12 12:11:13 +0100 | [diff] [blame] | 102 | ARM64_FTR_BITS(FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV2_SHIFT, 4, 0), |
| 103 | ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 24, 0), |
Suzuki K. Poulose | 3c739b5 | 2015-10-19 14:24:45 +0100 | [diff] [blame] | 104 | ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 28, 4, 0), |
| 105 | ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_GIC_SHIFT, 4, 0), |
Suzuki K Poulose | 0710cfd | 2016-01-26 10:58:14 +0000 | [diff] [blame] | 106 | S_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI), |
| 107 | S_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI), |
Suzuki K. Poulose | 3c739b5 | 2015-10-19 14:24:45 +0100 | [diff] [blame] | 108 | /* Linux doesn't care about the EL3 */ |
| 109 | ARM64_FTR_BITS(FTR_NONSTRICT, FTR_EXACT, ID_AA64PFR0_EL3_SHIFT, 4, 0), |
| 110 | ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_EL2_SHIFT, 4, 0), |
| 111 | ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_EL1_64BIT_ONLY), |
| 112 | ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_EL0_64BIT_ONLY), |
| 113 | ARM64_FTR_END, |
| 114 | }; |
| 115 | |
Ard Biesheuvel | 5e49d73 | 2016-08-31 11:31:08 +0100 | [diff] [blame] | 116 | static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = { |
Suzuki K. Poulose | 3c739b5 | 2015-10-19 14:24:45 +0100 | [diff] [blame] | 117 | ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0), |
Suzuki K Poulose | 0710cfd | 2016-01-26 10:58:14 +0000 | [diff] [blame] | 118 | S_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI), |
| 119 | S_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI), |
Suzuki K. Poulose | 3c739b5 | 2015-10-19 14:24:45 +0100 | [diff] [blame] | 120 | ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI), |
| 121 | ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0), |
| 122 | /* Linux shouldn't care about secure memory */ |
| 123 | ARM64_FTR_BITS(FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0), |
| 124 | ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_BIGENDEL_SHIFT, 4, 0), |
| 125 | ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_ASID_SHIFT, 4, 0), |
| 126 | /* |
| 127 | * Differing PARange is fine as long as all peripherals and memory are mapped |
| 128 | * within the minimum PARange of all CPUs |
| 129 | */ |
Suzuki K Poulose | 0710cfd | 2016-01-26 10:58:14 +0000 | [diff] [blame] | 130 | ARM64_FTR_BITS(FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0), |
Suzuki K. Poulose | 3c739b5 | 2015-10-19 14:24:45 +0100 | [diff] [blame] | 131 | ARM64_FTR_END, |
| 132 | }; |
| 133 | |
Ard Biesheuvel | 5e49d73 | 2016-08-31 11:31:08 +0100 | [diff] [blame] | 134 | static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = { |
Suzuki K. Poulose | 3c739b5 | 2015-10-19 14:24:45 +0100 | [diff] [blame] | 135 | ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0), |
| 136 | ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0), |
| 137 | ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_LOR_SHIFT, 4, 0), |
| 138 | ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_HPD_SHIFT, 4, 0), |
| 139 | ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_VHE_SHIFT, 4, 0), |
| 140 | ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0), |
| 141 | ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_HADBS_SHIFT, 4, 0), |
| 142 | ARM64_FTR_END, |
| 143 | }; |
| 144 | |
Ard Biesheuvel | 5e49d73 | 2016-08-31 11:31:08 +0100 | [diff] [blame] | 145 | static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = { |
Kefeng Wang | 7d7b4ae | 2016-03-25 17:30:07 +0800 | [diff] [blame] | 146 | ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR2_LVA_SHIFT, 4, 0), |
| 147 | ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR2_IESB_SHIFT, 4, 0), |
| 148 | ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR2_LSM_SHIFT, 4, 0), |
James Morse | 406e308 | 2016-02-05 14:58:47 +0000 | [diff] [blame] | 149 | ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR2_UAO_SHIFT, 4, 0), |
Kefeng Wang | 7d7b4ae | 2016-03-25 17:30:07 +0800 | [diff] [blame] | 150 | ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR2_CNP_SHIFT, 4, 0), |
James Morse | 406e308 | 2016-02-05 14:58:47 +0000 | [diff] [blame] | 151 | ARM64_FTR_END, |
| 152 | }; |
| 153 | |
Ard Biesheuvel | 5e49d73 | 2016-08-31 11:31:08 +0100 | [diff] [blame] | 154 | static const struct arm64_ftr_bits ftr_ctr[] = { |
Will Deacon | e364e9a | 2019-08-05 18:13:54 +0100 | [diff] [blame] | 155 | ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */ |
| 156 | ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 30, 1, 0), |
| 157 | ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 29, 1, 1), /* DIC */ |
| 158 | ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 28, 1, 1), /* IDC */ |
Will Deacon | 3c5dbb9 | 2019-08-05 18:13:55 +0100 | [diff] [blame] | 159 | ARM64_FTR_BITS(FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, 24, 4, 0), /* CWG */ |
| 160 | ARM64_FTR_BITS(FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, 20, 4, 0), /* ERG */ |
Suzuki K Poulose | a683009 | 2018-07-04 23:07:45 +0100 | [diff] [blame] | 161 | ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, CTR_DMINLINE_SHIFT, 4, 1), |
Suzuki K. Poulose | 3c739b5 | 2015-10-19 14:24:45 +0100 | [diff] [blame] | 162 | /* |
| 163 | * Linux can handle differing I-cache policies. Userspace JITs will |
Suzuki K Poulose | ee7bc63 | 2016-09-09 14:07:08 +0100 | [diff] [blame] | 164 | * make use of *minLine. |
| 165 | * If we have differing I-cache policies, report it as the weakest - AIVIVT. |
Suzuki K. Poulose | 3c739b5 | 2015-10-19 14:24:45 +0100 | [diff] [blame] | 166 | */ |
Suzuki K Poulose | ee7bc63 | 2016-09-09 14:07:08 +0100 | [diff] [blame] | 167 | ARM64_FTR_BITS(FTR_NONSTRICT, FTR_EXACT, 14, 2, ICACHE_POLICY_AIVIVT), /* L1Ip */ |
Suzuki K. Poulose | 3c739b5 | 2015-10-19 14:24:45 +0100 | [diff] [blame] | 168 | ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 10, 0), /* RAZ */ |
Suzuki K Poulose | a683009 | 2018-07-04 23:07:45 +0100 | [diff] [blame] | 169 | ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, CTR_IMINLINE_SHIFT, 4, 0), |
Suzuki K. Poulose | 3c739b5 | 2015-10-19 14:24:45 +0100 | [diff] [blame] | 170 | ARM64_FTR_END, |
| 171 | }; |
| 172 | |
Ard Biesheuvel | 675b056 | 2016-08-31 11:31:10 +0100 | [diff] [blame] | 173 | struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = { |
| 174 | .name = "SYS_CTR_EL0", |
| 175 | .ftr_bits = ftr_ctr |
| 176 | }; |
| 177 | |
Ard Biesheuvel | 5e49d73 | 2016-08-31 11:31:08 +0100 | [diff] [blame] | 178 | static const struct arm64_ftr_bits ftr_id_mmfr0[] = { |
Suzuki K Poulose | 0710cfd | 2016-01-26 10:58:14 +0000 | [diff] [blame] | 179 | S_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 28, 4, 0xf), /* InnerShr */ |
Suzuki K. Poulose | 3c739b5 | 2015-10-19 14:24:45 +0100 | [diff] [blame] | 180 | ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 24, 4, 0), /* FCSE */ |
| 181 | ARM64_FTR_BITS(FTR_NONSTRICT, FTR_LOWER_SAFE, 20, 4, 0), /* AuxReg */ |
| 182 | ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 16, 4, 0), /* TCM */ |
| 183 | ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 12, 4, 0), /* ShareLvl */ |
Suzuki K Poulose | 0710cfd | 2016-01-26 10:58:14 +0000 | [diff] [blame] | 184 | S_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 4, 0xf), /* OuterShr */ |
Suzuki K. Poulose | 3c739b5 | 2015-10-19 14:24:45 +0100 | [diff] [blame] | 185 | ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0), /* PMSA */ |
| 186 | ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0), /* VMSA */ |
| 187 | ARM64_FTR_END, |
| 188 | }; |
| 189 | |
Ard Biesheuvel | 5e49d73 | 2016-08-31 11:31:08 +0100 | [diff] [blame] | 190 | static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = { |
Suzuki K. Poulose | 3c739b5 | 2015-10-19 14:24:45 +0100 | [diff] [blame] | 191 | ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0), |
Suzuki K Poulose | 0710cfd | 2016-01-26 10:58:14 +0000 | [diff] [blame] | 192 | ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0), |
| 193 | ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0), |
| 194 | ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0), |
| 195 | S_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0), |
| 196 | ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64DFR0_TRACEVER_SHIFT, 4, 0), |
| 197 | ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6), |
Suzuki K. Poulose | 3c739b5 | 2015-10-19 14:24:45 +0100 | [diff] [blame] | 198 | ARM64_FTR_END, |
| 199 | }; |
| 200 | |
Ard Biesheuvel | 5e49d73 | 2016-08-31 11:31:08 +0100 | [diff] [blame] | 201 | static const struct arm64_ftr_bits ftr_mvfr2[] = { |
Suzuki K. Poulose | 3c739b5 | 2015-10-19 14:24:45 +0100 | [diff] [blame] | 202 | ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 24, 0), /* RAZ */ |
| 203 | ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0), /* FPMisc */ |
| 204 | ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0), /* SIMDMisc */ |
| 205 | ARM64_FTR_END, |
| 206 | }; |
| 207 | |
Ard Biesheuvel | 5e49d73 | 2016-08-31 11:31:08 +0100 | [diff] [blame] | 208 | static const struct arm64_ftr_bits ftr_dczid[] = { |
Suzuki K. Poulose | 3c739b5 | 2015-10-19 14:24:45 +0100 | [diff] [blame] | 209 | ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 5, 27, 0), /* RAZ */ |
| 210 | ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 1, 1), /* DZP */ |
| 211 | ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* BS */ |
| 212 | ARM64_FTR_END, |
| 213 | }; |
| 214 | |
| 215 | |
Ard Biesheuvel | 5e49d73 | 2016-08-31 11:31:08 +0100 | [diff] [blame] | 216 | static const struct arm64_ftr_bits ftr_id_isar5[] = { |
Suzuki K. Poulose | 3c739b5 | 2015-10-19 14:24:45 +0100 | [diff] [blame] | 217 | ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_RDM_SHIFT, 4, 0), |
| 218 | ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 20, 4, 0), /* RAZ */ |
| 219 | ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_CRC32_SHIFT, 4, 0), |
| 220 | ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_SHA2_SHIFT, 4, 0), |
| 221 | ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_SHA1_SHIFT, 4, 0), |
| 222 | ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_AES_SHIFT, 4, 0), |
| 223 | ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_SEVL_SHIFT, 4, 0), |
| 224 | ARM64_FTR_END, |
| 225 | }; |
| 226 | |
Ard Biesheuvel | 5e49d73 | 2016-08-31 11:31:08 +0100 | [diff] [blame] | 227 | static const struct arm64_ftr_bits ftr_id_mmfr4[] = { |
Suzuki K. Poulose | 3c739b5 | 2015-10-19 14:24:45 +0100 | [diff] [blame] | 228 | ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 24, 0), /* RAZ */ |
| 229 | ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0), /* ac2 */ |
| 230 | ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0), /* RAZ */ |
| 231 | ARM64_FTR_END, |
| 232 | }; |
| 233 | |
Ard Biesheuvel | 5e49d73 | 2016-08-31 11:31:08 +0100 | [diff] [blame] | 234 | static const struct arm64_ftr_bits ftr_id_pfr0[] = { |
Suzuki K. Poulose | 3c739b5 | 2015-10-19 14:24:45 +0100 | [diff] [blame] | 235 | ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 16, 16, 0), /* RAZ */ |
| 236 | ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 12, 4, 0), /* State3 */ |
| 237 | ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 4, 0), /* State2 */ |
| 238 | ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0), /* State1 */ |
| 239 | ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0), /* State0 */ |
| 240 | ARM64_FTR_END, |
| 241 | }; |
| 242 | |
Ard Biesheuvel | 5e49d73 | 2016-08-31 11:31:08 +0100 | [diff] [blame] | 243 | static const struct arm64_ftr_bits ftr_id_dfr0[] = { |
Suzuki K Poulose | e534350 | 2016-01-26 10:58:13 +0000 | [diff] [blame] | 244 | ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0), |
Suzuki K Poulose | 0710cfd | 2016-01-26 10:58:14 +0000 | [diff] [blame] | 245 | S_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0xf), /* PerfMon */ |
Suzuki K Poulose | e534350 | 2016-01-26 10:58:13 +0000 | [diff] [blame] | 246 | ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), |
| 247 | ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0), |
| 248 | ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), |
| 249 | ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0), |
| 250 | ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), |
| 251 | ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), |
| 252 | ARM64_FTR_END, |
| 253 | }; |
| 254 | |
Suzuki K. Poulose | 3c739b5 | 2015-10-19 14:24:45 +0100 | [diff] [blame] | 255 | /* |
| 256 | * Common ftr bits for a 32bit register with all hidden, strict |
| 257 | * attributes, with 4bit feature fields and a default safe value of |
| 258 | * 0. Covers the following 32bit registers: |
| 259 | * id_isar[0-4], id_mmfr[1-3], id_pfr1, mvfr[0-1] |
| 260 | */ |
Ard Biesheuvel | 5e49d73 | 2016-08-31 11:31:08 +0100 | [diff] [blame] | 261 | static const struct arm64_ftr_bits ftr_generic_32bits[] = { |
Suzuki K. Poulose | 3c739b5 | 2015-10-19 14:24:45 +0100 | [diff] [blame] | 262 | ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0), |
| 263 | ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0), |
| 264 | ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), |
| 265 | ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0), |
| 266 | ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), |
| 267 | ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0), |
| 268 | ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), |
| 269 | ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), |
| 270 | ARM64_FTR_END, |
| 271 | }; |
| 272 | |
Ard Biesheuvel | 5e49d73 | 2016-08-31 11:31:08 +0100 | [diff] [blame] | 273 | static const struct arm64_ftr_bits ftr_generic[] = { |
Suzuki K. Poulose | 3c739b5 | 2015-10-19 14:24:45 +0100 | [diff] [blame] | 274 | ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 64, 0), |
| 275 | ARM64_FTR_END, |
| 276 | }; |
| 277 | |
Ard Biesheuvel | 5e49d73 | 2016-08-31 11:31:08 +0100 | [diff] [blame] | 278 | static const struct arm64_ftr_bits ftr_generic32[] = { |
Suzuki K. Poulose | 3c739b5 | 2015-10-19 14:24:45 +0100 | [diff] [blame] | 279 | ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 32, 0), |
| 280 | ARM64_FTR_END, |
| 281 | }; |
| 282 | |
Ard Biesheuvel | 5e49d73 | 2016-08-31 11:31:08 +0100 | [diff] [blame] | 283 | static const struct arm64_ftr_bits ftr_aa64raz[] = { |
Suzuki K. Poulose | 3c739b5 | 2015-10-19 14:24:45 +0100 | [diff] [blame] | 284 | ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 64, 0), |
| 285 | ARM64_FTR_END, |
| 286 | }; |
| 287 | |
Ard Biesheuvel | 6f2b7ee | 2016-08-31 11:31:09 +0100 | [diff] [blame] | 288 | #define ARM64_FTR_REG(id, table) { \ |
| 289 | .sys_id = id, \ |
| 290 | .reg = &(struct arm64_ftr_reg){ \ |
Suzuki K. Poulose | 3c739b5 | 2015-10-19 14:24:45 +0100 | [diff] [blame] | 291 | .name = #id, \ |
| 292 | .ftr_bits = &((table)[0]), \ |
Ard Biesheuvel | 6f2b7ee | 2016-08-31 11:31:09 +0100 | [diff] [blame] | 293 | }} |
Suzuki K. Poulose | 3c739b5 | 2015-10-19 14:24:45 +0100 | [diff] [blame] | 294 | |
Ard Biesheuvel | 6f2b7ee | 2016-08-31 11:31:09 +0100 | [diff] [blame] | 295 | static const struct __ftr_reg_entry { |
| 296 | u32 sys_id; |
| 297 | struct arm64_ftr_reg *reg; |
| 298 | } arm64_ftr_regs[] = { |
Suzuki K. Poulose | 3c739b5 | 2015-10-19 14:24:45 +0100 | [diff] [blame] | 299 | |
| 300 | /* Op1 = 0, CRn = 0, CRm = 1 */ |
| 301 | ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0), |
| 302 | ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_generic_32bits), |
Suzuki K Poulose | e534350 | 2016-01-26 10:58:13 +0000 | [diff] [blame] | 303 | ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0), |
Suzuki K. Poulose | 3c739b5 | 2015-10-19 14:24:45 +0100 | [diff] [blame] | 304 | ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0), |
| 305 | ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits), |
| 306 | ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits), |
| 307 | ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits), |
| 308 | |
| 309 | /* Op1 = 0, CRn = 0, CRm = 2 */ |
| 310 | ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_generic_32bits), |
| 311 | ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits), |
| 312 | ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits), |
| 313 | ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits), |
| 314 | ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_generic_32bits), |
| 315 | ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5), |
| 316 | ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4), |
| 317 | |
| 318 | /* Op1 = 0, CRn = 0, CRm = 3 */ |
| 319 | ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits), |
| 320 | ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits), |
| 321 | ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2), |
| 322 | |
| 323 | /* Op1 = 0, CRn = 0, CRm = 4 */ |
| 324 | ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0), |
| 325 | ARM64_FTR_REG(SYS_ID_AA64PFR1_EL1, ftr_aa64raz), |
| 326 | |
| 327 | /* Op1 = 0, CRn = 0, CRm = 5 */ |
| 328 | ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0), |
| 329 | ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_generic), |
| 330 | |
| 331 | /* Op1 = 0, CRn = 0, CRm = 6 */ |
| 332 | ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0), |
| 333 | ARM64_FTR_REG(SYS_ID_AA64ISAR1_EL1, ftr_aa64raz), |
| 334 | |
| 335 | /* Op1 = 0, CRn = 0, CRm = 7 */ |
| 336 | ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0), |
| 337 | ARM64_FTR_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1), |
James Morse | 406e308 | 2016-02-05 14:58:47 +0000 | [diff] [blame] | 338 | ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2), |
Suzuki K. Poulose | 3c739b5 | 2015-10-19 14:24:45 +0100 | [diff] [blame] | 339 | |
| 340 | /* Op1 = 3, CRn = 0, CRm = 0 */ |
Ard Biesheuvel | 675b056 | 2016-08-31 11:31:10 +0100 | [diff] [blame] | 341 | { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 }, |
Suzuki K. Poulose | 3c739b5 | 2015-10-19 14:24:45 +0100 | [diff] [blame] | 342 | ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid), |
| 343 | |
| 344 | /* Op1 = 3, CRn = 14, CRm = 0 */ |
| 345 | ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_generic32), |
| 346 | }; |
| 347 | |
| 348 | static int search_cmp_ftr_reg(const void *id, const void *regp) |
| 349 | { |
Ard Biesheuvel | 6f2b7ee | 2016-08-31 11:31:09 +0100 | [diff] [blame] | 350 | return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id; |
Suzuki K. Poulose | 3c739b5 | 2015-10-19 14:24:45 +0100 | [diff] [blame] | 351 | } |
| 352 | |
| 353 | /* |
| 354 | * get_arm64_ftr_reg - Lookup a feature register entry using its |
| 355 | * sys_reg() encoding. With the array arm64_ftr_regs sorted in the |
| 356 | * ascending order of sys_id , we use binary search to find a matching |
| 357 | * entry. |
| 358 | * |
| 359 | * returns - Upon success, matching ftr_reg entry for id. |
| 360 | * - NULL on failure. It is upto the caller to decide |
| 361 | * the impact of a failure. |
| 362 | */ |
| 363 | static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id) |
| 364 | { |
Ard Biesheuvel | 6f2b7ee | 2016-08-31 11:31:09 +0100 | [diff] [blame] | 365 | const struct __ftr_reg_entry *ret; |
| 366 | |
| 367 | ret = bsearch((const void *)(unsigned long)sys_id, |
Suzuki K. Poulose | 3c739b5 | 2015-10-19 14:24:45 +0100 | [diff] [blame] | 368 | arm64_ftr_regs, |
| 369 | ARRAY_SIZE(arm64_ftr_regs), |
| 370 | sizeof(arm64_ftr_regs[0]), |
| 371 | search_cmp_ftr_reg); |
Ard Biesheuvel | 6f2b7ee | 2016-08-31 11:31:09 +0100 | [diff] [blame] | 372 | if (ret) |
| 373 | return ret->reg; |
| 374 | return NULL; |
Suzuki K. Poulose | 3c739b5 | 2015-10-19 14:24:45 +0100 | [diff] [blame] | 375 | } |
| 376 | |
Ard Biesheuvel | 5e49d73 | 2016-08-31 11:31:08 +0100 | [diff] [blame] | 377 | static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg, |
| 378 | s64 ftr_val) |
Suzuki K. Poulose | 3c739b5 | 2015-10-19 14:24:45 +0100 | [diff] [blame] | 379 | { |
| 380 | u64 mask = arm64_ftr_mask(ftrp); |
| 381 | |
| 382 | reg &= ~mask; |
| 383 | reg |= (ftr_val << ftrp->shift) & mask; |
| 384 | return reg; |
| 385 | } |
| 386 | |
Ard Biesheuvel | 5e49d73 | 2016-08-31 11:31:08 +0100 | [diff] [blame] | 387 | static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new, |
| 388 | s64 cur) |
Suzuki K. Poulose | 3c739b5 | 2015-10-19 14:24:45 +0100 | [diff] [blame] | 389 | { |
| 390 | s64 ret = 0; |
| 391 | |
| 392 | switch (ftrp->type) { |
| 393 | case FTR_EXACT: |
| 394 | ret = ftrp->safe_val; |
| 395 | break; |
| 396 | case FTR_LOWER_SAFE: |
| 397 | ret = new < cur ? new : cur; |
| 398 | break; |
Will Deacon | 3c5dbb9 | 2019-08-05 18:13:55 +0100 | [diff] [blame] | 399 | case FTR_HIGHER_OR_ZERO_SAFE: |
| 400 | if (!cur || !new) |
| 401 | break; |
| 402 | /* Fallthrough */ |
Suzuki K. Poulose | 3c739b5 | 2015-10-19 14:24:45 +0100 | [diff] [blame] | 403 | case FTR_HIGHER_SAFE: |
| 404 | ret = new > cur ? new : cur; |
| 405 | break; |
| 406 | default: |
| 407 | BUG(); |
| 408 | } |
| 409 | |
| 410 | return ret; |
| 411 | } |
| 412 | |
Suzuki K. Poulose | 3c739b5 | 2015-10-19 14:24:45 +0100 | [diff] [blame] | 413 | static void __init sort_ftr_regs(void) |
| 414 | { |
Ard Biesheuvel | 6f2b7ee | 2016-08-31 11:31:09 +0100 | [diff] [blame] | 415 | int i; |
| 416 | |
| 417 | /* Check that the array is sorted so that we can do the binary search */ |
| 418 | for (i = 1; i < ARRAY_SIZE(arm64_ftr_regs); i++) |
| 419 | BUG_ON(arm64_ftr_regs[i].sys_id < arm64_ftr_regs[i - 1].sys_id); |
Suzuki K. Poulose | 3c739b5 | 2015-10-19 14:24:45 +0100 | [diff] [blame] | 420 | } |
| 421 | |
| 422 | /* |
| 423 | * Initialise the CPU feature register from Boot CPU values. |
| 424 | * Also initiliases the strict_mask for the register. |
| 425 | */ |
| 426 | static void __init init_cpu_ftr_reg(u32 sys_reg, u64 new) |
| 427 | { |
| 428 | u64 val = 0; |
| 429 | u64 strict_mask = ~0x0ULL; |
Ard Biesheuvel | 5e49d73 | 2016-08-31 11:31:08 +0100 | [diff] [blame] | 430 | const struct arm64_ftr_bits *ftrp; |
Suzuki K. Poulose | 3c739b5 | 2015-10-19 14:24:45 +0100 | [diff] [blame] | 431 | struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg); |
| 432 | |
| 433 | BUG_ON(!reg); |
| 434 | |
| 435 | for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { |
| 436 | s64 ftr_new = arm64_ftr_value(ftrp, new); |
| 437 | |
| 438 | val = arm64_ftr_set_value(ftrp, val, ftr_new); |
| 439 | if (!ftrp->strict) |
| 440 | strict_mask &= ~arm64_ftr_mask(ftrp); |
| 441 | } |
| 442 | reg->sys_val = val; |
| 443 | reg->strict_mask = strict_mask; |
| 444 | } |
| 445 | |
| 446 | void __init init_cpu_features(struct cpuinfo_arm64 *info) |
| 447 | { |
| 448 | /* Before we start using the tables, make sure it is sorted */ |
| 449 | sort_ftr_regs(); |
| 450 | |
| 451 | init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr); |
| 452 | init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid); |
| 453 | init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq); |
| 454 | init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0); |
| 455 | init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1); |
| 456 | init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0); |
| 457 | init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1); |
| 458 | init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0); |
| 459 | init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1); |
James Morse | 406e308 | 2016-02-05 14:58:47 +0000 | [diff] [blame] | 460 | init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2); |
Suzuki K. Poulose | 3c739b5 | 2015-10-19 14:24:45 +0100 | [diff] [blame] | 461 | init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0); |
| 462 | init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1); |
Suzuki K Poulose | a6dc3cd | 2016-04-18 10:28:35 +0100 | [diff] [blame] | 463 | |
| 464 | if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) { |
| 465 | init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0); |
| 466 | init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0); |
| 467 | init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1); |
| 468 | init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2); |
| 469 | init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3); |
| 470 | init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4); |
| 471 | init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5); |
| 472 | init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0); |
| 473 | init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1); |
| 474 | init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2); |
| 475 | init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3); |
| 476 | init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0); |
| 477 | init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1); |
| 478 | init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0); |
| 479 | init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1); |
| 480 | init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2); |
| 481 | } |
| 482 | |
Suzuki K. Poulose | 3c739b5 | 2015-10-19 14:24:45 +0100 | [diff] [blame] | 483 | } |
| 484 | |
Suzuki K. Poulose | 3086d39 | 2015-10-19 14:24:46 +0100 | [diff] [blame] | 485 | static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new) |
Suzuki K. Poulose | 3c739b5 | 2015-10-19 14:24:45 +0100 | [diff] [blame] | 486 | { |
Ard Biesheuvel | 5e49d73 | 2016-08-31 11:31:08 +0100 | [diff] [blame] | 487 | const struct arm64_ftr_bits *ftrp; |
Suzuki K. Poulose | 3c739b5 | 2015-10-19 14:24:45 +0100 | [diff] [blame] | 488 | |
| 489 | for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { |
| 490 | s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val); |
| 491 | s64 ftr_new = arm64_ftr_value(ftrp, new); |
| 492 | |
| 493 | if (ftr_cur == ftr_new) |
| 494 | continue; |
| 495 | /* Find a safe value */ |
| 496 | ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur); |
| 497 | reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new); |
| 498 | } |
| 499 | |
| 500 | } |
| 501 | |
Suzuki K. Poulose | 3086d39 | 2015-10-19 14:24:46 +0100 | [diff] [blame] | 502 | static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot) |
Suzuki K. Poulose | cdcf817 | 2015-10-19 14:24:42 +0100 | [diff] [blame] | 503 | { |
Suzuki K. Poulose | 3086d39 | 2015-10-19 14:24:46 +0100 | [diff] [blame] | 504 | struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id); |
| 505 | |
| 506 | BUG_ON(!regp); |
| 507 | update_cpu_ftr_reg(regp, val); |
| 508 | if ((boot & regp->strict_mask) == (val & regp->strict_mask)) |
| 509 | return 0; |
| 510 | pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n", |
| 511 | regp->name, boot, cpu, val); |
| 512 | return 1; |
| 513 | } |
| 514 | |
| 515 | /* |
| 516 | * Update system wide CPU feature registers with the values from a |
| 517 | * non-boot CPU. Also performs SANITY checks to make sure that there |
| 518 | * aren't any insane variations from that of the boot CPU. |
| 519 | */ |
| 520 | void update_cpu_features(int cpu, |
| 521 | struct cpuinfo_arm64 *info, |
| 522 | struct cpuinfo_arm64 *boot) |
| 523 | { |
| 524 | int taint = 0; |
| 525 | |
| 526 | /* |
| 527 | * The kernel can handle differing I-cache policies, but otherwise |
| 528 | * caches should look identical. Userspace JITs will make use of |
| 529 | * *minLine. |
| 530 | */ |
| 531 | taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu, |
| 532 | info->reg_ctr, boot->reg_ctr); |
| 533 | |
| 534 | /* |
| 535 | * Userspace may perform DC ZVA instructions. Mismatched block sizes |
| 536 | * could result in too much or too little memory being zeroed if a |
| 537 | * process is preempted and migrated between CPUs. |
| 538 | */ |
| 539 | taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu, |
| 540 | info->reg_dczid, boot->reg_dczid); |
| 541 | |
| 542 | /* If different, timekeeping will be broken (especially with KVM) */ |
| 543 | taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu, |
| 544 | info->reg_cntfrq, boot->reg_cntfrq); |
| 545 | |
| 546 | /* |
| 547 | * The kernel uses self-hosted debug features and expects CPUs to |
| 548 | * support identical debug features. We presently need CTX_CMPs, WRPs, |
| 549 | * and BRPs to be identical. |
| 550 | * ID_AA64DFR1 is currently RES0. |
| 551 | */ |
| 552 | taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu, |
| 553 | info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0); |
| 554 | taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu, |
| 555 | info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1); |
| 556 | /* |
| 557 | * Even in big.LITTLE, processors should be identical instruction-set |
| 558 | * wise. |
| 559 | */ |
| 560 | taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu, |
| 561 | info->reg_id_aa64isar0, boot->reg_id_aa64isar0); |
| 562 | taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu, |
| 563 | info->reg_id_aa64isar1, boot->reg_id_aa64isar1); |
| 564 | |
| 565 | /* |
| 566 | * Differing PARange support is fine as long as all peripherals and |
| 567 | * memory are mapped within the minimum PARange of all CPUs. |
| 568 | * Linux should not care about secure memory. |
| 569 | */ |
| 570 | taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu, |
| 571 | info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0); |
| 572 | taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu, |
| 573 | info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1); |
James Morse | 406e308 | 2016-02-05 14:58:47 +0000 | [diff] [blame] | 574 | taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu, |
| 575 | info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2); |
Suzuki K. Poulose | 3086d39 | 2015-10-19 14:24:46 +0100 | [diff] [blame] | 576 | |
| 577 | /* |
| 578 | * EL3 is not our concern. |
| 579 | * ID_AA64PFR1 is currently RES0. |
| 580 | */ |
| 581 | taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu, |
| 582 | info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0); |
| 583 | taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu, |
| 584 | info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1); |
| 585 | |
| 586 | /* |
Suzuki K Poulose | a6dc3cd | 2016-04-18 10:28:35 +0100 | [diff] [blame] | 587 | * If we have AArch32, we care about 32-bit features for compat. |
| 588 | * If the system doesn't support AArch32, don't update them. |
Suzuki K. Poulose | 3086d39 | 2015-10-19 14:24:46 +0100 | [diff] [blame] | 589 | */ |
Suzuki K Poulose | a6dc3cd | 2016-04-18 10:28:35 +0100 | [diff] [blame] | 590 | if (id_aa64pfr0_32bit_el0(read_system_reg(SYS_ID_AA64PFR0_EL1)) && |
| 591 | id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) { |
| 592 | |
| 593 | taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu, |
Suzuki K. Poulose | 3086d39 | 2015-10-19 14:24:46 +0100 | [diff] [blame] | 594 | info->reg_id_dfr0, boot->reg_id_dfr0); |
Suzuki K Poulose | a6dc3cd | 2016-04-18 10:28:35 +0100 | [diff] [blame] | 595 | taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu, |
Suzuki K. Poulose | 3086d39 | 2015-10-19 14:24:46 +0100 | [diff] [blame] | 596 | info->reg_id_isar0, boot->reg_id_isar0); |
Suzuki K Poulose | a6dc3cd | 2016-04-18 10:28:35 +0100 | [diff] [blame] | 597 | taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu, |
Suzuki K. Poulose | 3086d39 | 2015-10-19 14:24:46 +0100 | [diff] [blame] | 598 | info->reg_id_isar1, boot->reg_id_isar1); |
Suzuki K Poulose | a6dc3cd | 2016-04-18 10:28:35 +0100 | [diff] [blame] | 599 | taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu, |
Suzuki K. Poulose | 3086d39 | 2015-10-19 14:24:46 +0100 | [diff] [blame] | 600 | info->reg_id_isar2, boot->reg_id_isar2); |
Suzuki K Poulose | a6dc3cd | 2016-04-18 10:28:35 +0100 | [diff] [blame] | 601 | taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu, |
Suzuki K. Poulose | 3086d39 | 2015-10-19 14:24:46 +0100 | [diff] [blame] | 602 | info->reg_id_isar3, boot->reg_id_isar3); |
Suzuki K Poulose | a6dc3cd | 2016-04-18 10:28:35 +0100 | [diff] [blame] | 603 | taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu, |
Suzuki K. Poulose | 3086d39 | 2015-10-19 14:24:46 +0100 | [diff] [blame] | 604 | info->reg_id_isar4, boot->reg_id_isar4); |
Suzuki K Poulose | a6dc3cd | 2016-04-18 10:28:35 +0100 | [diff] [blame] | 605 | taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu, |
Suzuki K. Poulose | 3086d39 | 2015-10-19 14:24:46 +0100 | [diff] [blame] | 606 | info->reg_id_isar5, boot->reg_id_isar5); |
| 607 | |
Suzuki K Poulose | a6dc3cd | 2016-04-18 10:28:35 +0100 | [diff] [blame] | 608 | /* |
| 609 | * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and |
| 610 | * ACTLR formats could differ across CPUs and therefore would have to |
| 611 | * be trapped for virtualization anyway. |
| 612 | */ |
| 613 | taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu, |
Suzuki K. Poulose | 3086d39 | 2015-10-19 14:24:46 +0100 | [diff] [blame] | 614 | info->reg_id_mmfr0, boot->reg_id_mmfr0); |
Suzuki K Poulose | a6dc3cd | 2016-04-18 10:28:35 +0100 | [diff] [blame] | 615 | taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu, |
Suzuki K. Poulose | 3086d39 | 2015-10-19 14:24:46 +0100 | [diff] [blame] | 616 | info->reg_id_mmfr1, boot->reg_id_mmfr1); |
Suzuki K Poulose | a6dc3cd | 2016-04-18 10:28:35 +0100 | [diff] [blame] | 617 | taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu, |
Suzuki K. Poulose | 3086d39 | 2015-10-19 14:24:46 +0100 | [diff] [blame] | 618 | info->reg_id_mmfr2, boot->reg_id_mmfr2); |
Suzuki K Poulose | a6dc3cd | 2016-04-18 10:28:35 +0100 | [diff] [blame] | 619 | taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu, |
Suzuki K. Poulose | 3086d39 | 2015-10-19 14:24:46 +0100 | [diff] [blame] | 620 | info->reg_id_mmfr3, boot->reg_id_mmfr3); |
Suzuki K Poulose | a6dc3cd | 2016-04-18 10:28:35 +0100 | [diff] [blame] | 621 | taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu, |
Suzuki K. Poulose | 3086d39 | 2015-10-19 14:24:46 +0100 | [diff] [blame] | 622 | info->reg_id_pfr0, boot->reg_id_pfr0); |
Suzuki K Poulose | a6dc3cd | 2016-04-18 10:28:35 +0100 | [diff] [blame] | 623 | taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu, |
Suzuki K. Poulose | 3086d39 | 2015-10-19 14:24:46 +0100 | [diff] [blame] | 624 | info->reg_id_pfr1, boot->reg_id_pfr1); |
Suzuki K Poulose | a6dc3cd | 2016-04-18 10:28:35 +0100 | [diff] [blame] | 625 | taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu, |
Suzuki K. Poulose | 3086d39 | 2015-10-19 14:24:46 +0100 | [diff] [blame] | 626 | info->reg_mvfr0, boot->reg_mvfr0); |
Suzuki K Poulose | a6dc3cd | 2016-04-18 10:28:35 +0100 | [diff] [blame] | 627 | taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu, |
Suzuki K. Poulose | 3086d39 | 2015-10-19 14:24:46 +0100 | [diff] [blame] | 628 | info->reg_mvfr1, boot->reg_mvfr1); |
Suzuki K Poulose | a6dc3cd | 2016-04-18 10:28:35 +0100 | [diff] [blame] | 629 | taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu, |
Suzuki K. Poulose | 3086d39 | 2015-10-19 14:24:46 +0100 | [diff] [blame] | 630 | info->reg_mvfr2, boot->reg_mvfr2); |
Suzuki K Poulose | a6dc3cd | 2016-04-18 10:28:35 +0100 | [diff] [blame] | 631 | } |
Suzuki K. Poulose | 3086d39 | 2015-10-19 14:24:46 +0100 | [diff] [blame] | 632 | |
| 633 | /* |
| 634 | * Mismatched CPU features are a recipe for disaster. Don't even |
| 635 | * pretend to support them. |
| 636 | */ |
| 637 | WARN_TAINT_ONCE(taint, TAINT_CPU_OUT_OF_SPEC, |
| 638 | "Unsupported CPU feature variation.\n"); |
Suzuki K. Poulose | cdcf817 | 2015-10-19 14:24:42 +0100 | [diff] [blame] | 639 | } |
| 640 | |
Suzuki K. Poulose | b3f1537 | 2015-10-19 14:24:47 +0100 | [diff] [blame] | 641 | u64 read_system_reg(u32 id) |
| 642 | { |
| 643 | struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id); |
| 644 | |
| 645 | /* We shouldn't get a request for an unsupported register */ |
| 646 | BUG_ON(!regp); |
| 647 | return regp->sys_val; |
| 648 | } |
Marc Zyngier | 359b706 | 2015-03-27 13:09:23 +0000 | [diff] [blame] | 649 | |
Suzuki K Poulose | 92406f0 | 2016-04-22 12:25:31 +0100 | [diff] [blame] | 650 | /* |
| 651 | * __raw_read_system_reg() - Used by a STARTING cpu before cpuinfo is populated. |
| 652 | * Read the system register on the current CPU |
| 653 | */ |
| 654 | static u64 __raw_read_system_reg(u32 sys_id) |
| 655 | { |
| 656 | switch (sys_id) { |
| 657 | case SYS_ID_PFR0_EL1: return read_cpuid(ID_PFR0_EL1); |
| 658 | case SYS_ID_PFR1_EL1: return read_cpuid(ID_PFR1_EL1); |
| 659 | case SYS_ID_DFR0_EL1: return read_cpuid(ID_DFR0_EL1); |
| 660 | case SYS_ID_MMFR0_EL1: return read_cpuid(ID_MMFR0_EL1); |
| 661 | case SYS_ID_MMFR1_EL1: return read_cpuid(ID_MMFR1_EL1); |
| 662 | case SYS_ID_MMFR2_EL1: return read_cpuid(ID_MMFR2_EL1); |
| 663 | case SYS_ID_MMFR3_EL1: return read_cpuid(ID_MMFR3_EL1); |
| 664 | case SYS_ID_ISAR0_EL1: return read_cpuid(ID_ISAR0_EL1); |
| 665 | case SYS_ID_ISAR1_EL1: return read_cpuid(ID_ISAR1_EL1); |
| 666 | case SYS_ID_ISAR2_EL1: return read_cpuid(ID_ISAR2_EL1); |
| 667 | case SYS_ID_ISAR3_EL1: return read_cpuid(ID_ISAR3_EL1); |
| 668 | case SYS_ID_ISAR4_EL1: return read_cpuid(ID_ISAR4_EL1); |
Mark Rutland | 7127d43 | 2017-02-02 17:32:14 +0000 | [diff] [blame] | 669 | case SYS_ID_ISAR5_EL1: return read_cpuid(ID_ISAR5_EL1); |
Suzuki K Poulose | 92406f0 | 2016-04-22 12:25:31 +0100 | [diff] [blame] | 670 | case SYS_MVFR0_EL1: return read_cpuid(MVFR0_EL1); |
| 671 | case SYS_MVFR1_EL1: return read_cpuid(MVFR1_EL1); |
| 672 | case SYS_MVFR2_EL1: return read_cpuid(MVFR2_EL1); |
| 673 | |
| 674 | case SYS_ID_AA64PFR0_EL1: return read_cpuid(ID_AA64PFR0_EL1); |
Mark Rutland | 7127d43 | 2017-02-02 17:32:14 +0000 | [diff] [blame] | 675 | case SYS_ID_AA64PFR1_EL1: return read_cpuid(ID_AA64PFR1_EL1); |
Suzuki K Poulose | 92406f0 | 2016-04-22 12:25:31 +0100 | [diff] [blame] | 676 | case SYS_ID_AA64DFR0_EL1: return read_cpuid(ID_AA64DFR0_EL1); |
Mark Rutland | 7127d43 | 2017-02-02 17:32:14 +0000 | [diff] [blame] | 677 | case SYS_ID_AA64DFR1_EL1: return read_cpuid(ID_AA64DFR1_EL1); |
Suzuki K Poulose | 92406f0 | 2016-04-22 12:25:31 +0100 | [diff] [blame] | 678 | case SYS_ID_AA64MMFR0_EL1: return read_cpuid(ID_AA64MMFR0_EL1); |
| 679 | case SYS_ID_AA64MMFR1_EL1: return read_cpuid(ID_AA64MMFR1_EL1); |
| 680 | case SYS_ID_AA64MMFR2_EL1: return read_cpuid(ID_AA64MMFR2_EL1); |
| 681 | case SYS_ID_AA64ISAR0_EL1: return read_cpuid(ID_AA64ISAR0_EL1); |
| 682 | case SYS_ID_AA64ISAR1_EL1: return read_cpuid(ID_AA64ISAR1_EL1); |
| 683 | |
| 684 | case SYS_CNTFRQ_EL0: return read_cpuid(CNTFRQ_EL0); |
| 685 | case SYS_CTR_EL0: return read_cpuid(CTR_EL0); |
| 686 | case SYS_DCZID_EL0: return read_cpuid(DCZID_EL0); |
| 687 | default: |
| 688 | BUG(); |
| 689 | return 0; |
| 690 | } |
| 691 | } |
| 692 | |
Marc Zyngier | 963fcd4 | 2015-09-30 11:50:04 +0100 | [diff] [blame] | 693 | #include <linux/irqchip/arm-gic-v3.h> |
| 694 | |
Marc Zyngier | 94a9e04 | 2015-06-12 12:06:36 +0100 | [diff] [blame] | 695 | static bool |
James Morse | 18ffa04 | 2015-07-21 13:23:29 +0100 | [diff] [blame] | 696 | feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry) |
| 697 | { |
Suzuki K Poulose | 28c5dcb | 2016-01-26 10:58:16 +0000 | [diff] [blame] | 698 | int val = cpuid_feature_extract_field(reg, entry->field_pos, entry->sign); |
James Morse | 18ffa04 | 2015-07-21 13:23:29 +0100 | [diff] [blame] | 699 | |
| 700 | return val >= entry->min_field_value; |
| 701 | } |
| 702 | |
Suzuki K. Poulose | da8d02d | 2015-10-19 14:24:51 +0100 | [diff] [blame] | 703 | static bool |
Suzuki K Poulose | 92406f0 | 2016-04-22 12:25:31 +0100 | [diff] [blame] | 704 | has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope) |
Suzuki K. Poulose | da8d02d | 2015-10-19 14:24:51 +0100 | [diff] [blame] | 705 | { |
| 706 | u64 val; |
Marc Zyngier | 94a9e04 | 2015-06-12 12:06:36 +0100 | [diff] [blame] | 707 | |
Suzuki K Poulose | 92406f0 | 2016-04-22 12:25:31 +0100 | [diff] [blame] | 708 | WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); |
| 709 | if (scope == SCOPE_SYSTEM) |
| 710 | val = read_system_reg(entry->sys_reg); |
| 711 | else |
| 712 | val = __raw_read_system_reg(entry->sys_reg); |
| 713 | |
Suzuki K. Poulose | da8d02d | 2015-10-19 14:24:51 +0100 | [diff] [blame] | 714 | return feature_matches(val, entry); |
| 715 | } |
James Morse | 338d4f4 | 2015-07-22 19:05:54 +0100 | [diff] [blame] | 716 | |
Suzuki K Poulose | 92406f0 | 2016-04-22 12:25:31 +0100 | [diff] [blame] | 717 | static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope) |
Marc Zyngier | 963fcd4 | 2015-09-30 11:50:04 +0100 | [diff] [blame] | 718 | { |
| 719 | bool has_sre; |
| 720 | |
Suzuki K Poulose | 92406f0 | 2016-04-22 12:25:31 +0100 | [diff] [blame] | 721 | if (!has_cpuid_feature(entry, scope)) |
Marc Zyngier | 963fcd4 | 2015-09-30 11:50:04 +0100 | [diff] [blame] | 722 | return false; |
| 723 | |
| 724 | has_sre = gic_enable_sre(); |
| 725 | if (!has_sre) |
| 726 | pr_warn_once("%s present but disabled by higher exception level\n", |
| 727 | entry->desc); |
| 728 | |
| 729 | return has_sre; |
| 730 | } |
| 731 | |
Suzuki K Poulose | 92406f0 | 2016-04-22 12:25:31 +0100 | [diff] [blame] | 732 | static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry, int __unused) |
Will Deacon | d5370f7 | 2016-02-02 12:46:24 +0000 | [diff] [blame] | 733 | { |
| 734 | u32 midr = read_cpuid_id(); |
| 735 | u32 rv_min, rv_max; |
| 736 | |
| 737 | /* Cavium ThunderX pass 1.x and 2.x */ |
| 738 | rv_min = 0; |
| 739 | rv_max = (1 << MIDR_VARIANT_SHIFT) | MIDR_REVISION_MASK; |
| 740 | |
| 741 | return MIDR_IS_CPU_MODEL_RANGE(midr, MIDR_THUNDERX, rv_min, rv_max); |
| 742 | } |
| 743 | |
Suzuki K Poulose | 92406f0 | 2016-04-22 12:25:31 +0100 | [diff] [blame] | 744 | static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused) |
Marc Zyngier | d88701b | 2015-01-29 11:24:05 +0000 | [diff] [blame] | 745 | { |
| 746 | return is_kernel_in_hyp_mode(); |
| 747 | } |
| 748 | |
Marc Zyngier | d174591 | 2016-06-30 18:40:42 +0100 | [diff] [blame] | 749 | static bool hyp_offset_low(const struct arm64_cpu_capabilities *entry, |
| 750 | int __unused) |
| 751 | { |
Laura Abbott | f8fee94e | 2017-01-10 13:35:49 -0800 | [diff] [blame] | 752 | phys_addr_t idmap_addr = __pa_symbol(__hyp_idmap_text_start); |
Marc Zyngier | d174591 | 2016-06-30 18:40:42 +0100 | [diff] [blame] | 753 | |
| 754 | /* |
| 755 | * Activate the lower HYP offset only if: |
| 756 | * - the idmap doesn't clash with it, |
| 757 | * - the kernel is not running at EL2. |
| 758 | */ |
| 759 | return idmap_addr > GENMASK(VA_BITS - 2, 0) && !is_kernel_in_hyp_mode(); |
| 760 | } |
| 761 | |
Will Deacon | f79ff2d | 2017-11-14 14:38:19 +0000 | [diff] [blame] | 762 | #ifdef CONFIG_UNMAP_KERNEL_AT_EL0 |
| 763 | static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */ |
| 764 | |
| 765 | static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry, |
| 766 | int __unused) |
| 767 | { |
Marc Zyngier | da93510 | 2018-04-03 12:09:21 +0100 | [diff] [blame] | 768 | char const *str = "command line option"; |
Will Deacon | 7354772 | 2018-04-03 12:09:14 +0100 | [diff] [blame] | 769 | u64 pfr0 = read_system_reg(SYS_ID_AA64PFR0_EL1); |
| 770 | |
Marc Zyngier | da93510 | 2018-04-03 12:09:21 +0100 | [diff] [blame] | 771 | /* |
| 772 | * For reasons that aren't entirely clear, enabling KPTI on Cavium |
| 773 | * ThunderX leads to apparent I-cache corruption of kernel text, which |
| 774 | * ends as well as you might imagine. Don't even try. |
| 775 | */ |
Suzuki K Poulose | fe64d7d | 2016-11-08 13:56:20 +0000 | [diff] [blame] | 776 | if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_27456)) { |
Marc Zyngier | da93510 | 2018-04-03 12:09:21 +0100 | [diff] [blame] | 777 | str = "ARM64_WORKAROUND_CAVIUM_27456"; |
| 778 | __kpti_forced = -1; |
| 779 | } |
| 780 | |
| 781 | /* Forced? */ |
Will Deacon | f79ff2d | 2017-11-14 14:38:19 +0000 | [diff] [blame] | 782 | if (__kpti_forced) { |
Marc Zyngier | da93510 | 2018-04-03 12:09:21 +0100 | [diff] [blame] | 783 | pr_info_once("kernel page table isolation forced %s by %s\n", |
| 784 | __kpti_forced > 0 ? "ON" : "OFF", str); |
Will Deacon | f79ff2d | 2017-11-14 14:38:19 +0000 | [diff] [blame] | 785 | return __kpti_forced > 0; |
| 786 | } |
| 787 | |
| 788 | /* Useful for KASLR robustness */ |
| 789 | if (IS_ENABLED(CONFIG_RANDOMIZE_BASE)) |
| 790 | return true; |
| 791 | |
Jayachandran C | 2adcb1f | 2018-04-03 12:09:18 +0100 | [diff] [blame] | 792 | /* Don't force KPTI for CPUs that are not vulnerable */ |
| 793 | switch (read_cpuid_id() & MIDR_CPU_MODEL_MASK) { |
| 794 | case MIDR_CAVIUM_THUNDERX2: |
| 795 | case MIDR_BRCM_VULCAN: |
Will Deacon | 564907b | 2018-12-13 13:47:38 +0000 | [diff] [blame] | 796 | case MIDR_CORTEX_A53: |
| 797 | case MIDR_CORTEX_A55: |
| 798 | case MIDR_CORTEX_A57: |
| 799 | case MIDR_CORTEX_A72: |
| 800 | case MIDR_CORTEX_A73: |
Jayachandran C | 2adcb1f | 2018-04-03 12:09:18 +0100 | [diff] [blame] | 801 | return false; |
| 802 | } |
| 803 | |
Will Deacon | 7354772 | 2018-04-03 12:09:14 +0100 | [diff] [blame] | 804 | /* Defer to CPU feature registers */ |
| 805 | return !cpuid_feature_extract_unsigned_field(pfr0, |
| 806 | ID_AA64PFR0_CSV3_SHIFT); |
Will Deacon | bfca157 | 2018-04-03 12:09:09 +0100 | [diff] [blame] | 807 | } |
| 808 | |
Greg Hackmann | eba1ffe | 2018-04-09 13:48:49 -0700 | [diff] [blame] | 809 | static int __nocfi kpti_install_ng_mappings(void *__unused) |
Will Deacon | 4025fe1 | 2018-04-03 12:09:20 +0100 | [diff] [blame] | 810 | { |
| 811 | typedef void (kpti_remap_fn)(int, int, phys_addr_t); |
| 812 | extern kpti_remap_fn idmap_kpti_install_ng_mappings; |
| 813 | kpti_remap_fn *remap_fn; |
| 814 | |
| 815 | static bool kpti_applied = false; |
| 816 | int cpu = smp_processor_id(); |
| 817 | |
| 818 | if (kpti_applied) |
| 819 | return 0; |
| 820 | |
| 821 | remap_fn = (void *)__pa_symbol(idmap_kpti_install_ng_mappings); |
| 822 | |
| 823 | cpu_install_idmap(); |
| 824 | remap_fn(cpu, num_online_cpus(), __pa_symbol(swapper_pg_dir)); |
| 825 | cpu_uninstall_idmap(); |
| 826 | |
| 827 | if (!cpu) |
| 828 | kpti_applied = true; |
| 829 | |
| 830 | return 0; |
Will Deacon | f79ff2d | 2017-11-14 14:38:19 +0000 | [diff] [blame] | 831 | } |
| 832 | |
| 833 | static int __init parse_kpti(char *str) |
| 834 | { |
| 835 | bool enabled; |
| 836 | int ret = strtobool(str, &enabled); |
| 837 | |
| 838 | if (ret) |
| 839 | return ret; |
| 840 | |
| 841 | __kpti_forced = enabled ? 1 : -1; |
| 842 | return 0; |
| 843 | } |
Will Deacon | 12942d5 | 2018-06-22 10:25:25 +0100 | [diff] [blame] | 844 | early_param("kpti", parse_kpti); |
Will Deacon | f79ff2d | 2017-11-14 14:38:19 +0000 | [diff] [blame] | 845 | #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */ |
| 846 | |
James Morse | eea5902 | 2018-07-20 10:56:16 +0100 | [diff] [blame] | 847 | static int cpu_copy_el2regs(void *__unused) |
| 848 | { |
| 849 | /* |
| 850 | * Copy register values that aren't redirected by hardware. |
| 851 | * |
| 852 | * Before code patching, we only set tpidr_el1, all CPUs need to copy |
| 853 | * this value to tpidr_el2 before we patch the code. Once we've done |
| 854 | * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to |
| 855 | * do anything here. |
| 856 | */ |
| 857 | if (!alternatives_applied) |
| 858 | write_sysreg(read_sysreg(tpidr_el1), tpidr_el2); |
| 859 | |
| 860 | return 0; |
| 861 | } |
| 862 | |
Marc Zyngier | 359b706 | 2015-03-27 13:09:23 +0000 | [diff] [blame] | 863 | static const struct arm64_cpu_capabilities arm64_features[] = { |
Marc Zyngier | 94a9e04 | 2015-06-12 12:06:36 +0100 | [diff] [blame] | 864 | { |
| 865 | .desc = "GIC system register CPU interface", |
| 866 | .capability = ARM64_HAS_SYSREG_GIC_CPUIF, |
Suzuki K Poulose | 92406f0 | 2016-04-22 12:25:31 +0100 | [diff] [blame] | 867 | .def_scope = SCOPE_SYSTEM, |
Marc Zyngier | 963fcd4 | 2015-09-30 11:50:04 +0100 | [diff] [blame] | 868 | .matches = has_useable_gicv3_cpuif, |
Suzuki K. Poulose | da8d02d | 2015-10-19 14:24:51 +0100 | [diff] [blame] | 869 | .sys_reg = SYS_ID_AA64PFR0_EL1, |
| 870 | .field_pos = ID_AA64PFR0_GIC_SHIFT, |
Suzuki K Poulose | ff96f7b | 2016-01-26 10:58:15 +0000 | [diff] [blame] | 871 | .sign = FTR_UNSIGNED, |
James Morse | 18ffa04 | 2015-07-21 13:23:29 +0100 | [diff] [blame] | 872 | .min_field_value = 1, |
Marc Zyngier | 94a9e04 | 2015-06-12 12:06:36 +0100 | [diff] [blame] | 873 | }, |
James Morse | 338d4f4 | 2015-07-22 19:05:54 +0100 | [diff] [blame] | 874 | #ifdef CONFIG_ARM64_PAN |
| 875 | { |
| 876 | .desc = "Privileged Access Never", |
| 877 | .capability = ARM64_HAS_PAN, |
Suzuki K Poulose | 92406f0 | 2016-04-22 12:25:31 +0100 | [diff] [blame] | 878 | .def_scope = SCOPE_SYSTEM, |
Suzuki K. Poulose | da8d02d | 2015-10-19 14:24:51 +0100 | [diff] [blame] | 879 | .matches = has_cpuid_feature, |
| 880 | .sys_reg = SYS_ID_AA64MMFR1_EL1, |
| 881 | .field_pos = ID_AA64MMFR1_PAN_SHIFT, |
Suzuki K Poulose | ff96f7b | 2016-01-26 10:58:15 +0000 | [diff] [blame] | 882 | .sign = FTR_UNSIGNED, |
James Morse | 338d4f4 | 2015-07-22 19:05:54 +0100 | [diff] [blame] | 883 | .min_field_value = 1, |
| 884 | .enable = cpu_enable_pan, |
| 885 | }, |
| 886 | #endif /* CONFIG_ARM64_PAN */ |
Will Deacon | 2e94da1 | 2015-07-27 16:23:58 +0100 | [diff] [blame] | 887 | #if defined(CONFIG_AS_LSE) && defined(CONFIG_ARM64_LSE_ATOMICS) |
| 888 | { |
| 889 | .desc = "LSE atomic instructions", |
| 890 | .capability = ARM64_HAS_LSE_ATOMICS, |
Suzuki K Poulose | 92406f0 | 2016-04-22 12:25:31 +0100 | [diff] [blame] | 891 | .def_scope = SCOPE_SYSTEM, |
Suzuki K. Poulose | da8d02d | 2015-10-19 14:24:51 +0100 | [diff] [blame] | 892 | .matches = has_cpuid_feature, |
| 893 | .sys_reg = SYS_ID_AA64ISAR0_EL1, |
| 894 | .field_pos = ID_AA64ISAR0_ATOMICS_SHIFT, |
Suzuki K Poulose | ff96f7b | 2016-01-26 10:58:15 +0000 | [diff] [blame] | 895 | .sign = FTR_UNSIGNED, |
Will Deacon | 2e94da1 | 2015-07-27 16:23:58 +0100 | [diff] [blame] | 896 | .min_field_value = 2, |
| 897 | }, |
| 898 | #endif /* CONFIG_AS_LSE && CONFIG_ARM64_LSE_ATOMICS */ |
Marc Zyngier | d88701b | 2015-01-29 11:24:05 +0000 | [diff] [blame] | 899 | { |
Will Deacon | d5370f7 | 2016-02-02 12:46:24 +0000 | [diff] [blame] | 900 | .desc = "Software prefetching using PRFM", |
| 901 | .capability = ARM64_HAS_NO_HW_PREFETCH, |
Suzuki K Poulose | 92406f0 | 2016-04-22 12:25:31 +0100 | [diff] [blame] | 902 | .def_scope = SCOPE_SYSTEM, |
Will Deacon | d5370f7 | 2016-02-02 12:46:24 +0000 | [diff] [blame] | 903 | .matches = has_no_hw_prefetch, |
| 904 | }, |
James Morse | 57f4959 | 2016-02-05 14:58:48 +0000 | [diff] [blame] | 905 | #ifdef CONFIG_ARM64_UAO |
| 906 | { |
| 907 | .desc = "User Access Override", |
| 908 | .capability = ARM64_HAS_UAO, |
Suzuki K Poulose | 92406f0 | 2016-04-22 12:25:31 +0100 | [diff] [blame] | 909 | .def_scope = SCOPE_SYSTEM, |
James Morse | 57f4959 | 2016-02-05 14:58:48 +0000 | [diff] [blame] | 910 | .matches = has_cpuid_feature, |
| 911 | .sys_reg = SYS_ID_AA64MMFR2_EL1, |
| 912 | .field_pos = ID_AA64MMFR2_UAO_SHIFT, |
| 913 | .min_field_value = 1, |
| 914 | .enable = cpu_enable_uao, |
| 915 | }, |
| 916 | #endif /* CONFIG_ARM64_UAO */ |
James Morse | 7054419 | 2016-02-05 14:58:50 +0000 | [diff] [blame] | 917 | #ifdef CONFIG_ARM64_PAN |
| 918 | { |
| 919 | .capability = ARM64_ALT_PAN_NOT_UAO, |
Suzuki K Poulose | 92406f0 | 2016-04-22 12:25:31 +0100 | [diff] [blame] | 920 | .def_scope = SCOPE_SYSTEM, |
James Morse | 7054419 | 2016-02-05 14:58:50 +0000 | [diff] [blame] | 921 | .matches = cpufeature_pan_not_uao, |
| 922 | }, |
| 923 | #endif /* CONFIG_ARM64_PAN */ |
Linus Torvalds | 588ab3f | 2016-03-17 20:03:47 -0700 | [diff] [blame] | 924 | { |
Marc Zyngier | d88701b | 2015-01-29 11:24:05 +0000 | [diff] [blame] | 925 | .desc = "Virtualization Host Extensions", |
| 926 | .capability = ARM64_HAS_VIRT_HOST_EXTN, |
Suzuki K Poulose | 92406f0 | 2016-04-22 12:25:31 +0100 | [diff] [blame] | 927 | .def_scope = SCOPE_SYSTEM, |
Marc Zyngier | d88701b | 2015-01-29 11:24:05 +0000 | [diff] [blame] | 928 | .matches = runs_at_el2, |
James Morse | eea5902 | 2018-07-20 10:56:16 +0100 | [diff] [blame] | 929 | .enable = cpu_copy_el2regs, |
Marc Zyngier | d88701b | 2015-01-29 11:24:05 +0000 | [diff] [blame] | 930 | }, |
Suzuki K Poulose | 042446a | 2016-04-18 10:28:36 +0100 | [diff] [blame] | 931 | { |
| 932 | .desc = "32-bit EL0 Support", |
| 933 | .capability = ARM64_HAS_32BIT_EL0, |
Suzuki K Poulose | 92406f0 | 2016-04-22 12:25:31 +0100 | [diff] [blame] | 934 | .def_scope = SCOPE_SYSTEM, |
Suzuki K Poulose | 042446a | 2016-04-18 10:28:36 +0100 | [diff] [blame] | 935 | .matches = has_cpuid_feature, |
| 936 | .sys_reg = SYS_ID_AA64PFR0_EL1, |
| 937 | .sign = FTR_UNSIGNED, |
| 938 | .field_pos = ID_AA64PFR0_EL0_SHIFT, |
| 939 | .min_field_value = ID_AA64PFR0_EL0_32BIT_64BIT, |
| 940 | }, |
Marc Zyngier | d174591 | 2016-06-30 18:40:42 +0100 | [diff] [blame] | 941 | { |
| 942 | .desc = "Reduced HYP mapping offset", |
| 943 | .capability = ARM64_HYP_OFFSET_LOW, |
| 944 | .def_scope = SCOPE_SYSTEM, |
| 945 | .matches = hyp_offset_low, |
| 946 | }, |
Will Deacon | f79ff2d | 2017-11-14 14:38:19 +0000 | [diff] [blame] | 947 | #ifdef CONFIG_UNMAP_KERNEL_AT_EL0 |
| 948 | { |
Will Deacon | 7354772 | 2018-04-03 12:09:14 +0100 | [diff] [blame] | 949 | .desc = "Kernel page table isolation (KPTI)", |
Will Deacon | f79ff2d | 2017-11-14 14:38:19 +0000 | [diff] [blame] | 950 | .capability = ARM64_UNMAP_KERNEL_AT_EL0, |
| 951 | .def_scope = SCOPE_SYSTEM, |
| 952 | .matches = unmap_kernel_at_el0, |
Will Deacon | 4025fe1 | 2018-04-03 12:09:20 +0100 | [diff] [blame] | 953 | .enable = kpti_install_ng_mappings, |
Will Deacon | f79ff2d | 2017-11-14 14:38:19 +0000 | [diff] [blame] | 954 | }, |
| 955 | #endif |
Marc Zyngier | 359b706 | 2015-03-27 13:09:23 +0000 | [diff] [blame] | 956 | {}, |
| 957 | }; |
| 958 | |
Suzuki K Poulose | ff96f7b | 2016-01-26 10:58:15 +0000 | [diff] [blame] | 959 | #define HWCAP_CAP(reg, field, s, min_value, type, cap) \ |
Suzuki K. Poulose | 37b01d53 | 2015-10-19 14:24:52 +0100 | [diff] [blame] | 960 | { \ |
| 961 | .desc = #cap, \ |
Suzuki K Poulose | 92406f0 | 2016-04-22 12:25:31 +0100 | [diff] [blame] | 962 | .def_scope = SCOPE_SYSTEM, \ |
Suzuki K. Poulose | 37b01d53 | 2015-10-19 14:24:52 +0100 | [diff] [blame] | 963 | .matches = has_cpuid_feature, \ |
| 964 | .sys_reg = reg, \ |
| 965 | .field_pos = field, \ |
Suzuki K Poulose | ff96f7b | 2016-01-26 10:58:15 +0000 | [diff] [blame] | 966 | .sign = s, \ |
Suzuki K. Poulose | 37b01d53 | 2015-10-19 14:24:52 +0100 | [diff] [blame] | 967 | .min_field_value = min_value, \ |
| 968 | .hwcap_type = type, \ |
| 969 | .hwcap = cap, \ |
| 970 | } |
| 971 | |
Suzuki K Poulose | f3efb67 | 2016-04-18 10:28:32 +0100 | [diff] [blame] | 972 | static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { |
Suzuki K Poulose | ff96f7b | 2016-01-26 10:58:15 +0000 | [diff] [blame] | 973 | HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_PMULL), |
| 974 | HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_AES), |
| 975 | HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA1), |
| 976 | HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA2), |
Suzuki K Poulose | ba62b30 | 2017-10-11 14:01:02 +0100 | [diff] [blame] | 977 | HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_SHA512), |
Suzuki K Poulose | ff96f7b | 2016-01-26 10:58:15 +0000 | [diff] [blame] | 978 | HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_CRC32), |
| 979 | HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_ATOMICS), |
Suzuki K Poulose | ba62b30 | 2017-10-11 14:01:02 +0100 | [diff] [blame] | 980 | HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA3), |
| 981 | HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SM3), |
| 982 | HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM4_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SM4), |
| 983 | HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_DP_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_ASIMDDP), |
Suzuki K Poulose | ff96f7b | 2016-01-26 10:58:15 +0000 | [diff] [blame] | 984 | HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, HWCAP_FP), |
Suzuki K Poulose | bf50061 | 2016-01-26 15:52:46 +0000 | [diff] [blame] | 985 | HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_FPHP), |
Suzuki K Poulose | ff96f7b | 2016-01-26 10:58:15 +0000 | [diff] [blame] | 986 | HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, HWCAP_ASIMD), |
Suzuki K Poulose | bf50061 | 2016-01-26 15:52:46 +0000 | [diff] [blame] | 987 | HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_ASIMDHP), |
Suzuki K Poulose | 7528350 | 2016-04-18 10:28:33 +0100 | [diff] [blame] | 988 | {}, |
| 989 | }; |
| 990 | |
| 991 | static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = { |
Suzuki K. Poulose | 37b01d53 | 2015-10-19 14:24:52 +0100 | [diff] [blame] | 992 | #ifdef CONFIG_COMPAT |
Suzuki K Poulose | ff96f7b | 2016-01-26 10:58:15 +0000 | [diff] [blame] | 993 | HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL), |
| 994 | HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES), |
| 995 | HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1), |
| 996 | HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2), |
| 997 | HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32), |
Suzuki K. Poulose | 37b01d53 | 2015-10-19 14:24:52 +0100 | [diff] [blame] | 998 | #endif |
| 999 | {}, |
| 1000 | }; |
| 1001 | |
Suzuki K Poulose | f3efb67 | 2016-04-18 10:28:32 +0100 | [diff] [blame] | 1002 | static void __init cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap) |
Suzuki K. Poulose | 37b01d53 | 2015-10-19 14:24:52 +0100 | [diff] [blame] | 1003 | { |
| 1004 | switch (cap->hwcap_type) { |
| 1005 | case CAP_HWCAP: |
| 1006 | elf_hwcap |= cap->hwcap; |
| 1007 | break; |
| 1008 | #ifdef CONFIG_COMPAT |
| 1009 | case CAP_COMPAT_HWCAP: |
| 1010 | compat_elf_hwcap |= (u32)cap->hwcap; |
| 1011 | break; |
| 1012 | case CAP_COMPAT_HWCAP2: |
| 1013 | compat_elf_hwcap2 |= (u32)cap->hwcap; |
| 1014 | break; |
| 1015 | #endif |
| 1016 | default: |
| 1017 | WARN_ON(1); |
| 1018 | break; |
| 1019 | } |
| 1020 | } |
| 1021 | |
| 1022 | /* Check if we have a particular HWCAP enabled */ |
Suzuki K Poulose | f3efb67 | 2016-04-18 10:28:32 +0100 | [diff] [blame] | 1023 | static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap) |
Suzuki K. Poulose | 37b01d53 | 2015-10-19 14:24:52 +0100 | [diff] [blame] | 1024 | { |
| 1025 | bool rc; |
| 1026 | |
| 1027 | switch (cap->hwcap_type) { |
| 1028 | case CAP_HWCAP: |
| 1029 | rc = (elf_hwcap & cap->hwcap) != 0; |
| 1030 | break; |
| 1031 | #ifdef CONFIG_COMPAT |
| 1032 | case CAP_COMPAT_HWCAP: |
| 1033 | rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0; |
| 1034 | break; |
| 1035 | case CAP_COMPAT_HWCAP2: |
| 1036 | rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0; |
| 1037 | break; |
| 1038 | #endif |
| 1039 | default: |
| 1040 | WARN_ON(1); |
| 1041 | rc = false; |
| 1042 | } |
| 1043 | |
| 1044 | return rc; |
| 1045 | } |
| 1046 | |
Suzuki K Poulose | 7528350 | 2016-04-18 10:28:33 +0100 | [diff] [blame] | 1047 | static void __init setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps) |
Suzuki K. Poulose | 37b01d53 | 2015-10-19 14:24:52 +0100 | [diff] [blame] | 1048 | { |
Suzuki K Poulose | 7528350 | 2016-04-18 10:28:33 +0100 | [diff] [blame] | 1049 | for (; hwcaps->matches; hwcaps++) |
Suzuki K Poulose | 92406f0 | 2016-04-22 12:25:31 +0100 | [diff] [blame] | 1050 | if (hwcaps->matches(hwcaps, hwcaps->def_scope)) |
Suzuki K Poulose | 7528350 | 2016-04-18 10:28:33 +0100 | [diff] [blame] | 1051 | cap_set_elf_hwcap(hwcaps); |
Suzuki K. Poulose | 37b01d53 | 2015-10-19 14:24:52 +0100 | [diff] [blame] | 1052 | } |
| 1053 | |
Suzuki K Poulose | 1e0946d | 2018-04-03 12:09:16 +0100 | [diff] [blame] | 1054 | /* |
| 1055 | * Check if the current CPU has a given feature capability. |
| 1056 | * Should be called from non-preemptible context. |
| 1057 | */ |
| 1058 | static bool __this_cpu_has_cap(const struct arm64_cpu_capabilities *cap_array, |
| 1059 | unsigned int cap) |
| 1060 | { |
| 1061 | const struct arm64_cpu_capabilities *caps; |
| 1062 | |
| 1063 | if (WARN_ON(preemptible())) |
| 1064 | return false; |
| 1065 | |
Mark Rutland | 93f339e | 2018-04-12 12:11:07 +0100 | [diff] [blame] | 1066 | for (caps = cap_array; caps->matches; caps++) |
Suzuki K Poulose | 1e0946d | 2018-04-03 12:09:16 +0100 | [diff] [blame] | 1067 | if (caps->capability == cap && |
Suzuki K Poulose | 1e0946d | 2018-04-03 12:09:16 +0100 | [diff] [blame] | 1068 | caps->matches(caps, SCOPE_LOCAL_CPU)) |
| 1069 | return true; |
| 1070 | return false; |
| 1071 | } |
| 1072 | |
Suzuki K. Poulose | ce8b602 | 2015-10-19 14:24:49 +0100 | [diff] [blame] | 1073 | void update_cpu_capabilities(const struct arm64_cpu_capabilities *caps, |
Marc Zyngier | 359b706 | 2015-03-27 13:09:23 +0000 | [diff] [blame] | 1074 | const char *info) |
| 1075 | { |
Suzuki K Poulose | 7528350 | 2016-04-18 10:28:33 +0100 | [diff] [blame] | 1076 | for (; caps->matches; caps++) { |
Suzuki K Poulose | 92406f0 | 2016-04-22 12:25:31 +0100 | [diff] [blame] | 1077 | if (!caps->matches(caps, caps->def_scope)) |
Marc Zyngier | 359b706 | 2015-03-27 13:09:23 +0000 | [diff] [blame] | 1078 | continue; |
| 1079 | |
Suzuki K Poulose | 7528350 | 2016-04-18 10:28:33 +0100 | [diff] [blame] | 1080 | if (!cpus_have_cap(caps->capability) && caps->desc) |
| 1081 | pr_info("%s %s\n", info, caps->desc); |
| 1082 | cpus_set_cap(caps->capability); |
Marc Zyngier | 359b706 | 2015-03-27 13:09:23 +0000 | [diff] [blame] | 1083 | } |
Suzuki K. Poulose | ce8b602 | 2015-10-19 14:24:49 +0100 | [diff] [blame] | 1084 | } |
James Morse | 1c07630 | 2015-07-21 13:23:28 +0100 | [diff] [blame] | 1085 | |
Suzuki K. Poulose | ce8b602 | 2015-10-19 14:24:49 +0100 | [diff] [blame] | 1086 | /* |
Suzuki K. Poulose | dbb4e15 | 2015-10-19 14:24:50 +0100 | [diff] [blame] | 1087 | * Run through the enabled capabilities and enable() it on all active |
| 1088 | * CPUs |
Suzuki K. Poulose | ce8b602 | 2015-10-19 14:24:49 +0100 | [diff] [blame] | 1089 | */ |
Andre Przywara | 8e23185 | 2016-06-28 18:07:30 +0100 | [diff] [blame] | 1090 | void __init enable_cpu_capabilities(const struct arm64_cpu_capabilities *caps) |
Suzuki K. Poulose | ce8b602 | 2015-10-19 14:24:49 +0100 | [diff] [blame] | 1091 | { |
Mark Rutland | b1d5708 | 2017-05-16 15:18:05 +0100 | [diff] [blame] | 1092 | for (; caps->matches; caps++) { |
| 1093 | unsigned int num = caps->capability; |
| 1094 | |
| 1095 | if (!cpus_have_cap(num)) |
| 1096 | continue; |
| 1097 | |
| 1098 | /* Ensure cpus_have_const_cap(num) works */ |
| 1099 | static_branch_enable(&cpu_hwcap_keys[num]); |
| 1100 | |
| 1101 | if (caps->enable) { |
James Morse | 2a6dcb2 | 2016-10-18 11:27:46 +0100 | [diff] [blame] | 1102 | /* |
| 1103 | * Use stop_machine() as it schedules the work allowing |
| 1104 | * us to modify PSTATE, instead of on_each_cpu() which |
| 1105 | * uses an IPI, giving us a PSTATE that disappears when |
| 1106 | * we return. |
| 1107 | */ |
Mark Rutland | 92e7a83 | 2018-04-12 12:11:09 +0100 | [diff] [blame] | 1108 | stop_machine(caps->enable, (void *)caps, cpu_online_mask); |
Mark Rutland | b1d5708 | 2017-05-16 15:18:05 +0100 | [diff] [blame] | 1109 | } |
| 1110 | } |
Suzuki K. Poulose | dbb4e15 | 2015-10-19 14:24:50 +0100 | [diff] [blame] | 1111 | } |
| 1112 | |
Suzuki K. Poulose | dbb4e15 | 2015-10-19 14:24:50 +0100 | [diff] [blame] | 1113 | /* |
| 1114 | * Flag to indicate if we have computed the system wide |
| 1115 | * capabilities based on the boot time active CPUs. This |
| 1116 | * will be used to determine if a new booting CPU should |
| 1117 | * go through the verification process to make sure that it |
| 1118 | * supports the system capabilities, without using a hotplug |
| 1119 | * notifier. |
| 1120 | */ |
| 1121 | static bool sys_caps_initialised; |
| 1122 | |
| 1123 | static inline void set_sys_caps_initialised(void) |
| 1124 | { |
| 1125 | sys_caps_initialised = true; |
| 1126 | } |
| 1127 | |
| 1128 | /* |
Suzuki K Poulose | 13f417f | 2016-02-23 10:31:45 +0000 | [diff] [blame] | 1129 | * Check for CPU features that are used in early boot |
| 1130 | * based on the Boot CPU value. |
Suzuki K. Poulose | dbb4e15 | 2015-10-19 14:24:50 +0100 | [diff] [blame] | 1131 | */ |
Suzuki K Poulose | 13f417f | 2016-02-23 10:31:45 +0000 | [diff] [blame] | 1132 | static void check_early_cpu_features(void) |
Marc Zyngier | 359b706 | 2015-03-27 13:09:23 +0000 | [diff] [blame] | 1133 | { |
Suzuki K Poulose | ac1ad20 | 2016-04-13 14:41:33 +0100 | [diff] [blame] | 1134 | verify_cpu_run_el(); |
Suzuki K Poulose | 13f417f | 2016-02-23 10:31:45 +0000 | [diff] [blame] | 1135 | verify_cpu_asid_bits(); |
Suzuki K. Poulose | dbb4e15 | 2015-10-19 14:24:50 +0100 | [diff] [blame] | 1136 | } |
| 1137 | |
Suzuki K Poulose | 7528350 | 2016-04-18 10:28:33 +0100 | [diff] [blame] | 1138 | static void |
| 1139 | verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps) |
| 1140 | { |
| 1141 | |
Suzuki K Poulose | 92406f0 | 2016-04-22 12:25:31 +0100 | [diff] [blame] | 1142 | for (; caps->matches; caps++) |
| 1143 | if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) { |
Suzuki K Poulose | 7528350 | 2016-04-18 10:28:33 +0100 | [diff] [blame] | 1144 | pr_crit("CPU%d: missing HWCAP: %s\n", |
| 1145 | smp_processor_id(), caps->desc); |
| 1146 | cpu_die_early(); |
| 1147 | } |
Suzuki K Poulose | 7528350 | 2016-04-18 10:28:33 +0100 | [diff] [blame] | 1148 | } |
| 1149 | |
| 1150 | static void |
Suzuki K Poulose | 1e0946d | 2018-04-03 12:09:16 +0100 | [diff] [blame] | 1151 | verify_local_cpu_features(const struct arm64_cpu_capabilities *caps_list) |
Suzuki K Poulose | 7528350 | 2016-04-18 10:28:33 +0100 | [diff] [blame] | 1152 | { |
Suzuki K Poulose | 1e0946d | 2018-04-03 12:09:16 +0100 | [diff] [blame] | 1153 | const struct arm64_cpu_capabilities *caps = caps_list; |
Suzuki K Poulose | 7528350 | 2016-04-18 10:28:33 +0100 | [diff] [blame] | 1154 | for (; caps->matches; caps++) { |
Suzuki K Poulose | 92406f0 | 2016-04-22 12:25:31 +0100 | [diff] [blame] | 1155 | if (!cpus_have_cap(caps->capability)) |
Suzuki K Poulose | 7528350 | 2016-04-18 10:28:33 +0100 | [diff] [blame] | 1156 | continue; |
| 1157 | /* |
| 1158 | * If the new CPU misses an advertised feature, we cannot proceed |
| 1159 | * further, park the cpu. |
| 1160 | */ |
Suzuki K Poulose | 1e0946d | 2018-04-03 12:09:16 +0100 | [diff] [blame] | 1161 | if (!__this_cpu_has_cap(caps_list, caps->capability)) { |
Suzuki K Poulose | 7528350 | 2016-04-18 10:28:33 +0100 | [diff] [blame] | 1162 | pr_crit("CPU%d: missing feature: %s\n", |
| 1163 | smp_processor_id(), caps->desc); |
| 1164 | cpu_die_early(); |
| 1165 | } |
| 1166 | if (caps->enable) |
Mark Rutland | 92e7a83 | 2018-04-12 12:11:09 +0100 | [diff] [blame] | 1167 | caps->enable((void *)caps); |
Suzuki K Poulose | 7528350 | 2016-04-18 10:28:33 +0100 | [diff] [blame] | 1168 | } |
| 1169 | } |
| 1170 | |
Suzuki K. Poulose | dbb4e15 | 2015-10-19 14:24:50 +0100 | [diff] [blame] | 1171 | /* |
| 1172 | * Run through the enabled system capabilities and enable() it on this CPU. |
| 1173 | * The capabilities were decided based on the available CPUs at the boot time. |
| 1174 | * Any new CPU should match the system wide status of the capability. If the |
| 1175 | * new CPU doesn't have a capability which the system now has enabled, we |
| 1176 | * cannot do anything to fix it up and could cause unexpected failures. So |
| 1177 | * we park the CPU. |
| 1178 | */ |
Suzuki K Poulose | c47a190 | 2016-09-09 14:07:10 +0100 | [diff] [blame] | 1179 | static void verify_local_cpu_capabilities(void) |
Suzuki K. Poulose | dbb4e15 | 2015-10-19 14:24:50 +0100 | [diff] [blame] | 1180 | { |
Suzuki K Poulose | 89ba264 | 2016-09-09 14:07:09 +0100 | [diff] [blame] | 1181 | verify_local_cpu_errata_workarounds(); |
Suzuki K Poulose | 7528350 | 2016-04-18 10:28:33 +0100 | [diff] [blame] | 1182 | verify_local_cpu_features(arm64_features); |
| 1183 | verify_local_elf_hwcaps(arm64_elf_hwcaps); |
Suzuki K Poulose | 643d703 | 2016-04-18 10:28:37 +0100 | [diff] [blame] | 1184 | if (system_supports_32bit_el0()) |
| 1185 | verify_local_elf_hwcaps(compat_elf_hwcaps); |
Marc Zyngier | 359b706 | 2015-03-27 13:09:23 +0000 | [diff] [blame] | 1186 | } |
| 1187 | |
Suzuki K Poulose | c47a190 | 2016-09-09 14:07:10 +0100 | [diff] [blame] | 1188 | void check_local_cpu_capabilities(void) |
| 1189 | { |
| 1190 | /* |
| 1191 | * All secondary CPUs should conform to the early CPU features |
| 1192 | * in use by the kernel based on boot CPU. |
| 1193 | */ |
| 1194 | check_early_cpu_features(); |
| 1195 | |
| 1196 | /* |
| 1197 | * If we haven't finalised the system capabilities, this CPU gets |
| 1198 | * a chance to update the errata work arounds. |
| 1199 | * Otherwise, this CPU should verify that it has all the system |
| 1200 | * advertised capabilities. |
| 1201 | */ |
| 1202 | if (!sys_caps_initialised) |
| 1203 | update_cpu_errata_workarounds(); |
| 1204 | else |
| 1205 | verify_local_cpu_capabilities(); |
| 1206 | } |
| 1207 | |
Jisheng Zhang | a7c61a3 | 2015-11-20 17:59:10 +0800 | [diff] [blame] | 1208 | static void __init setup_feature_capabilities(void) |
Marc Zyngier | 359b706 | 2015-03-27 13:09:23 +0000 | [diff] [blame] | 1209 | { |
Suzuki K. Poulose | ce8b602 | 2015-10-19 14:24:49 +0100 | [diff] [blame] | 1210 | update_cpu_capabilities(arm64_features, "detected feature:"); |
| 1211 | enable_cpu_capabilities(arm64_features); |
Marc Zyngier | 359b706 | 2015-03-27 13:09:23 +0000 | [diff] [blame] | 1212 | } |
Suzuki K. Poulose | 9cdf8ec | 2015-10-19 14:24:41 +0100 | [diff] [blame] | 1213 | |
Mark Rutland | b1d5708 | 2017-05-16 15:18:05 +0100 | [diff] [blame] | 1214 | DEFINE_STATIC_KEY_FALSE(arm64_const_caps_ready); |
| 1215 | EXPORT_SYMBOL(arm64_const_caps_ready); |
| 1216 | |
| 1217 | static void __init mark_const_caps_ready(void) |
| 1218 | { |
| 1219 | static_branch_enable(&arm64_const_caps_ready); |
| 1220 | } |
| 1221 | |
Marc Zyngier | 1d648e4 | 2018-04-03 12:09:15 +0100 | [diff] [blame] | 1222 | extern const struct arm64_cpu_capabilities arm64_errata[]; |
| 1223 | |
Marc Zyngier | e3661b1 | 2016-04-22 12:25:32 +0100 | [diff] [blame] | 1224 | bool this_cpu_has_cap(unsigned int cap) |
| 1225 | { |
Marc Zyngier | 1d648e4 | 2018-04-03 12:09:15 +0100 | [diff] [blame] | 1226 | return (__this_cpu_has_cap(arm64_features, cap) || |
| 1227 | __this_cpu_has_cap(arm64_errata, cap)); |
Marc Zyngier | e3661b1 | 2016-04-22 12:25:32 +0100 | [diff] [blame] | 1228 | } |
| 1229 | |
Suzuki K. Poulose | 9cdf8ec | 2015-10-19 14:24:41 +0100 | [diff] [blame] | 1230 | void __init setup_cpu_features(void) |
| 1231 | { |
Suzuki K. Poulose | 9cdf8ec | 2015-10-19 14:24:41 +0100 | [diff] [blame] | 1232 | u32 cwg; |
| 1233 | int cls; |
| 1234 | |
Suzuki K. Poulose | dbb4e15 | 2015-10-19 14:24:50 +0100 | [diff] [blame] | 1235 | /* Set the CPU feature capabilies */ |
| 1236 | setup_feature_capabilities(); |
Andre Przywara | 8e23185 | 2016-06-28 18:07:30 +0100 | [diff] [blame] | 1237 | enable_errata_workarounds(); |
Mark Rutland | b1d5708 | 2017-05-16 15:18:05 +0100 | [diff] [blame] | 1238 | mark_const_caps_ready(); |
Suzuki K Poulose | 7528350 | 2016-04-18 10:28:33 +0100 | [diff] [blame] | 1239 | setup_elf_hwcaps(arm64_elf_hwcaps); |
Suzuki K Poulose | 643d703 | 2016-04-18 10:28:37 +0100 | [diff] [blame] | 1240 | |
| 1241 | if (system_supports_32bit_el0()) |
| 1242 | setup_elf_hwcaps(compat_elf_hwcaps); |
Suzuki K. Poulose | dbb4e15 | 2015-10-19 14:24:50 +0100 | [diff] [blame] | 1243 | |
| 1244 | /* Advertise that we have computed the system capabilities */ |
| 1245 | set_sys_caps_initialised(); |
| 1246 | |
Suzuki K. Poulose | 9cdf8ec | 2015-10-19 14:24:41 +0100 | [diff] [blame] | 1247 | /* |
| 1248 | * Check for sane CTR_EL0.CWG value. |
| 1249 | */ |
| 1250 | cwg = cache_type_cwg(); |
| 1251 | cls = cache_line_size(); |
| 1252 | if (!cwg) |
| 1253 | pr_warn("No Cache Writeback Granule information, assuming cache line size %d\n", |
| 1254 | cls); |
| 1255 | if (L1_CACHE_BYTES < cls) |
| 1256 | pr_warn("L1_CACHE_BYTES smaller than the Cache Writeback Granule (%d < %d)\n", |
| 1257 | L1_CACHE_BYTES, cls); |
Marc Zyngier | 359b706 | 2015-03-27 13:09:23 +0000 | [diff] [blame] | 1258 | } |
James Morse | 7054419 | 2016-02-05 14:58:50 +0000 | [diff] [blame] | 1259 | |
| 1260 | static bool __maybe_unused |
Suzuki K Poulose | 92406f0 | 2016-04-22 12:25:31 +0100 | [diff] [blame] | 1261 | cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused) |
James Morse | 7054419 | 2016-02-05 14:58:50 +0000 | [diff] [blame] | 1262 | { |
Suzuki K Poulose | fe64d7d | 2016-11-08 13:56:20 +0000 | [diff] [blame] | 1263 | return (cpus_have_const_cap(ARM64_HAS_PAN) && !cpus_have_const_cap(ARM64_HAS_UAO)); |
James Morse | 7054419 | 2016-02-05 14:58:50 +0000 | [diff] [blame] | 1264 | } |