blob: 09d813d313f4a44986a2f358d8ddc08c619533f1 [file] [log] [blame]
Anton Salnikov7c7e92a2008-02-06 02:57:48 +01001/*
2 * Palmchip bk3710 IDE controller
3 *
4 * Copyright (C) 2006 Texas Instruments.
5 * Copyright (C) 2007 MontaVista Software, Inc., <source@mvista.com>
6 *
7 * ----------------------------------------------------------------------------
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 * ----------------------------------------------------------------------------
23 *
24 */
25
26#include <linux/types.h>
27#include <linux/module.h>
28#include <linux/kernel.h>
29#include <linux/ioport.h>
Anton Salnikov7c7e92a2008-02-06 02:57:48 +010030#include <linux/ide.h>
31#include <linux/delay.h>
32#include <linux/init.h>
33#include <linux/clk.h>
34#include <linux/platform_device.h>
35
36/* Offset of the primary interface registers */
37#define IDE_PALM_ATA_PRI_REG_OFFSET 0x1F0
38
39/* Primary Control Offset */
40#define IDE_PALM_ATA_PRI_CTL_OFFSET 0x3F6
41
Anton Salnikov7c7e92a2008-02-06 02:57:48 +010042#define BK3710_BMICP 0x00
43#define BK3710_BMISP 0x02
44#define BK3710_BMIDTP 0x04
Anton Salnikov7c7e92a2008-02-06 02:57:48 +010045#define BK3710_IDETIMP 0x40
Anton Salnikov7c7e92a2008-02-06 02:57:48 +010046#define BK3710_IDESTATUS 0x47
47#define BK3710_UDMACTL 0x48
Anton Salnikov7c7e92a2008-02-06 02:57:48 +010048#define BK3710_MISCCTL 0x50
49#define BK3710_REGSTB 0x54
50#define BK3710_REGRCVR 0x58
51#define BK3710_DATSTB 0x5C
52#define BK3710_DATRCVR 0x60
53#define BK3710_DMASTB 0x64
54#define BK3710_DMARCVR 0x68
55#define BK3710_UDMASTB 0x6C
56#define BK3710_UDMATRP 0x70
57#define BK3710_UDMAENV 0x74
58#define BK3710_IORDYTMP 0x78
Anton Salnikov7c7e92a2008-02-06 02:57:48 +010059
Sergei Shtylyovffab6cf2008-07-08 19:27:22 +020060static unsigned ideclk_period; /* in nanoseconds */
Anton Salnikov7c7e92a2008-02-06 02:57:48 +010061
David Brownelldb2f38c2009-04-22 20:33:40 +020062struct palm_bk3710_udmatiming {
63 unsigned int rptime; /* tRP -- Ready to pause time (nsec) */
64 unsigned int cycletime; /* tCYCTYP2/2 -- avg Cycle Time (nsec) */
65 /* tENV is always a minimum of 20 nsec */
66};
67
Anton Salnikov7c7e92a2008-02-06 02:57:48 +010068static const struct palm_bk3710_udmatiming palm_bk3710_udmatimings[6] = {
Bartlomiej Zolnierkiewiczd7f514352009-04-23 22:53:45 +020069 { 160, 240 / 2 }, /* UDMA Mode 0 */
70 { 125, 160 / 2 }, /* UDMA Mode 1 */
71 { 100, 120 / 2 }, /* UDMA Mode 2 */
72 { 100, 90 / 2 }, /* UDMA Mode 3 */
73 { 100, 60 / 2 }, /* UDMA Mode 4 */
74 { 85, 40 / 2 }, /* UDMA Mode 5 */
Anton Salnikov7c7e92a2008-02-06 02:57:48 +010075};
76
Anton Salnikov7c7e92a2008-02-06 02:57:48 +010077static void palm_bk3710_setudmamode(void __iomem *base, unsigned int dev,
78 unsigned int mode)
79{
80 u8 tenv, trp, t0;
81 u32 val32;
82 u16 val16;
83
84 /* DMA Data Setup */
Julia Lawall00fe8b72008-04-26 17:36:35 +020085 t0 = DIV_ROUND_UP(palm_bk3710_udmatimings[mode].cycletime,
Sergei Shtylyovffab6cf2008-07-08 19:27:22 +020086 ideclk_period) - 1;
87 tenv = DIV_ROUND_UP(20, ideclk_period) - 1;
Julia Lawall00fe8b72008-04-26 17:36:35 +020088 trp = DIV_ROUND_UP(palm_bk3710_udmatimings[mode].rptime,
Sergei Shtylyovffab6cf2008-07-08 19:27:22 +020089 ideclk_period) - 1;
Anton Salnikov7c7e92a2008-02-06 02:57:48 +010090
Anton Salnikov7c7e92a2008-02-06 02:57:48 +010091 /* udmastb Ultra DMA Access Strobe Width */
92 val32 = readl(base + BK3710_UDMASTB) & (0xFF << (dev ? 0 : 8));
93 val32 |= (t0 << (dev ? 8 : 0));
94 writel(val32, base + BK3710_UDMASTB);
95
96 /* udmatrp Ultra DMA Ready to Pause Time */
97 val32 = readl(base + BK3710_UDMATRP) & (0xFF << (dev ? 0 : 8));
98 val32 |= (trp << (dev ? 8 : 0));
99 writel(val32, base + BK3710_UDMATRP);
100
101 /* udmaenv Ultra DMA envelop Time */
102 val32 = readl(base + BK3710_UDMAENV) & (0xFF << (dev ? 0 : 8));
103 val32 |= (tenv << (dev ? 8 : 0));
104 writel(val32, base + BK3710_UDMAENV);
105
106 /* Enable UDMA for Device */
107 val16 = readw(base + BK3710_UDMACTL) | (1 << dev);
108 writew(val16, base + BK3710_UDMACTL);
109}
110
111static void palm_bk3710_setdmamode(void __iomem *base, unsigned int dev,
112 unsigned short min_cycle,
113 unsigned int mode)
114{
115 u8 td, tkw, t0;
116 u32 val32;
117 u16 val16;
118 struct ide_timing *t;
119 int cycletime;
120
121 t = ide_timing_find_mode(mode);
122 cycletime = max_t(int, t->cycle, min_cycle);
123
124 /* DMA Data Setup */
Sergei Shtylyovffab6cf2008-07-08 19:27:22 +0200125 t0 = DIV_ROUND_UP(cycletime, ideclk_period);
126 td = DIV_ROUND_UP(t->active, ideclk_period);
Anton Salnikov7c7e92a2008-02-06 02:57:48 +0100127 tkw = t0 - td - 1;
128 td -= 1;
129
130 val32 = readl(base + BK3710_DMASTB) & (0xFF << (dev ? 0 : 8));
131 val32 |= (td << (dev ? 8 : 0));
132 writel(val32, base + BK3710_DMASTB);
133
134 val32 = readl(base + BK3710_DMARCVR) & (0xFF << (dev ? 0 : 8));
135 val32 |= (tkw << (dev ? 8 : 0));
136 writel(val32, base + BK3710_DMARCVR);
137
138 /* Disable UDMA for Device */
139 val16 = readw(base + BK3710_UDMACTL) & ~(1 << dev);
140 writew(val16, base + BK3710_UDMACTL);
141}
142
143static void palm_bk3710_setpiomode(void __iomem *base, ide_drive_t *mate,
144 unsigned int dev, unsigned int cycletime,
145 unsigned int mode)
146{
147 u8 t2, t2i, t0;
148 u32 val32;
149 struct ide_timing *t;
150
David Brownell33e86012009-04-23 22:53:43 +0200151 t = ide_timing_find_mode(XFER_PIO_0 + mode);
152
Anton Salnikov7c7e92a2008-02-06 02:57:48 +0100153 /* PIO Data Setup */
Sergei Shtylyovffab6cf2008-07-08 19:27:22 +0200154 t0 = DIV_ROUND_UP(cycletime, ideclk_period);
David Brownell33e86012009-04-23 22:53:43 +0200155 t2 = DIV_ROUND_UP(t->active, ideclk_period);
Anton Salnikov7c7e92a2008-02-06 02:57:48 +0100156
157 t2i = t0 - t2 - 1;
158 t2 -= 1;
159
160 val32 = readl(base + BK3710_DATSTB) & (0xFF << (dev ? 0 : 8));
161 val32 |= (t2 << (dev ? 8 : 0));
162 writel(val32, base + BK3710_DATSTB);
163
164 val32 = readl(base + BK3710_DATRCVR) & (0xFF << (dev ? 0 : 8));
165 val32 |= (t2i << (dev ? 8 : 0));
166 writel(val32, base + BK3710_DATRCVR);
167
Bartlomiej Zolnierkiewicz7e59ea22008-10-10 22:39:26 +0200168 if (mate) {
Anton Salnikov7c7e92a2008-02-06 02:57:48 +0100169 u8 mode2 = ide_get_best_pio_mode(mate, 255, 4);
170
171 if (mode2 < mode)
172 mode = mode2;
173 }
174
175 /* TASKFILE Setup */
Sergei Shtylyovffab6cf2008-07-08 19:27:22 +0200176 t0 = DIV_ROUND_UP(t->cyc8b, ideclk_period);
177 t2 = DIV_ROUND_UP(t->act8b, ideclk_period);
Anton Salnikov7c7e92a2008-02-06 02:57:48 +0100178
179 t2i = t0 - t2 - 1;
180 t2 -= 1;
181
182 val32 = readl(base + BK3710_REGSTB) & (0xFF << (dev ? 0 : 8));
183 val32 |= (t2 << (dev ? 8 : 0));
184 writel(val32, base + BK3710_REGSTB);
185
186 val32 = readl(base + BK3710_REGRCVR) & (0xFF << (dev ? 0 : 8));
187 val32 |= (t2i << (dev ? 8 : 0));
188 writel(val32, base + BK3710_REGRCVR);
189}
190
191static void palm_bk3710_set_dma_mode(ide_drive_t *drive, u8 xferspeed)
192{
193 int is_slave = drive->dn & 1;
194 void __iomem *base = (void *)drive->hwif->dma_base;
195
196 if (xferspeed >= XFER_UDMA_0) {
197 palm_bk3710_setudmamode(base, is_slave,
198 xferspeed - XFER_UDMA_0);
199 } else {
Bartlomiej Zolnierkiewicz4dde4492008-10-10 22:39:19 +0200200 palm_bk3710_setdmamode(base, is_slave,
201 drive->id[ATA_ID_EIDE_DMA_MIN],
Anton Salnikov7c7e92a2008-02-06 02:57:48 +0100202 xferspeed);
203 }
204}
205
206static void palm_bk3710_set_pio_mode(ide_drive_t *drive, u8 pio)
207{
208 unsigned int cycle_time;
209 int is_slave = drive->dn & 1;
210 ide_drive_t *mate;
211 void __iomem *base = (void *)drive->hwif->dma_base;
212
213 /*
214 * Obtain the drive PIO data for tuning the Palm Chip registers
215 */
216 cycle_time = ide_pio_cycle_time(drive, pio);
Bartlomiej Zolnierkiewicz7e59ea22008-10-10 22:39:26 +0200217 mate = ide_get_pair_dev(drive);
Anton Salnikov7c7e92a2008-02-06 02:57:48 +0100218 palm_bk3710_setpiomode(base, mate, is_slave, cycle_time, pio);
219}
220
221static void __devinit palm_bk3710_chipinit(void __iomem *base)
222{
223 /*
David Brownell33e86012009-04-23 22:53:43 +0200224 * REVISIT: the ATA reset signal needs to be managed through a
225 * GPIO, which means it should come from platform_data. Until
226 * we get and use such information, we have to trust that things
227 * have been reset before we get here.
Anton Salnikov7c7e92a2008-02-06 02:57:48 +0100228 */
Anton Salnikov7c7e92a2008-02-06 02:57:48 +0100229
230 /*
231 * Program the IDETIMP Register Value based on the following assumptions
232 *
233 * (ATA_IDETIMP_IDEEN , ENABLE ) |
Anton Salnikov7c7e92a2008-02-06 02:57:48 +0100234 * (ATA_IDETIMP_PREPOST1 , DISABLE) |
Anton Salnikov7c7e92a2008-02-06 02:57:48 +0100235 * (ATA_IDETIMP_PREPOST0 , DISABLE) |
David Brownell33e86012009-04-23 22:53:43 +0200236 *
237 * DM6446 silicon rev 2.1 and earlier have no observed net benefit
238 * from enabling prefetch/postwrite.
Anton Salnikov7c7e92a2008-02-06 02:57:48 +0100239 */
David Brownell33e86012009-04-23 22:53:43 +0200240 writew(BIT(15), base + BK3710_IDETIMP);
Anton Salnikov7c7e92a2008-02-06 02:57:48 +0100241
242 /*
243 * UDMACTL Ultra-ATA DMA Control
244 * (ATA_UDMACTL_UDMAP1 , 0 ) |
245 * (ATA_UDMACTL_UDMAP0 , 0 )
246 *
247 */
248 writew(0, base + BK3710_UDMACTL);
249
250 /*
251 * MISCCTL Miscellaneous Conrol Register
David Brownell33e86012009-04-23 22:53:43 +0200252 * (ATA_MISCCTL_HWNHLD1P , 1 cycle)
253 * (ATA_MISCCTL_HWNHLD0P , 1 cycle)
Anton Salnikov7c7e92a2008-02-06 02:57:48 +0100254 * (ATA_MISCCTL_TIMORIDE , 1)
255 */
David Brownell33e86012009-04-23 22:53:43 +0200256 writel(0x001, base + BK3710_MISCCTL);
Anton Salnikov7c7e92a2008-02-06 02:57:48 +0100257
258 /*
259 * IORDYTMP IORDY Timer for Primary Register
260 * (ATA_IORDYTMP_IORDYTMP , 0xffff )
261 */
262 writel(0xFFFF, base + BK3710_IORDYTMP);
263
264 /*
265 * Configure BMISP Register
266 * (ATA_BMISP_DMAEN1 , DISABLE ) |
267 * (ATA_BMISP_DMAEN0 , DISABLE ) |
268 * (ATA_BMISP_IORDYINT , CLEAR) |
269 * (ATA_BMISP_INTRSTAT , CLEAR) |
270 * (ATA_BMISP_DMAERROR , CLEAR)
271 */
272 writew(0, base + BK3710_BMISP);
273
274 palm_bk3710_setpiomode(base, NULL, 0, 600, 0);
275 palm_bk3710_setpiomode(base, NULL, 1, 600, 0);
276}
Bartlomiej Zolnierkiewiczc79b60d2008-02-11 00:32:13 +0100277
Bartlomiej Zolnierkiewiczf454cbe2008-08-05 18:17:04 +0200278static u8 palm_bk3710_cable_detect(ide_hwif_t *hwif)
Bartlomiej Zolnierkiewiczc79b60d2008-02-11 00:32:13 +0100279{
280 return ATA_CBL_PATA80;
281}
282
Bartlomiej Zolnierkiewiczb552a2c2008-04-26 22:25:23 +0200283static int __devinit palm_bk3710_init_dma(ide_hwif_t *hwif,
284 const struct ide_port_info *d)
285{
Bartlomiej Zolnierkiewiczb552a2c2008-04-26 22:25:23 +0200286 printk(KERN_INFO " %s: MMIO-DMA\n", hwif->name);
287
288 if (ide_allocate_dma_engine(hwif))
289 return -1;
290
Bartlomiej Zolnierkiewicz81e8d5a2008-07-23 19:55:51 +0200291 hwif->dma_base = hwif->io_ports.data_addr - IDE_PALM_ATA_PRI_REG_OFFSET;
292
Bartlomiej Zolnierkiewiczb552a2c2008-04-26 22:25:23 +0200293 return 0;
294}
295
Bartlomiej Zolnierkiewiczac95bee2008-04-26 22:25:14 +0200296static const struct ide_port_ops palm_bk3710_ports_ops = {
297 .set_pio_mode = palm_bk3710_set_pio_mode,
298 .set_dma_mode = palm_bk3710_set_dma_mode,
299 .cable_detect = palm_bk3710_cable_detect,
300};
Bartlomiej Zolnierkiewiczc79b60d2008-02-11 00:32:13 +0100301
Sergei Shtylyova0f403b2008-07-24 22:53:34 +0200302static struct ide_port_info __devinitdata palm_bk3710_port_info = {
Bartlomiej Zolnierkiewiczb552a2c2008-04-26 22:25:23 +0200303 .init_dma = palm_bk3710_init_dma,
Bartlomiej Zolnierkiewiczac95bee2008-04-26 22:25:14 +0200304 .port_ops = &palm_bk3710_ports_ops,
Sergei Shtylyov3f023b02009-01-06 17:21:01 +0100305 .dma_ops = &sff_dma_ops,
Bartlomiej Zolnierkiewiczc5dd43e2008-04-28 23:44:37 +0200306 .host_flags = IDE_HFLAG_MMIO,
Bartlomiej Zolnierkiewiczc79b60d2008-02-11 00:32:13 +0100307 .pio_mask = ATA_PIO4,
Bartlomiej Zolnierkiewiczc79b60d2008-02-11 00:32:13 +0100308 .mwdma_mask = ATA_MWDMA2,
309};
310
David Brownellbfc2f012008-09-02 20:18:47 +0200311static int __init palm_bk3710_probe(struct platform_device *pdev)
Anton Salnikov7c7e92a2008-02-06 02:57:48 +0100312{
Sergei Shtylyovffab6cf2008-07-08 19:27:22 +0200313 struct clk *clk;
Anton Salnikov7c7e92a2008-02-06 02:57:48 +0100314 struct resource *mem, *irq;
David Brownellef183f62009-01-19 13:46:57 +0100315 void __iomem *base;
Kevin Hilman13b88602009-01-30 11:59:27 -0800316 unsigned long rate, mem_size;
Bartlomiej Zolnierkiewicz6f904d02008-07-23 19:55:57 +0200317 int i, rc;
Bartlomiej Zolnierkiewiczc97c6ac2008-07-23 19:55:50 +0200318 hw_regs_t hw, *hws[] = { &hw, NULL, NULL, NULL };
Anton Salnikov7c7e92a2008-02-06 02:57:48 +0100319
Sergei Shtylyova0f403b2008-07-24 22:53:34 +0200320 clk = clk_get(&pdev->dev, "IDECLK");
Sergei Shtylyovffab6cf2008-07-08 19:27:22 +0200321 if (IS_ERR(clk))
Anton Salnikov7c7e92a2008-02-06 02:57:48 +0100322 return -ENODEV;
323
Sergei Shtylyovffab6cf2008-07-08 19:27:22 +0200324 clk_enable(clk);
325 rate = clk_get_rate(clk);
Sergei Shtylyovffab6cf2008-07-08 19:27:22 +0200326
David Brownell33e86012009-04-23 22:53:43 +0200327 /* NOTE: round *down* to meet minimum timings; we count in clocks */
328 ideclk_period = 1000000000UL / rate;
Anton Salnikov7c7e92a2008-02-06 02:57:48 +0100329
330 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
331 if (mem == NULL) {
332 printk(KERN_ERR "failed to get memory region resource\n");
333 return -ENODEV;
334 }
Sergei Shtylyovce42a542008-06-20 20:53:32 +0200335
Anton Salnikov7c7e92a2008-02-06 02:57:48 +0100336 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
337 if (irq == NULL) {
338 printk(KERN_ERR "failed to get IRQ resource\n");
339 return -ENODEV;
340 }
341
Kevin Hilman13b88602009-01-30 11:59:27 -0800342 mem_size = mem->end - mem->start + 1;
343 if (request_mem_region(mem->start, mem_size, "palm_bk3710") == NULL) {
Sergei Shtylyovce42a542008-06-20 20:53:32 +0200344 printk(KERN_ERR "failed to request memory region\n");
345 return -EBUSY;
346 }
347
Kevin Hilman13b88602009-01-30 11:59:27 -0800348 base = ioremap(mem->start, mem_size);
349 if (!base) {
350 printk(KERN_ERR "failed to map IO memory\n");
351 release_mem_region(mem->start, mem_size);
352 return -ENOMEM;
353 }
Anton Salnikov7c7e92a2008-02-06 02:57:48 +0100354
355 /* Configure the Palm Chip controller */
David Brownellef183f62009-01-19 13:46:57 +0100356 palm_bk3710_chipinit(base);
Anton Salnikov7c7e92a2008-02-06 02:57:48 +0100357
David Brownell33e86012009-04-23 22:53:43 +0200358 memset(&hw, 0, sizeof(hw));
Bartlomiej Zolnierkiewicz7824bc62008-02-11 00:32:12 +0100359 for (i = 0; i < IDE_NR_PORTS - 2; i++)
David Brownellef183f62009-01-19 13:46:57 +0100360 hw.io_ports_array[i] = (unsigned long)
361 (base + IDE_PALM_ATA_PRI_REG_OFFSET + i);
362 hw.io_ports.ctl_addr = (unsigned long)
363 (base + IDE_PALM_ATA_PRI_CTL_OFFSET);
Bartlomiej Zolnierkiewicz7824bc62008-02-11 00:32:12 +0100364 hw.irq = irq->start;
David Brownellbfc2f012008-09-02 20:18:47 +0200365 hw.dev = &pdev->dev;
Bartlomiej Zolnierkiewicz7824bc62008-02-11 00:32:12 +0100366 hw.chipset = ide_palm3710;
Anton Salnikov7c7e92a2008-02-06 02:57:48 +0100367
Sergei Shtylyova0f403b2008-07-24 22:53:34 +0200368 palm_bk3710_port_info.udma_mask = rate < 100000000 ? ATA_UDMA4 :
369 ATA_UDMA5;
370
David Brownell33e86012009-04-23 22:53:43 +0200371 /* Register the IDE interface with Linux */
Bartlomiej Zolnierkiewicz6f904d02008-07-23 19:55:57 +0200372 rc = ide_host_add(&palm_bk3710_port_info, hws, NULL);
373 if (rc)
Bartlomiej Zolnierkiewicz7824bc62008-02-11 00:32:12 +0100374 goto out;
375
Anton Salnikov7c7e92a2008-02-06 02:57:48 +0100376 return 0;
Bartlomiej Zolnierkiewicz7824bc62008-02-11 00:32:12 +0100377out:
378 printk(KERN_WARNING "Palm Chip BK3710 IDE Register Fail\n");
Bartlomiej Zolnierkiewicz6f904d02008-07-23 19:55:57 +0200379 return rc;
Anton Salnikov7c7e92a2008-02-06 02:57:48 +0100380}
381
Kay Sievers458622f2008-04-18 13:41:57 -0700382/* work with hotplug and coldplug */
383MODULE_ALIAS("platform:palm_bk3710");
384
Anton Salnikov7c7e92a2008-02-06 02:57:48 +0100385static struct platform_driver platform_bk_driver = {
386 .driver = {
387 .name = "palm_bk3710",
Kay Sievers458622f2008-04-18 13:41:57 -0700388 .owner = THIS_MODULE,
Anton Salnikov7c7e92a2008-02-06 02:57:48 +0100389 },
Anton Salnikov7c7e92a2008-02-06 02:57:48 +0100390};
391
392static int __init palm_bk3710_init(void)
393{
David Brownellbfc2f012008-09-02 20:18:47 +0200394 return platform_driver_probe(&platform_bk_driver, palm_bk3710_probe);
Anton Salnikov7c7e92a2008-02-06 02:57:48 +0100395}
396
397module_init(palm_bk3710_init);
398MODULE_LICENSE("GPL");