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Tony Lindgren1dbae812005-11-10 14:26:51 +00001/*
Uwe Zeisbergerf30c2262006-10-03 23:01:26 +02002 * linux/arch/arm/mach-omap2/irq.c
Tony Lindgren1dbae812005-11-10 14:26:51 +00003 *
4 * Interrupt handler for OMAP2 boards.
5 *
6 * Copyright (C) 2005 Nokia Corporation
7 * Author: Paul Mundt <paul.mundt@nokia.com>
8 *
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
11 * for more details.
12 */
13#include <linux/kernel.h>
Benoit Cousson52fa2122011-11-30 19:21:07 +010014#include <linux/module.h>
Tony Lindgren1dbae812005-11-10 14:26:51 +000015#include <linux/init.h>
Tony Lindgren1dbae812005-11-10 14:26:51 +000016#include <linux/interrupt.h>
Paul Walmsley2e7509e2008-10-09 17:51:28 +030017#include <linux/io.h>
Tony Lindgrenee0839c2012-02-24 10:34:35 -080018
Marc Zyngier2db14992011-09-06 09:56:17 +010019#include <asm/exception.h>
Benoit Cousson52fa2122011-11-30 19:21:07 +010020#include <linux/irqdomain.h>
21#include <linux/of.h>
22#include <linux/of_address.h>
R Sricharanc4082d42012-06-05 16:31:06 +053023#include <linux/of_irq.h>
Tony Lindgren1dbae812005-11-10 14:26:51 +000024
Felipe Balbi85980662014-09-15 16:15:02 -050025#include "irqchip.h"
26
27/* Define these here for now until we drop all board-files */
28#define OMAP24XX_IC_BASE 0x480fe000
29#define OMAP34XX_IC_BASE 0x48200000
Paul Walmsley2e7509e2008-10-09 17:51:28 +030030
31/* selected INTC register offsets */
32
33#define INTC_REVISION 0x0000
34#define INTC_SYSCONFIG 0x0010
35#define INTC_SYSSTATUS 0x0014
Tony Lindgren6ccc4c02008-12-10 17:36:52 -080036#define INTC_SIR 0x0040
Paul Walmsley2e7509e2008-10-09 17:51:28 +030037#define INTC_CONTROL 0x0048
Rajendra Nayak0addd612008-09-26 17:48:20 +053038#define INTC_PROTECTION 0x004C
39#define INTC_IDLE 0x0050
40#define INTC_THRESHOLD 0x0068
41#define INTC_MIR0 0x0084
Paul Walmsley2e7509e2008-10-09 17:51:28 +030042#define INTC_MIR_CLEAR0 0x0088
43#define INTC_MIR_SET0 0x008c
44#define INTC_PENDING_IRQ0 0x0098
Felipe Balbi11983652014-09-08 17:54:37 -070045#define INTC_PENDING_IRQ1 0x00b8
46#define INTC_PENDING_IRQ2 0x00d8
47#define INTC_PENDING_IRQ3 0x00f8
Felipe Balbi33c7c7b2014-09-08 17:54:32 -070048#define INTC_ILR0 0x0100
Tony Lindgren1dbae812005-11-10 14:26:51 +000049
Marc Zyngier2db14992011-09-06 09:56:17 +010050#define ACTIVEIRQ_MASK 0x7f /* omap2/3 active interrupt bits */
Felipe Balbia88ab432014-09-08 17:54:35 -070051#define INTCPS_NR_ILR_REGS 128
Felipe Balbi74b6c8e2014-09-15 16:15:08 -050052#define INTCPS_NR_MIR_REGS 4
Marc Zyngier2db14992011-09-06 09:56:17 +010053
Felipe Balbib3079142014-09-15 16:15:07 -050054#define INTC_IDLE_FUNCIDLE (1 << 0)
55#define INTC_IDLE_TURBO (1 << 1)
56
Felipe Balbi9836ee92014-09-15 16:15:06 -050057#define INTC_PROTECTION_ENABLE (1 << 0)
58
Felipe Balbi272a8b02014-09-08 17:54:38 -070059struct omap_intc_regs {
Rajendra Nayak0addd612008-09-26 17:48:20 +053060 u32 sysconfig;
61 u32 protection;
62 u32 idle;
63 u32 threshold;
Felipe Balbia88ab432014-09-08 17:54:35 -070064 u32 ilr[INTCPS_NR_ILR_REGS];
Rajendra Nayak0addd612008-09-26 17:48:20 +053065 u32 mir[INTCPS_NR_MIR_REGS];
66};
Felipe Balbi131b48c2014-09-08 17:54:42 -070067static struct omap_intc_regs intc_context;
68
69static struct irq_domain *domain;
70static void __iomem *omap_irq_base;
Felipe Balbi52b1e122014-09-08 17:54:57 -070071static int omap_nr_pending = 3;
Felipe Balbi131b48c2014-09-08 17:54:42 -070072static int omap_nr_irqs = 96;
Rajendra Nayak0addd612008-09-26 17:48:20 +053073
Felipe Balbi71be00c2014-09-08 17:54:32 -070074static void intc_writel(u32 reg, u32 val)
Paul Walmsley2e7509e2008-10-09 17:51:28 +030075{
Felipe Balbi71be00c2014-09-08 17:54:32 -070076 writel_relaxed(val, omap_irq_base + reg);
Paul Walmsley2e7509e2008-10-09 17:51:28 +030077}
78
Felipe Balbi71be00c2014-09-08 17:54:32 -070079static u32 intc_readl(u32 reg)
Paul Walmsley2e7509e2008-10-09 17:51:28 +030080{
Felipe Balbi71be00c2014-09-08 17:54:32 -070081 return readl_relaxed(omap_irq_base + reg);
Paul Walmsley2e7509e2008-10-09 17:51:28 +030082}
83
Felipe Balbi131b48c2014-09-08 17:54:42 -070084void omap_intc_save_context(void)
85{
86 int i;
87
88 intc_context.sysconfig =
89 intc_readl(INTC_SYSCONFIG);
90 intc_context.protection =
91 intc_readl(INTC_PROTECTION);
92 intc_context.idle =
93 intc_readl(INTC_IDLE);
94 intc_context.threshold =
95 intc_readl(INTC_THRESHOLD);
96
97 for (i = 0; i < omap_nr_irqs; i++)
98 intc_context.ilr[i] =
99 intc_readl((INTC_ILR0 + 0x4 * i));
100 for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
101 intc_context.mir[i] =
102 intc_readl(INTC_MIR0 + (0x20 * i));
103}
104
105void omap_intc_restore_context(void)
106{
107 int i;
108
109 intc_writel(INTC_SYSCONFIG, intc_context.sysconfig);
110 intc_writel(INTC_PROTECTION, intc_context.protection);
111 intc_writel(INTC_IDLE, intc_context.idle);
112 intc_writel(INTC_THRESHOLD, intc_context.threshold);
113
114 for (i = 0; i < omap_nr_irqs; i++)
115 intc_writel(INTC_ILR0 + 0x4 * i,
116 intc_context.ilr[i]);
117
118 for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
119 intc_writel(INTC_MIR0 + 0x20 * i,
120 intc_context.mir[i]);
121 /* MIRs are saved and restore with other PRCM registers */
122}
123
124void omap3_intc_prepare_idle(void)
125{
126 /*
127 * Disable autoidle as it can stall interrupt controller,
128 * cf. errata ID i540 for 3430 (all revisions up to 3.1.x)
129 */
130 intc_writel(INTC_SYSCONFIG, 0);
Felipe Balbib3079142014-09-15 16:15:07 -0500131 intc_writel(INTC_IDLE, INTC_IDLE_TURBO);
Felipe Balbi131b48c2014-09-08 17:54:42 -0700132}
133
134void omap3_intc_resume_idle(void)
135{
136 /* Re-enable autoidle */
137 intc_writel(INTC_SYSCONFIG, 1);
Felipe Balbib3079142014-09-15 16:15:07 -0500138 intc_writel(INTC_IDLE, 0);
Felipe Balbi131b48c2014-09-08 17:54:42 -0700139}
140
Tony Lindgren1dbae812005-11-10 14:26:51 +0000141/* XXX: FIQ and additional INTC support (only MPU at the moment) */
Lennert Buytenhekdf303472010-11-29 10:39:59 +0100142static void omap_ack_irq(struct irq_data *d)
Tony Lindgren1dbae812005-11-10 14:26:51 +0000143{
Felipe Balbi71be00c2014-09-08 17:54:32 -0700144 intc_writel(INTC_CONTROL, 0x1);
Tony Lindgren1dbae812005-11-10 14:26:51 +0000145}
146
Lennert Buytenhekdf303472010-11-29 10:39:59 +0100147static void omap_mask_ack_irq(struct irq_data *d)
Tony Lindgren1dbae812005-11-10 14:26:51 +0000148{
Tony Lindgren667a11f2011-05-16 02:07:38 -0700149 irq_gc_mask_disable_reg(d);
Lennert Buytenhekdf303472010-11-29 10:39:59 +0100150 omap_ack_irq(d);
Tony Lindgren1dbae812005-11-10 14:26:51 +0000151}
152
Felipe Balbia88ab432014-09-08 17:54:35 -0700153static void __init omap_irq_soft_reset(void)
Tony Lindgren1dbae812005-11-10 14:26:51 +0000154{
155 unsigned long tmp;
156
Felipe Balbi71be00c2014-09-08 17:54:32 -0700157 tmp = intc_readl(INTC_REVISION) & 0xff;
Felipe Balbia88ab432014-09-08 17:54:35 -0700158
Paul Walmsley7852ec02012-07-26 00:54:26 -0600159 pr_info("IRQ: Found an INTC at 0x%p (revision %ld.%ld) with %d interrupts\n",
Felipe Balbia88ab432014-09-08 17:54:35 -0700160 omap_irq_base, tmp >> 4, tmp & 0xf, omap_nr_irqs);
Tony Lindgren1dbae812005-11-10 14:26:51 +0000161
Felipe Balbi71be00c2014-09-08 17:54:32 -0700162 tmp = intc_readl(INTC_SYSCONFIG);
Tony Lindgren1dbae812005-11-10 14:26:51 +0000163 tmp |= 1 << 1; /* soft reset */
Felipe Balbi71be00c2014-09-08 17:54:32 -0700164 intc_writel(INTC_SYSCONFIG, tmp);
Tony Lindgren1dbae812005-11-10 14:26:51 +0000165
Felipe Balbi71be00c2014-09-08 17:54:32 -0700166 while (!(intc_readl(INTC_SYSSTATUS) & 0x1))
Tony Lindgren1dbae812005-11-10 14:26:51 +0000167 /* Wait for reset to complete */;
Juha Yrjola375e12a2006-12-06 17:13:50 -0800168
169 /* Enable autoidle */
Felipe Balbi71be00c2014-09-08 17:54:32 -0700170 intc_writel(INTC_SYSCONFIG, 1 << 0);
Tony Lindgren1dbae812005-11-10 14:26:51 +0000171}
172
Jouni Hogander94434532009-02-03 15:49:04 -0800173int omap_irq_pending(void)
174{
Felipe Balbi6bd0f162014-09-15 16:15:03 -0500175 int i;
Jouni Hogander94434532009-02-03 15:49:04 -0800176
Felipe Balbi6bd0f162014-09-15 16:15:03 -0500177 for (i = 0; i < omap_nr_pending; i++)
178 if (intc_readl(INTC_PENDING_IRQ0 + (0x20 * i)))
Felipe Balbia88ab432014-09-08 17:54:35 -0700179 return 1;
Jouni Hogander94434532009-02-03 15:49:04 -0800180 return 0;
181}
182
Felipe Balbi131b48c2014-09-08 17:54:42 -0700183void omap3_intc_suspend(void)
184{
185 /* A pending interrupt would prevent OMAP from entering suspend */
186 omap_ack_irq(NULL);
187}
188
Felipe Balbi55601c9f2014-09-08 17:54:58 -0700189static int __init omap_alloc_gc_of(struct irq_domain *d, void __iomem *base)
190{
191 int ret;
192 int i;
193
194 ret = irq_alloc_domain_generic_chips(d, 32, 1, "INTC",
195 handle_level_irq, IRQ_NOREQUEST | IRQ_NOPROBE,
196 IRQ_LEVEL, 0);
197 if (ret) {
198 pr_warn("Failed to allocate irq chips\n");
199 return ret;
200 }
201
202 for (i = 0; i < omap_nr_pending; i++) {
203 struct irq_chip_generic *gc;
204 struct irq_chip_type *ct;
205
206 gc = irq_get_domain_generic_chip(d, 32 * i);
207 gc->reg_base = base;
208 ct = gc->chip_types;
209
210 ct->type = IRQ_TYPE_LEVEL_MASK;
211 ct->handler = handle_level_irq;
212
213 ct->chip.irq_ack = omap_mask_ack_irq;
214 ct->chip.irq_mask = irq_gc_mask_disable_reg;
215 ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
216
217 ct->chip.flags |= IRQCHIP_SKIP_SET_WAKE;
218
219 ct->regs.enable = INTC_MIR_CLEAR0 + 32 * i;
220 ct->regs.disable = INTC_MIR_SET0 + 32 * i;
221 }
222
223 return 0;
224}
225
226static void __init omap_alloc_gc_legacy(void __iomem *base,
227 unsigned int irq_start, unsigned int num)
Tony Lindgren667a11f2011-05-16 02:07:38 -0700228{
229 struct irq_chip_generic *gc;
230 struct irq_chip_type *ct;
231
232 gc = irq_alloc_generic_chip("INTC", 1, irq_start, base,
Felipe Balbi55601c9f2014-09-08 17:54:58 -0700233 handle_level_irq);
Tony Lindgren667a11f2011-05-16 02:07:38 -0700234 ct = gc->chip_types;
235 ct->chip.irq_ack = omap_mask_ack_irq;
236 ct->chip.irq_mask = irq_gc_mask_disable_reg;
237 ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
NeilBrowne3c83c22012-04-25 13:05:24 +1000238 ct->chip.flags |= IRQCHIP_SKIP_SET_WAKE;
Tony Lindgren667a11f2011-05-16 02:07:38 -0700239
Tony Lindgren667a11f2011-05-16 02:07:38 -0700240 ct->regs.enable = INTC_MIR_CLEAR0;
241 ct->regs.disable = INTC_MIR_SET0;
242 irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
Felipe Balbi55601c9f2014-09-08 17:54:58 -0700243 IRQ_NOREQUEST | IRQ_NOPROBE, 0);
Tony Lindgren667a11f2011-05-16 02:07:38 -0700244}
245
Felipe Balbi55601c9f2014-09-08 17:54:58 -0700246static int __init omap_init_irq_of(struct device_node *node)
247{
248 int ret;
249
250 omap_irq_base = of_iomap(node, 0);
251 if (WARN_ON(!omap_irq_base))
252 return -ENOMEM;
253
254 domain = irq_domain_add_linear(node, omap_nr_irqs,
255 &irq_generic_chip_ops, NULL);
256
257 omap_irq_soft_reset();
258
259 ret = omap_alloc_gc_of(domain, omap_irq_base);
260 if (ret < 0)
261 irq_domain_remove(domain);
262
263 return ret;
264}
265
Felipe Balbi4b149e42015-01-06 14:38:08 -0600266static int __init omap_init_irq_legacy(u32 base, struct device_node *node)
Tony Lindgren1dbae812005-11-10 14:26:51 +0000267{
Felipe Balbia88ab432014-09-08 17:54:35 -0700268 int j, irq_base;
Tony Lindgren1dbae812005-11-10 14:26:51 +0000269
Tony Lindgren741e3a82011-05-17 03:51:26 -0700270 omap_irq_base = ioremap(base, SZ_4K);
271 if (WARN_ON(!omap_irq_base))
Felipe Balbi55601c9f2014-09-08 17:54:58 -0700272 return -ENOMEM;
Tony Lindgren741e3a82011-05-17 03:51:26 -0700273
Felipe Balbia74f0a12014-09-08 17:54:55 -0700274 irq_base = irq_alloc_descs(-1, 0, omap_nr_irqs, 0);
Benoit Cousson52fa2122011-11-30 19:21:07 +0100275 if (irq_base < 0) {
276 pr_warn("Couldn't allocate IRQ numbers\n");
277 irq_base = 0;
278 }
279
Felipe Balbi4b149e42015-01-06 14:38:08 -0600280 domain = irq_domain_add_legacy(node, omap_nr_irqs, irq_base, 0,
Felipe Balbia88ab432014-09-08 17:54:35 -0700281 &irq_domain_simple_ops, NULL);
Benoit Cousson52fa2122011-11-30 19:21:07 +0100282
Felipe Balbia88ab432014-09-08 17:54:35 -0700283 omap_irq_soft_reset();
Tony Lindgren1dbae812005-11-10 14:26:51 +0000284
Felipe Balbia88ab432014-09-08 17:54:35 -0700285 for (j = 0; j < omap_nr_irqs; j += 32)
Felipe Balbi55601c9f2014-09-08 17:54:58 -0700286 omap_alloc_gc_legacy(omap_irq_base + j, j + irq_base, 32);
287
288 return 0;
289}
290
Felipe Balbi9836ee92014-09-15 16:15:06 -0500291static void __init omap_irq_enable_protection(void)
292{
293 u32 reg;
294
295 reg = intc_readl(INTC_PROTECTION);
296 reg |= INTC_PROTECTION_ENABLE;
297 intc_writel(INTC_PROTECTION, reg);
298}
299
Felipe Balbi55601c9f2014-09-08 17:54:58 -0700300static int __init omap_init_irq(u32 base, struct device_node *node)
301{
Felipe Balbi9836ee92014-09-15 16:15:06 -0500302 int ret;
303
Felipe Balbi4b149e42015-01-06 14:38:08 -0600304 /*
305 * FIXME legacy OMAP DMA driver sitting under arch/arm/plat-omap/dma.c
306 * depends is still not ready for linear IRQ domains; because of that
307 * we need to temporarily "blacklist" OMAP2 and OMAP3 devices from using
308 * linear IRQ Domain until that driver is finally fixed.
309 */
310 if (of_device_is_compatible(node, "ti,omap2-intc") ||
311 of_device_is_compatible(node, "ti,omap3-intc")) {
312 struct resource res;
313
314 if (of_address_to_resource(node, 0, &res))
315 return -ENOMEM;
316
317 base = res.start;
318 ret = omap_init_irq_legacy(base, node);
319 } else if (node) {
Felipe Balbi9836ee92014-09-15 16:15:06 -0500320 ret = omap_init_irq_of(node);
Felipe Balbi4b149e42015-01-06 14:38:08 -0600321 } else {
322 ret = omap_init_irq_legacy(base, NULL);
323 }
Felipe Balbi9836ee92014-09-15 16:15:06 -0500324
325 if (ret == 0)
326 omap_irq_enable_protection();
327
328 return ret;
Tony Lindgren1dbae812005-11-10 14:26:51 +0000329}
330
Felipe Balbi2aced892014-09-08 17:54:52 -0700331static asmlinkage void __exception_irq_entry
332omap_intc_handle_irq(struct pt_regs *regs)
Marc Zyngier2db14992011-09-06 09:56:17 +0100333{
Felipe Balbid6a7c5c2014-09-08 17:54:57 -0700334 u32 irqnr = 0;
Stefan Sørensen698b4852014-03-06 16:27:15 +0100335 int handled_irq = 0;
Felipe Balbid6a7c5c2014-09-08 17:54:57 -0700336 int i;
Marc Zyngier2db14992011-09-06 09:56:17 +0100337
338 do {
Felipe Balbid6a7c5c2014-09-08 17:54:57 -0700339 for (i = 0; i < omap_nr_pending; i++) {
340 irqnr = intc_readl(INTC_PENDING_IRQ0 + (0x20 * i));
341 if (irqnr)
342 goto out;
343 }
Marc Zyngier2db14992011-09-06 09:56:17 +0100344
345out:
346 if (!irqnr)
347 break;
348
Felipe Balbi11983652014-09-08 17:54:37 -0700349 irqnr = intc_readl(INTC_SIR);
Marc Zyngier2db14992011-09-06 09:56:17 +0100350 irqnr &= ACTIVEIRQ_MASK;
351
Benoit Cousson52fa2122011-11-30 19:21:07 +0100352 if (irqnr) {
Linus Torvalds782d59c2014-10-09 06:42:04 -0400353 handle_domain_irq(domain, irqnr, regs);
Stefan Sørensen698b4852014-03-06 16:27:15 +0100354 handled_irq = 1;
Benoit Cousson52fa2122011-11-30 19:21:07 +0100355 }
Marc Zyngier2db14992011-09-06 09:56:17 +0100356 } while (irqnr);
Stefan Sørensen698b4852014-03-06 16:27:15 +0100357
Felipe Balbi503b8d12014-09-15 16:15:04 -0500358 /*
359 * If an irq is masked or deasserted while active, we will
Stefan Sørensen698b4852014-03-06 16:27:15 +0100360 * keep ending up here with no irq handled. So remove it from
Felipe Balbi503b8d12014-09-15 16:15:04 -0500361 * the INTC with an ack.
362 */
Stefan Sørensen698b4852014-03-06 16:27:15 +0100363 if (!handled_irq)
364 omap_ack_irq(NULL);
Marc Zyngier2db14992011-09-06 09:56:17 +0100365}
366
Felipe Balbia4d3c5d2014-09-08 17:54:51 -0700367void __init omap2_init_irq(void)
368{
Felipe Balbia74f0a12014-09-08 17:54:55 -0700369 omap_nr_irqs = 96;
Felipe Balbi52b1e122014-09-08 17:54:57 -0700370 omap_nr_pending = 3;
Felipe Balbia74f0a12014-09-08 17:54:55 -0700371 omap_init_irq(OMAP24XX_IC_BASE, NULL);
Felipe Balbi2aced892014-09-08 17:54:52 -0700372 set_handle_irq(omap_intc_handle_irq);
Felipe Balbia4d3c5d2014-09-08 17:54:51 -0700373}
374
375void __init omap3_init_irq(void)
376{
Felipe Balbia74f0a12014-09-08 17:54:55 -0700377 omap_nr_irqs = 96;
Felipe Balbi52b1e122014-09-08 17:54:57 -0700378 omap_nr_pending = 3;
Felipe Balbia74f0a12014-09-08 17:54:55 -0700379 omap_init_irq(OMAP34XX_IC_BASE, NULL);
Felipe Balbi2aced892014-09-08 17:54:52 -0700380 set_handle_irq(omap_intc_handle_irq);
Felipe Balbia4d3c5d2014-09-08 17:54:51 -0700381}
382
383void __init ti81xx_init_irq(void)
384{
Felipe Balbia74f0a12014-09-08 17:54:55 -0700385 omap_nr_irqs = 96;
Felipe Balbi52b1e122014-09-08 17:54:57 -0700386 omap_nr_pending = 4;
Felipe Balbia74f0a12014-09-08 17:54:55 -0700387 omap_init_irq(OMAP34XX_IC_BASE, NULL);
Felipe Balbi2aced892014-09-08 17:54:52 -0700388 set_handle_irq(omap_intc_handle_irq);
Felipe Balbia4d3c5d2014-09-08 17:54:51 -0700389}
390
Felipe Balbi00b6b032014-09-08 17:54:43 -0700391static int __init intc_of_init(struct device_node *node,
Benoit Cousson52fa2122011-11-30 19:21:07 +0100392 struct device_node *parent)
393{
Felipe Balbi55601c9f2014-09-08 17:54:58 -0700394 int ret;
Felipe Balbia74f0a12014-09-08 17:54:55 -0700395
Felipe Balbi52b1e122014-09-08 17:54:57 -0700396 omap_nr_pending = 3;
Felipe Balbia74f0a12014-09-08 17:54:55 -0700397 omap_nr_irqs = 96;
Benoit Cousson52fa2122011-11-30 19:21:07 +0100398
399 if (WARN_ON(!node))
400 return -ENODEV;
401
Felipe Balbi52b1e122014-09-08 17:54:57 -0700402 if (of_device_is_compatible(node, "ti,am33xx-intc")) {
Felipe Balbia74f0a12014-09-08 17:54:55 -0700403 omap_nr_irqs = 128;
Felipe Balbi52b1e122014-09-08 17:54:57 -0700404 omap_nr_pending = 4;
405 }
Felipe Balbi470f30d2014-09-08 17:54:47 -0700406
Felipe Balbi55601c9f2014-09-08 17:54:58 -0700407 ret = omap_init_irq(-1, of_node_get(node));
408 if (ret < 0)
409 return ret;
Benoit Cousson52fa2122011-11-30 19:21:07 +0100410
Felipe Balbi2aced892014-09-08 17:54:52 -0700411 set_handle_irq(omap_intc_handle_irq);
Felipe Balbib15c76b2014-09-08 17:54:43 -0700412
Benoit Cousson52fa2122011-11-30 19:21:07 +0100413 return 0;
414}
415
Felipe Balbia35db9a2014-09-08 17:54:46 -0700416IRQCHIP_DECLARE(omap2_intc, "ti,omap2-intc", intc_of_init);
417IRQCHIP_DECLARE(omap3_intc, "ti,omap3-intc", intc_of_init);
418IRQCHIP_DECLARE(am33xx_intc, "ti,am33xx-intc", intc_of_init);