blob: 11d366ad4036021cc6623be569d46d14e8e6b381 [file] [log] [blame]
Ben Skeggs6ee73862009-12-11 19:24:15 +10001/*
2 * Copyright (C) 2008 Maarten Maathuis.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial
15 * portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 *
25 */
26
27#include "nv50_display.h"
28#include "nouveau_crtc.h"
29#include "nouveau_encoder.h"
30#include "nouveau_connector.h"
31#include "nouveau_fb.h"
Dave Airlie4abe3522010-03-30 05:34:18 +000032#include "nouveau_fbcon.h"
Ben Skeggsa8eaebc2010-09-01 15:24:31 +100033#include "nouveau_ramht.h"
Ben Skeggs6ee73862009-12-11 19:24:15 +100034#include "drm_crtc_helper.h"
35
Ben Skeggs8597a1b2010-09-06 11:39:25 +100036static inline int
37nv50_sor_nr(struct drm_device *dev)
38{
39 struct drm_nouveau_private *dev_priv = dev->dev_private;
40
41 if (dev_priv->chipset < 0x90 ||
42 dev_priv->chipset == 0x92 ||
43 dev_priv->chipset == 0xa0)
44 return 2;
45
46 return 4;
47}
48
Ben Skeggs6ee73862009-12-11 19:24:15 +100049static void
50nv50_evo_channel_del(struct nouveau_channel **pchan)
51{
52 struct nouveau_channel *chan = *pchan;
53
54 if (!chan)
55 return;
56 *pchan = NULL;
57
58 nouveau_gpuobj_channel_takedown(chan);
Ben Skeggs9d59e8a2010-08-27 13:04:41 +100059 nouveau_bo_unmap(chan->pushbuf_bo);
Ben Skeggs6ee73862009-12-11 19:24:15 +100060 nouveau_bo_ref(NULL, &chan->pushbuf_bo);
61
62 if (chan->user)
63 iounmap(chan->user);
64
65 kfree(chan);
66}
67
68static int
69nv50_evo_dmaobj_new(struct nouveau_channel *evo, uint32_t class, uint32_t name,
70 uint32_t tile_flags, uint32_t magic_flags,
71 uint32_t offset, uint32_t limit)
72{
73 struct drm_nouveau_private *dev_priv = evo->dev->dev_private;
74 struct drm_device *dev = evo->dev;
75 struct nouveau_gpuobj *obj = NULL;
76 int ret;
77
78 ret = nouveau_gpuobj_new(dev, evo, 6*4, 32, 0, &obj);
79 if (ret)
80 return ret;
81 obj->engine = NVOBJ_ENGINE_DISPLAY;
82
Ben Skeggsb3beb162010-09-01 15:24:29 +100083 nv_wo32(obj, 0, (tile_flags << 22) | (magic_flags << 16) | class);
84 nv_wo32(obj, 4, limit);
85 nv_wo32(obj, 8, offset);
86 nv_wo32(obj, 12, 0x00000000);
87 nv_wo32(obj, 16, 0x00000000);
Ben Skeggs0165d152010-08-04 17:24:57 +100088 if (dev_priv->card_type < NV_C0)
Ben Skeggsb3beb162010-09-01 15:24:29 +100089 nv_wo32(obj, 20, 0x00010000);
Ben Skeggs0165d152010-08-04 17:24:57 +100090 else
Ben Skeggsb3beb162010-09-01 15:24:29 +100091 nv_wo32(obj, 20, 0x00020000);
Ben Skeggsf56cb862010-07-08 11:29:10 +100092 dev_priv->engine.instmem.flush(dev);
Ben Skeggs6ee73862009-12-11 19:24:15 +100093
Ben Skeggsa8eaebc2010-09-01 15:24:31 +100094 ret = nouveau_ramht_insert(evo, name, obj);
95 nouveau_gpuobj_ref(NULL, &obj);
96 if (ret) {
97 return ret;
98 }
99
Ben Skeggs6ee73862009-12-11 19:24:15 +1000100 return 0;
101}
102
103static int
104nv50_evo_channel_new(struct drm_device *dev, struct nouveau_channel **pchan)
105{
106 struct drm_nouveau_private *dev_priv = dev->dev_private;
Ben Skeggsa8eaebc2010-09-01 15:24:31 +1000107 struct nouveau_gpuobj *ramht = NULL;
Ben Skeggs6ee73862009-12-11 19:24:15 +1000108 struct nouveau_channel *chan;
109 int ret;
110
111 chan = kzalloc(sizeof(struct nouveau_channel), GFP_KERNEL);
112 if (!chan)
113 return -ENOMEM;
114 *pchan = chan;
115
116 chan->id = -1;
117 chan->dev = dev;
118 chan->user_get = 4;
119 chan->user_put = 0;
120
Ben Skeggsa8eaebc2010-09-01 15:24:31 +1000121 ret = nouveau_gpuobj_new(dev, NULL, 32768, 0x1000,
122 NVOBJ_FLAG_ZERO_ALLOC, &chan->ramin);
Ben Skeggs6ee73862009-12-11 19:24:15 +1000123 if (ret) {
124 NV_ERROR(dev, "Error allocating EVO channel memory: %d\n", ret);
125 nv50_evo_channel_del(pchan);
126 return ret;
127 }
128
Ben Skeggsde3a6c02010-09-01 15:24:30 +1000129 ret = drm_mm_init(&chan->ramin_heap, 0, 32768);
Ben Skeggs6ee73862009-12-11 19:24:15 +1000130 if (ret) {
131 NV_ERROR(dev, "Error initialising EVO PRAMIN heap: %d\n", ret);
132 nv50_evo_channel_del(pchan);
133 return ret;
134 }
135
Ben Skeggsa8eaebc2010-09-01 15:24:31 +1000136 ret = nouveau_gpuobj_new(dev, chan, 4096, 16, 0, &ramht);
Ben Skeggs6ee73862009-12-11 19:24:15 +1000137 if (ret) {
138 NV_ERROR(dev, "Unable to allocate EVO RAMHT: %d\n", ret);
139 nv50_evo_channel_del(pchan);
140 return ret;
141 }
142
Ben Skeggsa8eaebc2010-09-01 15:24:31 +1000143 ret = nouveau_ramht_new(dev, ramht, &chan->ramht);
144 nouveau_gpuobj_ref(NULL, &ramht);
145 if (ret) {
146 nv50_evo_channel_del(pchan);
147 return ret;
148 }
149
Ben Skeggs6ee73862009-12-11 19:24:15 +1000150 if (dev_priv->chipset != 0x50) {
151 ret = nv50_evo_dmaobj_new(chan, 0x3d, NvEvoFB16, 0x70, 0x19,
152 0, 0xffffffff);
153 if (ret) {
154 nv50_evo_channel_del(pchan);
155 return ret;
156 }
157
158
159 ret = nv50_evo_dmaobj_new(chan, 0x3d, NvEvoFB32, 0x7a, 0x19,
160 0, 0xffffffff);
161 if (ret) {
162 nv50_evo_channel_del(pchan);
163 return ret;
164 }
165 }
166
167 ret = nv50_evo_dmaobj_new(chan, 0x3d, NvEvoVRAM, 0, 0x19,
Ben Skeggsa76fb4e2010-03-18 09:45:20 +1000168 0, dev_priv->vram_size);
Ben Skeggs6ee73862009-12-11 19:24:15 +1000169 if (ret) {
170 nv50_evo_channel_del(pchan);
171 return ret;
172 }
173
174 ret = nouveau_bo_new(dev, NULL, 4096, 0, TTM_PL_FLAG_VRAM, 0, 0,
175 false, true, &chan->pushbuf_bo);
176 if (ret == 0)
177 ret = nouveau_bo_pin(chan->pushbuf_bo, TTM_PL_FLAG_VRAM);
178 if (ret) {
179 NV_ERROR(dev, "Error creating EVO DMA push buffer: %d\n", ret);
180 nv50_evo_channel_del(pchan);
181 return ret;
182 }
183
184 ret = nouveau_bo_map(chan->pushbuf_bo);
185 if (ret) {
186 NV_ERROR(dev, "Error mapping EVO DMA push buffer: %d\n", ret);
187 nv50_evo_channel_del(pchan);
188 return ret;
189 }
190
191 chan->user = ioremap(pci_resource_start(dev->pdev, 0) +
192 NV50_PDISPLAY_USER(0), PAGE_SIZE);
193 if (!chan->user) {
194 NV_ERROR(dev, "Error mapping EVO control regs.\n");
195 nv50_evo_channel_del(pchan);
196 return -ENOMEM;
197 }
198
199 return 0;
200}
201
202int
Francisco Jerezc88c2e02010-07-24 17:37:33 +0200203nv50_display_early_init(struct drm_device *dev)
204{
205 return 0;
206}
207
208void
209nv50_display_late_takedown(struct drm_device *dev)
210{
211}
212
213int
Ben Skeggs6ee73862009-12-11 19:24:15 +1000214nv50_display_init(struct drm_device *dev)
215{
216 struct drm_nouveau_private *dev_priv = dev->dev_private;
217 struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
Ben Skeggsee2e0132010-07-26 09:28:25 +1000218 struct nouveau_gpio_engine *pgpio = &dev_priv->engine.gpio;
Ben Skeggs6ee73862009-12-11 19:24:15 +1000219 struct nouveau_channel *evo = dev_priv->evo;
220 struct drm_connector *connector;
Ben Skeggsd0875ed2010-07-23 11:31:08 +1000221 uint32_t val, ram_amount;
Ben Skeggs6ee73862009-12-11 19:24:15 +1000222 uint64_t start;
223 int ret, i;
224
Maarten Maathuisef2bb502009-12-13 16:53:12 +0100225 NV_DEBUG_KMS(dev, "\n");
Ben Skeggs6ee73862009-12-11 19:24:15 +1000226
227 nv_wr32(dev, 0x00610184, nv_rd32(dev, 0x00614004));
228 /*
229 * I think the 0x006101XX range is some kind of main control area
230 * that enables things.
231 */
232 /* CRTC? */
233 for (i = 0; i < 2; i++) {
234 val = nv_rd32(dev, 0x00616100 + (i * 0x800));
235 nv_wr32(dev, 0x00610190 + (i * 0x10), val);
236 val = nv_rd32(dev, 0x00616104 + (i * 0x800));
237 nv_wr32(dev, 0x00610194 + (i * 0x10), val);
238 val = nv_rd32(dev, 0x00616108 + (i * 0x800));
239 nv_wr32(dev, 0x00610198 + (i * 0x10), val);
240 val = nv_rd32(dev, 0x0061610c + (i * 0x800));
241 nv_wr32(dev, 0x0061019c + (i * 0x10), val);
242 }
243 /* DAC */
244 for (i = 0; i < 3; i++) {
245 val = nv_rd32(dev, 0x0061a000 + (i * 0x800));
246 nv_wr32(dev, 0x006101d0 + (i * 0x04), val);
247 }
248 /* SOR */
Ben Skeggs8597a1b2010-09-06 11:39:25 +1000249 for (i = 0; i < nv50_sor_nr(dev); i++) {
Ben Skeggs6ee73862009-12-11 19:24:15 +1000250 val = nv_rd32(dev, 0x0061c000 + (i * 0x800));
251 nv_wr32(dev, 0x006101e0 + (i * 0x04), val);
252 }
Ben Skeggs8597a1b2010-09-06 11:39:25 +1000253 /* EXT */
Ben Skeggs6ee73862009-12-11 19:24:15 +1000254 for (i = 0; i < 3; i++) {
255 val = nv_rd32(dev, 0x0061e000 + (i * 0x800));
256 nv_wr32(dev, 0x006101f0 + (i * 0x04), val);
257 }
258
259 for (i = 0; i < 3; i++) {
260 nv_wr32(dev, NV50_PDISPLAY_DAC_DPMS_CTRL(i), 0x00550000 |
261 NV50_PDISPLAY_DAC_DPMS_CTRL_PENDING);
262 nv_wr32(dev, NV50_PDISPLAY_DAC_CLK_CTRL1(i), 0x00000001);
263 }
264
265 /* This used to be in crtc unblank, but seems out of place there. */
266 nv_wr32(dev, NV50_PDISPLAY_UNK_380, 0);
267 /* RAM is clamped to 256 MiB. */
Ben Skeggsa76fb4e2010-03-18 09:45:20 +1000268 ram_amount = dev_priv->vram_size;
Maarten Maathuisef2bb502009-12-13 16:53:12 +0100269 NV_DEBUG_KMS(dev, "ram_amount %d\n", ram_amount);
Ben Skeggs6ee73862009-12-11 19:24:15 +1000270 if (ram_amount > 256*1024*1024)
271 ram_amount = 256*1024*1024;
272 nv_wr32(dev, NV50_PDISPLAY_RAM_AMOUNT, ram_amount - 1);
273 nv_wr32(dev, NV50_PDISPLAY_UNK_388, 0x150000);
274 nv_wr32(dev, NV50_PDISPLAY_UNK_38C, 0);
275
276 /* The precise purpose is unknown, i suspect it has something to do
277 * with text mode.
278 */
279 if (nv_rd32(dev, NV50_PDISPLAY_INTR_1) & 0x100) {
280 nv_wr32(dev, NV50_PDISPLAY_INTR_1, 0x100);
281 nv_wr32(dev, 0x006194e8, nv_rd32(dev, 0x006194e8) & ~1);
Francisco Jerez4b5c1522010-09-07 17:34:44 +0200282 if (!nv_wait(dev, 0x006194e8, 2, 0)) {
Ben Skeggs6ee73862009-12-11 19:24:15 +1000283 NV_ERROR(dev, "timeout: (0x6194e8 & 2) != 0\n");
284 NV_ERROR(dev, "0x6194e8 = 0x%08x\n",
285 nv_rd32(dev, 0x6194e8));
286 return -EBUSY;
287 }
288 }
289
290 /* taken from nv bug #12637, attempts to un-wedge the hw if it's
291 * stuck in some unspecified state
292 */
293 start = ptimer->read(dev);
294 nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0), 0x2b00);
295 while ((val = nv_rd32(dev, NV50_PDISPLAY_CHANNEL_STAT(0))) & 0x1e0000) {
296 if ((val & 0x9f0000) == 0x20000)
297 nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0),
298 val | 0x800000);
299
300 if ((val & 0x3f0000) == 0x30000)
301 nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0),
302 val | 0x200000);
303
304 if (ptimer->read(dev) - start > 1000000000ULL) {
305 NV_ERROR(dev, "timeout: (0x610200 & 0x1e0000) != 0\n");
306 NV_ERROR(dev, "0x610200 = 0x%08x\n", val);
307 return -EBUSY;
308 }
309 }
310
311 nv_wr32(dev, NV50_PDISPLAY_CTRL_STATE, NV50_PDISPLAY_CTRL_STATE_ENABLE);
312 nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0), 0x1000b03);
Francisco Jerez4b5c1522010-09-07 17:34:44 +0200313 if (!nv_wait(dev, NV50_PDISPLAY_CHANNEL_STAT(0),
314 0x40000000, 0x40000000)) {
Ben Skeggs6ee73862009-12-11 19:24:15 +1000315 NV_ERROR(dev, "timeout: (0x610200 & 0x40000000) == 0x40000000\n");
316 NV_ERROR(dev, "0x610200 = 0x%08x\n",
317 nv_rd32(dev, NV50_PDISPLAY_CHANNEL_STAT(0)));
318 return -EBUSY;
319 }
320
321 for (i = 0; i < 2; i++) {
322 nv_wr32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i), 0x2000);
Francisco Jerez4b5c1522010-09-07 17:34:44 +0200323 if (!nv_wait(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i),
Ben Skeggs6ee73862009-12-11 19:24:15 +1000324 NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS, 0)) {
325 NV_ERROR(dev, "timeout: CURSOR_CTRL2_STATUS == 0\n");
326 NV_ERROR(dev, "CURSOR_CTRL2 = 0x%08x\n",
327 nv_rd32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i)));
328 return -EBUSY;
329 }
330
331 nv_wr32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i),
332 NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_ON);
Francisco Jerez4b5c1522010-09-07 17:34:44 +0200333 if (!nv_wait(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i),
Ben Skeggs6ee73862009-12-11 19:24:15 +1000334 NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS,
335 NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS_ACTIVE)) {
336 NV_ERROR(dev, "timeout: "
337 "CURSOR_CTRL2_STATUS_ACTIVE(%d)\n", i);
338 NV_ERROR(dev, "CURSOR_CTRL2(%d) = 0x%08x\n", i,
339 nv_rd32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i)));
340 return -EBUSY;
341 }
342 }
343
Ben Skeggsa8eaebc2010-09-01 15:24:31 +1000344 nv_wr32(dev, NV50_PDISPLAY_OBJECTS, (evo->ramin->vinst >> 8) | 9);
Ben Skeggs6ee73862009-12-11 19:24:15 +1000345
346 /* initialise fifo */
347 nv_wr32(dev, NV50_PDISPLAY_CHANNEL_DMA_CB(0),
348 ((evo->pushbuf_bo->bo.mem.mm_node->start << PAGE_SHIFT) >> 8) |
349 NV50_PDISPLAY_CHANNEL_DMA_CB_LOCATION_VRAM |
350 NV50_PDISPLAY_CHANNEL_DMA_CB_VALID);
351 nv_wr32(dev, NV50_PDISPLAY_CHANNEL_UNK2(0), 0x00010000);
352 nv_wr32(dev, NV50_PDISPLAY_CHANNEL_UNK3(0), 0x00000002);
Francisco Jerez4b5c1522010-09-07 17:34:44 +0200353 if (!nv_wait(dev, 0x610200, 0x80000000, 0x00000000)) {
Ben Skeggs6ee73862009-12-11 19:24:15 +1000354 NV_ERROR(dev, "timeout: (0x610200 & 0x80000000) == 0\n");
355 NV_ERROR(dev, "0x610200 = 0x%08x\n", nv_rd32(dev, 0x610200));
356 return -EBUSY;
357 }
358 nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0),
359 (nv_rd32(dev, NV50_PDISPLAY_CHANNEL_STAT(0)) & ~0x00000003) |
360 NV50_PDISPLAY_CHANNEL_STAT_DMA_ENABLED);
361 nv_wr32(dev, NV50_PDISPLAY_USER_PUT(0), 0);
362 nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0), 0x01000003 |
363 NV50_PDISPLAY_CHANNEL_STAT_DMA_ENABLED);
364 nv_wr32(dev, 0x610300, nv_rd32(dev, 0x610300) & ~1);
365
366 evo->dma.max = (4096/4) - 2;
367 evo->dma.put = 0;
368 evo->dma.cur = evo->dma.put;
369 evo->dma.free = evo->dma.max - evo->dma.cur;
370
371 ret = RING_SPACE(evo, NOUVEAU_DMA_SKIPS);
372 if (ret)
373 return ret;
374
375 for (i = 0; i < NOUVEAU_DMA_SKIPS; i++)
376 OUT_RING(evo, 0);
377
378 ret = RING_SPACE(evo, 11);
379 if (ret)
380 return ret;
381 BEGIN_RING(evo, 0, NV50_EVO_UNK84, 2);
382 OUT_RING(evo, NV50_EVO_UNK84_NOTIFY_DISABLED);
383 OUT_RING(evo, NV50_EVO_DMA_NOTIFY_HANDLE_NONE);
384 BEGIN_RING(evo, 0, NV50_EVO_CRTC(0, FB_DMA), 1);
385 OUT_RING(evo, NV50_EVO_CRTC_FB_DMA_HANDLE_NONE);
386 BEGIN_RING(evo, 0, NV50_EVO_CRTC(0, UNK0800), 1);
387 OUT_RING(evo, 0);
388 BEGIN_RING(evo, 0, NV50_EVO_CRTC(0, DISPLAY_START), 1);
389 OUT_RING(evo, 0);
390 BEGIN_RING(evo, 0, NV50_EVO_CRTC(0, UNK082C), 1);
391 OUT_RING(evo, 0);
392 FIRE_RING(evo);
Francisco Jerez4b5c1522010-09-07 17:34:44 +0200393 if (!nv_wait(dev, 0x640004, 0xffffffff, evo->dma.put << 2))
Ben Skeggs6ee73862009-12-11 19:24:15 +1000394 NV_ERROR(dev, "evo pushbuf stalled\n");
395
396 /* enable clock change interrupts. */
397 nv_wr32(dev, 0x610028, 0x00010001);
398 nv_wr32(dev, NV50_PDISPLAY_INTR_EN, (NV50_PDISPLAY_INTR_EN_CLK_UNK10 |
399 NV50_PDISPLAY_INTR_EN_CLK_UNK20 |
400 NV50_PDISPLAY_INTR_EN_CLK_UNK40));
401
402 /* enable hotplug interrupts */
Ben Skeggs6ee73862009-12-11 19:24:15 +1000403 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
404 struct nouveau_connector *conn = nouveau_connector(connector);
Ben Skeggs6ee73862009-12-11 19:24:15 +1000405
Ben Skeggs0ccb3a72010-07-26 11:35:37 +1000406 if (conn->dcb->gpio_tag == 0xff)
407 continue;
408
Ben Skeggsee2e0132010-07-26 09:28:25 +1000409 pgpio->irq_enable(dev, conn->dcb->gpio_tag, true);
Ben Skeggs6ee73862009-12-11 19:24:15 +1000410 }
411
412 return 0;
413}
414
415static int nv50_display_disable(struct drm_device *dev)
416{
417 struct drm_nouveau_private *dev_priv = dev->dev_private;
418 struct drm_crtc *drm_crtc;
419 int ret, i;
420
Maarten Maathuisef2bb502009-12-13 16:53:12 +0100421 NV_DEBUG_KMS(dev, "\n");
Ben Skeggs6ee73862009-12-11 19:24:15 +1000422
423 list_for_each_entry(drm_crtc, &dev->mode_config.crtc_list, head) {
424 struct nouveau_crtc *crtc = nouveau_crtc(drm_crtc);
425
426 nv50_crtc_blank(crtc, true);
427 }
428
429 ret = RING_SPACE(dev_priv->evo, 2);
430 if (ret == 0) {
431 BEGIN_RING(dev_priv->evo, 0, NV50_EVO_UPDATE, 1);
432 OUT_RING(dev_priv->evo, 0);
433 }
434 FIRE_RING(dev_priv->evo);
435
436 /* Almost like ack'ing a vblank interrupt, maybe in the spirit of
437 * cleaning up?
438 */
439 list_for_each_entry(drm_crtc, &dev->mode_config.crtc_list, head) {
440 struct nouveau_crtc *crtc = nouveau_crtc(drm_crtc);
441 uint32_t mask = NV50_PDISPLAY_INTR_1_VBLANK_CRTC_(crtc->index);
442
443 if (!crtc->base.enabled)
444 continue;
445
446 nv_wr32(dev, NV50_PDISPLAY_INTR_1, mask);
Francisco Jerez4b5c1522010-09-07 17:34:44 +0200447 if (!nv_wait(dev, NV50_PDISPLAY_INTR_1, mask, mask)) {
Ben Skeggs6ee73862009-12-11 19:24:15 +1000448 NV_ERROR(dev, "timeout: (0x610024 & 0x%08x) == "
449 "0x%08x\n", mask, mask);
450 NV_ERROR(dev, "0x610024 = 0x%08x\n",
451 nv_rd32(dev, NV50_PDISPLAY_INTR_1));
452 }
453 }
454
455 nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0), 0);
456 nv_wr32(dev, NV50_PDISPLAY_CTRL_STATE, 0);
Francisco Jerez4b5c1522010-09-07 17:34:44 +0200457 if (!nv_wait(dev, NV50_PDISPLAY_CHANNEL_STAT(0), 0x1e0000, 0)) {
Ben Skeggs6ee73862009-12-11 19:24:15 +1000458 NV_ERROR(dev, "timeout: (0x610200 & 0x1e0000) == 0\n");
459 NV_ERROR(dev, "0x610200 = 0x%08x\n",
460 nv_rd32(dev, NV50_PDISPLAY_CHANNEL_STAT(0)));
461 }
462
463 for (i = 0; i < 3; i++) {
Francisco Jerez4b5c1522010-09-07 17:34:44 +0200464 if (!nv_wait(dev, NV50_PDISPLAY_SOR_DPMS_STATE(i),
Ben Skeggs6ee73862009-12-11 19:24:15 +1000465 NV50_PDISPLAY_SOR_DPMS_STATE_WAIT, 0)) {
466 NV_ERROR(dev, "timeout: SOR_DPMS_STATE_WAIT(%d) == 0\n", i);
467 NV_ERROR(dev, "SOR_DPMS_STATE(%d) = 0x%08x\n", i,
468 nv_rd32(dev, NV50_PDISPLAY_SOR_DPMS_STATE(i)));
469 }
470 }
471
472 /* disable interrupts. */
473 nv_wr32(dev, NV50_PDISPLAY_INTR_EN, 0x00000000);
474
475 /* disable hotplug interrupts */
476 nv_wr32(dev, 0xe054, 0xffffffff);
477 nv_wr32(dev, 0xe050, 0x00000000);
478 if (dev_priv->chipset >= 0x90) {
479 nv_wr32(dev, 0xe074, 0xffffffff);
480 nv_wr32(dev, 0xe070, 0x00000000);
481 }
482 return 0;
483}
484
485int nv50_display_create(struct drm_device *dev)
486{
487 struct drm_nouveau_private *dev_priv = dev->dev_private;
Ben Skeggs04a39c52010-02-24 10:03:05 +1000488 struct dcb_table *dcb = &dev_priv->vbios.dcb;
Ben Skeggs8f1a6082010-06-28 14:35:50 +1000489 struct drm_connector *connector, *ct;
Ben Skeggs6ee73862009-12-11 19:24:15 +1000490 int ret, i;
491
Maarten Maathuisef2bb502009-12-13 16:53:12 +0100492 NV_DEBUG_KMS(dev, "\n");
Ben Skeggs6ee73862009-12-11 19:24:15 +1000493
494 /* init basic kernel modesetting */
495 drm_mode_config_init(dev);
496
497 /* Initialise some optional connector properties. */
498 drm_mode_create_scaling_mode_property(dev);
499 drm_mode_create_dithering_property(dev);
500
501 dev->mode_config.min_width = 0;
502 dev->mode_config.min_height = 0;
503
504 dev->mode_config.funcs = (void *)&nouveau_mode_config_funcs;
505
506 dev->mode_config.max_width = 8192;
507 dev->mode_config.max_height = 8192;
508
509 dev->mode_config.fb_base = dev_priv->fb_phys;
510
511 /* Create EVO channel */
512 ret = nv50_evo_channel_new(dev, &dev_priv->evo);
513 if (ret) {
514 NV_ERROR(dev, "Error creating EVO channel: %d\n", ret);
515 return ret;
516 }
517
518 /* Create CRTC objects */
519 for (i = 0; i < 2; i++)
520 nv50_crtc_create(dev, i);
521
522 /* We setup the encoders from the BIOS table */
523 for (i = 0 ; i < dcb->entries; i++) {
524 struct dcb_entry *entry = &dcb->entry[i];
525
526 if (entry->location != DCB_LOC_ON_CHIP) {
527 NV_WARN(dev, "Off-chip encoder %d/%d unsupported\n",
528 entry->type, ffs(entry->or) - 1);
529 continue;
530 }
531
Ben Skeggs8f1a6082010-06-28 14:35:50 +1000532 connector = nouveau_connector_create(dev, entry->connector);
533 if (IS_ERR(connector))
534 continue;
535
Ben Skeggs6ee73862009-12-11 19:24:15 +1000536 switch (entry->type) {
537 case OUTPUT_TMDS:
538 case OUTPUT_LVDS:
539 case OUTPUT_DP:
Ben Skeggs8f1a6082010-06-28 14:35:50 +1000540 nv50_sor_create(connector, entry);
Ben Skeggs6ee73862009-12-11 19:24:15 +1000541 break;
542 case OUTPUT_ANALOG:
Ben Skeggs8f1a6082010-06-28 14:35:50 +1000543 nv50_dac_create(connector, entry);
Ben Skeggs6ee73862009-12-11 19:24:15 +1000544 break;
545 default:
546 NV_WARN(dev, "DCB encoder %d unknown\n", entry->type);
547 continue;
548 }
Ben Skeggs6ee73862009-12-11 19:24:15 +1000549 }
550
Ben Skeggs8f1a6082010-06-28 14:35:50 +1000551 list_for_each_entry_safe(connector, ct,
552 &dev->mode_config.connector_list, head) {
553 if (!connector->encoder_ids[0]) {
554 NV_WARN(dev, "%s has no encoders, removing\n",
555 drm_get_connector_name(connector));
556 connector->funcs->destroy(connector);
557 }
Ben Skeggs6ee73862009-12-11 19:24:15 +1000558 }
559
560 ret = nv50_display_init(dev);
Ben Skeggsa1663ed2010-03-25 16:01:04 +1000561 if (ret) {
562 nv50_display_destroy(dev);
Ben Skeggs6ee73862009-12-11 19:24:15 +1000563 return ret;
Ben Skeggsa1663ed2010-03-25 16:01:04 +1000564 }
Ben Skeggs6ee73862009-12-11 19:24:15 +1000565
566 return 0;
567}
568
Francisco Jerezc88c2e02010-07-24 17:37:33 +0200569void
570nv50_display_destroy(struct drm_device *dev)
Ben Skeggs6ee73862009-12-11 19:24:15 +1000571{
572 struct drm_nouveau_private *dev_priv = dev->dev_private;
573
Maarten Maathuisef2bb502009-12-13 16:53:12 +0100574 NV_DEBUG_KMS(dev, "\n");
Ben Skeggs6ee73862009-12-11 19:24:15 +1000575
576 drm_mode_config_cleanup(dev);
577
578 nv50_display_disable(dev);
579 nv50_evo_channel_del(&dev_priv->evo);
Ben Skeggs6ee73862009-12-11 19:24:15 +1000580}
581
Ben Skeggs87c0e0e2010-07-06 08:54:34 +1000582static u16
583nv50_display_script_select(struct drm_device *dev, struct dcb_entry *dcb,
584 u32 mc, int pxclk)
Ben Skeggs6ee73862009-12-11 19:24:15 +1000585{
586 struct drm_nouveau_private *dev_priv = dev->dev_private;
Ben Skeggs75c722d2009-12-21 12:16:52 +1000587 struct nouveau_connector *nv_connector = NULL;
588 struct drm_encoder *encoder;
Ben Skeggs04a39c52010-02-24 10:03:05 +1000589 struct nvbios *bios = &dev_priv->vbios;
Ben Skeggs87c0e0e2010-07-06 08:54:34 +1000590 u32 script = 0, or;
Ben Skeggs6ee73862009-12-11 19:24:15 +1000591
Ben Skeggs75c722d2009-12-21 12:16:52 +1000592 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
593 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
594
Ben Skeggs87c0e0e2010-07-06 08:54:34 +1000595 if (nv_encoder->dcb != dcb)
Ben Skeggs75c722d2009-12-21 12:16:52 +1000596 continue;
597
598 nv_connector = nouveau_encoder_connector_get(nv_encoder);
599 break;
600 }
601
Ben Skeggs87c0e0e2010-07-06 08:54:34 +1000602 or = ffs(dcb->or) - 1;
603 switch (dcb->type) {
Ben Skeggs6ee73862009-12-11 19:24:15 +1000604 case OUTPUT_LVDS:
605 script = (mc >> 8) & 0xf;
Ben Skeggs04a39c52010-02-24 10:03:05 +1000606 if (bios->fp_no_ddc) {
Ben Skeggs6ee73862009-12-11 19:24:15 +1000607 if (bios->fp.dual_link)
608 script |= 0x0100;
609 if (bios->fp.if_is_24bit)
610 script |= 0x0200;
611 } else {
612 if (pxclk >= bios->fp.duallink_transition_clk) {
613 script |= 0x0100;
614 if (bios->fp.strapless_is_24bit & 2)
615 script |= 0x0200;
616 } else
617 if (bios->fp.strapless_is_24bit & 1)
618 script |= 0x0200;
Ben Skeggs75c722d2009-12-21 12:16:52 +1000619
620 if (nv_connector && nv_connector->edid &&
621 (nv_connector->edid->revision >= 4) &&
622 (nv_connector->edid->input & 0x70) >= 0x20)
623 script |= 0x0200;
Ben Skeggs6ee73862009-12-11 19:24:15 +1000624 }
625
626 if (nouveau_uscript_lvds >= 0) {
627 NV_INFO(dev, "override script 0x%04x with 0x%04x "
628 "for output LVDS-%d\n", script,
629 nouveau_uscript_lvds, or);
630 script = nouveau_uscript_lvds;
631 }
632 break;
633 case OUTPUT_TMDS:
634 script = (mc >> 8) & 0xf;
635 if (pxclk >= 165000)
636 script |= 0x0100;
637
638 if (nouveau_uscript_tmds >= 0) {
639 NV_INFO(dev, "override script 0x%04x with 0x%04x "
640 "for output TMDS-%d\n", script,
641 nouveau_uscript_tmds, or);
642 script = nouveau_uscript_tmds;
643 }
644 break;
645 case OUTPUT_DP:
646 script = (mc >> 8) & 0xf;
647 break;
648 case OUTPUT_ANALOG:
649 script = 0xff;
650 break;
651 default:
652 NV_ERROR(dev, "modeset on unsupported output type!\n");
653 break;
654 }
655
656 return script;
657}
658
659static void
660nv50_display_vblank_crtc_handler(struct drm_device *dev, int crtc)
661{
662 struct drm_nouveau_private *dev_priv = dev->dev_private;
663 struct nouveau_channel *chan;
664 struct list_head *entry, *tmp;
665
666 list_for_each_safe(entry, tmp, &dev_priv->vbl_waiting) {
667 chan = list_entry(entry, struct nouveau_channel, nvsw.vbl_wait);
668
669 nouveau_bo_wr32(chan->notifier_bo, chan->nvsw.vblsem_offset,
670 chan->nvsw.vblsem_rval);
671 list_del(&chan->nvsw.vbl_wait);
672 }
673}
674
675static void
676nv50_display_vblank_handler(struct drm_device *dev, uint32_t intr)
677{
678 intr &= NV50_PDISPLAY_INTR_1_VBLANK_CRTC;
679
680 if (intr & NV50_PDISPLAY_INTR_1_VBLANK_CRTC_0)
681 nv50_display_vblank_crtc_handler(dev, 0);
682
683 if (intr & NV50_PDISPLAY_INTR_1_VBLANK_CRTC_1)
684 nv50_display_vblank_crtc_handler(dev, 1);
685
686 nv_wr32(dev, NV50_PDISPLAY_INTR_EN, nv_rd32(dev,
687 NV50_PDISPLAY_INTR_EN) & ~intr);
688 nv_wr32(dev, NV50_PDISPLAY_INTR_1, intr);
689}
690
691static void
692nv50_display_unk10_handler(struct drm_device *dev)
693{
Ben Skeggs87c0e0e2010-07-06 08:54:34 +1000694 struct drm_nouveau_private *dev_priv = dev->dev_private;
695 u32 unk30 = nv_rd32(dev, 0x610030), mc;
696 int i, crtc, or, type = OUTPUT_ANY;
Ben Skeggs6ee73862009-12-11 19:24:15 +1000697
Ben Skeggs87c0e0e2010-07-06 08:54:34 +1000698 NV_DEBUG_KMS(dev, "0x610030: 0x%08x\n", unk30);
699 dev_priv->evo_irq.dcb = NULL;
Ben Skeggs6ee73862009-12-11 19:24:15 +1000700
701 nv_wr32(dev, 0x619494, nv_rd32(dev, 0x619494) & ~8);
702
Ben Skeggs87c0e0e2010-07-06 08:54:34 +1000703 /* Determine which CRTC we're dealing with, only 1 ever will be
704 * signalled at the same time with the current nouveau code.
705 */
706 crtc = ffs((unk30 & 0x00000060) >> 5) - 1;
707 if (crtc < 0)
708 goto ack;
Ben Skeggs6ee73862009-12-11 19:24:15 +1000709
Ben Skeggs87c0e0e2010-07-06 08:54:34 +1000710 /* Nothing needs to be done for the encoder */
711 crtc = ffs((unk30 & 0x00000180) >> 7) - 1;
712 if (crtc < 0)
713 goto ack;
714
715 /* Find which encoder was connected to the CRTC */
716 for (i = 0; type == OUTPUT_ANY && i < 3; i++) {
717 mc = nv_rd32(dev, NV50_PDISPLAY_DAC_MODE_CTRL_C(i));
718 NV_DEBUG_KMS(dev, "DAC-%d mc: 0x%08x\n", i, mc);
719 if (!(mc & (1 << crtc)))
720 continue;
721
722 switch ((mc & 0x00000f00) >> 8) {
723 case 0: type = OUTPUT_ANALOG; break;
724 case 1: type = OUTPUT_TV; break;
725 default:
726 NV_ERROR(dev, "invalid mc, DAC-%d: 0x%08x\n", i, mc);
727 goto ack;
728 }
729
730 or = i;
731 }
732
Ben Skeggs8597a1b2010-09-06 11:39:25 +1000733 for (i = 0; type == OUTPUT_ANY && i < nv50_sor_nr(dev); i++) {
Ben Skeggs87c0e0e2010-07-06 08:54:34 +1000734 if (dev_priv->chipset < 0x90 ||
735 dev_priv->chipset == 0x92 ||
736 dev_priv->chipset == 0xa0)
737 mc = nv_rd32(dev, NV50_PDISPLAY_SOR_MODE_CTRL_C(i));
738 else
739 mc = nv_rd32(dev, NV90_PDISPLAY_SOR_MODE_CTRL_C(i));
740
741 NV_DEBUG_KMS(dev, "SOR-%d mc: 0x%08x\n", i, mc);
742 if (!(mc & (1 << crtc)))
743 continue;
744
745 switch ((mc & 0x00000f00) >> 8) {
746 case 0: type = OUTPUT_LVDS; break;
747 case 1: type = OUTPUT_TMDS; break;
748 case 2: type = OUTPUT_TMDS; break;
749 case 5: type = OUTPUT_TMDS; break;
750 case 8: type = OUTPUT_DP; break;
751 case 9: type = OUTPUT_DP; break;
752 default:
753 NV_ERROR(dev, "invalid mc, SOR-%d: 0x%08x\n", i, mc);
754 goto ack;
755 }
756
757 or = i;
758 }
759
760 /* There was no encoder to disable */
761 if (type == OUTPUT_ANY)
762 goto ack;
763
764 /* Disable the encoder */
765 for (i = 0; i < dev_priv->vbios.dcb.entries; i++) {
766 struct dcb_entry *dcb = &dev_priv->vbios.dcb.entry[i];
767
768 if (dcb->type == type && (dcb->or & (1 << or))) {
769 nouveau_bios_run_display_table(dev, dcb, 0, -1);
770 dev_priv->evo_irq.dcb = dcb;
771 goto ack;
772 }
773 }
774
775 NV_ERROR(dev, "no dcb for %d %d 0x%08x\n", or, type, mc);
Ben Skeggs6ee73862009-12-11 19:24:15 +1000776ack:
777 nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK10);
778 nv_wr32(dev, 0x610030, 0x80000000);
779}
780
781static void
Ben Skeggsafa3b4c2010-04-23 08:21:48 +1000782nv50_display_unk20_dp_hack(struct drm_device *dev, struct dcb_entry *dcb)
783{
784 int or = ffs(dcb->or) - 1, link = !(dcb->dpconf.sor.link & 1);
785 struct drm_encoder *encoder;
786 uint32_t tmp, unk0 = 0, unk1 = 0;
787
788 if (dcb->type != OUTPUT_DP)
789 return;
790
791 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
792 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
793
794 if (nv_encoder->dcb == dcb) {
795 unk0 = nv_encoder->dp.unk0;
796 unk1 = nv_encoder->dp.unk1;
797 break;
798 }
799 }
800
801 if (unk0 || unk1) {
802 tmp = nv_rd32(dev, NV50_SOR_DP_CTRL(or, link));
803 tmp &= 0xfffffe03;
804 nv_wr32(dev, NV50_SOR_DP_CTRL(or, link), tmp | unk0);
805
806 tmp = nv_rd32(dev, NV50_SOR_DP_UNK128(or, link));
807 tmp &= 0xfef080c0;
808 nv_wr32(dev, NV50_SOR_DP_UNK128(or, link), tmp | unk1);
809 }
810}
811
812static void
Ben Skeggs6ee73862009-12-11 19:24:15 +1000813nv50_display_unk20_handler(struct drm_device *dev)
814{
Ben Skeggs87c0e0e2010-07-06 08:54:34 +1000815 struct drm_nouveau_private *dev_priv = dev->dev_private;
816 u32 unk30 = nv_rd32(dev, 0x610030), tmp, pclk, script, mc;
817 struct dcb_entry *dcb;
818 int i, crtc, or, type = OUTPUT_ANY;
Ben Skeggs6ee73862009-12-11 19:24:15 +1000819
Ben Skeggs87c0e0e2010-07-06 08:54:34 +1000820 NV_DEBUG_KMS(dev, "0x610030: 0x%08x\n", unk30);
821 dcb = dev_priv->evo_irq.dcb;
822 if (dcb) {
823 nouveau_bios_run_display_table(dev, dcb, 0, -2);
824 dev_priv->evo_irq.dcb = NULL;
825 }
826
827 /* CRTC clock change requested? */
828 crtc = ffs((unk30 & 0x00000600) >> 9) - 1;
829 if (crtc >= 0) {
830 pclk = nv_rd32(dev, NV50_PDISPLAY_CRTC_P(crtc, CLOCK));
831 pclk &= 0x003fffff;
832
833 nv50_crtc_set_clock(dev, crtc, pclk);
834
835 tmp = nv_rd32(dev, NV50_PDISPLAY_CRTC_CLK_CTRL2(crtc));
836 tmp &= ~0x000000f;
837 nv_wr32(dev, NV50_PDISPLAY_CRTC_CLK_CTRL2(crtc), tmp);
838 }
839
840 /* Nothing needs to be done for the encoder */
841 crtc = ffs((unk30 & 0x00000180) >> 7) - 1;
842 if (crtc < 0)
Ben Skeggs6ee73862009-12-11 19:24:15 +1000843 goto ack;
Ben Skeggs87c0e0e2010-07-06 08:54:34 +1000844 pclk = nv_rd32(dev, NV50_PDISPLAY_CRTC_P(crtc, CLOCK)) & 0x003fffff;
Ben Skeggs6ee73862009-12-11 19:24:15 +1000845
Ben Skeggs87c0e0e2010-07-06 08:54:34 +1000846 /* Find which encoder is connected to the CRTC */
847 for (i = 0; type == OUTPUT_ANY && i < 3; i++) {
848 mc = nv_rd32(dev, NV50_PDISPLAY_DAC_MODE_CTRL_P(i));
849 NV_DEBUG_KMS(dev, "DAC-%d mc: 0x%08x\n", i, mc);
850 if (!(mc & (1 << crtc)))
851 continue;
Ben Skeggs6ee73862009-12-11 19:24:15 +1000852
Ben Skeggs87c0e0e2010-07-06 08:54:34 +1000853 switch ((mc & 0x00000f00) >> 8) {
854 case 0: type = OUTPUT_ANALOG; break;
855 case 1: type = OUTPUT_TV; break;
856 default:
857 NV_ERROR(dev, "invalid mc, DAC-%d: 0x%08x\n", i, mc);
858 goto ack;
859 }
Ben Skeggs6ee73862009-12-11 19:24:15 +1000860
Ben Skeggs87c0e0e2010-07-06 08:54:34 +1000861 or = i;
862 }
Ben Skeggs6ee73862009-12-11 19:24:15 +1000863
Ben Skeggs8597a1b2010-09-06 11:39:25 +1000864 for (i = 0; type == OUTPUT_ANY && i < nv50_sor_nr(dev); i++) {
Ben Skeggs87c0e0e2010-07-06 08:54:34 +1000865 if (dev_priv->chipset < 0x90 ||
866 dev_priv->chipset == 0x92 ||
867 dev_priv->chipset == 0xa0)
868 mc = nv_rd32(dev, NV50_PDISPLAY_SOR_MODE_CTRL_P(i));
869 else
870 mc = nv_rd32(dev, NV90_PDISPLAY_SOR_MODE_CTRL_P(i));
Ben Skeggs6ee73862009-12-11 19:24:15 +1000871
Ben Skeggs87c0e0e2010-07-06 08:54:34 +1000872 NV_DEBUG_KMS(dev, "SOR-%d mc: 0x%08x\n", i, mc);
873 if (!(mc & (1 << crtc)))
874 continue;
Ben Skeggsafa3b4c2010-04-23 08:21:48 +1000875
Ben Skeggs87c0e0e2010-07-06 08:54:34 +1000876 switch ((mc & 0x00000f00) >> 8) {
877 case 0: type = OUTPUT_LVDS; break;
878 case 1: type = OUTPUT_TMDS; break;
879 case 2: type = OUTPUT_TMDS; break;
880 case 5: type = OUTPUT_TMDS; break;
881 case 8: type = OUTPUT_DP; break;
882 case 9: type = OUTPUT_DP; break;
883 default:
884 NV_ERROR(dev, "invalid mc, SOR-%d: 0x%08x\n", i, mc);
885 goto ack;
886 }
Ben Skeggs6ee73862009-12-11 19:24:15 +1000887
Ben Skeggs87c0e0e2010-07-06 08:54:34 +1000888 or = i;
889 }
890
891 if (type == OUTPUT_ANY)
892 goto ack;
893
894 /* Enable the encoder */
895 for (i = 0; i < dev_priv->vbios.dcb.entries; i++) {
896 dcb = &dev_priv->vbios.dcb.entry[i];
897 if (dcb->type == type && (dcb->or & (1 << or)))
898 break;
899 }
900
901 if (i == dev_priv->vbios.dcb.entries) {
902 NV_ERROR(dev, "no dcb for %d %d 0x%08x\n", or, type, mc);
903 goto ack;
904 }
905
906 script = nv50_display_script_select(dev, dcb, mc, pclk);
907 nouveau_bios_run_display_table(dev, dcb, script, pclk);
908
909 nv50_display_unk20_dp_hack(dev, dcb);
Ben Skeggs87c0e0e2010-07-06 08:54:34 +1000910
911 if (dcb->type != OUTPUT_ANALOG) {
Ben Skeggs6ee73862009-12-11 19:24:15 +1000912 tmp = nv_rd32(dev, NV50_PDISPLAY_SOR_CLK_CTRL2(or));
913 tmp &= ~0x00000f0f;
914 if (script & 0x0100)
915 tmp |= 0x00000101;
916 nv_wr32(dev, NV50_PDISPLAY_SOR_CLK_CTRL2(or), tmp);
917 } else {
918 nv_wr32(dev, NV50_PDISPLAY_DAC_CLK_CTRL2(or), 0);
919 }
920
Ben Skeggs87c0e0e2010-07-06 08:54:34 +1000921 dev_priv->evo_irq.dcb = dcb;
922 dev_priv->evo_irq.pclk = pclk;
923 dev_priv->evo_irq.script = script;
924
Ben Skeggs6ee73862009-12-11 19:24:15 +1000925ack:
926 nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK20);
927 nv_wr32(dev, 0x610030, 0x80000000);
928}
929
Ben Skeggs271f29e2010-07-09 10:37:42 +1000930/* If programming a TMDS output on a SOR that can also be configured for
931 * DisplayPort, make sure NV50_SOR_DP_CTRL_ENABLE is forced off.
932 *
933 * It looks like the VBIOS TMDS scripts make an attempt at this, however,
934 * the VBIOS scripts on at least one board I have only switch it off on
935 * link 0, causing a blank display if the output has previously been
936 * programmed for DisplayPort.
937 */
938static void
939nv50_display_unk40_dp_set_tmds(struct drm_device *dev, struct dcb_entry *dcb)
940{
941 int or = ffs(dcb->or) - 1, link = !(dcb->dpconf.sor.link & 1);
942 struct drm_encoder *encoder;
943 u32 tmp;
944
945 if (dcb->type != OUTPUT_TMDS)
946 return;
947
948 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
949 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
950
951 if (nv_encoder->dcb->type == OUTPUT_DP &&
952 nv_encoder->dcb->or & (1 << or)) {
953 tmp = nv_rd32(dev, NV50_SOR_DP_CTRL(or, link));
954 tmp &= ~NV50_SOR_DP_CTRL_ENABLED;
955 nv_wr32(dev, NV50_SOR_DP_CTRL(or, link), tmp);
956 break;
957 }
958 }
959}
960
Ben Skeggs6ee73862009-12-11 19:24:15 +1000961static void
962nv50_display_unk40_handler(struct drm_device *dev)
963{
Ben Skeggs87c0e0e2010-07-06 08:54:34 +1000964 struct drm_nouveau_private *dev_priv = dev->dev_private;
965 struct dcb_entry *dcb = dev_priv->evo_irq.dcb;
966 u16 script = dev_priv->evo_irq.script;
967 u32 unk30 = nv_rd32(dev, 0x610030), pclk = dev_priv->evo_irq.pclk;
Ben Skeggs6ee73862009-12-11 19:24:15 +1000968
Ben Skeggs87c0e0e2010-07-06 08:54:34 +1000969 NV_DEBUG_KMS(dev, "0x610030: 0x%08x\n", unk30);
970 dev_priv->evo_irq.dcb = NULL;
971 if (!dcb)
Ben Skeggs6ee73862009-12-11 19:24:15 +1000972 goto ack;
Ben Skeggs6ee73862009-12-11 19:24:15 +1000973
Ben Skeggs87c0e0e2010-07-06 08:54:34 +1000974 nouveau_bios_run_display_table(dev, dcb, script, -pclk);
Ben Skeggs271f29e2010-07-09 10:37:42 +1000975 nv50_display_unk40_dp_set_tmds(dev, dcb);
976
Ben Skeggs6ee73862009-12-11 19:24:15 +1000977ack:
978 nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK40);
979 nv_wr32(dev, 0x610030, 0x80000000);
980 nv_wr32(dev, 0x619494, nv_rd32(dev, 0x619494) | 8);
981}
982
983void
984nv50_display_irq_handler_bh(struct work_struct *work)
985{
986 struct drm_nouveau_private *dev_priv =
987 container_of(work, struct drm_nouveau_private, irq_work);
988 struct drm_device *dev = dev_priv->dev;
989
990 for (;;) {
991 uint32_t intr0 = nv_rd32(dev, NV50_PDISPLAY_INTR_0);
992 uint32_t intr1 = nv_rd32(dev, NV50_PDISPLAY_INTR_1);
993
Maarten Maathuisef2bb502009-12-13 16:53:12 +0100994 NV_DEBUG_KMS(dev, "PDISPLAY_INTR_BH 0x%08x 0x%08x\n", intr0, intr1);
Ben Skeggs6ee73862009-12-11 19:24:15 +1000995
996 if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK10)
997 nv50_display_unk10_handler(dev);
998 else
999 if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK20)
1000 nv50_display_unk20_handler(dev);
1001 else
1002 if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK40)
1003 nv50_display_unk40_handler(dev);
1004 else
1005 break;
1006 }
1007
1008 nv_wr32(dev, NV03_PMC_INTR_EN_0, 1);
1009}
1010
1011static void
1012nv50_display_error_handler(struct drm_device *dev)
1013{
1014 uint32_t addr, data;
1015
1016 nv_wr32(dev, NV50_PDISPLAY_INTR_0, 0x00010000);
1017 addr = nv_rd32(dev, NV50_PDISPLAY_TRAPPED_ADDR);
1018 data = nv_rd32(dev, NV50_PDISPLAY_TRAPPED_DATA);
1019
1020 NV_ERROR(dev, "EvoCh %d Mthd 0x%04x Data 0x%08x (0x%04x 0x%02x)\n",
1021 0, addr & 0xffc, data, addr >> 16, (addr >> 12) & 0xf);
1022
1023 nv_wr32(dev, NV50_PDISPLAY_TRAPPED_ADDR, 0x90000000);
1024}
1025
Ben Skeggsa5acac62010-03-30 15:14:41 +10001026void
1027nv50_display_irq_hotplug_bh(struct work_struct *work)
Ben Skeggs6ee73862009-12-11 19:24:15 +10001028{
Ben Skeggsa5acac62010-03-30 15:14:41 +10001029 struct drm_nouveau_private *dev_priv =
1030 container_of(work, struct drm_nouveau_private, hpd_work);
1031 struct drm_device *dev = dev_priv->dev;
Ben Skeggs6ee73862009-12-11 19:24:15 +10001032 struct drm_connector *connector;
1033 const uint32_t gpio_reg[4] = { 0xe104, 0xe108, 0xe280, 0xe284 };
1034 uint32_t unplug_mask, plug_mask, change_mask;
1035 uint32_t hpd0, hpd1 = 0;
1036
1037 hpd0 = nv_rd32(dev, 0xe054) & nv_rd32(dev, 0xe050);
1038 if (dev_priv->chipset >= 0x90)
1039 hpd1 = nv_rd32(dev, 0xe074) & nv_rd32(dev, 0xe070);
1040
1041 plug_mask = (hpd0 & 0x0000ffff) | (hpd1 << 16);
1042 unplug_mask = (hpd0 >> 16) | (hpd1 & 0xffff0000);
1043 change_mask = plug_mask | unplug_mask;
1044
1045 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1046 struct drm_encoder_helper_funcs *helper;
1047 struct nouveau_connector *nv_connector =
1048 nouveau_connector(connector);
1049 struct nouveau_encoder *nv_encoder;
1050 struct dcb_gpio_entry *gpio;
1051 uint32_t reg;
1052 bool plugged;
1053
1054 if (!nv_connector->dcb)
1055 continue;
1056
1057 gpio = nouveau_bios_gpio_entry(dev, nv_connector->dcb->gpio_tag);
1058 if (!gpio || !(change_mask & (1 << gpio->line)))
1059 continue;
1060
1061 reg = nv_rd32(dev, gpio_reg[gpio->line >> 3]);
1062 plugged = !!(reg & (4 << ((gpio->line & 7) << 2)));
1063 NV_INFO(dev, "%splugged %s\n", plugged ? "" : "un",
1064 drm_get_connector_name(connector)) ;
1065
1066 if (!connector->encoder || !connector->encoder->crtc ||
1067 !connector->encoder->crtc->enabled)
1068 continue;
1069 nv_encoder = nouveau_encoder(connector->encoder);
1070 helper = connector->encoder->helper_private;
1071
1072 if (nv_encoder->dcb->type != OUTPUT_DP)
1073 continue;
1074
1075 if (plugged)
1076 helper->dpms(connector->encoder, DRM_MODE_DPMS_ON);
1077 else
1078 helper->dpms(connector->encoder, DRM_MODE_DPMS_OFF);
1079 }
1080
1081 nv_wr32(dev, 0xe054, nv_rd32(dev, 0xe054));
1082 if (dev_priv->chipset >= 0x90)
1083 nv_wr32(dev, 0xe074, nv_rd32(dev, 0xe074));
Dave Airlie4abe3522010-03-30 05:34:18 +00001084
Dave Airlieeb1f8e42010-05-07 06:42:51 +00001085 drm_helper_hpd_irq_event(dev);
Ben Skeggs6ee73862009-12-11 19:24:15 +10001086}
1087
1088void
1089nv50_display_irq_handler(struct drm_device *dev)
1090{
1091 struct drm_nouveau_private *dev_priv = dev->dev_private;
1092 uint32_t delayed = 0;
1093
Ben Skeggsa5acac62010-03-30 15:14:41 +10001094 if (nv_rd32(dev, NV50_PMC_INTR_0) & NV50_PMC_INTR_0_HOTPLUG) {
1095 if (!work_pending(&dev_priv->hpd_work))
1096 queue_work(dev_priv->wq, &dev_priv->hpd_work);
1097 }
Ben Skeggs6ee73862009-12-11 19:24:15 +10001098
1099 while (nv_rd32(dev, NV50_PMC_INTR_0) & NV50_PMC_INTR_0_DISPLAY) {
1100 uint32_t intr0 = nv_rd32(dev, NV50_PDISPLAY_INTR_0);
1101 uint32_t intr1 = nv_rd32(dev, NV50_PDISPLAY_INTR_1);
1102 uint32_t clock;
1103
Maarten Maathuisef2bb502009-12-13 16:53:12 +01001104 NV_DEBUG_KMS(dev, "PDISPLAY_INTR 0x%08x 0x%08x\n", intr0, intr1);
Ben Skeggs6ee73862009-12-11 19:24:15 +10001105
1106 if (!intr0 && !(intr1 & ~delayed))
1107 break;
1108
1109 if (intr0 & 0x00010000) {
1110 nv50_display_error_handler(dev);
1111 intr0 &= ~0x00010000;
1112 }
1113
1114 if (intr1 & NV50_PDISPLAY_INTR_1_VBLANK_CRTC) {
1115 nv50_display_vblank_handler(dev, intr1);
1116 intr1 &= ~NV50_PDISPLAY_INTR_1_VBLANK_CRTC;
1117 }
1118
1119 clock = (intr1 & (NV50_PDISPLAY_INTR_1_CLK_UNK10 |
1120 NV50_PDISPLAY_INTR_1_CLK_UNK20 |
1121 NV50_PDISPLAY_INTR_1_CLK_UNK40));
1122 if (clock) {
1123 nv_wr32(dev, NV03_PMC_INTR_EN_0, 0);
1124 if (!work_pending(&dev_priv->irq_work))
1125 queue_work(dev_priv->wq, &dev_priv->irq_work);
1126 delayed |= clock;
1127 intr1 &= ~clock;
1128 }
1129
1130 if (intr0) {
1131 NV_ERROR(dev, "unknown PDISPLAY_INTR_0: 0x%08x\n", intr0);
1132 nv_wr32(dev, NV50_PDISPLAY_INTR_0, intr0);
1133 }
1134
1135 if (intr1) {
1136 NV_ERROR(dev,
1137 "unknown PDISPLAY_INTR_1: 0x%08x\n", intr1);
1138 nv_wr32(dev, NV50_PDISPLAY_INTR_1, intr1);
1139 }
1140 }
1141}
1142