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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/* via-rhine.c: A Linux Ethernet device driver for VIA Rhine family chips. */
2/*
3 Written 1998-2001 by Donald Becker.
4
5 Current Maintainer: Roger Luethi <rl@hellgate.ch>
6
7 This software may be used and distributed according to the terms of
8 the GNU General Public License (GPL), incorporated herein by reference.
9 Drivers based on or derived from this code fall under the GPL and must
10 retain the authorship, copyright and license notice. This file is not
11 a complete program and may only be used when the entire operating
12 system is licensed under the GPL.
13
14 This driver is designed for the VIA VT86C100A Rhine-I.
15 It also works with the Rhine-II (6102) and Rhine-III (6105/6105L/6105LOM
16 and management NIC 6105M).
17
18 The author may be reached as becker@scyld.com, or C/O
19 Scyld Computing Corporation
20 410 Severn Ave., Suite 210
21 Annapolis MD 21403
22
23
24 This driver contains some changes from the original Donald Becker
25 version. He may or may not be interested in bug reports on this
26 code. You can find his versions at:
27 http://www.scyld.com/network/via-rhine.html
28
29
30 Linux kernel version history:
31
32 LK1.1.0:
33 - Jeff Garzik: softnet 'n stuff
34
35 LK1.1.1:
36 - Justin Guyett: softnet and locking fixes
37 - Jeff Garzik: use PCI interface
38
39 LK1.1.2:
40 - Urban Widmark: minor cleanups, merges from Becker 1.03a/1.04 versions
41
42 LK1.1.3:
43 - Urban Widmark: use PCI DMA interface (with thanks to the eepro100.c
44 code) update "Theory of Operation" with
45 softnet/locking changes
46 - Dave Miller: PCI DMA and endian fixups
47 - Jeff Garzik: MOD_xxx race fixes, updated PCI resource allocation
48
49 LK1.1.4:
50 - Urban Widmark: fix gcc 2.95.2 problem and
51 remove writel's to fixed address 0x7c
52
53 LK1.1.5:
54 - Urban Widmark: mdio locking, bounce buffer changes
55 merges from Beckers 1.05 version
56 added netif_running_on/off support
57
58 LK1.1.6:
59 - Urban Widmark: merges from Beckers 1.08b version (VT6102 + mdio)
60 set netif_running_on/off on startup, del_timer_sync
61
62 LK1.1.7:
63 - Manfred Spraul: added reset into tx_timeout
64
65 LK1.1.9:
66 - Urban Widmark: merges from Beckers 1.10 version
67 (media selection + eeprom reload)
68 - David Vrabel: merges from D-Link "1.11" version
69 (disable WOL and PME on startup)
70
71 LK1.1.10:
72 - Manfred Spraul: use "singlecopy" for unaligned buffers
73 don't allocate bounce buffers for !ReqTxAlign cards
74
75 LK1.1.11:
76 - David Woodhouse: Set dev->base_addr before the first time we call
77 wait_for_reset(). It's a lot happier that way.
78 Free np->tx_bufs only if we actually allocated it.
79
80 LK1.1.12:
81 - Martin Eriksson: Allow Memory-Mapped IO to be enabled.
82
83 LK1.1.13 (jgarzik):
84 - Add ethtool support
85 - Replace some MII-related magic numbers with constants
86
87 LK1.1.14 (Ivan G.):
88 - fixes comments for Rhine-III
89 - removes W_MAX_TIMEOUT (unused)
90 - adds HasDavicomPhy for Rhine-I (basis: linuxfet driver; my card
91 is R-I and has Davicom chip, flag is referenced in kernel driver)
92 - sends chip_id as a parameter to wait_for_reset since np is not
93 initialized on first call
94 - changes mmio "else if (chip_id==VT6102)" to "else" so it will work
95 for Rhine-III's (documentation says same bit is correct)
96 - transmit frame queue message is off by one - fixed
97 - adds IntrNormalSummary to "Something Wicked" exclusion list
98 so normal interrupts will not trigger the message (src: Donald Becker)
99 (Roger Luethi)
100 - show confused chip where to continue after Tx error
101 - location of collision counter is chip specific
102 - allow selecting backoff algorithm (module parameter)
103
104 LK1.1.15 (jgarzik):
105 - Use new MII lib helper generic_mii_ioctl
106
107 LK1.1.16 (Roger Luethi)
108 - Etherleak fix
109 - Handle Tx buffer underrun
110 - Fix bugs in full duplex handling
111 - New reset code uses "force reset" cmd on Rhine-II
112 - Various clean ups
113
114 LK1.1.17 (Roger Luethi)
115 - Fix race in via_rhine_start_tx()
116 - On errors, wait for Tx engine to turn off before scavenging
117 - Handle Tx descriptor write-back race on Rhine-II
118 - Force flushing for PCI posted writes
119 - More reset code changes
120
121 LK1.1.18 (Roger Luethi)
122 - No filtering multicast in promisc mode (Edward Peng)
123 - Fix for Rhine-I Tx timeouts
124
125 LK1.1.19 (Roger Luethi)
126 - Increase Tx threshold for unspecified errors
127
128 LK1.2.0-2.6 (Roger Luethi)
129 - Massive clean-up
130 - Rewrite PHY, media handling (remove options, full_duplex, backoff)
131 - Fix Tx engine race for good
132
133*/
134
135#define DRV_NAME "via-rhine"
136#define DRV_VERSION "1.2.0-2.6"
137#define DRV_RELDATE "June-10-2004"
138
139
140/* A few user-configurable values.
141 These may be modified when a driver module is loaded. */
142
143static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */
144static int max_interrupt_work = 20;
145
146/* Set the copy breakpoint for the copy-only-tiny-frames scheme.
147 Setting to > 1518 effectively disables this feature. */
148static int rx_copybreak;
149
150/*
151 * In case you are looking for 'options[]' or 'full_duplex[]', they
152 * are gone. Use ethtool(8) instead.
153 */
154
155/* Maximum number of multicast addresses to filter (vs. rx-all-multicast).
156 The Rhine has a 64 element 8390-like hash table. */
157static const int multicast_filter_limit = 32;
158
159
160/* Operational parameters that are set at compile time. */
161
162/* Keep the ring sizes a power of two for compile efficiency.
163 The compiler will convert <unsigned>'%'<2^N> into a bit mask.
164 Making the Tx ring too large decreases the effectiveness of channel
165 bonding and packet priority.
166 There are no ill effects from too-large receive rings. */
167#define TX_RING_SIZE 16
168#define TX_QUEUE_LEN 10 /* Limit ring entries actually used. */
169#define RX_RING_SIZE 16
170
171
172/* Operational parameters that usually are not changed. */
173
174/* Time in jiffies before concluding the transmitter is hung. */
175#define TX_TIMEOUT (2*HZ)
176
177#define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
178
179#include <linux/module.h>
180#include <linux/moduleparam.h>
181#include <linux/kernel.h>
182#include <linux/string.h>
183#include <linux/timer.h>
184#include <linux/errno.h>
185#include <linux/ioport.h>
186#include <linux/slab.h>
187#include <linux/interrupt.h>
188#include <linux/pci.h>
Domen Puncer1e7f0bd2005-06-26 18:22:14 -0400189#include <linux/dma-mapping.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -0700190#include <linux/netdevice.h>
191#include <linux/etherdevice.h>
192#include <linux/skbuff.h>
193#include <linux/init.h>
194#include <linux/delay.h>
195#include <linux/mii.h>
196#include <linux/ethtool.h>
197#include <linux/crc32.h>
198#include <linux/bitops.h>
199#include <asm/processor.h> /* Processor type for cache alignment. */
200#include <asm/io.h>
201#include <asm/irq.h>
202#include <asm/uaccess.h>
203
204/* These identify the driver base version and may not be removed. */
205static char version[] __devinitdata =
206KERN_INFO DRV_NAME ".c:v1.10-LK" DRV_VERSION " " DRV_RELDATE " Written by Donald Becker\n";
207
208/* This driver was written to use PCI memory space. Some early versions
209 of the Rhine may only work correctly with I/O space accesses. */
210#ifdef CONFIG_VIA_RHINE_MMIO
211#define USE_MMIO
212#else
213#endif
214
215MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
216MODULE_DESCRIPTION("VIA Rhine PCI Fast Ethernet driver");
217MODULE_LICENSE("GPL");
218
219module_param(max_interrupt_work, int, 0);
220module_param(debug, int, 0);
221module_param(rx_copybreak, int, 0);
222MODULE_PARM_DESC(max_interrupt_work, "VIA Rhine maximum events handled per interrupt");
223MODULE_PARM_DESC(debug, "VIA Rhine debug level (0-7)");
224MODULE_PARM_DESC(rx_copybreak, "VIA Rhine copy breakpoint for copy-only-tiny-frames");
225
226/*
227 Theory of Operation
228
229I. Board Compatibility
230
231This driver is designed for the VIA 86c100A Rhine-II PCI Fast Ethernet
232controller.
233
234II. Board-specific settings
235
236Boards with this chip are functional only in a bus-master PCI slot.
237
238Many operational settings are loaded from the EEPROM to the Config word at
239offset 0x78. For most of these settings, this driver assumes that they are
240correct.
241If this driver is compiled to use PCI memory space operations the EEPROM
242must be configured to enable memory ops.
243
244III. Driver operation
245
246IIIa. Ring buffers
247
248This driver uses two statically allocated fixed-size descriptor lists
249formed into rings by a branch from the final descriptor to the beginning of
250the list. The ring sizes are set at compile time by RX/TX_RING_SIZE.
251
252IIIb/c. Transmit/Receive Structure
253
254This driver attempts to use a zero-copy receive and transmit scheme.
255
256Alas, all data buffers are required to start on a 32 bit boundary, so
257the driver must often copy transmit packets into bounce buffers.
258
259The driver allocates full frame size skbuffs for the Rx ring buffers at
260open() time and passes the skb->data field to the chip as receive data
261buffers. When an incoming frame is less than RX_COPYBREAK bytes long,
262a fresh skbuff is allocated and the frame is copied to the new skbuff.
263When the incoming frame is larger, the skbuff is passed directly up the
264protocol stack. Buffers consumed this way are replaced by newly allocated
265skbuffs in the last phase of rhine_rx().
266
267The RX_COPYBREAK value is chosen to trade-off the memory wasted by
268using a full-sized skbuff for small frames vs. the copying costs of larger
269frames. New boards are typically used in generously configured machines
270and the underfilled buffers have negligible impact compared to the benefit of
271a single allocation size, so the default value of zero results in never
272copying packets. When copying is done, the cost is usually mitigated by using
273a combined copy/checksum routine. Copying also preloads the cache, which is
274most useful with small frames.
275
276Since the VIA chips are only able to transfer data to buffers on 32 bit
277boundaries, the IP header at offset 14 in an ethernet frame isn't
278longword aligned for further processing. Copying these unaligned buffers
279has the beneficial effect of 16-byte aligning the IP header.
280
281IIId. Synchronization
282
283The driver runs as two independent, single-threaded flows of control. One
284is the send-packet routine, which enforces single-threaded use by the
285dev->priv->lock spinlock. The other thread is the interrupt handler, which
286is single threaded by the hardware and interrupt handling software.
287
288The send packet thread has partial control over the Tx ring. It locks the
289dev->priv->lock whenever it's queuing a Tx packet. If the next slot in the ring
290is not available it stops the transmit queue by calling netif_stop_queue.
291
292The interrupt handler has exclusive control over the Rx ring and records stats
293from the Tx ring. After reaping the stats, it marks the Tx queue entry as
294empty by incrementing the dirty_tx mark. If at least half of the entries in
295the Rx ring are available the transmit queue is woken up if it was stopped.
296
297IV. Notes
298
299IVb. References
300
301Preliminary VT86C100A manual from http://www.via.com.tw/
302http://www.scyld.com/expert/100mbps.html
303http://www.scyld.com/expert/NWay.html
304ftp://ftp.via.com.tw/public/lan/Products/NIC/VT86C100A/Datasheet/VT86C100A03.pdf
305ftp://ftp.via.com.tw/public/lan/Products/NIC/VT6102/Datasheet/VT6102_021.PDF
306
307
308IVc. Errata
309
310The VT86C100A manual is not reliable information.
311The 3043 chip does not handle unaligned transmit or receive buffers, resulting
312in significant performance degradation for bounce buffer copies on transmit
313and unaligned IP headers on receive.
314The chip does not pad to minimum transmit length.
315
316*/
317
318
319/* This table drives the PCI probe routines. It's mostly boilerplate in all
320 of the drivers, and will likely be provided by some future kernel.
321 Note the matching code -- the first table entry matchs all 56** cards but
322 second only the 1234 card.
323*/
324
325enum rhine_revs {
326 VT86C100A = 0x00,
327 VTunknown0 = 0x20,
328 VT6102 = 0x40,
329 VT8231 = 0x50, /* Integrated MAC */
330 VT8233 = 0x60, /* Integrated MAC */
331 VT8235 = 0x74, /* Integrated MAC */
332 VT8237 = 0x78, /* Integrated MAC */
333 VTunknown1 = 0x7C,
334 VT6105 = 0x80,
335 VT6105_B0 = 0x83,
336 VT6105L = 0x8A,
337 VT6107 = 0x8C,
338 VTunknown2 = 0x8E,
339 VT6105M = 0x90, /* Management adapter */
340};
341
342enum rhine_quirks {
343 rqWOL = 0x0001, /* Wake-On-LAN support */
344 rqForceReset = 0x0002,
345 rq6patterns = 0x0040, /* 6 instead of 4 patterns for WOL */
346 rqStatusWBRace = 0x0080, /* Tx Status Writeback Error possible */
347 rqRhineI = 0x0100, /* See comment below */
348};
349/*
350 * rqRhineI: VT86C100A (aka Rhine-I) uses different bits to enable
351 * MMIO as well as for the collision counter and the Tx FIFO underflow
352 * indicator. In addition, Tx and Rx buffers need to 4 byte aligned.
353 */
354
355/* Beware of PCI posted writes */
356#define IOSYNC do { ioread8(ioaddr + StationAddr); } while (0)
357
358static struct pci_device_id rhine_pci_tbl[] =
359{
360 {0x1106, 0x3043, PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, /* VT86C100A */
361 {0x1106, 0x3065, PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, /* VT6102 */
362 {0x1106, 0x3106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, /* 6105{,L,LOM} */
363 {0x1106, 0x3053, PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, /* VT6105M */
364 { } /* terminate list */
365};
366MODULE_DEVICE_TABLE(pci, rhine_pci_tbl);
367
368
369/* Offsets to the device registers. */
370enum register_offsets {
371 StationAddr=0x00, RxConfig=0x06, TxConfig=0x07, ChipCmd=0x08,
372 ChipCmd1=0x09,
373 IntrStatus=0x0C, IntrEnable=0x0E,
374 MulticastFilter0=0x10, MulticastFilter1=0x14,
375 RxRingPtr=0x18, TxRingPtr=0x1C, GFIFOTest=0x54,
376 MIIPhyAddr=0x6C, MIIStatus=0x6D, PCIBusConfig=0x6E,
377 MIICmd=0x70, MIIRegAddr=0x71, MIIData=0x72, MACRegEEcsr=0x74,
378 ConfigA=0x78, ConfigB=0x79, ConfigC=0x7A, ConfigD=0x7B,
379 RxMissed=0x7C, RxCRCErrs=0x7E, MiscCmd=0x81,
380 StickyHW=0x83, IntrStatus2=0x84,
381 WOLcrSet=0xA0, PwcfgSet=0xA1, WOLcgSet=0xA3, WOLcrClr=0xA4,
382 WOLcrClr1=0xA6, WOLcgClr=0xA7,
383 PwrcsrSet=0xA8, PwrcsrSet1=0xA9, PwrcsrClr=0xAC, PwrcsrClr1=0xAD,
384};
385
386/* Bits in ConfigD */
387enum backoff_bits {
388 BackOptional=0x01, BackModify=0x02,
389 BackCaptureEffect=0x04, BackRandom=0x08
390};
391
392#ifdef USE_MMIO
393/* Registers we check that mmio and reg are the same. */
394static const int mmio_verify_registers[] = {
395 RxConfig, TxConfig, IntrEnable, ConfigA, ConfigB, ConfigC, ConfigD,
396 0
397};
398#endif
399
400/* Bits in the interrupt status/mask registers. */
401enum intr_status_bits {
402 IntrRxDone=0x0001, IntrRxErr=0x0004, IntrRxEmpty=0x0020,
403 IntrTxDone=0x0002, IntrTxError=0x0008, IntrTxUnderrun=0x0210,
404 IntrPCIErr=0x0040,
405 IntrStatsMax=0x0080, IntrRxEarly=0x0100,
406 IntrRxOverflow=0x0400, IntrRxDropped=0x0800, IntrRxNoBuf=0x1000,
407 IntrTxAborted=0x2000, IntrLinkChange=0x4000,
408 IntrRxWakeUp=0x8000,
409 IntrNormalSummary=0x0003, IntrAbnormalSummary=0xC260,
410 IntrTxDescRace=0x080000, /* mapped from IntrStatus2 */
411 IntrTxErrSummary=0x082218,
412};
413
414/* Bits in WOLcrSet/WOLcrClr and PwrcsrSet/PwrcsrClr */
415enum wol_bits {
416 WOLucast = 0x10,
417 WOLmagic = 0x20,
418 WOLbmcast = 0x30,
419 WOLlnkon = 0x40,
420 WOLlnkoff = 0x80,
421};
422
423/* The Rx and Tx buffer descriptors. */
424struct rx_desc {
425 s32 rx_status;
426 u32 desc_length; /* Chain flag, Buffer/frame length */
427 u32 addr;
428 u32 next_desc;
429};
430struct tx_desc {
431 s32 tx_status;
432 u32 desc_length; /* Chain flag, Tx Config, Frame length */
433 u32 addr;
434 u32 next_desc;
435};
436
437/* Initial value for tx_desc.desc_length, Buffer size goes to bits 0-10 */
438#define TXDESC 0x00e08000
439
440enum rx_status_bits {
441 RxOK=0x8000, RxWholePkt=0x0300, RxErr=0x008F
442};
443
444/* Bits in *_desc.*_status */
445enum desc_status_bits {
446 DescOwn=0x80000000
447};
448
449/* Bits in ChipCmd. */
450enum chip_cmd_bits {
451 CmdInit=0x01, CmdStart=0x02, CmdStop=0x04, CmdRxOn=0x08,
452 CmdTxOn=0x10, Cmd1TxDemand=0x20, CmdRxDemand=0x40,
453 Cmd1EarlyRx=0x01, Cmd1EarlyTx=0x02, Cmd1FDuplex=0x04,
454 Cmd1NoTxPoll=0x08, Cmd1Reset=0x80,
455};
456
457struct rhine_private {
458 /* Descriptor rings */
459 struct rx_desc *rx_ring;
460 struct tx_desc *tx_ring;
461 dma_addr_t rx_ring_dma;
462 dma_addr_t tx_ring_dma;
463
464 /* The addresses of receive-in-place skbuffs. */
465 struct sk_buff *rx_skbuff[RX_RING_SIZE];
466 dma_addr_t rx_skbuff_dma[RX_RING_SIZE];
467
468 /* The saved address of a sent-in-place packet/buffer, for later free(). */
469 struct sk_buff *tx_skbuff[TX_RING_SIZE];
470 dma_addr_t tx_skbuff_dma[TX_RING_SIZE];
471
Roger Luethi4be5de22006-04-04 20:49:16 +0200472 /* Tx bounce buffers (Rhine-I only) */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700473 unsigned char *tx_buf[TX_RING_SIZE];
474 unsigned char *tx_bufs;
475 dma_addr_t tx_bufs_dma;
476
477 struct pci_dev *pdev;
478 long pioaddr;
479 struct net_device_stats stats;
480 spinlock_t lock;
481
482 /* Frequently used values: keep some adjacent for cache effect. */
483 u32 quirks;
484 struct rx_desc *rx_head_desc;
485 unsigned int cur_rx, dirty_rx; /* Producer/consumer ring indices */
486 unsigned int cur_tx, dirty_tx;
487 unsigned int rx_buf_sz; /* Based on MTU+slack. */
488 u8 wolopts;
489
490 u8 tx_thresh, rx_thresh;
491
492 struct mii_if_info mii_if;
John W. Linville6ba98d32005-10-18 21:31:02 -0400493 struct work_struct tx_timeout_task;
494 struct work_struct check_media_task;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700495 void __iomem *base;
496};
497
498static int mdio_read(struct net_device *dev, int phy_id, int location);
499static void mdio_write(struct net_device *dev, int phy_id, int location, int value);
500static int rhine_open(struct net_device *dev);
501static void rhine_tx_timeout(struct net_device *dev);
John W. Linville6ba98d32005-10-18 21:31:02 -0400502static void rhine_tx_timeout_task(struct net_device *dev);
503static void rhine_check_media_task(struct net_device *dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700504static int rhine_start_tx(struct sk_buff *skb, struct net_device *dev);
505static irqreturn_t rhine_interrupt(int irq, void *dev_instance, struct pt_regs *regs);
506static void rhine_tx(struct net_device *dev);
507static void rhine_rx(struct net_device *dev);
508static void rhine_error(struct net_device *dev, int intr_status);
509static void rhine_set_rx_mode(struct net_device *dev);
510static struct net_device_stats *rhine_get_stats(struct net_device *dev);
511static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
512static struct ethtool_ops netdev_ethtool_ops;
513static int rhine_close(struct net_device *dev);
Greg Kroah-Hartmand18c3db2005-06-23 17:35:56 -0700514static void rhine_shutdown (struct pci_dev *pdev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700515
516#define RHINE_WAIT_FOR(condition) do { \
517 int i=1024; \
518 while (!(condition) && --i) \
519 ; \
520 if (debug > 1 && i < 512) \
521 printk(KERN_INFO "%s: %4d cycles used @ %s:%d\n", \
522 DRV_NAME, 1024-i, __func__, __LINE__); \
523} while(0)
524
525static inline u32 get_intr_status(struct net_device *dev)
526{
527 struct rhine_private *rp = netdev_priv(dev);
528 void __iomem *ioaddr = rp->base;
529 u32 intr_status;
530
531 intr_status = ioread16(ioaddr + IntrStatus);
532 /* On Rhine-II, Bit 3 indicates Tx descriptor write-back race. */
533 if (rp->quirks & rqStatusWBRace)
534 intr_status |= ioread8(ioaddr + IntrStatus2) << 16;
535 return intr_status;
536}
537
538/*
539 * Get power related registers into sane state.
540 * Notify user about past WOL event.
541 */
542static void rhine_power_init(struct net_device *dev)
543{
544 struct rhine_private *rp = netdev_priv(dev);
545 void __iomem *ioaddr = rp->base;
546 u16 wolstat;
547
548 if (rp->quirks & rqWOL) {
549 /* Make sure chip is in power state D0 */
550 iowrite8(ioread8(ioaddr + StickyHW) & 0xFC, ioaddr + StickyHW);
551
552 /* Disable "force PME-enable" */
553 iowrite8(0x80, ioaddr + WOLcgClr);
554
555 /* Clear power-event config bits (WOL) */
556 iowrite8(0xFF, ioaddr + WOLcrClr);
557 /* More recent cards can manage two additional patterns */
558 if (rp->quirks & rq6patterns)
559 iowrite8(0x03, ioaddr + WOLcrClr1);
560
561 /* Save power-event status bits */
562 wolstat = ioread8(ioaddr + PwrcsrSet);
563 if (rp->quirks & rq6patterns)
564 wolstat |= (ioread8(ioaddr + PwrcsrSet1) & 0x03) << 8;
565
566 /* Clear power-event status bits */
567 iowrite8(0xFF, ioaddr + PwrcsrClr);
568 if (rp->quirks & rq6patterns)
569 iowrite8(0x03, ioaddr + PwrcsrClr1);
570
571 if (wolstat) {
572 char *reason;
573 switch (wolstat) {
574 case WOLmagic:
575 reason = "Magic packet";
576 break;
577 case WOLlnkon:
578 reason = "Link went up";
579 break;
580 case WOLlnkoff:
581 reason = "Link went down";
582 break;
583 case WOLucast:
584 reason = "Unicast packet";
585 break;
586 case WOLbmcast:
587 reason = "Multicast/broadcast packet";
588 break;
589 default:
590 reason = "Unknown";
591 }
592 printk(KERN_INFO "%s: Woke system up. Reason: %s.\n",
593 DRV_NAME, reason);
594 }
595 }
596}
597
598static void rhine_chip_reset(struct net_device *dev)
599{
600 struct rhine_private *rp = netdev_priv(dev);
601 void __iomem *ioaddr = rp->base;
602
603 iowrite8(Cmd1Reset, ioaddr + ChipCmd1);
604 IOSYNC;
605
606 if (ioread8(ioaddr + ChipCmd1) & Cmd1Reset) {
607 printk(KERN_INFO "%s: Reset not complete yet. "
608 "Trying harder.\n", DRV_NAME);
609
610 /* Force reset */
611 if (rp->quirks & rqForceReset)
612 iowrite8(0x40, ioaddr + MiscCmd);
613
614 /* Reset can take somewhat longer (rare) */
615 RHINE_WAIT_FOR(!(ioread8(ioaddr + ChipCmd1) & Cmd1Reset));
616 }
617
618 if (debug > 1)
619 printk(KERN_INFO "%s: Reset %s.\n", dev->name,
620 (ioread8(ioaddr + ChipCmd1) & Cmd1Reset) ?
621 "failed" : "succeeded");
622}
623
624#ifdef USE_MMIO
625static void enable_mmio(long pioaddr, u32 quirks)
626{
627 int n;
628 if (quirks & rqRhineI) {
629 /* More recent docs say that this bit is reserved ... */
630 n = inb(pioaddr + ConfigA) | 0x20;
631 outb(n, pioaddr + ConfigA);
632 } else {
633 n = inb(pioaddr + ConfigD) | 0x80;
634 outb(n, pioaddr + ConfigD);
635 }
636}
637#endif
638
639/*
640 * Loads bytes 0x00-0x05, 0x6E-0x6F, 0x78-0x7B from EEPROM
641 * (plus 0x6C for Rhine-I/II)
642 */
643static void __devinit rhine_reload_eeprom(long pioaddr, struct net_device *dev)
644{
645 struct rhine_private *rp = netdev_priv(dev);
646 void __iomem *ioaddr = rp->base;
647
648 outb(0x20, pioaddr + MACRegEEcsr);
649 RHINE_WAIT_FOR(!(inb(pioaddr + MACRegEEcsr) & 0x20));
650
651#ifdef USE_MMIO
652 /*
653 * Reloading from EEPROM overwrites ConfigA-D, so we must re-enable
654 * MMIO. If reloading EEPROM was done first this could be avoided, but
655 * it is not known if that still works with the "win98-reboot" problem.
656 */
657 enable_mmio(pioaddr, rp->quirks);
658#endif
659
660 /* Turn off EEPROM-controlled wake-up (magic packet) */
661 if (rp->quirks & rqWOL)
662 iowrite8(ioread8(ioaddr + ConfigA) & 0xFC, ioaddr + ConfigA);
663
664}
665
666#ifdef CONFIG_NET_POLL_CONTROLLER
667static void rhine_poll(struct net_device *dev)
668{
669 disable_irq(dev->irq);
670 rhine_interrupt(dev->irq, (void *)dev, NULL);
671 enable_irq(dev->irq);
672}
673#endif
674
675static void rhine_hw_init(struct net_device *dev, long pioaddr)
676{
677 struct rhine_private *rp = netdev_priv(dev);
678
679 /* Reset the chip to erase previous misconfiguration. */
680 rhine_chip_reset(dev);
681
682 /* Rhine-I needs extra time to recuperate before EEPROM reload */
683 if (rp->quirks & rqRhineI)
684 msleep(5);
685
686 /* Reload EEPROM controlled bytes cleared by soft reset */
687 rhine_reload_eeprom(pioaddr, dev);
688}
689
690static int __devinit rhine_init_one(struct pci_dev *pdev,
691 const struct pci_device_id *ent)
692{
693 struct net_device *dev;
694 struct rhine_private *rp;
695 int i, rc;
696 u8 pci_rev;
697 u32 quirks;
698 long pioaddr;
699 long memaddr;
700 void __iomem *ioaddr;
701 int io_size, phy_id;
702 const char *name;
703#ifdef USE_MMIO
704 int bar = 1;
705#else
706 int bar = 0;
707#endif
708
709/* when built into the kernel, we only print version if device is found */
710#ifndef MODULE
711 static int printed_version;
712 if (!printed_version++)
713 printk(version);
714#endif
715
716 pci_read_config_byte(pdev, PCI_REVISION_ID, &pci_rev);
717
718 io_size = 256;
719 phy_id = 0;
720 quirks = 0;
721 name = "Rhine";
722 if (pci_rev < VTunknown0) {
723 quirks = rqRhineI;
724 io_size = 128;
725 }
726 else if (pci_rev >= VT6102) {
727 quirks = rqWOL | rqForceReset;
728 if (pci_rev < VT6105) {
729 name = "Rhine II";
730 quirks |= rqStatusWBRace; /* Rhine-II exclusive */
731 }
732 else {
733 phy_id = 1; /* Integrated PHY, phy_id fixed to 1 */
734 if (pci_rev >= VT6105_B0)
735 quirks |= rq6patterns;
736 if (pci_rev < VT6105M)
737 name = "Rhine III";
738 else
739 name = "Rhine III (Management Adapter)";
740 }
741 }
742
743 rc = pci_enable_device(pdev);
744 if (rc)
745 goto err_out;
746
747 /* this should always be supported */
Domen Puncer1e7f0bd2005-06-26 18:22:14 -0400748 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700749 if (rc) {
750 printk(KERN_ERR "32-bit PCI DMA addresses not supported by "
751 "the card!?\n");
752 goto err_out;
753 }
754
755 /* sanity check */
756 if ((pci_resource_len(pdev, 0) < io_size) ||
757 (pci_resource_len(pdev, 1) < io_size)) {
758 rc = -EIO;
759 printk(KERN_ERR "Insufficient PCI resources, aborting\n");
760 goto err_out;
761 }
762
763 pioaddr = pci_resource_start(pdev, 0);
764 memaddr = pci_resource_start(pdev, 1);
765
766 pci_set_master(pdev);
767
768 dev = alloc_etherdev(sizeof(struct rhine_private));
769 if (!dev) {
770 rc = -ENOMEM;
771 printk(KERN_ERR "alloc_etherdev failed\n");
772 goto err_out;
773 }
774 SET_MODULE_OWNER(dev);
775 SET_NETDEV_DEV(dev, &pdev->dev);
776
777 rp = netdev_priv(dev);
778 rp->quirks = quirks;
779 rp->pioaddr = pioaddr;
780 rp->pdev = pdev;
781
782 rc = pci_request_regions(pdev, DRV_NAME);
783 if (rc)
784 goto err_out_free_netdev;
785
786 ioaddr = pci_iomap(pdev, bar, io_size);
787 if (!ioaddr) {
788 rc = -EIO;
789 printk(KERN_ERR "ioremap failed for device %s, region 0x%X "
790 "@ 0x%lX\n", pci_name(pdev), io_size, memaddr);
791 goto err_out_free_res;
792 }
793
794#ifdef USE_MMIO
795 enable_mmio(pioaddr, quirks);
796
797 /* Check that selected MMIO registers match the PIO ones */
798 i = 0;
799 while (mmio_verify_registers[i]) {
800 int reg = mmio_verify_registers[i++];
801 unsigned char a = inb(pioaddr+reg);
802 unsigned char b = readb(ioaddr+reg);
803 if (a != b) {
804 rc = -EIO;
805 printk(KERN_ERR "MMIO do not match PIO [%02x] "
806 "(%02x != %02x)\n", reg, a, b);
807 goto err_out_unmap;
808 }
809 }
810#endif /* USE_MMIO */
811
812 dev->base_addr = (unsigned long)ioaddr;
813 rp->base = ioaddr;
814
815 /* Get chip registers into a sane state */
816 rhine_power_init(dev);
817 rhine_hw_init(dev, pioaddr);
818
819 for (i = 0; i < 6; i++)
820 dev->dev_addr[i] = ioread8(ioaddr + StationAddr + i);
John W. Linvilleb81e8e12005-09-12 10:48:58 -0400821 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700822
John W. Linvilleb81e8e12005-09-12 10:48:58 -0400823 if (!is_valid_ether_addr(dev->perm_addr)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700824 rc = -EIO;
825 printk(KERN_ERR "Invalid MAC address\n");
826 goto err_out_unmap;
827 }
828
829 /* For Rhine-I/II, phy_id is loaded from EEPROM */
830 if (!phy_id)
831 phy_id = ioread8(ioaddr + 0x6C);
832
833 dev->irq = pdev->irq;
834
835 spin_lock_init(&rp->lock);
836 rp->mii_if.dev = dev;
837 rp->mii_if.mdio_read = mdio_read;
838 rp->mii_if.mdio_write = mdio_write;
839 rp->mii_if.phy_id_mask = 0x1f;
840 rp->mii_if.reg_num_mask = 0x1f;
841
842 /* The chip-specific entries in the device structure. */
843 dev->open = rhine_open;
844 dev->hard_start_xmit = rhine_start_tx;
845 dev->stop = rhine_close;
846 dev->get_stats = rhine_get_stats;
847 dev->set_multicast_list = rhine_set_rx_mode;
848 dev->do_ioctl = netdev_ioctl;
849 dev->ethtool_ops = &netdev_ethtool_ops;
850 dev->tx_timeout = rhine_tx_timeout;
851 dev->watchdog_timeo = TX_TIMEOUT;
852#ifdef CONFIG_NET_POLL_CONTROLLER
853 dev->poll_controller = rhine_poll;
854#endif
855 if (rp->quirks & rqRhineI)
856 dev->features |= NETIF_F_SG|NETIF_F_HW_CSUM;
857
John W. Linville6ba98d32005-10-18 21:31:02 -0400858 INIT_WORK(&rp->tx_timeout_task,
859 (void (*)(void *))rhine_tx_timeout_task, dev);
860
861 INIT_WORK(&rp->check_media_task,
862 (void (*)(void *))rhine_check_media_task, dev);
863
Linus Torvalds1da177e2005-04-16 15:20:36 -0700864 /* dev->name not defined before register_netdev()! */
865 rc = register_netdev(dev);
866 if (rc)
867 goto err_out_unmap;
868
869 printk(KERN_INFO "%s: VIA %s at 0x%lx, ",
870 dev->name, name,
871#ifdef USE_MMIO
872 memaddr
873#else
874 (long)ioaddr
875#endif
876 );
877
878 for (i = 0; i < 5; i++)
879 printk("%2.2x:", dev->dev_addr[i]);
880 printk("%2.2x, IRQ %d.\n", dev->dev_addr[i], pdev->irq);
881
882 pci_set_drvdata(pdev, dev);
883
884 {
885 u16 mii_cmd;
886 int mii_status = mdio_read(dev, phy_id, 1);
887 mii_cmd = mdio_read(dev, phy_id, MII_BMCR) & ~BMCR_ISOLATE;
888 mdio_write(dev, phy_id, MII_BMCR, mii_cmd);
889 if (mii_status != 0xffff && mii_status != 0x0000) {
890 rp->mii_if.advertising = mdio_read(dev, phy_id, 4);
891 printk(KERN_INFO "%s: MII PHY found at address "
892 "%d, status 0x%4.4x advertising %4.4x "
893 "Link %4.4x.\n", dev->name, phy_id,
894 mii_status, rp->mii_if.advertising,
895 mdio_read(dev, phy_id, 5));
896
897 /* set IFF_RUNNING */
898 if (mii_status & BMSR_LSTATUS)
899 netif_carrier_on(dev);
900 else
901 netif_carrier_off(dev);
902
903 }
904 }
905 rp->mii_if.phy_id = phy_id;
906
907 return 0;
908
909err_out_unmap:
910 pci_iounmap(pdev, ioaddr);
911err_out_free_res:
912 pci_release_regions(pdev);
913err_out_free_netdev:
914 free_netdev(dev);
915err_out:
916 return rc;
917}
918
919static int alloc_ring(struct net_device* dev)
920{
921 struct rhine_private *rp = netdev_priv(dev);
922 void *ring;
923 dma_addr_t ring_dma;
924
925 ring = pci_alloc_consistent(rp->pdev,
926 RX_RING_SIZE * sizeof(struct rx_desc) +
927 TX_RING_SIZE * sizeof(struct tx_desc),
928 &ring_dma);
929 if (!ring) {
930 printk(KERN_ERR "Could not allocate DMA memory.\n");
931 return -ENOMEM;
932 }
933 if (rp->quirks & rqRhineI) {
934 rp->tx_bufs = pci_alloc_consistent(rp->pdev,
935 PKT_BUF_SZ * TX_RING_SIZE,
936 &rp->tx_bufs_dma);
937 if (rp->tx_bufs == NULL) {
938 pci_free_consistent(rp->pdev,
939 RX_RING_SIZE * sizeof(struct rx_desc) +
940 TX_RING_SIZE * sizeof(struct tx_desc),
941 ring, ring_dma);
942 return -ENOMEM;
943 }
944 }
945
946 rp->rx_ring = ring;
947 rp->tx_ring = ring + RX_RING_SIZE * sizeof(struct rx_desc);
948 rp->rx_ring_dma = ring_dma;
949 rp->tx_ring_dma = ring_dma + RX_RING_SIZE * sizeof(struct rx_desc);
950
951 return 0;
952}
953
954static void free_ring(struct net_device* dev)
955{
956 struct rhine_private *rp = netdev_priv(dev);
957
958 pci_free_consistent(rp->pdev,
959 RX_RING_SIZE * sizeof(struct rx_desc) +
960 TX_RING_SIZE * sizeof(struct tx_desc),
961 rp->rx_ring, rp->rx_ring_dma);
962 rp->tx_ring = NULL;
963
964 if (rp->tx_bufs)
965 pci_free_consistent(rp->pdev, PKT_BUF_SZ * TX_RING_SIZE,
966 rp->tx_bufs, rp->tx_bufs_dma);
967
968 rp->tx_bufs = NULL;
969
970}
971
972static void alloc_rbufs(struct net_device *dev)
973{
974 struct rhine_private *rp = netdev_priv(dev);
975 dma_addr_t next;
976 int i;
977
978 rp->dirty_rx = rp->cur_rx = 0;
979
980 rp->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32);
981 rp->rx_head_desc = &rp->rx_ring[0];
982 next = rp->rx_ring_dma;
983
984 /* Init the ring entries */
985 for (i = 0; i < RX_RING_SIZE; i++) {
986 rp->rx_ring[i].rx_status = 0;
987 rp->rx_ring[i].desc_length = cpu_to_le32(rp->rx_buf_sz);
988 next += sizeof(struct rx_desc);
989 rp->rx_ring[i].next_desc = cpu_to_le32(next);
990 rp->rx_skbuff[i] = NULL;
991 }
992 /* Mark the last entry as wrapping the ring. */
993 rp->rx_ring[i-1].next_desc = cpu_to_le32(rp->rx_ring_dma);
994
995 /* Fill in the Rx buffers. Handle allocation failure gracefully. */
996 for (i = 0; i < RX_RING_SIZE; i++) {
997 struct sk_buff *skb = dev_alloc_skb(rp->rx_buf_sz);
998 rp->rx_skbuff[i] = skb;
999 if (skb == NULL)
1000 break;
1001 skb->dev = dev; /* Mark as being used by this device. */
1002
1003 rp->rx_skbuff_dma[i] =
David S. Miller689be432005-06-28 15:25:31 -07001004 pci_map_single(rp->pdev, skb->data, rp->rx_buf_sz,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001005 PCI_DMA_FROMDEVICE);
1006
1007 rp->rx_ring[i].addr = cpu_to_le32(rp->rx_skbuff_dma[i]);
1008 rp->rx_ring[i].rx_status = cpu_to_le32(DescOwn);
1009 }
1010 rp->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
1011}
1012
1013static void free_rbufs(struct net_device* dev)
1014{
1015 struct rhine_private *rp = netdev_priv(dev);
1016 int i;
1017
1018 /* Free all the skbuffs in the Rx queue. */
1019 for (i = 0; i < RX_RING_SIZE; i++) {
1020 rp->rx_ring[i].rx_status = 0;
1021 rp->rx_ring[i].addr = cpu_to_le32(0xBADF00D0); /* An invalid address. */
1022 if (rp->rx_skbuff[i]) {
1023 pci_unmap_single(rp->pdev,
1024 rp->rx_skbuff_dma[i],
1025 rp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1026 dev_kfree_skb(rp->rx_skbuff[i]);
1027 }
1028 rp->rx_skbuff[i] = NULL;
1029 }
1030}
1031
1032static void alloc_tbufs(struct net_device* dev)
1033{
1034 struct rhine_private *rp = netdev_priv(dev);
1035 dma_addr_t next;
1036 int i;
1037
1038 rp->dirty_tx = rp->cur_tx = 0;
1039 next = rp->tx_ring_dma;
1040 for (i = 0; i < TX_RING_SIZE; i++) {
1041 rp->tx_skbuff[i] = NULL;
1042 rp->tx_ring[i].tx_status = 0;
1043 rp->tx_ring[i].desc_length = cpu_to_le32(TXDESC);
1044 next += sizeof(struct tx_desc);
1045 rp->tx_ring[i].next_desc = cpu_to_le32(next);
Roger Luethi4be5de22006-04-04 20:49:16 +02001046 if (rp->quirks & rqRhineI)
1047 rp->tx_buf[i] = &rp->tx_bufs[i * PKT_BUF_SZ];
Linus Torvalds1da177e2005-04-16 15:20:36 -07001048 }
1049 rp->tx_ring[i-1].next_desc = cpu_to_le32(rp->tx_ring_dma);
1050
1051}
1052
1053static void free_tbufs(struct net_device* dev)
1054{
1055 struct rhine_private *rp = netdev_priv(dev);
1056 int i;
1057
1058 for (i = 0; i < TX_RING_SIZE; i++) {
1059 rp->tx_ring[i].tx_status = 0;
1060 rp->tx_ring[i].desc_length = cpu_to_le32(TXDESC);
1061 rp->tx_ring[i].addr = cpu_to_le32(0xBADF00D0); /* An invalid address. */
1062 if (rp->tx_skbuff[i]) {
1063 if (rp->tx_skbuff_dma[i]) {
1064 pci_unmap_single(rp->pdev,
1065 rp->tx_skbuff_dma[i],
1066 rp->tx_skbuff[i]->len,
1067 PCI_DMA_TODEVICE);
1068 }
1069 dev_kfree_skb(rp->tx_skbuff[i]);
1070 }
1071 rp->tx_skbuff[i] = NULL;
1072 rp->tx_buf[i] = NULL;
1073 }
1074}
1075
1076static void rhine_check_media(struct net_device *dev, unsigned int init_media)
1077{
1078 struct rhine_private *rp = netdev_priv(dev);
1079 void __iomem *ioaddr = rp->base;
1080
1081 mii_check_media(&rp->mii_if, debug, init_media);
1082
1083 if (rp->mii_if.full_duplex)
1084 iowrite8(ioread8(ioaddr + ChipCmd1) | Cmd1FDuplex,
1085 ioaddr + ChipCmd1);
1086 else
1087 iowrite8(ioread8(ioaddr + ChipCmd1) & ~Cmd1FDuplex,
1088 ioaddr + ChipCmd1);
Roger Luethi00b428c2006-03-28 20:53:56 +02001089 if (debug > 1)
1090 printk(KERN_INFO "%s: force_media %d, carrier %d\n", dev->name,
1091 rp->mii_if.force_media, netif_carrier_ok(dev));
1092}
1093
1094/* Called after status of force_media possibly changed */
1095void rhine_set_carrier(struct mii_if_info *mii)
1096{
1097 if (mii->force_media) {
1098 /* autoneg is off: Link is always assumed to be up */
1099 if (!netif_carrier_ok(mii->dev))
1100 netif_carrier_on(mii->dev);
1101 }
1102 else /* Let MMI library update carrier status */
1103 rhine_check_media(mii->dev, 0);
1104 if (debug > 1)
1105 printk(KERN_INFO "%s: force_media %d, carrier %d\n",
1106 mii->dev->name, mii->force_media,
1107 netif_carrier_ok(mii->dev));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001108}
1109
John W. Linville6ba98d32005-10-18 21:31:02 -04001110static void rhine_check_media_task(struct net_device *dev)
1111{
1112 rhine_check_media(dev, 0);
1113}
1114
Linus Torvalds1da177e2005-04-16 15:20:36 -07001115static void init_registers(struct net_device *dev)
1116{
1117 struct rhine_private *rp = netdev_priv(dev);
1118 void __iomem *ioaddr = rp->base;
1119 int i;
1120
1121 for (i = 0; i < 6; i++)
1122 iowrite8(dev->dev_addr[i], ioaddr + StationAddr + i);
1123
1124 /* Initialize other registers. */
1125 iowrite16(0x0006, ioaddr + PCIBusConfig); /* Tune configuration??? */
1126 /* Configure initial FIFO thresholds. */
1127 iowrite8(0x20, ioaddr + TxConfig);
1128 rp->tx_thresh = 0x20;
1129 rp->rx_thresh = 0x60; /* Written in rhine_set_rx_mode(). */
1130
1131 iowrite32(rp->rx_ring_dma, ioaddr + RxRingPtr);
1132 iowrite32(rp->tx_ring_dma, ioaddr + TxRingPtr);
1133
1134 rhine_set_rx_mode(dev);
1135
1136 /* Enable interrupts by setting the interrupt mask. */
1137 iowrite16(IntrRxDone | IntrRxErr | IntrRxEmpty| IntrRxOverflow |
1138 IntrRxDropped | IntrRxNoBuf | IntrTxAborted |
1139 IntrTxDone | IntrTxError | IntrTxUnderrun |
1140 IntrPCIErr | IntrStatsMax | IntrLinkChange,
1141 ioaddr + IntrEnable);
1142
1143 iowrite16(CmdStart | CmdTxOn | CmdRxOn | (Cmd1NoTxPoll << 8),
1144 ioaddr + ChipCmd);
1145 rhine_check_media(dev, 1);
1146}
1147
1148/* Enable MII link status auto-polling (required for IntrLinkChange) */
1149static void rhine_enable_linkmon(void __iomem *ioaddr)
1150{
1151 iowrite8(0, ioaddr + MIICmd);
1152 iowrite8(MII_BMSR, ioaddr + MIIRegAddr);
1153 iowrite8(0x80, ioaddr + MIICmd);
1154
1155 RHINE_WAIT_FOR((ioread8(ioaddr + MIIRegAddr) & 0x20));
1156
1157 iowrite8(MII_BMSR | 0x40, ioaddr + MIIRegAddr);
1158}
1159
1160/* Disable MII link status auto-polling (required for MDIO access) */
1161static void rhine_disable_linkmon(void __iomem *ioaddr, u32 quirks)
1162{
1163 iowrite8(0, ioaddr + MIICmd);
1164
1165 if (quirks & rqRhineI) {
1166 iowrite8(0x01, ioaddr + MIIRegAddr); // MII_BMSR
1167
John W. Linville6ba98d32005-10-18 21:31:02 -04001168 /* Do not call from ISR! */
1169 msleep(1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001170
1171 /* 0x80 must be set immediately before turning it off */
1172 iowrite8(0x80, ioaddr + MIICmd);
1173
1174 RHINE_WAIT_FOR(ioread8(ioaddr + MIIRegAddr) & 0x20);
1175
1176 /* Heh. Now clear 0x80 again. */
1177 iowrite8(0, ioaddr + MIICmd);
1178 }
1179 else
1180 RHINE_WAIT_FOR(ioread8(ioaddr + MIIRegAddr) & 0x80);
1181}
1182
1183/* Read and write over the MII Management Data I/O (MDIO) interface. */
1184
1185static int mdio_read(struct net_device *dev, int phy_id, int regnum)
1186{
1187 struct rhine_private *rp = netdev_priv(dev);
1188 void __iomem *ioaddr = rp->base;
1189 int result;
1190
1191 rhine_disable_linkmon(ioaddr, rp->quirks);
1192
1193 /* rhine_disable_linkmon already cleared MIICmd */
1194 iowrite8(phy_id, ioaddr + MIIPhyAddr);
1195 iowrite8(regnum, ioaddr + MIIRegAddr);
1196 iowrite8(0x40, ioaddr + MIICmd); /* Trigger read */
1197 RHINE_WAIT_FOR(!(ioread8(ioaddr + MIICmd) & 0x40));
1198 result = ioread16(ioaddr + MIIData);
1199
1200 rhine_enable_linkmon(ioaddr);
1201 return result;
1202}
1203
1204static void mdio_write(struct net_device *dev, int phy_id, int regnum, int value)
1205{
1206 struct rhine_private *rp = netdev_priv(dev);
1207 void __iomem *ioaddr = rp->base;
1208
1209 rhine_disable_linkmon(ioaddr, rp->quirks);
1210
1211 /* rhine_disable_linkmon already cleared MIICmd */
1212 iowrite8(phy_id, ioaddr + MIIPhyAddr);
1213 iowrite8(regnum, ioaddr + MIIRegAddr);
1214 iowrite16(value, ioaddr + MIIData);
1215 iowrite8(0x20, ioaddr + MIICmd); /* Trigger write */
1216 RHINE_WAIT_FOR(!(ioread8(ioaddr + MIICmd) & 0x20));
1217
1218 rhine_enable_linkmon(ioaddr);
1219}
1220
1221static int rhine_open(struct net_device *dev)
1222{
1223 struct rhine_private *rp = netdev_priv(dev);
1224 void __iomem *ioaddr = rp->base;
1225 int rc;
1226
1227 rc = request_irq(rp->pdev->irq, &rhine_interrupt, SA_SHIRQ, dev->name,
1228 dev);
1229 if (rc)
1230 return rc;
1231
1232 if (debug > 1)
1233 printk(KERN_DEBUG "%s: rhine_open() irq %d.\n",
1234 dev->name, rp->pdev->irq);
1235
1236 rc = alloc_ring(dev);
1237 if (rc) {
1238 free_irq(rp->pdev->irq, dev);
1239 return rc;
1240 }
1241 alloc_rbufs(dev);
1242 alloc_tbufs(dev);
1243 rhine_chip_reset(dev);
1244 init_registers(dev);
1245 if (debug > 2)
1246 printk(KERN_DEBUG "%s: Done rhine_open(), status %4.4x "
1247 "MII status: %4.4x.\n",
1248 dev->name, ioread16(ioaddr + ChipCmd),
1249 mdio_read(dev, rp->mii_if.phy_id, MII_BMSR));
1250
1251 netif_start_queue(dev);
1252
1253 return 0;
1254}
1255
1256static void rhine_tx_timeout(struct net_device *dev)
1257{
1258 struct rhine_private *rp = netdev_priv(dev);
John W. Linville6ba98d32005-10-18 21:31:02 -04001259
1260 /*
1261 * Move bulk of work outside of interrupt context
1262 */
1263 schedule_work(&rp->tx_timeout_task);
1264}
1265
1266static void rhine_tx_timeout_task(struct net_device *dev)
1267{
1268 struct rhine_private *rp = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001269 void __iomem *ioaddr = rp->base;
1270
1271 printk(KERN_WARNING "%s: Transmit timed out, status %4.4x, PHY status "
1272 "%4.4x, resetting...\n",
1273 dev->name, ioread16(ioaddr + IntrStatus),
1274 mdio_read(dev, rp->mii_if.phy_id, MII_BMSR));
1275
1276 /* protect against concurrent rx interrupts */
1277 disable_irq(rp->pdev->irq);
1278
1279 spin_lock(&rp->lock);
1280
1281 /* clear all descriptors */
1282 free_tbufs(dev);
1283 free_rbufs(dev);
1284 alloc_tbufs(dev);
1285 alloc_rbufs(dev);
1286
1287 /* Reinitialize the hardware. */
1288 rhine_chip_reset(dev);
1289 init_registers(dev);
1290
1291 spin_unlock(&rp->lock);
1292 enable_irq(rp->pdev->irq);
1293
1294 dev->trans_start = jiffies;
1295 rp->stats.tx_errors++;
1296 netif_wake_queue(dev);
1297}
1298
1299static int rhine_start_tx(struct sk_buff *skb, struct net_device *dev)
1300{
1301 struct rhine_private *rp = netdev_priv(dev);
1302 void __iomem *ioaddr = rp->base;
1303 unsigned entry;
1304
1305 /* Caution: the write order is important here, set the field
1306 with the "ownership" bits last. */
1307
1308 /* Calculate the next Tx descriptor entry. */
1309 entry = rp->cur_tx % TX_RING_SIZE;
1310
1311 if (skb->len < ETH_ZLEN) {
1312 skb = skb_padto(skb, ETH_ZLEN);
1313 if (skb == NULL)
1314 return 0;
1315 }
1316
1317 rp->tx_skbuff[entry] = skb;
1318
1319 if ((rp->quirks & rqRhineI) &&
1320 (((unsigned long)skb->data & 3) || skb_shinfo(skb)->nr_frags != 0 || skb->ip_summed == CHECKSUM_HW)) {
1321 /* Must use alignment buffer. */
1322 if (skb->len > PKT_BUF_SZ) {
1323 /* packet too long, drop it */
1324 dev_kfree_skb(skb);
1325 rp->tx_skbuff[entry] = NULL;
1326 rp->stats.tx_dropped++;
1327 return 0;
1328 }
1329 skb_copy_and_csum_dev(skb, rp->tx_buf[entry]);
1330 rp->tx_skbuff_dma[entry] = 0;
1331 rp->tx_ring[entry].addr = cpu_to_le32(rp->tx_bufs_dma +
1332 (rp->tx_buf[entry] -
1333 rp->tx_bufs));
1334 } else {
1335 rp->tx_skbuff_dma[entry] =
1336 pci_map_single(rp->pdev, skb->data, skb->len,
1337 PCI_DMA_TODEVICE);
1338 rp->tx_ring[entry].addr = cpu_to_le32(rp->tx_skbuff_dma[entry]);
1339 }
1340
1341 rp->tx_ring[entry].desc_length =
1342 cpu_to_le32(TXDESC | (skb->len >= ETH_ZLEN ? skb->len : ETH_ZLEN));
1343
1344 /* lock eth irq */
1345 spin_lock_irq(&rp->lock);
1346 wmb();
1347 rp->tx_ring[entry].tx_status = cpu_to_le32(DescOwn);
1348 wmb();
1349
1350 rp->cur_tx++;
1351
1352 /* Non-x86 Todo: explicitly flush cache lines here. */
1353
1354 /* Wake the potentially-idle transmit channel */
1355 iowrite8(ioread8(ioaddr + ChipCmd1) | Cmd1TxDemand,
1356 ioaddr + ChipCmd1);
1357 IOSYNC;
1358
1359 if (rp->cur_tx == rp->dirty_tx + TX_QUEUE_LEN)
1360 netif_stop_queue(dev);
1361
1362 dev->trans_start = jiffies;
1363
1364 spin_unlock_irq(&rp->lock);
1365
1366 if (debug > 4) {
1367 printk(KERN_DEBUG "%s: Transmit frame #%d queued in slot %d.\n",
1368 dev->name, rp->cur_tx-1, entry);
1369 }
1370 return 0;
1371}
1372
1373/* The interrupt handler does all of the Rx thread work and cleans up
1374 after the Tx thread. */
1375static irqreturn_t rhine_interrupt(int irq, void *dev_instance, struct pt_regs *rgs)
1376{
1377 struct net_device *dev = dev_instance;
1378 struct rhine_private *rp = netdev_priv(dev);
1379 void __iomem *ioaddr = rp->base;
1380 u32 intr_status;
1381 int boguscnt = max_interrupt_work;
1382 int handled = 0;
1383
1384 while ((intr_status = get_intr_status(dev))) {
1385 handled = 1;
1386
1387 /* Acknowledge all of the current interrupt sources ASAP. */
1388 if (intr_status & IntrTxDescRace)
1389 iowrite8(0x08, ioaddr + IntrStatus2);
1390 iowrite16(intr_status & 0xffff, ioaddr + IntrStatus);
1391 IOSYNC;
1392
1393 if (debug > 4)
1394 printk(KERN_DEBUG "%s: Interrupt, status %8.8x.\n",
1395 dev->name, intr_status);
1396
1397 if (intr_status & (IntrRxDone | IntrRxErr | IntrRxDropped |
1398 IntrRxWakeUp | IntrRxEmpty | IntrRxNoBuf))
1399 rhine_rx(dev);
1400
1401 if (intr_status & (IntrTxErrSummary | IntrTxDone)) {
1402 if (intr_status & IntrTxErrSummary) {
1403 /* Avoid scavenging before Tx engine turned off */
1404 RHINE_WAIT_FOR(!(ioread8(ioaddr+ChipCmd) & CmdTxOn));
1405 if (debug > 2 &&
1406 ioread8(ioaddr+ChipCmd) & CmdTxOn)
1407 printk(KERN_WARNING "%s: "
1408 "rhine_interrupt() Tx engine"
1409 "still on.\n", dev->name);
1410 }
1411 rhine_tx(dev);
1412 }
1413
1414 /* Abnormal error summary/uncommon events handlers. */
1415 if (intr_status & (IntrPCIErr | IntrLinkChange |
1416 IntrStatsMax | IntrTxError | IntrTxAborted |
1417 IntrTxUnderrun | IntrTxDescRace))
1418 rhine_error(dev, intr_status);
1419
1420 if (--boguscnt < 0) {
1421 printk(KERN_WARNING "%s: Too much work at interrupt, "
1422 "status=%#8.8x.\n",
1423 dev->name, intr_status);
1424 break;
1425 }
1426 }
1427
1428 if (debug > 3)
1429 printk(KERN_DEBUG "%s: exiting interrupt, status=%8.8x.\n",
1430 dev->name, ioread16(ioaddr + IntrStatus));
1431 return IRQ_RETVAL(handled);
1432}
1433
1434/* This routine is logically part of the interrupt handler, but isolated
1435 for clarity. */
1436static void rhine_tx(struct net_device *dev)
1437{
1438 struct rhine_private *rp = netdev_priv(dev);
1439 int txstatus = 0, entry = rp->dirty_tx % TX_RING_SIZE;
1440
1441 spin_lock(&rp->lock);
1442
1443 /* find and cleanup dirty tx descriptors */
1444 while (rp->dirty_tx != rp->cur_tx) {
1445 txstatus = le32_to_cpu(rp->tx_ring[entry].tx_status);
1446 if (debug > 6)
Denis Vlasenkoed4030d2005-06-17 08:23:17 +03001447 printk(KERN_DEBUG "Tx scavenge %d status %8.8x.\n",
Linus Torvalds1da177e2005-04-16 15:20:36 -07001448 entry, txstatus);
1449 if (txstatus & DescOwn)
1450 break;
1451 if (txstatus & 0x8000) {
1452 if (debug > 1)
1453 printk(KERN_DEBUG "%s: Transmit error, "
1454 "Tx status %8.8x.\n",
1455 dev->name, txstatus);
1456 rp->stats.tx_errors++;
1457 if (txstatus & 0x0400) rp->stats.tx_carrier_errors++;
1458 if (txstatus & 0x0200) rp->stats.tx_window_errors++;
1459 if (txstatus & 0x0100) rp->stats.tx_aborted_errors++;
1460 if (txstatus & 0x0080) rp->stats.tx_heartbeat_errors++;
1461 if (((rp->quirks & rqRhineI) && txstatus & 0x0002) ||
1462 (txstatus & 0x0800) || (txstatus & 0x1000)) {
1463 rp->stats.tx_fifo_errors++;
1464 rp->tx_ring[entry].tx_status = cpu_to_le32(DescOwn);
1465 break; /* Keep the skb - we try again */
1466 }
1467 /* Transmitter restarted in 'abnormal' handler. */
1468 } else {
1469 if (rp->quirks & rqRhineI)
1470 rp->stats.collisions += (txstatus >> 3) & 0x0F;
1471 else
1472 rp->stats.collisions += txstatus & 0x0F;
1473 if (debug > 6)
1474 printk(KERN_DEBUG "collisions: %1.1x:%1.1x\n",
1475 (txstatus >> 3) & 0xF,
1476 txstatus & 0xF);
1477 rp->stats.tx_bytes += rp->tx_skbuff[entry]->len;
1478 rp->stats.tx_packets++;
1479 }
1480 /* Free the original skb. */
1481 if (rp->tx_skbuff_dma[entry]) {
1482 pci_unmap_single(rp->pdev,
1483 rp->tx_skbuff_dma[entry],
1484 rp->tx_skbuff[entry]->len,
1485 PCI_DMA_TODEVICE);
1486 }
1487 dev_kfree_skb_irq(rp->tx_skbuff[entry]);
1488 rp->tx_skbuff[entry] = NULL;
1489 entry = (++rp->dirty_tx) % TX_RING_SIZE;
1490 }
1491 if ((rp->cur_tx - rp->dirty_tx) < TX_QUEUE_LEN - 4)
1492 netif_wake_queue(dev);
1493
1494 spin_unlock(&rp->lock);
1495}
1496
1497/* This routine is logically part of the interrupt handler, but isolated
1498 for clarity and better register allocation. */
1499static void rhine_rx(struct net_device *dev)
1500{
1501 struct rhine_private *rp = netdev_priv(dev);
1502 int entry = rp->cur_rx % RX_RING_SIZE;
1503 int boguscnt = rp->dirty_rx + RX_RING_SIZE - rp->cur_rx;
1504
1505 if (debug > 4) {
1506 printk(KERN_DEBUG "%s: rhine_rx(), entry %d status %8.8x.\n",
1507 dev->name, entry,
1508 le32_to_cpu(rp->rx_head_desc->rx_status));
1509 }
1510
1511 /* If EOP is set on the next entry, it's a new packet. Send it up. */
1512 while (!(rp->rx_head_desc->rx_status & cpu_to_le32(DescOwn))) {
1513 struct rx_desc *desc = rp->rx_head_desc;
1514 u32 desc_status = le32_to_cpu(desc->rx_status);
1515 int data_size = desc_status >> 16;
1516
1517 if (debug > 4)
Denis Vlasenkoed4030d2005-06-17 08:23:17 +03001518 printk(KERN_DEBUG "rhine_rx() status is %8.8x.\n",
Linus Torvalds1da177e2005-04-16 15:20:36 -07001519 desc_status);
1520 if (--boguscnt < 0)
1521 break;
1522 if ((desc_status & (RxWholePkt | RxErr)) != RxWholePkt) {
1523 if ((desc_status & RxWholePkt) != RxWholePkt) {
1524 printk(KERN_WARNING "%s: Oversized Ethernet "
1525 "frame spanned multiple buffers, entry "
1526 "%#x length %d status %8.8x!\n",
1527 dev->name, entry, data_size,
1528 desc_status);
1529 printk(KERN_WARNING "%s: Oversized Ethernet "
1530 "frame %p vs %p.\n", dev->name,
1531 rp->rx_head_desc, &rp->rx_ring[entry]);
1532 rp->stats.rx_length_errors++;
1533 } else if (desc_status & RxErr) {
1534 /* There was a error. */
1535 if (debug > 2)
Denis Vlasenkoed4030d2005-06-17 08:23:17 +03001536 printk(KERN_DEBUG "rhine_rx() Rx "
Linus Torvalds1da177e2005-04-16 15:20:36 -07001537 "error was %8.8x.\n",
1538 desc_status);
1539 rp->stats.rx_errors++;
1540 if (desc_status & 0x0030) rp->stats.rx_length_errors++;
1541 if (desc_status & 0x0048) rp->stats.rx_fifo_errors++;
1542 if (desc_status & 0x0004) rp->stats.rx_frame_errors++;
1543 if (desc_status & 0x0002) {
1544 /* this can also be updated outside the interrupt handler */
1545 spin_lock(&rp->lock);
1546 rp->stats.rx_crc_errors++;
1547 spin_unlock(&rp->lock);
1548 }
1549 }
1550 } else {
1551 struct sk_buff *skb;
1552 /* Length should omit the CRC */
1553 int pkt_len = data_size - 4;
1554
1555 /* Check if the packet is long enough to accept without
1556 copying to a minimally-sized skbuff. */
1557 if (pkt_len < rx_copybreak &&
1558 (skb = dev_alloc_skb(pkt_len + 2)) != NULL) {
1559 skb->dev = dev;
1560 skb_reserve(skb, 2); /* 16 byte align the IP header */
1561 pci_dma_sync_single_for_cpu(rp->pdev,
1562 rp->rx_skbuff_dma[entry],
1563 rp->rx_buf_sz,
1564 PCI_DMA_FROMDEVICE);
1565
1566 eth_copy_and_sum(skb,
David S. Miller689be432005-06-28 15:25:31 -07001567 rp->rx_skbuff[entry]->data,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001568 pkt_len, 0);
1569 skb_put(skb, pkt_len);
1570 pci_dma_sync_single_for_device(rp->pdev,
1571 rp->rx_skbuff_dma[entry],
1572 rp->rx_buf_sz,
1573 PCI_DMA_FROMDEVICE);
1574 } else {
1575 skb = rp->rx_skbuff[entry];
1576 if (skb == NULL) {
1577 printk(KERN_ERR "%s: Inconsistent Rx "
1578 "descriptor chain.\n",
1579 dev->name);
1580 break;
1581 }
1582 rp->rx_skbuff[entry] = NULL;
1583 skb_put(skb, pkt_len);
1584 pci_unmap_single(rp->pdev,
1585 rp->rx_skbuff_dma[entry],
1586 rp->rx_buf_sz,
1587 PCI_DMA_FROMDEVICE);
1588 }
1589 skb->protocol = eth_type_trans(skb, dev);
1590 netif_rx(skb);
1591 dev->last_rx = jiffies;
1592 rp->stats.rx_bytes += pkt_len;
1593 rp->stats.rx_packets++;
1594 }
1595 entry = (++rp->cur_rx) % RX_RING_SIZE;
1596 rp->rx_head_desc = &rp->rx_ring[entry];
1597 }
1598
1599 /* Refill the Rx ring buffers. */
1600 for (; rp->cur_rx - rp->dirty_rx > 0; rp->dirty_rx++) {
1601 struct sk_buff *skb;
1602 entry = rp->dirty_rx % RX_RING_SIZE;
1603 if (rp->rx_skbuff[entry] == NULL) {
1604 skb = dev_alloc_skb(rp->rx_buf_sz);
1605 rp->rx_skbuff[entry] = skb;
1606 if (skb == NULL)
1607 break; /* Better luck next round. */
1608 skb->dev = dev; /* Mark as being used by this device. */
1609 rp->rx_skbuff_dma[entry] =
David S. Miller689be432005-06-28 15:25:31 -07001610 pci_map_single(rp->pdev, skb->data,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001611 rp->rx_buf_sz,
1612 PCI_DMA_FROMDEVICE);
1613 rp->rx_ring[entry].addr = cpu_to_le32(rp->rx_skbuff_dma[entry]);
1614 }
1615 rp->rx_ring[entry].rx_status = cpu_to_le32(DescOwn);
1616 }
1617}
1618
1619/*
1620 * Clears the "tally counters" for CRC errors and missed frames(?).
1621 * It has been reported that some chips need a write of 0 to clear
1622 * these, for others the counters are set to 1 when written to and
1623 * instead cleared when read. So we clear them both ways ...
1624 */
1625static inline void clear_tally_counters(void __iomem *ioaddr)
1626{
1627 iowrite32(0, ioaddr + RxMissed);
1628 ioread16(ioaddr + RxCRCErrs);
1629 ioread16(ioaddr + RxMissed);
1630}
1631
1632static void rhine_restart_tx(struct net_device *dev) {
1633 struct rhine_private *rp = netdev_priv(dev);
1634 void __iomem *ioaddr = rp->base;
1635 int entry = rp->dirty_tx % TX_RING_SIZE;
1636 u32 intr_status;
1637
1638 /*
1639 * If new errors occured, we need to sort them out before doing Tx.
1640 * In that case the ISR will be back here RSN anyway.
1641 */
1642 intr_status = get_intr_status(dev);
1643
1644 if ((intr_status & IntrTxErrSummary) == 0) {
1645
1646 /* We know better than the chip where it should continue. */
1647 iowrite32(rp->tx_ring_dma + entry * sizeof(struct tx_desc),
1648 ioaddr + TxRingPtr);
1649
1650 iowrite8(ioread8(ioaddr + ChipCmd) | CmdTxOn,
1651 ioaddr + ChipCmd);
1652 iowrite8(ioread8(ioaddr + ChipCmd1) | Cmd1TxDemand,
1653 ioaddr + ChipCmd1);
1654 IOSYNC;
1655 }
1656 else {
1657 /* This should never happen */
1658 if (debug > 1)
1659 printk(KERN_WARNING "%s: rhine_restart_tx() "
1660 "Another error occured %8.8x.\n",
1661 dev->name, intr_status);
1662 }
1663
1664}
1665
1666static void rhine_error(struct net_device *dev, int intr_status)
1667{
1668 struct rhine_private *rp = netdev_priv(dev);
1669 void __iomem *ioaddr = rp->base;
1670
1671 spin_lock(&rp->lock);
1672
1673 if (intr_status & IntrLinkChange)
John W. Linville6ba98d32005-10-18 21:31:02 -04001674 schedule_work(&rp->check_media_task);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001675 if (intr_status & IntrStatsMax) {
1676 rp->stats.rx_crc_errors += ioread16(ioaddr + RxCRCErrs);
1677 rp->stats.rx_missed_errors += ioread16(ioaddr + RxMissed);
1678 clear_tally_counters(ioaddr);
1679 }
1680 if (intr_status & IntrTxAborted) {
1681 if (debug > 1)
1682 printk(KERN_INFO "%s: Abort %8.8x, frame dropped.\n",
1683 dev->name, intr_status);
1684 }
1685 if (intr_status & IntrTxUnderrun) {
1686 if (rp->tx_thresh < 0xE0)
1687 iowrite8(rp->tx_thresh += 0x20, ioaddr + TxConfig);
1688 if (debug > 1)
1689 printk(KERN_INFO "%s: Transmitter underrun, Tx "
1690 "threshold now %2.2x.\n",
1691 dev->name, rp->tx_thresh);
1692 }
1693 if (intr_status & IntrTxDescRace) {
1694 if (debug > 2)
1695 printk(KERN_INFO "%s: Tx descriptor write-back race.\n",
1696 dev->name);
1697 }
1698 if ((intr_status & IntrTxError) &&
1699 (intr_status & (IntrTxAborted |
1700 IntrTxUnderrun | IntrTxDescRace)) == 0) {
1701 if (rp->tx_thresh < 0xE0) {
1702 iowrite8(rp->tx_thresh += 0x20, ioaddr + TxConfig);
1703 }
1704 if (debug > 1)
1705 printk(KERN_INFO "%s: Unspecified error. Tx "
1706 "threshold now %2.2x.\n",
1707 dev->name, rp->tx_thresh);
1708 }
1709 if (intr_status & (IntrTxAborted | IntrTxUnderrun | IntrTxDescRace |
1710 IntrTxError))
1711 rhine_restart_tx(dev);
1712
1713 if (intr_status & ~(IntrLinkChange | IntrStatsMax | IntrTxUnderrun |
1714 IntrTxError | IntrTxAborted | IntrNormalSummary |
1715 IntrTxDescRace)) {
1716 if (debug > 1)
1717 printk(KERN_ERR "%s: Something Wicked happened! "
1718 "%8.8x.\n", dev->name, intr_status);
1719 }
1720
1721 spin_unlock(&rp->lock);
1722}
1723
1724static struct net_device_stats *rhine_get_stats(struct net_device *dev)
1725{
1726 struct rhine_private *rp = netdev_priv(dev);
1727 void __iomem *ioaddr = rp->base;
1728 unsigned long flags;
1729
1730 spin_lock_irqsave(&rp->lock, flags);
1731 rp->stats.rx_crc_errors += ioread16(ioaddr + RxCRCErrs);
1732 rp->stats.rx_missed_errors += ioread16(ioaddr + RxMissed);
1733 clear_tally_counters(ioaddr);
1734 spin_unlock_irqrestore(&rp->lock, flags);
1735
1736 return &rp->stats;
1737}
1738
1739static void rhine_set_rx_mode(struct net_device *dev)
1740{
1741 struct rhine_private *rp = netdev_priv(dev);
1742 void __iomem *ioaddr = rp->base;
1743 u32 mc_filter[2]; /* Multicast hash filter */
1744 u8 rx_mode; /* Note: 0x02=accept runt, 0x01=accept errs */
1745
1746 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1747 /* Unconditionally log net taps. */
1748 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
1749 dev->name);
1750 rx_mode = 0x1C;
1751 iowrite32(0xffffffff, ioaddr + MulticastFilter0);
1752 iowrite32(0xffffffff, ioaddr + MulticastFilter1);
1753 } else if ((dev->mc_count > multicast_filter_limit)
1754 || (dev->flags & IFF_ALLMULTI)) {
1755 /* Too many to match, or accept all multicasts. */
1756 iowrite32(0xffffffff, ioaddr + MulticastFilter0);
1757 iowrite32(0xffffffff, ioaddr + MulticastFilter1);
1758 rx_mode = 0x0C;
1759 } else {
1760 struct dev_mc_list *mclist;
1761 int i;
1762 memset(mc_filter, 0, sizeof(mc_filter));
1763 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1764 i++, mclist = mclist->next) {
1765 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
1766
1767 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
1768 }
1769 iowrite32(mc_filter[0], ioaddr + MulticastFilter0);
1770 iowrite32(mc_filter[1], ioaddr + MulticastFilter1);
1771 rx_mode = 0x0C;
1772 }
1773 iowrite8(rp->rx_thresh | rx_mode, ioaddr + RxConfig);
1774}
1775
1776static void netdev_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1777{
1778 struct rhine_private *rp = netdev_priv(dev);
1779
1780 strcpy(info->driver, DRV_NAME);
1781 strcpy(info->version, DRV_VERSION);
1782 strcpy(info->bus_info, pci_name(rp->pdev));
1783}
1784
1785static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1786{
1787 struct rhine_private *rp = netdev_priv(dev);
1788 int rc;
1789
1790 spin_lock_irq(&rp->lock);
1791 rc = mii_ethtool_gset(&rp->mii_if, cmd);
1792 spin_unlock_irq(&rp->lock);
1793
1794 return rc;
1795}
1796
1797static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1798{
1799 struct rhine_private *rp = netdev_priv(dev);
1800 int rc;
1801
1802 spin_lock_irq(&rp->lock);
1803 rc = mii_ethtool_sset(&rp->mii_if, cmd);
1804 spin_unlock_irq(&rp->lock);
Roger Luethi00b428c2006-03-28 20:53:56 +02001805 rhine_set_carrier(&rp->mii_if);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001806
1807 return rc;
1808}
1809
1810static int netdev_nway_reset(struct net_device *dev)
1811{
1812 struct rhine_private *rp = netdev_priv(dev);
1813
1814 return mii_nway_restart(&rp->mii_if);
1815}
1816
1817static u32 netdev_get_link(struct net_device *dev)
1818{
1819 struct rhine_private *rp = netdev_priv(dev);
1820
1821 return mii_link_ok(&rp->mii_if);
1822}
1823
1824static u32 netdev_get_msglevel(struct net_device *dev)
1825{
1826 return debug;
1827}
1828
1829static void netdev_set_msglevel(struct net_device *dev, u32 value)
1830{
1831 debug = value;
1832}
1833
1834static void rhine_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1835{
1836 struct rhine_private *rp = netdev_priv(dev);
1837
1838 if (!(rp->quirks & rqWOL))
1839 return;
1840
1841 spin_lock_irq(&rp->lock);
1842 wol->supported = WAKE_PHY | WAKE_MAGIC |
1843 WAKE_UCAST | WAKE_MCAST | WAKE_BCAST; /* Untested */
1844 wol->wolopts = rp->wolopts;
1845 spin_unlock_irq(&rp->lock);
1846}
1847
1848static int rhine_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1849{
1850 struct rhine_private *rp = netdev_priv(dev);
1851 u32 support = WAKE_PHY | WAKE_MAGIC |
1852 WAKE_UCAST | WAKE_MCAST | WAKE_BCAST; /* Untested */
1853
1854 if (!(rp->quirks & rqWOL))
1855 return -EINVAL;
1856
1857 if (wol->wolopts & ~support)
1858 return -EINVAL;
1859
1860 spin_lock_irq(&rp->lock);
1861 rp->wolopts = wol->wolopts;
1862 spin_unlock_irq(&rp->lock);
1863
1864 return 0;
1865}
1866
1867static struct ethtool_ops netdev_ethtool_ops = {
1868 .get_drvinfo = netdev_get_drvinfo,
1869 .get_settings = netdev_get_settings,
1870 .set_settings = netdev_set_settings,
1871 .nway_reset = netdev_nway_reset,
1872 .get_link = netdev_get_link,
1873 .get_msglevel = netdev_get_msglevel,
1874 .set_msglevel = netdev_set_msglevel,
1875 .get_wol = rhine_get_wol,
1876 .set_wol = rhine_set_wol,
1877 .get_sg = ethtool_op_get_sg,
1878 .get_tx_csum = ethtool_op_get_tx_csum,
John W. Linvilleb81e8e12005-09-12 10:48:58 -04001879 .get_perm_addr = ethtool_op_get_perm_addr,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001880};
1881
1882static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1883{
1884 struct rhine_private *rp = netdev_priv(dev);
1885 int rc;
1886
1887 if (!netif_running(dev))
1888 return -EINVAL;
1889
1890 spin_lock_irq(&rp->lock);
1891 rc = generic_mii_ioctl(&rp->mii_if, if_mii(rq), cmd, NULL);
1892 spin_unlock_irq(&rp->lock);
Roger Luethi00b428c2006-03-28 20:53:56 +02001893 rhine_set_carrier(&rp->mii_if);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001894
1895 return rc;
1896}
1897
1898static int rhine_close(struct net_device *dev)
1899{
1900 struct rhine_private *rp = netdev_priv(dev);
1901 void __iomem *ioaddr = rp->base;
1902
1903 spin_lock_irq(&rp->lock);
1904
1905 netif_stop_queue(dev);
1906
1907 if (debug > 1)
1908 printk(KERN_DEBUG "%s: Shutting down ethercard, "
1909 "status was %4.4x.\n",
1910 dev->name, ioread16(ioaddr + ChipCmd));
1911
1912 /* Switch to loopback mode to avoid hardware races. */
1913 iowrite8(rp->tx_thresh | 0x02, ioaddr + TxConfig);
1914
1915 /* Disable interrupts by clearing the interrupt mask. */
1916 iowrite16(0x0000, ioaddr + IntrEnable);
1917
1918 /* Stop the chip's Tx and Rx processes. */
1919 iowrite16(CmdStop, ioaddr + ChipCmd);
1920
1921 spin_unlock_irq(&rp->lock);
1922
1923 free_irq(rp->pdev->irq, dev);
John W. Linville6ba98d32005-10-18 21:31:02 -04001924
1925 flush_scheduled_work();
1926
Linus Torvalds1da177e2005-04-16 15:20:36 -07001927 free_rbufs(dev);
1928 free_tbufs(dev);
1929 free_ring(dev);
1930
1931 return 0;
1932}
1933
1934
1935static void __devexit rhine_remove_one(struct pci_dev *pdev)
1936{
1937 struct net_device *dev = pci_get_drvdata(pdev);
1938 struct rhine_private *rp = netdev_priv(dev);
1939
1940 unregister_netdev(dev);
1941
1942 pci_iounmap(pdev, rp->base);
1943 pci_release_regions(pdev);
1944
1945 free_netdev(dev);
1946 pci_disable_device(pdev);
1947 pci_set_drvdata(pdev, NULL);
1948}
1949
Greg Kroah-Hartmand18c3db2005-06-23 17:35:56 -07001950static void rhine_shutdown (struct pci_dev *pdev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001951{
Linus Torvalds1da177e2005-04-16 15:20:36 -07001952 struct net_device *dev = pci_get_drvdata(pdev);
1953 struct rhine_private *rp = netdev_priv(dev);
1954 void __iomem *ioaddr = rp->base;
1955
1956 if (!(rp->quirks & rqWOL))
1957 return; /* Nothing to do for non-WOL adapters */
1958
1959 rhine_power_init(dev);
1960
1961 /* Make sure we use pattern 0, 1 and not 4, 5 */
1962 if (rp->quirks & rq6patterns)
1963 iowrite8(0x04, ioaddr + 0xA7);
1964
1965 if (rp->wolopts & WAKE_MAGIC) {
1966 iowrite8(WOLmagic, ioaddr + WOLcrSet);
1967 /*
1968 * Turn EEPROM-controlled wake-up back on -- some hardware may
1969 * not cooperate otherwise.
1970 */
1971 iowrite8(ioread8(ioaddr + ConfigA) | 0x03, ioaddr + ConfigA);
1972 }
1973
1974 if (rp->wolopts & (WAKE_BCAST|WAKE_MCAST))
1975 iowrite8(WOLbmcast, ioaddr + WOLcgSet);
1976
1977 if (rp->wolopts & WAKE_PHY)
1978 iowrite8(WOLlnkon | WOLlnkoff, ioaddr + WOLcrSet);
1979
1980 if (rp->wolopts & WAKE_UCAST)
1981 iowrite8(WOLucast, ioaddr + WOLcrSet);
1982
1983 if (rp->wolopts) {
1984 /* Enable legacy WOL (for old motherboards) */
1985 iowrite8(0x01, ioaddr + PwcfgSet);
1986 iowrite8(ioread8(ioaddr + StickyHW) | 0x04, ioaddr + StickyHW);
1987 }
1988
1989 /* Hit power state D3 (sleep) */
1990 iowrite8(ioread8(ioaddr + StickyHW) | 0x03, ioaddr + StickyHW);
1991
1992 /* TODO: Check use of pci_enable_wake() */
1993
1994}
1995
1996#ifdef CONFIG_PM
1997static int rhine_suspend(struct pci_dev *pdev, pm_message_t state)
1998{
1999 struct net_device *dev = pci_get_drvdata(pdev);
2000 struct rhine_private *rp = netdev_priv(dev);
2001 unsigned long flags;
2002
2003 if (!netif_running(dev))
2004 return 0;
2005
2006 netif_device_detach(dev);
2007 pci_save_state(pdev);
2008
2009 spin_lock_irqsave(&rp->lock, flags);
Greg Kroah-Hartmand18c3db2005-06-23 17:35:56 -07002010 rhine_shutdown(pdev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002011 spin_unlock_irqrestore(&rp->lock, flags);
2012
2013 free_irq(dev->irq, dev);
2014 return 0;
2015}
2016
2017static int rhine_resume(struct pci_dev *pdev)
2018{
2019 struct net_device *dev = pci_get_drvdata(pdev);
2020 struct rhine_private *rp = netdev_priv(dev);
2021 unsigned long flags;
2022 int ret;
2023
2024 if (!netif_running(dev))
2025 return 0;
2026
2027 if (request_irq(dev->irq, rhine_interrupt, SA_SHIRQ, dev->name, dev))
2028 printk(KERN_ERR "via-rhine %s: request_irq failed\n", dev->name);
2029
2030 ret = pci_set_power_state(pdev, PCI_D0);
2031 if (debug > 1)
2032 printk(KERN_INFO "%s: Entering power state D0 %s (%d).\n",
2033 dev->name, ret ? "failed" : "succeeded", ret);
2034
2035 pci_restore_state(pdev);
2036
2037 spin_lock_irqsave(&rp->lock, flags);
2038#ifdef USE_MMIO
2039 enable_mmio(rp->pioaddr, rp->quirks);
2040#endif
2041 rhine_power_init(dev);
2042 free_tbufs(dev);
2043 free_rbufs(dev);
2044 alloc_tbufs(dev);
2045 alloc_rbufs(dev);
2046 init_registers(dev);
2047 spin_unlock_irqrestore(&rp->lock, flags);
2048
2049 netif_device_attach(dev);
2050
2051 return 0;
2052}
2053#endif /* CONFIG_PM */
2054
2055static struct pci_driver rhine_driver = {
2056 .name = DRV_NAME,
2057 .id_table = rhine_pci_tbl,
2058 .probe = rhine_init_one,
2059 .remove = __devexit_p(rhine_remove_one),
2060#ifdef CONFIG_PM
2061 .suspend = rhine_suspend,
2062 .resume = rhine_resume,
2063#endif /* CONFIG_PM */
Greg Kroah-Hartmand18c3db2005-06-23 17:35:56 -07002064 .shutdown = rhine_shutdown,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002065};
2066
2067
2068static int __init rhine_init(void)
2069{
2070/* when a module, this is printed whether or not devices are found in probe */
2071#ifdef MODULE
2072 printk(version);
2073#endif
2074 return pci_module_init(&rhine_driver);
2075}
2076
2077
2078static void __exit rhine_cleanup(void)
2079{
2080 pci_unregister_driver(&rhine_driver);
2081}
2082
2083
2084module_init(rhine_init);
2085module_exit(rhine_cleanup);