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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/****************************************************************************/
2
3/*
4 * m527xsim.h -- ColdFire 5270/5271 System Integration Module support.
5 *
6 * (C) Copyright 2004, Greg Ungerer (gerg@snapgear.com)
7 */
8
9/****************************************************************************/
10#ifndef m527xsim_h
11#define m527xsim_h
12/****************************************************************************/
13
Linus Torvalds1da177e2005-04-16 15:20:36 -070014
15/*
16 * Define the 5270/5271 SIM register set addresses.
17 */
18#define MCFICM_INTC0 0x0c00 /* Base for Interrupt Ctrl 0 */
19#define MCFICM_INTC1 0x0d00 /* Base for Interrupt Ctrl 1 */
20#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
21#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
22#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
23#define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */
24#define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */
25#define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */
26#define MCFINTC_IRLR 0x18 /* */
27#define MCFINTC_IACKL 0x19 /* */
28#define MCFINTC_ICR0 0x40 /* Base ICR register */
29
30#define MCFINT_VECBASE 64 /* Vector base number */
31#define MCFINT_UART0 13 /* Interrupt number for UART0 */
32#define MCFINT_UART1 14 /* Interrupt number for UART1 */
33#define MCFINT_UART2 15 /* Interrupt number for UART2 */
34#define MCFINT_PIT1 36 /* Interrupt number for PIT1 */
35
36/*
37 * SDRAM configuration registers.
38 */
Greg Ungererd8716292005-09-12 11:18:10 +100039#ifdef CONFIG_M5271
Linus Torvalds1da177e2005-04-16 15:20:36 -070040#define MCFSIM_DCR 0x40 /* SDRAM control */
41#define MCFSIM_DACR0 0x48 /* SDRAM base address 0 */
42#define MCFSIM_DMR0 0x4c /* SDRAM address mask 0 */
43#define MCFSIM_DACR1 0x50 /* SDRAM base address 1 */
44#define MCFSIM_DMR1 0x54 /* SDRAM address mask 1 */
Greg Ungererd8716292005-09-12 11:18:10 +100045#endif
46#ifdef CONFIG_M5275
Linus Torvalds1da177e2005-04-16 15:20:36 -070047#define MCFSIM_DMR 0x40 /* SDRAM mode */
48#define MCFSIM_DCR 0x44 /* SDRAM control */
49#define MCFSIM_DCFG1 0x48 /* SDRAM configuration 1 */
50#define MCFSIM_DCFG2 0x4c /* SDRAM configuration 2 */
51#define MCFSIM_DBAR0 0x50 /* SDRAM base address 0 */
52#define MCFSIM_DMR0 0x54 /* SDRAM address mask 0 */
53#define MCFSIM_DBAR1 0x58 /* SDRAM base address 1 */
54#define MCFSIM_DMR1 0x5c /* SDRAM address mask 1 */
55#endif
56
Greg Ungererd8716292005-09-12 11:18:10 +100057/*
58 * GPIO pins setups to enable the UARTs.
59 */
60#ifdef CONFIG_M5271
61#define MCF_GPIO_PAR_UART 0x100048 /* PAR UART address */
62#define UART0_ENABLE_MASK 0x000f
63#define UART1_ENABLE_MASK 0x0ff0
64#define UART2_ENABLE_MASK 0x3000
65#endif
66#ifdef CONFIG_M5275
67#define MCF_GPIO_PAR_UART 0x10007c /* PAR UART address */
68#define UART0_ENABLE_MASK 0x000f
69#define UART1_ENABLE_MASK 0x00f0
70#define UART2_ENABLE_MASK 0x3f00
71#endif
72
Greg Ungerer4c0b0082009-04-30 23:06:45 +100073/*
74 * Reset Controll Unit (relative to IPSBAR).
75 */
76#define MCF_RCR 0x110000
77#define MCF_RSR 0x110001
78
79#define MCF_RCR_SWRESET 0x80 /* Software reset bit */
80#define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */
81
Linus Torvalds1da177e2005-04-16 15:20:36 -070082/****************************************************************************/
83#endif /* m527xsim_h */