Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * include/asm-ppc/immap_85xx.h |
| 3 | * |
| 4 | * MPC85xx Internal Memory Map |
| 5 | * |
Kumar Gala | 4c8d3d9 | 2005-11-13 16:06:30 -0800 | [diff] [blame^] | 6 | * Maintainer: Kumar Gala <galak@kernel.crashing.org> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7 | * |
| 8 | * Copyright 2004 Freescale Semiconductor, Inc |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify it |
| 11 | * under the terms of the GNU General Public License as published by the |
| 12 | * Free Software Foundation; either version 2 of the License, or (at your |
| 13 | * option) any later version. |
| 14 | * |
| 15 | */ |
| 16 | |
| 17 | #ifdef __KERNEL__ |
| 18 | #ifndef __ASM_IMMAP_85XX_H__ |
| 19 | #define __ASM_IMMAP_85XX_H__ |
| 20 | |
| 21 | /* Eventually this should define all the IO block registers in 85xx */ |
| 22 | |
| 23 | /* PCI Registers */ |
| 24 | typedef struct ccsr_pci { |
| 25 | uint cfg_addr; /* 0x.000 - PCI Configuration Address Register */ |
| 26 | uint cfg_data; /* 0x.004 - PCI Configuration Data Register */ |
| 27 | uint int_ack; /* 0x.008 - PCI Interrupt Acknowledge Register */ |
| 28 | char res1[3060]; |
| 29 | uint potar0; /* 0x.c00 - PCI Outbound Transaction Address Register 0 */ |
| 30 | uint potear0; /* 0x.c04 - PCI Outbound Translation Extended Address Register 0 */ |
| 31 | uint powbar0; /* 0x.c08 - PCI Outbound Window Base Address Register 0 */ |
| 32 | char res2[4]; |
| 33 | uint powar0; /* 0x.c10 - PCI Outbound Window Attributes Register 0 */ |
| 34 | char res3[12]; |
| 35 | uint potar1; /* 0x.c20 - PCI Outbound Transaction Address Register 1 */ |
| 36 | uint potear1; /* 0x.c24 - PCI Outbound Translation Extended Address Register 1 */ |
| 37 | uint powbar1; /* 0x.c28 - PCI Outbound Window Base Address Register 1 */ |
| 38 | char res4[4]; |
| 39 | uint powar1; /* 0x.c30 - PCI Outbound Window Attributes Register 1 */ |
| 40 | char res5[12]; |
| 41 | uint potar2; /* 0x.c40 - PCI Outbound Transaction Address Register 2 */ |
| 42 | uint potear2; /* 0x.c44 - PCI Outbound Translation Extended Address Register 2 */ |
| 43 | uint powbar2; /* 0x.c48 - PCI Outbound Window Base Address Register 2 */ |
| 44 | char res6[4]; |
| 45 | uint powar2; /* 0x.c50 - PCI Outbound Window Attributes Register 2 */ |
| 46 | char res7[12]; |
| 47 | uint potar3; /* 0x.c60 - PCI Outbound Transaction Address Register 3 */ |
| 48 | uint potear3; /* 0x.c64 - PCI Outbound Translation Extended Address Register 3 */ |
| 49 | uint powbar3; /* 0x.c68 - PCI Outbound Window Base Address Register 3 */ |
| 50 | char res8[4]; |
| 51 | uint powar3; /* 0x.c70 - PCI Outbound Window Attributes Register 3 */ |
| 52 | char res9[12]; |
| 53 | uint potar4; /* 0x.c80 - PCI Outbound Transaction Address Register 4 */ |
| 54 | uint potear4; /* 0x.c84 - PCI Outbound Translation Extended Address Register 4 */ |
| 55 | uint powbar4; /* 0x.c88 - PCI Outbound Window Base Address Register 4 */ |
| 56 | char res10[4]; |
| 57 | uint powar4; /* 0x.c90 - PCI Outbound Window Attributes Register 4 */ |
| 58 | char res11[268]; |
| 59 | uint pitar3; /* 0x.da0 - PCI Inbound Translation Address Register 3 */ |
| 60 | char res12[4]; |
| 61 | uint piwbar3; /* 0x.da8 - PCI Inbound Window Base Address Register 3 */ |
| 62 | uint piwbear3; /* 0x.dac - PCI Inbound Window Base Extended Address Register 3 */ |
| 63 | uint piwar3; /* 0x.db0 - PCI Inbound Window Attributes Register 3 */ |
| 64 | char res13[12]; |
| 65 | uint pitar2; /* 0x.dc0 - PCI Inbound Translation Address Register 2 */ |
| 66 | char res14[4]; |
| 67 | uint piwbar2; /* 0x.dc8 - PCI Inbound Window Base Address Register 2 */ |
| 68 | uint piwbear2; /* 0x.dcc - PCI Inbound Window Base Extended Address Register 2 */ |
| 69 | uint piwar2; /* 0x.dd0 - PCI Inbound Window Attributes Register 2 */ |
| 70 | char res15[12]; |
| 71 | uint pitar1; /* 0x.de0 - PCI Inbound Translation Address Register 1 */ |
| 72 | char res16[4]; |
| 73 | uint piwbar1; /* 0x.de8 - PCI Inbound Window Base Address Register 1 */ |
| 74 | char res17[4]; |
| 75 | uint piwar1; /* 0x.df0 - PCI Inbound Window Attributes Register 1 */ |
| 76 | char res18[12]; |
| 77 | uint err_dr; /* 0x.e00 - PCI Error Detect Register */ |
| 78 | uint err_cap_dr; /* 0x.e04 - PCI Error Capture Disable Register */ |
| 79 | uint err_en; /* 0x.e08 - PCI Error Enable Register */ |
| 80 | uint err_attrib; /* 0x.e0c - PCI Error Attributes Capture Register */ |
| 81 | uint err_addr; /* 0x.e10 - PCI Error Address Capture Register */ |
| 82 | uint err_ext_addr; /* 0x.e14 - PCI Error Extended Address Capture Register */ |
| 83 | uint err_dl; /* 0x.e18 - PCI Error Data Low Capture Register */ |
| 84 | uint err_dh; /* 0x.e1c - PCI Error Data High Capture Register */ |
| 85 | uint gas_timr; /* 0x.e20 - PCI Gasket Timer Register */ |
| 86 | uint pci_timr; /* 0x.e24 - PCI Timer Register */ |
| 87 | char res19[472]; |
| 88 | } ccsr_pci_t; |
| 89 | |
| 90 | /* Global Utility Registers */ |
| 91 | typedef struct ccsr_guts { |
| 92 | uint porpllsr; /* 0x.0000 - POR PLL Ratio Status Register */ |
| 93 | uint porbmsr; /* 0x.0004 - POR Boot Mode Status Register */ |
| 94 | uint porimpscr; /* 0x.0008 - POR I/O Impedance Status and Control Register */ |
| 95 | uint pordevsr; /* 0x.000c - POR I/O Device Status Register */ |
| 96 | uint pordbgmsr; /* 0x.0010 - POR Debug Mode Status Register */ |
| 97 | char res1[12]; |
| 98 | uint gpporcr; /* 0x.0020 - General-Purpose POR Configuration Register */ |
| 99 | char res2[12]; |
| 100 | uint gpiocr; /* 0x.0030 - GPIO Control Register */ |
| 101 | char res3[12]; |
| 102 | uint gpoutdr; /* 0x.0040 - General-Purpose Output Data Register */ |
| 103 | char res4[12]; |
| 104 | uint gpindr; /* 0x.0050 - General-Purpose Input Data Register */ |
| 105 | char res5[12]; |
| 106 | uint pmuxcr; /* 0x.0060 - Alternate Function Signal Multiplex Control */ |
| 107 | char res6[12]; |
| 108 | uint devdisr; /* 0x.0070 - Device Disable Control */ |
| 109 | char res7[12]; |
| 110 | uint powmgtcsr; /* 0x.0080 - Power Management Status and Control Register */ |
| 111 | char res8[12]; |
| 112 | uint mcpsumr; /* 0x.0090 - Machine Check Summary Register */ |
| 113 | char res9[12]; |
| 114 | uint pvr; /* 0x.00a0 - Processor Version Register */ |
| 115 | uint svr; /* 0x.00a4 - System Version Register */ |
| 116 | char res10[3416]; |
| 117 | uint clkocr; /* 0x.0e00 - Clock Out Select Register */ |
| 118 | char res11[12]; |
| 119 | uint ddrdllcr; /* 0x.0e10 - DDR DLL Control Register */ |
| 120 | char res12[12]; |
| 121 | uint lbcdllcr; /* 0x.0e20 - LBC DLL Control Register */ |
| 122 | char res13[61916]; |
| 123 | } ccsr_guts_t; |
| 124 | |
| 125 | #endif /* __ASM_IMMAP_85XX_H__ */ |
| 126 | #endif /* __KERNEL__ */ |