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Will Newtonf95f3852011-01-02 01:11:59 -05001/*
2 * Synopsys DesignWare Multimedia Card Interface driver
3 * (Based on NXP driver for lpc 31xx)
4 *
5 * Copyright (C) 2009 NXP Semiconductors
6 * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
Robert P. J. Day100e9182011-05-27 16:04:03 -040014#ifndef LINUX_MMC_DW_MMC_H
15#define LINUX_MMC_DW_MMC_H
Will Newtonf95f3852011-01-02 01:11:59 -050016
17#define MAX_MCI_SLOTS 2
18
19enum dw_mci_state {
20 STATE_IDLE = 0,
21 STATE_SENDING_CMD,
22 STATE_SENDING_DATA,
23 STATE_DATA_BUSY,
24 STATE_SENDING_STOP,
25 STATE_DATA_ERROR,
26};
27
28enum {
29 EVENT_CMD_COMPLETE = 0,
30 EVENT_XFER_COMPLETE,
31 EVENT_DATA_COMPLETE,
32 EVENT_DATA_ERROR,
33 EVENT_XFER_ERROR
34};
35
36struct mmc_data;
37
38/**
39 * struct dw_mci - MMC controller state shared between all slots
40 * @lock: Spinlock protecting the queue and associated data.
41 * @regs: Pointer to MMIO registers.
42 * @sg: Scatterlist entry currently being processed by PIO code, if any.
43 * @pio_offset: Offset into the current scatterlist entry.
44 * @cur_slot: The slot which is currently using the controller.
45 * @mrq: The request currently being processed on @cur_slot,
46 * or NULL if the controller is idle.
47 * @cmd: The command currently being sent to the card, or NULL.
48 * @data: The data currently being transferred, or NULL if no data
49 * transfer is in progress.
50 * @use_dma: Whether DMA channel is initialized or not.
James Hogan03e8cb52011-06-29 09:28:43 +010051 * @using_dma: Whether DMA is in use for the current transfer.
Will Newtonf95f3852011-01-02 01:11:59 -050052 * @sg_dma: Bus address of DMA buffer.
53 * @sg_cpu: Virtual address of DMA buffer.
54 * @dma_ops: Pointer to platform-specific DMA callbacks.
55 * @cmd_status: Snapshot of SR taken upon completion of the current
56 * command. Only valid when EVENT_CMD_COMPLETE is pending.
57 * @data_status: Snapshot of SR taken upon completion of the current
58 * data transfer. Only valid when EVENT_DATA_COMPLETE or
59 * EVENT_DATA_ERROR is pending.
60 * @stop_cmdr: Value to be loaded into CMDR when the stop command is
61 * to be sent.
62 * @dir_status: Direction of current transfer.
63 * @tasklet: Tasklet running the request state machine.
64 * @card_tasklet: Tasklet handling card detect.
65 * @pending_events: Bitmask of events flagged by the interrupt handler
66 * to be processed by the tasklet.
67 * @completed_events: Bitmask of events which the state machine has
68 * processed.
69 * @state: Tasklet state.
70 * @queue: List of slots waiting for access to the controller.
71 * @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus
72 * rate and timeout calculations.
73 * @current_speed: Configured rate of the controller.
74 * @num_slots: Number of slots available.
Jaehoon Chung4e0a5ad2011-10-17 19:36:23 +090075 * @verid: Denote Version ID.
76 * @data_offset: Set the offset of DATA register according to VERID.
Will Newtonf95f3852011-01-02 01:11:59 -050077 * @pdev: Platform device associated with the MMC controller.
78 * @pdata: Platform data associated with the MMC controller.
79 * @slot: Slots sharing this MMC controller.
James Hoganb86d8252011-06-24 13:57:18 +010080 * @fifo_depth: depth of FIFO.
Will Newtonf95f3852011-01-02 01:11:59 -050081 * @data_shift: log2 of FIFO item size.
James Hogan34b664a2011-06-24 13:57:56 +010082 * @part_buf_start: Start index in part_buf.
83 * @part_buf_count: Bytes of partial data in part_buf.
84 * @part_buf: Simple buffer for partial fifo reads/writes.
Will Newtonf95f3852011-01-02 01:11:59 -050085 * @push_data: Pointer to FIFO push function.
86 * @pull_data: Pointer to FIFO pull function.
87 * @quirks: Set of quirks that apply to specific versions of the IP.
88 *
89 * Locking
90 * =======
91 *
92 * @lock is a softirq-safe spinlock protecting @queue as well as
93 * @cur_slot, @mrq and @state. These must always be updated
94 * at the same time while holding @lock.
95 *
96 * The @mrq field of struct dw_mci_slot is also protected by @lock,
97 * and must always be written at the same time as the slot is added to
98 * @queue.
99 *
100 * @pending_events and @completed_events are accessed using atomic bit
101 * operations, so they don't need any locking.
102 *
103 * None of the fields touched by the interrupt handler need any
104 * locking. However, ordering is important: Before EVENT_DATA_ERROR or
105 * EVENT_DATA_COMPLETE is set in @pending_events, all data-related
106 * interrupts must be disabled and @data_status updated with a
107 * snapshot of SR. Similarly, before EVENT_CMD_COMPLETE is set, the
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300108 * CMDRDY interrupt must be disabled and @cmd_status updated with a
Will Newtonf95f3852011-01-02 01:11:59 -0500109 * snapshot of SR, and before EVENT_XFER_COMPLETE can be set, the
110 * bytes_xfered field of @data must be written. This is ensured by
111 * using barriers.
112 */
113struct dw_mci {
114 spinlock_t lock;
115 void __iomem *regs;
116
117 struct scatterlist *sg;
118 unsigned int pio_offset;
119
120 struct dw_mci_slot *cur_slot;
121 struct mmc_request *mrq;
122 struct mmc_command *cmd;
123 struct mmc_data *data;
124
125 /* DMA interface members*/
126 int use_dma;
James Hogan03e8cb52011-06-29 09:28:43 +0100127 int using_dma;
Will Newtonf95f3852011-01-02 01:11:59 -0500128
129 dma_addr_t sg_dma;
130 void *sg_cpu;
131 struct dw_mci_dma_ops *dma_ops;
132#ifdef CONFIG_MMC_DW_IDMAC
133 unsigned int ring_size;
134#else
135 struct dw_mci_dma_data *dma_data;
136#endif
137 u32 cmd_status;
138 u32 data_status;
139 u32 stop_cmdr;
140 u32 dir_status;
141 struct tasklet_struct tasklet;
James Hogan1791b13e2011-06-24 13:55:55 +0100142 struct work_struct card_work;
Will Newtonf95f3852011-01-02 01:11:59 -0500143 unsigned long pending_events;
144 unsigned long completed_events;
145 enum dw_mci_state state;
146 struct list_head queue;
147
148 u32 bus_hz;
149 u32 current_speed;
150 u32 num_slots;
Jaehoon Chunge61cf112011-03-17 20:32:33 +0900151 u32 fifoth_val;
Jaehoon Chung4e0a5ad2011-10-17 19:36:23 +0900152 u16 verid;
153 u16 data_offset;
Will Newtonf95f3852011-01-02 01:11:59 -0500154 struct platform_device *pdev;
155 struct dw_mci_board *pdata;
156 struct dw_mci_slot *slot[MAX_MCI_SLOTS];
157
158 /* FIFO push and pull */
James Hoganb86d8252011-06-24 13:57:18 +0100159 int fifo_depth;
Will Newtonf95f3852011-01-02 01:11:59 -0500160 int data_shift;
James Hogan34b664a2011-06-24 13:57:56 +0100161 u8 part_buf_start;
162 u8 part_buf_count;
163 union {
164 u16 part_buf16;
165 u32 part_buf32;
166 u64 part_buf;
167 };
Will Newtonf95f3852011-01-02 01:11:59 -0500168 void (*push_data)(struct dw_mci *host, void *buf, int cnt);
169 void (*pull_data)(struct dw_mci *host, void *buf, int cnt);
170
171 /* Workaround flags */
172 u32 quirks;
Jaehoon Chungc07946a2011-02-25 11:08:14 +0900173
174 struct regulator *vmmc; /* Power regulator */
Will Newtonf95f3852011-01-02 01:11:59 -0500175};
176
177/* DMA ops for Internal/External DMAC interface */
178struct dw_mci_dma_ops {
179 /* DMA Ops */
180 int (*init)(struct dw_mci *host);
181 void (*start)(struct dw_mci *host, unsigned int sg_len);
182 void (*complete)(struct dw_mci *host);
183 void (*stop)(struct dw_mci *host);
184 void (*cleanup)(struct dw_mci *host);
185 void (*exit)(struct dw_mci *host);
186};
187
188/* IP Quirks/flags. */
Will Newtonf95f3852011-01-02 01:11:59 -0500189/* DTO fix for command transmission with IDMAC configured */
Jaehoon Chungfc3d7722011-02-25 11:08:15 +0900190#define DW_MCI_QUIRK_IDMAC_DTO BIT(0)
Will Newtonf95f3852011-01-02 01:11:59 -0500191/* delay needed between retries on some 2.11a implementations */
Jaehoon Chungfc3d7722011-02-25 11:08:15 +0900192#define DW_MCI_QUIRK_RETRY_DELAY BIT(1)
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300193/* High Speed Capable - Supports HS cards (up to 50MHz) */
Jaehoon Chungfc3d7722011-02-25 11:08:15 +0900194#define DW_MCI_QUIRK_HIGHSPEED BIT(2)
195/* Unreliable card detection */
196#define DW_MCI_QUIRK_BROKEN_CARD_DETECTION BIT(3)
Will Newtonf95f3852011-01-02 01:11:59 -0500197
198
199struct dma_pdata;
200
201struct block_settings {
202 unsigned short max_segs; /* see blk_queue_max_segments */
203 unsigned int max_blk_size; /* maximum size of one mmc block */
204 unsigned int max_blk_count; /* maximum number of blocks in one req*/
205 unsigned int max_req_size; /* maximum number of bytes in one req*/
206 unsigned int max_seg_size; /* see blk_queue_max_segment_size */
207};
208
209/* Board platform data */
210struct dw_mci_board {
211 u32 num_slots;
212
213 u32 quirks; /* Workaround / Quirk flags */
214 unsigned int bus_hz; /* Bus speed */
215
Jaehoon Chungfc3d7722011-02-25 11:08:15 +0900216 unsigned int caps; /* Capabilities */
James Hoganb86d8252011-06-24 13:57:18 +0100217 /*
218 * Override fifo depth. If 0, autodetect it from the FIFOTH register,
219 * but note that this may not be reliable after a bootloader has used
220 * it.
221 */
222 unsigned int fifo_depth;
Jaehoon Chungfc3d7722011-02-25 11:08:15 +0900223
Will Newtonf95f3852011-01-02 01:11:59 -0500224 /* delay in mS before detecting cards after interrupt */
225 u32 detect_delay_ms;
226
227 int (*init)(u32 slot_id, irq_handler_t , void *);
228 int (*get_ro)(u32 slot_id);
229 int (*get_cd)(u32 slot_id);
230 int (*get_ocr)(u32 slot_id);
231 int (*get_bus_wd)(u32 slot_id);
232 /*
233 * Enable power to selected slot and set voltage to desired level.
234 * Voltage levels are specified using MMC_VDD_xxx defines defined
235 * in linux/mmc/host.h file.
236 */
237 void (*setpower)(u32 slot_id, u32 volt);
238 void (*exit)(u32 slot_id);
239 void (*select_slot)(u32 slot_id);
240
241 struct dw_mci_dma_ops *dma_ops;
242 struct dma_pdata *data;
243 struct block_settings *blk_settings;
244};
245
Robert P. J. Day100e9182011-05-27 16:04:03 -0400246#endif /* LINUX_MMC_DW_MMC_H */