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Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001/* bnx2x.h: Broadcom Everest network driver.
2 *
Eliezer Tamir49d66772008-02-28 11:53:13 -08003 * Copyright (c) 2007-2008 Broadcom Corporation
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
Eilon Greenstein24e3fce2008-06-12 14:30:28 -07009 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020011 * Based on code from Michael Chan's bnx2 driver
12 */
13
14#ifndef BNX2X_H
15#define BNX2X_H
16
Eilon Greenstein34f80b02008-06-23 20:33:01 -070017/* compilation time flags */
18
19/* define this to make the driver freeze on error to allow getting debug info
20 * (you will need to reboot afterwards) */
21/* #define BNX2X_STOP_ON_ERROR */
22
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020023/* error/debug prints */
24
Eilon Greenstein34f80b02008-06-23 20:33:01 -070025#define DRV_MODULE_NAME "bnx2x"
26#define PFX DRV_MODULE_NAME ": "
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020027
28/* for messages that are currently off */
Eilon Greenstein34f80b02008-06-23 20:33:01 -070029#define BNX2X_MSG_OFF 0
30#define BNX2X_MSG_MCP 0x010000 /* was: NETIF_MSG_HW */
31#define BNX2X_MSG_STATS 0x020000 /* was: NETIF_MSG_TIMER */
32#define BNX2X_MSG_NVM 0x040000 /* was: NETIF_MSG_HW */
33#define BNX2X_MSG_DMAE 0x080000 /* was: NETIF_MSG_HW */
Eliezer Tamirf1410642008-02-28 11:51:50 -080034#define BNX2X_MSG_SP 0x100000 /* was: NETIF_MSG_INTR */
35#define BNX2X_MSG_FP 0x200000 /* was: NETIF_MSG_INTR */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020036
Eilon Greenstein34f80b02008-06-23 20:33:01 -070037#define DP_LEVEL KERN_NOTICE /* was: KERN_DEBUG */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020038
39/* regular debug print */
40#define DP(__mask, __fmt, __args...) do { \
41 if (bp->msglevel & (__mask)) \
Eilon Greenstein34f80b02008-06-23 20:33:01 -070042 printk(DP_LEVEL "[%s:%d(%s)]" __fmt, __func__, __LINE__, \
Eilon Greenstein6378c022008-08-13 15:59:25 -070043 bp->dev ? (bp->dev->name) : "?", ##__args); \
Eilon Greenstein34f80b02008-06-23 20:33:01 -070044 } while (0)
45
46/* errors debug print */
47#define BNX2X_DBG_ERR(__fmt, __args...) do { \
48 if (bp->msglevel & NETIF_MSG_PROBE) \
49 printk(KERN_ERR "[%s:%d(%s)]" __fmt, __func__, __LINE__, \
Eilon Greenstein6378c022008-08-13 15:59:25 -070050 bp->dev ? (bp->dev->name) : "?", ##__args); \
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020051 } while (0)
52
53/* for errors (never masked) */
54#define BNX2X_ERR(__fmt, __args...) do { \
Eilon Greenstein34f80b02008-06-23 20:33:01 -070055 printk(KERN_ERR "[%s:%d(%s)]" __fmt, __func__, __LINE__, \
Eilon Greenstein6378c022008-08-13 15:59:25 -070056 bp->dev ? (bp->dev->name) : "?", ##__args); \
Eliezer Tamirf1410642008-02-28 11:51:50 -080057 } while (0)
58
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020059/* before we have a dev->name use dev_info() */
60#define BNX2X_DEV_INFO(__fmt, __args...) do { \
61 if (bp->msglevel & NETIF_MSG_PROBE) \
62 dev_info(&bp->pdev->dev, __fmt, ##__args); \
63 } while (0)
64
65
66#ifdef BNX2X_STOP_ON_ERROR
67#define bnx2x_panic() do { \
68 bp->panic = 1; \
69 BNX2X_ERR("driver assert\n"); \
Eilon Greenstein34f80b02008-06-23 20:33:01 -070070 bnx2x_int_disable(bp); \
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020071 bnx2x_panic_dump(bp); \
72 } while (0)
73#else
74#define bnx2x_panic() do { \
75 BNX2X_ERR("driver assert\n"); \
76 bnx2x_panic_dump(bp); \
77 } while (0)
78#endif
79
80
Eilon Greenstein34f80b02008-06-23 20:33:01 -070081#ifdef NETIF_F_HW_VLAN_TX
82#define BCM_VLAN 1
83#endif
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020084
85
Eilon Greenstein34f80b02008-06-23 20:33:01 -070086#define U64_LO(x) (u32)(((u64)(x)) & 0xffffffff)
87#define U64_HI(x) (u32)(((u64)(x)) >> 32)
88#define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo))
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020089
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020090
Eilon Greenstein34f80b02008-06-23 20:33:01 -070091#define REG_ADDR(bp, offset) (bp->regview + offset)
92
93#define REG_RD(bp, offset) readl(REG_ADDR(bp, offset))
94#define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset))
95#define REG_RD64(bp, offset) readq(REG_ADDR(bp, offset))
96
97#define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset))
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020098#define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset))
Eilon Greenstein34f80b02008-06-23 20:33:01 -070099#define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset))
100#define REG_WR32(bp, offset, val) REG_WR(bp, offset, val)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200101
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700102#define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset)
103#define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200104
Yaniv Rosnerc18487e2008-06-23 20:27:52 -0700105#define REG_RD_DMAE(bp, offset, valp, len32) \
106 do { \
107 bnx2x_read_dmae(bp, offset, len32);\
108 memcpy(valp, bnx2x_sp(bp, wb_data[0]), len32 * 4); \
109 } while (0)
110
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700111#define REG_WR_DMAE(bp, offset, valp, len32) \
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200112 do { \
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700113 memcpy(bnx2x_sp(bp, wb_data[0]), valp, len32 * 4); \
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200114 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \
115 offset, len32); \
116 } while (0)
117
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700118#define SHMEM_ADDR(bp, field) (bp->common.shmem_base + \
119 offsetof(struct shmem_region, field))
120#define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field))
121#define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200122
Eilon Greenstein345b5d52008-08-13 15:58:12 -0700123#define EMAC_RD(bp, reg) REG_RD(bp, emac_base + reg)
Eilon Greenstein3196a882008-08-13 15:58:49 -0700124#define EMAC_WR(bp, reg, val) REG_WR(bp, emac_base + reg, val)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200125
126
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -0700127/* fast path */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200128
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200129struct sw_rx_bd {
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700130 struct sk_buff *skb;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200131 DECLARE_PCI_UNMAP_ADDR(mapping)
132};
133
134struct sw_tx_bd {
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700135 struct sk_buff *skb;
136 u16 first_bd;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200137};
138
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -0700139struct sw_rx_page {
140 struct page *page;
141 DECLARE_PCI_UNMAP_ADDR(mapping)
142};
143
144
145/* MC hsi */
146#define BCM_PAGE_SHIFT 12
147#define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT)
148#define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1))
149#define BCM_PAGE_ALIGN(addr) (((addr) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK)
150
151#define PAGES_PER_SGE_SHIFT 0
152#define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT)
Eilon Greenstein4f40f2c2009-01-14 21:24:17 -0800153#define SGE_PAGE_SIZE PAGE_SIZE
154#define SGE_PAGE_SHIFT PAGE_SHIFT
155#define SGE_PAGE_ALIGN(addr) PAGE_ALIGN(addr)
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -0700156
Eilon Greenstein437cf2f2008-09-03 14:38:00 -0700157#define BCM_RX_ETH_PAYLOAD_ALIGN 64
158
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -0700159/* SGE ring related macros */
160#define NUM_RX_SGE_PAGES 2
161#define RX_SGE_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge))
162#define MAX_RX_SGE_CNT (RX_SGE_CNT - 2)
Eilon Greenstein33471622008-08-13 15:59:08 -0700163/* RX_SGE_CNT is promised to be a power of 2 */
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -0700164#define RX_SGE_MASK (RX_SGE_CNT - 1)
165#define NUM_RX_SGE (RX_SGE_CNT * NUM_RX_SGE_PAGES)
166#define MAX_RX_SGE (NUM_RX_SGE - 1)
167#define NEXT_SGE_IDX(x) ((((x) & RX_SGE_MASK) == \
168 (MAX_RX_SGE_CNT - 1)) ? (x) + 3 : (x) + 1)
169#define RX_SGE(x) ((x) & MAX_RX_SGE)
170
171/* SGE producer mask related macros */
172/* Number of bits in one sge_mask array element */
173#define RX_SGE_MASK_ELEM_SZ 64
174#define RX_SGE_MASK_ELEM_SHIFT 6
175#define RX_SGE_MASK_ELEM_MASK ((u64)RX_SGE_MASK_ELEM_SZ - 1)
176
177/* Creates a bitmask of all ones in less significant bits.
178 idx - index of the most significant bit in the created mask */
179#define RX_SGE_ONES_MASK(idx) \
180 (((u64)0x1 << (((idx) & RX_SGE_MASK_ELEM_MASK) + 1)) - 1)
181#define RX_SGE_MASK_ELEM_ONE_MASK ((u64)(~0))
182
183/* Number of u64 elements in SGE mask array */
184#define RX_SGE_MASK_LEN ((NUM_RX_SGE_PAGES * RX_SGE_CNT) / \
185 RX_SGE_MASK_ELEM_SZ)
186#define RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1)
187#define NEXT_SGE_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK)
188
189
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200190struct bnx2x_fastpath {
191
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700192 struct napi_struct napi;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200193
194 struct host_status_block *status_blk;
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700195 dma_addr_t status_blk_mapping;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200196
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700197 struct eth_tx_db_data *hw_tx_prods;
198 dma_addr_t tx_prods_mapping;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200199
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700200 struct sw_tx_bd *tx_buf_ring;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200201
202 struct eth_tx_bd *tx_desc_ring;
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700203 dma_addr_t tx_desc_mapping;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200204
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -0700205 struct sw_rx_bd *rx_buf_ring; /* BDs mappings ring */
206 struct sw_rx_page *rx_page_ring; /* SGE pages mappings ring */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200207
208 struct eth_rx_bd *rx_desc_ring;
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700209 dma_addr_t rx_desc_mapping;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200210
211 union eth_rx_cqe *rx_comp_ring;
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700212 dma_addr_t rx_comp_mapping;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200213
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -0700214 /* SGE ring */
215 struct eth_rx_sge *rx_sge_ring;
216 dma_addr_t rx_sge_mapping;
217
218 u64 sge_mask[RX_SGE_MASK_LEN];
219
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700220 int state;
221#define BNX2X_FP_STATE_CLOSED 0
222#define BNX2X_FP_STATE_IRQ 0x80000
223#define BNX2X_FP_STATE_OPENING 0x90000
224#define BNX2X_FP_STATE_OPEN 0xa0000
225#define BNX2X_FP_STATE_HALTING 0xb0000
226#define BNX2X_FP_STATE_HALTED 0xc0000
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200227
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700228 u8 index; /* number in fp array */
229 u8 cl_id; /* eth client id */
230 u8 sb_id; /* status block number in HW */
231#define FP_IDX(fp) (fp->index)
232#define FP_CL_ID(fp) (fp->cl_id)
233#define BP_CL_ID(bp) (bp->fp[0].cl_id)
234#define FP_SB_ID(fp) (fp->sb_id)
235#define CNIC_SB_ID 0
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200236
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700237 u16 tx_pkt_prod;
238 u16 tx_pkt_cons;
239 u16 tx_bd_prod;
240 u16 tx_bd_cons;
241 u16 *tx_cons_sb;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200242
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700243 u16 fp_c_idx;
244 u16 fp_u_idx;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200245
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700246 u16 rx_bd_prod;
247 u16 rx_bd_cons;
248 u16 rx_comp_prod;
249 u16 rx_comp_cons;
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -0700250 u16 rx_sge_prod;
251 /* The last maximal completed SGE */
252 u16 last_max_sge;
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700253 u16 *rx_cons_sb;
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -0700254 u16 *rx_bd_cons_sb;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200255
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700256 unsigned long tx_pkt,
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200257 rx_pkt,
Yitchak Gertner66e855f2008-08-13 15:49:05 -0700258 rx_calls;
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -0700259 /* TPA related */
260 struct sw_rx_bd tpa_pool[ETH_MAX_AGGREGATION_QUEUES_E1H];
261 u8 tpa_state[ETH_MAX_AGGREGATION_QUEUES_E1H];
262#define BNX2X_TPA_START 1
263#define BNX2X_TPA_STOP 2
264 u8 disable_tpa;
265#ifdef BNX2X_STOP_ON_ERROR
266 u64 tpa_queue_used;
267#endif
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200268
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700269 struct bnx2x *bp; /* parent */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200270};
271
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700272#define bnx2x_fp(bp, nr, var) (bp->fp[nr].var)
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -0700273
Vladislav Zolotarovda5a6622008-08-13 15:50:00 -0700274#define BNX2X_HAS_TX_WORK(fp) \
275 ((fp->tx_pkt_prod != le16_to_cpu(*fp->tx_cons_sb)) || \
276 (fp->tx_pkt_prod != fp->tx_pkt_cons))
277
278#define BNX2X_HAS_RX_WORK(fp) \
Eilon Greenstein2772f902008-08-25 15:19:17 -0700279 (fp->rx_comp_cons != rx_cons_sb)
Vladislav Zolotarovda5a6622008-08-13 15:50:00 -0700280
281#define BNX2X_HAS_WORK(fp) (BNX2X_HAS_RX_WORK(fp) || BNX2X_HAS_TX_WORK(fp))
282
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -0700283
284/* MC hsi */
285#define MAX_FETCH_BD 13 /* HW max BDs per packet */
286#define RX_COPY_THRESH 92
287
288#define NUM_TX_RINGS 16
289#define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_tx_bd))
290#define MAX_TX_DESC_CNT (TX_DESC_CNT - 1)
291#define NUM_TX_BD (TX_DESC_CNT * NUM_TX_RINGS)
292#define MAX_TX_BD (NUM_TX_BD - 1)
293#define MAX_TX_AVAIL (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2)
294#define NEXT_TX_IDX(x) ((((x) & MAX_TX_DESC_CNT) == \
295 (MAX_TX_DESC_CNT - 1)) ? (x) + 2 : (x) + 1)
296#define TX_BD(x) ((x) & MAX_TX_BD)
297#define TX_BD_POFF(x) ((x) & MAX_TX_DESC_CNT)
298
299/* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */
300#define NUM_RX_RINGS 8
301#define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd))
302#define MAX_RX_DESC_CNT (RX_DESC_CNT - 2)
303#define RX_DESC_MASK (RX_DESC_CNT - 1)
304#define NUM_RX_BD (RX_DESC_CNT * NUM_RX_RINGS)
305#define MAX_RX_BD (NUM_RX_BD - 1)
306#define MAX_RX_AVAIL (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2)
307#define NEXT_RX_IDX(x) ((((x) & RX_DESC_MASK) == \
308 (MAX_RX_DESC_CNT - 1)) ? (x) + 3 : (x) + 1)
309#define RX_BD(x) ((x) & MAX_RX_BD)
310
311/* As long as CQE is 4 times bigger than BD entry we have to allocate
312 4 times more pages for CQ ring in order to keep it balanced with
313 BD ring */
314#define NUM_RCQ_RINGS (NUM_RX_RINGS * 4)
315#define RCQ_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe))
316#define MAX_RCQ_DESC_CNT (RCQ_DESC_CNT - 1)
317#define NUM_RCQ_BD (RCQ_DESC_CNT * NUM_RCQ_RINGS)
318#define MAX_RCQ_BD (NUM_RCQ_BD - 1)
319#define MAX_RCQ_AVAIL (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2)
320#define NEXT_RCQ_IDX(x) ((((x) & MAX_RCQ_DESC_CNT) == \
321 (MAX_RCQ_DESC_CNT - 1)) ? (x) + 2 : (x) + 1)
322#define RCQ_BD(x) ((x) & MAX_RCQ_BD)
323
324
Eilon Greenstein33471622008-08-13 15:59:08 -0700325/* This is needed for determining of last_max */
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700326#define SUB_S16(a, b) (s16)((s16)(a) - (s16)(b))
327
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -0700328#define __SGE_MASK_SET_BIT(el, bit) \
329 do { \
330 el = ((el) | ((u64)0x1 << (bit))); \
331 } while (0)
332
333#define __SGE_MASK_CLEAR_BIT(el, bit) \
334 do { \
335 el = ((el) & (~((u64)0x1 << (bit)))); \
336 } while (0)
337
338#define SGE_MASK_SET_BIT(fp, idx) \
339 __SGE_MASK_SET_BIT(fp->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \
340 ((idx) & RX_SGE_MASK_ELEM_MASK))
341
342#define SGE_MASK_CLEAR_BIT(fp, idx) \
343 __SGE_MASK_CLEAR_BIT(fp->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \
344 ((idx) & RX_SGE_MASK_ELEM_MASK))
345
346
347/* used on a CID received from the HW */
348#define SW_CID(x) (le32_to_cpu(x) & \
349 (COMMON_RAMROD_ETH_RX_CQE_CID >> 7))
350#define CQE_CMD(x) (le32_to_cpu(x) >> \
351 COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT)
352
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -0700353#define BD_UNMAP_ADDR(bd) HILO_U64(le32_to_cpu((bd)->addr_hi), \
354 le32_to_cpu((bd)->addr_lo))
355#define BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes))
356
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -0700357
358#define DPM_TRIGER_TYPE 0x40
359#define DOORBELL(bp, cid, val) \
360 do { \
361 writel((u32)val, (bp)->doorbells + (BCM_PAGE_SIZE * cid) + \
362 DPM_TRIGER_TYPE); \
363 } while (0)
364
365
366/* TX CSUM helpers */
367#define SKB_CS_OFF(skb) (offsetof(struct tcphdr, check) - \
368 skb->csum_offset)
369#define SKB_CS(skb) (*(u16 *)(skb_transport_header(skb) + \
370 skb->csum_offset))
371
372#define pbd_tcp_flags(skb) (ntohl(tcp_flag_word(tcp_hdr(skb)))>>16 & 0xff)
373
374#define XMIT_PLAIN 0
375#define XMIT_CSUM_V4 0x1
376#define XMIT_CSUM_V6 0x2
377#define XMIT_CSUM_TCP 0x4
378#define XMIT_GSO_V4 0x8
379#define XMIT_GSO_V6 0x10
380
381#define XMIT_CSUM (XMIT_CSUM_V4 | XMIT_CSUM_V6)
382#define XMIT_GSO (XMIT_GSO_V4 | XMIT_GSO_V6)
383
384
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700385/* stuff added to make the code fit 80Col */
386
387#define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE)
388
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -0700389#define TPA_TYPE_START ETH_FAST_PATH_RX_CQE_START_FLG
390#define TPA_TYPE_END ETH_FAST_PATH_RX_CQE_END_FLG
391#define TPA_TYPE(cqe_fp_flags) ((cqe_fp_flags) & \
392 (TPA_TYPE_START | TPA_TYPE_END))
393
Eilon Greenstein1adcd8b2008-08-13 15:48:29 -0700394#define ETH_RX_ERROR_FALGS ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG
395
396#define BNX2X_IP_CSUM_ERR(cqe) \
397 (!((cqe)->fast_path_cqe.status_flags & \
398 ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG) && \
399 ((cqe)->fast_path_cqe.type_error_flags & \
400 ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG))
401
402#define BNX2X_L4_CSUM_ERR(cqe) \
403 (!((cqe)->fast_path_cqe.status_flags & \
404 ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG) && \
405 ((cqe)->fast_path_cqe.type_error_flags & \
406 ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG))
407
408#define BNX2X_RX_CSUM_OK(cqe) \
409 (!(BNX2X_L4_CSUM_ERR(cqe) || BNX2X_IP_CSUM_ERR(cqe)))
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -0700410
411#define BNX2X_RX_SUM_FIX(cqe) \
412 ((le16_to_cpu(cqe->fast_path_cqe.pars_flags.flags) & \
413 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) == \
414 (1 << PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT))
415
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200416
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -0700417#define FP_USB_FUNC_OFF (2 + 2*HC_USTORM_SB_NUM_INDICES)
418#define FP_CSB_FUNC_OFF (2 + 2*HC_CSTORM_SB_NUM_INDICES)
419
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700420#define U_SB_ETH_RX_CQ_INDEX HC_INDEX_U_ETH_RX_CQ_CONS
421#define U_SB_ETH_RX_BD_INDEX HC_INDEX_U_ETH_RX_BD_CONS
422#define C_SB_ETH_TX_CQ_INDEX HC_INDEX_C_ETH_TX_CQ_CONS
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200423
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700424#define BNX2X_RX_SB_INDEX \
425 (&fp->status_blk->u_status_block.index_values[U_SB_ETH_RX_CQ_INDEX])
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200426
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700427#define BNX2X_RX_SB_BD_INDEX \
428 (&fp->status_blk->u_status_block.index_values[U_SB_ETH_RX_BD_INDEX])
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200429
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700430#define BNX2X_RX_SB_INDEX_NUM \
431 (((U_SB_ETH_RX_CQ_INDEX << \
432 USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER_SHIFT) & \
433 USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER) | \
434 ((U_SB_ETH_RX_BD_INDEX << \
435 USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER_SHIFT) & \
436 USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER))
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200437
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700438#define BNX2X_TX_SB_INDEX \
439 (&fp->status_blk->c_status_block.index_values[C_SB_ETH_TX_CQ_INDEX])
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200440
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -0700441
442/* end of fast path */
443
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700444/* common */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200445
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700446struct bnx2x_common {
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200447
Eilon Greensteinad8d3942008-06-23 20:29:02 -0700448 u32 chip_id;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200449/* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700450#define CHIP_ID(bp) (bp->common.chip_id & 0xfffffff0)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200451
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700452#define CHIP_NUM(bp) (bp->common.chip_id >> 16)
Eilon Greensteinad8d3942008-06-23 20:29:02 -0700453#define CHIP_NUM_57710 0x164e
454#define CHIP_NUM_57711 0x164f
455#define CHIP_NUM_57711E 0x1650
456#define CHIP_IS_E1(bp) (CHIP_NUM(bp) == CHIP_NUM_57710)
457#define CHIP_IS_57711(bp) (CHIP_NUM(bp) == CHIP_NUM_57711)
458#define CHIP_IS_57711E(bp) (CHIP_NUM(bp) == CHIP_NUM_57711E)
459#define CHIP_IS_E1H(bp) (CHIP_IS_57711(bp) || \
460 CHIP_IS_57711E(bp))
461#define IS_E1H_OFFSET CHIP_IS_E1H(bp)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200462
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700463#define CHIP_REV(bp) (bp->common.chip_id & 0x0000f000)
Eilon Greensteinad8d3942008-06-23 20:29:02 -0700464#define CHIP_REV_Ax 0x00000000
465/* assume maximum 5 revisions */
466#define CHIP_REV_IS_SLOW(bp) (CHIP_REV(bp) > 0x00005000)
467/* Emul versions are A=>0xe, B=>0xc, C=>0xa, D=>8, E=>6 */
468#define CHIP_REV_IS_EMUL(bp) ((CHIP_REV_IS_SLOW(bp)) && \
469 !(CHIP_REV(bp) & 0x00001000))
470/* FPGA versions are A=>0xf, B=>0xd, C=>0xb, D=>9, E=>7 */
471#define CHIP_REV_IS_FPGA(bp) ((CHIP_REV_IS_SLOW(bp)) && \
472 (CHIP_REV(bp) & 0x00001000))
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200473
Eilon Greensteinad8d3942008-06-23 20:29:02 -0700474#define CHIP_TIME(bp) ((CHIP_REV_IS_EMUL(bp)) ? 2000 : \
475 ((CHIP_REV_IS_FPGA(bp)) ? 200 : 1))
476
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700477#define CHIP_METAL(bp) (bp->common.chip_id & 0x00000ff0)
478#define CHIP_BOND_ID(bp) (bp->common.chip_id & 0x0000000f)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200479
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700480 int flash_size;
481#define NVRAM_1MB_SIZE 0x20000 /* 1M bit in bytes */
482#define NVRAM_TIMEOUT_COUNT 30000
483#define NVRAM_PAGE_SIZE 256
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200484
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700485 u32 shmem_base;
486
487 u32 hw_config;
Eliezer Tamirf1410642008-02-28 11:51:50 -0800488 u32 board;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200489
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700490 u32 bc_ver;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200491
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700492 char *name;
493};
494
495
496/* end of common */
497
498/* port */
499
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -0700500struct nig_stats {
501 u32 brb_discard;
502 u32 brb_packet;
503 u32 brb_truncate;
504 u32 flow_ctrl_discard;
505 u32 flow_ctrl_octets;
506 u32 flow_ctrl_packet;
507 u32 mng_discard;
508 u32 mng_octet_inp;
509 u32 mng_octet_out;
510 u32 mng_packet_inp;
511 u32 mng_packet_out;
512 u32 pbf_octets;
513 u32 pbf_packet;
514 u32 safc_inp;
515 u32 egress_mac_pkt0_lo;
516 u32 egress_mac_pkt0_hi;
517 u32 egress_mac_pkt1_lo;
518 u32 egress_mac_pkt1_hi;
519};
520
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700521struct bnx2x_port {
522 u32 pmf;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200523
Yaniv Rosnerc18487e2008-06-23 20:27:52 -0700524 u32 link_config;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200525
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700526 u32 supported;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200527/* link settings - missing defines */
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700528#define SUPPORTED_2500baseX_Full (1 << 15)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200529
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700530 u32 advertising;
531/* link settings - missing defines */
532#define ADVERTISED_2500baseX_Full (1 << 15)
533
534 u32 phy_addr;
Yaniv Rosnerc18487e2008-06-23 20:27:52 -0700535
536 /* used to synchronize phy accesses */
537 struct mutex phy_mutex;
538
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700539 u32 port_stx;
540
541 struct nig_stats old_nig_stats;
542};
543
544/* end of port */
545
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -0700546
547enum bnx2x_stats_event {
548 STATS_EVENT_PMF = 0,
549 STATS_EVENT_LINK_UP,
550 STATS_EVENT_UPDATE,
551 STATS_EVENT_STOP,
552 STATS_EVENT_MAX
553};
554
555enum bnx2x_stats_state {
556 STATS_STATE_DISABLED = 0,
557 STATS_STATE_ENABLED,
558 STATS_STATE_MAX
559};
560
561struct bnx2x_eth_stats {
562 u32 total_bytes_received_hi;
563 u32 total_bytes_received_lo;
564 u32 total_bytes_transmitted_hi;
565 u32 total_bytes_transmitted_lo;
566 u32 total_unicast_packets_received_hi;
567 u32 total_unicast_packets_received_lo;
568 u32 total_multicast_packets_received_hi;
569 u32 total_multicast_packets_received_lo;
570 u32 total_broadcast_packets_received_hi;
571 u32 total_broadcast_packets_received_lo;
572 u32 total_unicast_packets_transmitted_hi;
573 u32 total_unicast_packets_transmitted_lo;
574 u32 total_multicast_packets_transmitted_hi;
575 u32 total_multicast_packets_transmitted_lo;
576 u32 total_broadcast_packets_transmitted_hi;
577 u32 total_broadcast_packets_transmitted_lo;
578 u32 valid_bytes_received_hi;
579 u32 valid_bytes_received_lo;
580
581 u32 error_bytes_received_hi;
582 u32 error_bytes_received_lo;
583
584 u32 rx_stat_ifhcinbadoctets_hi;
585 u32 rx_stat_ifhcinbadoctets_lo;
586 u32 tx_stat_ifhcoutbadoctets_hi;
587 u32 tx_stat_ifhcoutbadoctets_lo;
588 u32 rx_stat_dot3statsfcserrors_hi;
589 u32 rx_stat_dot3statsfcserrors_lo;
590 u32 rx_stat_dot3statsalignmenterrors_hi;
591 u32 rx_stat_dot3statsalignmenterrors_lo;
592 u32 rx_stat_dot3statscarriersenseerrors_hi;
593 u32 rx_stat_dot3statscarriersenseerrors_lo;
594 u32 rx_stat_falsecarriererrors_hi;
595 u32 rx_stat_falsecarriererrors_lo;
596 u32 rx_stat_etherstatsundersizepkts_hi;
597 u32 rx_stat_etherstatsundersizepkts_lo;
598 u32 rx_stat_dot3statsframestoolong_hi;
599 u32 rx_stat_dot3statsframestoolong_lo;
600 u32 rx_stat_etherstatsfragments_hi;
601 u32 rx_stat_etherstatsfragments_lo;
602 u32 rx_stat_etherstatsjabbers_hi;
603 u32 rx_stat_etherstatsjabbers_lo;
604 u32 rx_stat_maccontrolframesreceived_hi;
605 u32 rx_stat_maccontrolframesreceived_lo;
606 u32 rx_stat_bmac_xpf_hi;
607 u32 rx_stat_bmac_xpf_lo;
608 u32 rx_stat_bmac_xcf_hi;
609 u32 rx_stat_bmac_xcf_lo;
610 u32 rx_stat_xoffstateentered_hi;
611 u32 rx_stat_xoffstateentered_lo;
612 u32 rx_stat_xonpauseframesreceived_hi;
613 u32 rx_stat_xonpauseframesreceived_lo;
614 u32 rx_stat_xoffpauseframesreceived_hi;
615 u32 rx_stat_xoffpauseframesreceived_lo;
616 u32 tx_stat_outxonsent_hi;
617 u32 tx_stat_outxonsent_lo;
618 u32 tx_stat_outxoffsent_hi;
619 u32 tx_stat_outxoffsent_lo;
620 u32 tx_stat_flowcontroldone_hi;
621 u32 tx_stat_flowcontroldone_lo;
622 u32 tx_stat_etherstatscollisions_hi;
623 u32 tx_stat_etherstatscollisions_lo;
624 u32 tx_stat_dot3statssinglecollisionframes_hi;
625 u32 tx_stat_dot3statssinglecollisionframes_lo;
626 u32 tx_stat_dot3statsmultiplecollisionframes_hi;
627 u32 tx_stat_dot3statsmultiplecollisionframes_lo;
628 u32 tx_stat_dot3statsdeferredtransmissions_hi;
629 u32 tx_stat_dot3statsdeferredtransmissions_lo;
630 u32 tx_stat_dot3statsexcessivecollisions_hi;
631 u32 tx_stat_dot3statsexcessivecollisions_lo;
632 u32 tx_stat_dot3statslatecollisions_hi;
633 u32 tx_stat_dot3statslatecollisions_lo;
634 u32 tx_stat_etherstatspkts64octets_hi;
635 u32 tx_stat_etherstatspkts64octets_lo;
636 u32 tx_stat_etherstatspkts65octetsto127octets_hi;
637 u32 tx_stat_etherstatspkts65octetsto127octets_lo;
638 u32 tx_stat_etherstatspkts128octetsto255octets_hi;
639 u32 tx_stat_etherstatspkts128octetsto255octets_lo;
640 u32 tx_stat_etherstatspkts256octetsto511octets_hi;
641 u32 tx_stat_etherstatspkts256octetsto511octets_lo;
642 u32 tx_stat_etherstatspkts512octetsto1023octets_hi;
643 u32 tx_stat_etherstatspkts512octetsto1023octets_lo;
644 u32 tx_stat_etherstatspkts1024octetsto1522octets_hi;
645 u32 tx_stat_etherstatspkts1024octetsto1522octets_lo;
646 u32 tx_stat_etherstatspktsover1522octets_hi;
647 u32 tx_stat_etherstatspktsover1522octets_lo;
648 u32 tx_stat_bmac_2047_hi;
649 u32 tx_stat_bmac_2047_lo;
650 u32 tx_stat_bmac_4095_hi;
651 u32 tx_stat_bmac_4095_lo;
652 u32 tx_stat_bmac_9216_hi;
653 u32 tx_stat_bmac_9216_lo;
654 u32 tx_stat_bmac_16383_hi;
655 u32 tx_stat_bmac_16383_lo;
656 u32 tx_stat_dot3statsinternalmactransmiterrors_hi;
657 u32 tx_stat_dot3statsinternalmactransmiterrors_lo;
658 u32 tx_stat_bmac_ufl_hi;
659 u32 tx_stat_bmac_ufl_lo;
660
661 u32 brb_drop_hi;
662 u32 brb_drop_lo;
Yitchak Gertner66e855f2008-08-13 15:49:05 -0700663 u32 brb_truncate_hi;
664 u32 brb_truncate_lo;
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -0700665
666 u32 jabber_packets_received;
667
668 u32 etherstatspkts1024octetsto1522octets_hi;
669 u32 etherstatspkts1024octetsto1522octets_lo;
670 u32 etherstatspktsover1522octets_hi;
671 u32 etherstatspktsover1522octets_lo;
672
673 u32 no_buff_discard;
674
675 u32 mac_filter_discard;
676 u32 xxoverflow_discard;
677 u32 brb_truncate_discard;
678 u32 mac_discard;
679
680 u32 driver_xoff;
Yitchak Gertner66e855f2008-08-13 15:49:05 -0700681 u32 rx_err_discard_pkt;
682 u32 rx_skb_alloc_failed;
683 u32 hw_csum_err;
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -0700684};
685
686#define STATS_OFFSET32(stat_name) \
687 (offsetof(struct bnx2x_eth_stats, stat_name) / 4)
688
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700689
690#ifdef BNX2X_MULTI
691#define MAX_CONTEXT 16
692#else
693#define MAX_CONTEXT 1
694#endif
695
696union cdu_context {
697 struct eth_context eth;
698 char pad[1024];
699};
700
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -0700701#define MAX_DMAE_C 8
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700702
703/* DMA memory not used in fastpath */
704struct bnx2x_slowpath {
705 union cdu_context context[MAX_CONTEXT];
706 struct eth_stats_query fw_stats;
707 struct mac_configuration_cmd mac_config;
708 struct mac_configuration_cmd mcast_config;
709
710 /* used by dmae command executer */
711 struct dmae_command dmae[MAX_DMAE_C];
712
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -0700713 u32 stats_comp;
714 union mac_stats mac_stats;
715 struct nig_stats nig_stats;
716 struct host_port_stats port_stats;
717 struct host_func_stats func_stats;
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700718
719 u32 wb_comp;
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700720 u32 wb_data[4];
721};
722
723#define bnx2x_sp(bp, var) (&bp->slowpath->var)
724#define bnx2x_sp_mapping(bp, var) \
725 (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var))
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200726
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200727
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700728/* attn group wiring */
729#define MAX_DYNAMIC_ATTN_GRPS 8
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200730
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700731struct attn_route {
732 u32 sig[4];
733};
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200734
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700735struct bnx2x {
736 /* Fields used in the tx and intr/napi performance paths
737 * are grouped together in the beginning of the structure
738 */
739 struct bnx2x_fastpath fp[MAX_CONTEXT];
740 void __iomem *regview;
741 void __iomem *doorbells;
742#define BNX2X_DB_SIZE (16*2048)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200743
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700744 struct net_device *dev;
745 struct pci_dev *pdev;
746
747 atomic_t intr_sem;
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -0700748 struct msix_entry msix_table[MAX_CONTEXT+1];
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700749
750 int tx_ring_size;
751
752#ifdef BCM_VLAN
753 struct vlan_group *vlgrp;
754#endif
755
756 u32 rx_csum;
757 u32 rx_offset;
Eilon Greenstein437cf2f2008-09-03 14:38:00 -0700758 u32 rx_buf_size;
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700759#define ETH_OVREHEAD (ETH_HLEN + 8) /* 8 for CRC + VLAN */
760#define ETH_MIN_PACKET_SIZE 60
761#define ETH_MAX_PACKET_SIZE 1500
762#define ETH_MAX_JUMBO_PACKET_SIZE 9600
763
764 struct host_def_status_block *def_status_blk;
765#define DEF_SB_ID 16
766 u16 def_c_idx;
767 u16 def_u_idx;
768 u16 def_x_idx;
769 u16 def_t_idx;
770 u16 def_att_idx;
771 u32 attn_state;
772 struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS];
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700773 u32 nig_mask;
774
775 /* slow path ring */
776 struct eth_spe *spq;
777 dma_addr_t spq_mapping;
778 u16 spq_prod_idx;
779 struct eth_spe *spq_prod_bd;
780 struct eth_spe *spq_last_bd;
781 u16 *dsb_sp_prod;
782 u16 spq_left; /* serialize spq */
783 /* used to synchronize spq accesses */
784 spinlock_t spq_lock;
785
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -0700786 /* Flags for marking that there is a STAT_QUERY or
787 SET_MAC ramrod pending */
788 u8 stats_pending;
789 u8 set_mac_pending;
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700790
Eilon Greenstein33471622008-08-13 15:59:08 -0700791 /* End of fields used in the performance code paths */
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700792
793 int panic;
794 int msglevel;
795
796 u32 flags;
797#define PCIX_FLAG 1
798#define PCI_32BIT_FLAG 2
799#define ONE_TDMA_FLAG 4 /* no longer used */
800#define NO_WOL_FLAG 8
801#define USING_DAC_FLAG 0x10
802#define USING_MSIX_FLAG 0x20
803#define ASF_ENABLE_FLAG 0x40
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -0700804#define TPA_ENABLE_FLAG 0x80
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700805#define NO_MCP_FLAG 0x100
806#define BP_NOMCP(bp) (bp->flags & NO_MCP_FLAG)
807
808 int func;
809#define BP_PORT(bp) (bp->func % PORT_MAX)
810#define BP_FUNC(bp) (bp->func)
811#define BP_E1HVN(bp) (bp->func >> 1)
812#define BP_L_ID(bp) (BP_E1HVN(bp) << 2)
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700813
814 int pm_cap;
815 int pcie_cap;
816
Eilon Greenstein1cf167f2009-01-14 21:22:18 -0800817 struct delayed_work sp_task;
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700818 struct work_struct reset_task;
819
820 struct timer_list timer;
821 int timer_interval;
822 int current_interval;
823
824 u16 fw_seq;
825 u16 fw_drv_pulse_wr_seq;
826 u32 func_stx;
827
828 struct link_params link_params;
829 struct link_vars link_vars;
830
831 struct bnx2x_common common;
832 struct bnx2x_port port;
833
834 u32 mf_config;
835 u16 e1hov;
836 u8 e1hmf;
Eilon Greenstein3196a882008-08-13 15:58:49 -0700837#define IS_E1HMF(bp) (bp->e1hmf != 0)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200838
Eliezer Tamirf1410642008-02-28 11:51:50 -0800839 u8 wol;
840
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700841 int rx_ring_size;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200842
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700843 u16 tx_quick_cons_trip_int;
844 u16 tx_quick_cons_trip;
845 u16 tx_ticks_int;
846 u16 tx_ticks;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200847
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700848 u16 rx_quick_cons_trip_int;
849 u16 rx_quick_cons_trip;
850 u16 rx_ticks_int;
851 u16 rx_ticks;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200852
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700853 u32 lin_cnt;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200854
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700855 int state;
856#define BNX2X_STATE_CLOSED 0x0
857#define BNX2X_STATE_OPENING_WAIT4_LOAD 0x1000
858#define BNX2X_STATE_OPENING_WAIT4_PORT 0x2000
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200859#define BNX2X_STATE_OPEN 0x3000
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700860#define BNX2X_STATE_CLOSING_WAIT4_HALT 0x4000
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200861#define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000
862#define BNX2X_STATE_CLOSING_WAIT4_UNLOAD 0x6000
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700863#define BNX2X_STATE_DISABLED 0xd000
864#define BNX2X_STATE_DIAG 0xe000
865#define BNX2X_STATE_ERROR 0xf000
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200866
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700867 int num_queues;
Eilon Greenstein3196a882008-08-13 15:58:49 -0700868#define BP_MAX_QUEUES(bp) (IS_E1HMF(bp) ? 4 : 16)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200869
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700870 u32 rx_mode;
871#define BNX2X_RX_MODE_NONE 0
872#define BNX2X_RX_MODE_NORMAL 1
873#define BNX2X_RX_MODE_ALLMULTI 2
874#define BNX2X_RX_MODE_PROMISC 3
875#define BNX2X_MAX_MULTICAST 64
876#define BNX2X_MAX_EMUL_MULTI 16
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200877
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700878 dma_addr_t def_status_blk_mapping;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200879
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700880 struct bnx2x_slowpath *slowpath;
881 dma_addr_t slowpath_mapping;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200882
883#ifdef BCM_ISCSI
884 void *t1;
885 dma_addr_t t1_mapping;
886 void *t2;
887 dma_addr_t t2_mapping;
888 void *timers;
889 dma_addr_t timers_mapping;
890 void *qm;
891 dma_addr_t qm_mapping;
892#endif
893
Eilon Greensteinad8d3942008-06-23 20:29:02 -0700894 int dmae_ready;
895 /* used to synchronize dmae accesses */
896 struct mutex dmae_mutex;
897 struct dmae_command init_dmae;
898
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -0700899 /* used to synchronize stats collecting */
900 int stats_state;
901 /* used by dmae command loader */
902 struct dmae_command stats_dmae;
903 int executer_idx;
Eilon Greensteinad8d3942008-06-23 20:29:02 -0700904
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -0700905 u16 stats_counter;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200906 struct tstorm_per_client_stats old_tclient;
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -0700907 struct xstorm_per_client_stats old_xclient;
908 struct bnx2x_eth_stats eth_stats;
909
910 struct z_stream_s *strm;
911 void *gunzip_buf;
912 dma_addr_t gunzip_mapping;
913 int gunzip_outlen;
Eilon Greensteinad8d3942008-06-23 20:29:02 -0700914#define FW_BUF_SIZE 0x8000
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200915
916};
917
918
Eilon Greenstein3196a882008-08-13 15:58:49 -0700919#define for_each_queue(bp, var) for (var = 0; var < bp->num_queues; var++)
920
921#define for_each_nondefault_queue(bp, var) \
922 for (var = 1; var < bp->num_queues; var++)
923#define is_multi(bp) (bp->num_queues > 1)
924
925
Yaniv Rosnerc18487e2008-06-23 20:27:52 -0700926void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32);
927void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
928 u32 len32);
Eilon Greenstein17de50b2008-08-13 15:56:59 -0700929int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
Yaniv Rosnerc18487e2008-06-23 20:27:52 -0700930
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700931static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
932 int wait)
933{
934 u32 val;
935
936 do {
937 val = REG_RD(bp, reg);
938 if (val == expected)
939 break;
940 ms -= wait;
941 msleep(wait);
942
943 } while (ms > 0);
944
945 return val;
946}
947
948
949/* load/unload mode */
950#define LOAD_NORMAL 0
951#define LOAD_OPEN 1
952#define LOAD_DIAG 2
953#define UNLOAD_NORMAL 0
954#define UNLOAD_CLOSE 1
955
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -0700956
Eilon Greensteinad8d3942008-06-23 20:29:02 -0700957/* DMAE command defines */
958#define DMAE_CMD_SRC_PCI 0
959#define DMAE_CMD_SRC_GRC DMAE_COMMAND_SRC
960
961#define DMAE_CMD_DST_PCI (1 << DMAE_COMMAND_DST_SHIFT)
962#define DMAE_CMD_DST_GRC (2 << DMAE_COMMAND_DST_SHIFT)
963
964#define DMAE_CMD_C_DST_PCI 0
965#define DMAE_CMD_C_DST_GRC (1 << DMAE_COMMAND_C_DST_SHIFT)
966
967#define DMAE_CMD_C_ENABLE DMAE_COMMAND_C_TYPE_ENABLE
968
969#define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT)
970#define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT)
971#define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT)
972#define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT)
973
974#define DMAE_CMD_PORT_0 0
975#define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT
976
977#define DMAE_CMD_SRC_RESET DMAE_COMMAND_SRC_RESET
978#define DMAE_CMD_DST_RESET DMAE_COMMAND_DST_RESET
979#define DMAE_CMD_E1HVN_SHIFT DMAE_COMMAND_E1HVN_SHIFT
980
981#define DMAE_LEN32_RD_MAX 0x80
982#define DMAE_LEN32_WR_MAX 0x400
983
984#define DMAE_COMP_VAL 0xe0d0d0ae
985
986#define MAX_DMAE_C_PER_PORT 8
987#define INIT_DMAE_C(bp) (BP_PORT(bp)*MAX_DMAE_C_PER_PORT + \
988 BP_E1HVN(bp))
989#define PMF_DMAE_C(bp) (BP_PORT(bp)*MAX_DMAE_C_PER_PORT + \
990 E1HVN_MAX)
991
992
Eliezer Tamir25047952008-02-28 11:50:16 -0800993/* PCIE link and speed */
994#define PCICFG_LINK_WIDTH 0x1f00000
995#define PCICFG_LINK_WIDTH_SHIFT 20
996#define PCICFG_LINK_SPEED 0xf0000
997#define PCICFG_LINK_SPEED_SHIFT 16
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200998
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -0700999
Yitchak Gertner66e855f2008-08-13 15:49:05 -07001000#define BNX2X_NUM_STATS 42
Yitchak Gertnerbb2a0f72008-06-23 20:33:36 -07001001#define BNX2X_NUM_TESTS 8
1002
1003#define BNX2X_MAC_LOOPBACK 0
1004#define BNX2X_PHY_LOOPBACK 1
1005#define BNX2X_MAC_LOOPBACK_FAILED 1
1006#define BNX2X_PHY_LOOPBACK_FAILED 2
1007#define BNX2X_LOOPBACK_FAILED (BNX2X_MAC_LOOPBACK_FAILED | \
1008 BNX2X_PHY_LOOPBACK_FAILED)
Eliezer Tamir96fc1782008-02-28 11:57:55 -08001009
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -07001010
1011#define STROM_ASSERT_ARRAY_SIZE 50
1012
Eliezer Tamir96fc1782008-02-28 11:57:55 -08001013
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001014/* must be used on a CID before placing it on a HW ring */
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -07001015#define HW_CID(bp, x) ((BP_PORT(bp) << 23) | (BP_E1HVN(bp) << 17) | x)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001016
Vladislav Zolotarov7a9b2552008-06-23 20:34:36 -07001017#define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe))
1018#define MAX_SP_DESC_CNT (SP_DESC_CNT - 1)
1019
1020
1021#define BNX2X_BTR 3
1022#define MAX_SPQ_PENDING 8
1023
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001024
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001025/* CMNG constants
1026 derived from lab experiments, and not from system spec calculations !!! */
1027#define DEF_MIN_RATE 100
1028/* resolution of the rate shaping timer - 100 usec */
1029#define RS_PERIODIC_TIMEOUT_USEC 100
1030/* resolution of fairness algorithm in usecs -
Eilon Greenstein33471622008-08-13 15:59:08 -07001031 coefficient for calculating the actual t fair */
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001032#define T_FAIR_COEF 10000000
1033/* number of bytes in single QM arbitration cycle -
Eilon Greenstein33471622008-08-13 15:59:08 -07001034 coefficient for calculating the fairness timer */
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001035#define QM_ARB_BYTES 40000
1036#define FAIR_MEM 2
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001037
1038
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001039#define ATTN_NIG_FOR_FUNC (1L << 8)
1040#define ATTN_SW_TIMER_4_FUNC (1L << 9)
1041#define GPIO_2_FUNC (1L << 10)
1042#define GPIO_3_FUNC (1L << 11)
1043#define GPIO_4_FUNC (1L << 12)
1044#define ATTN_GENERAL_ATTN_1 (1L << 13)
1045#define ATTN_GENERAL_ATTN_2 (1L << 14)
1046#define ATTN_GENERAL_ATTN_3 (1L << 15)
1047#define ATTN_GENERAL_ATTN_4 (1L << 13)
1048#define ATTN_GENERAL_ATTN_5 (1L << 14)
1049#define ATTN_GENERAL_ATTN_6 (1L << 15)
1050
1051#define ATTN_HARD_WIRED_MASK 0xff00
1052#define ATTENTION_ID 4
1053
1054
1055/* stuff added to make the code fit 80Col */
1056
1057#define BNX2X_PMF_LINK_ASSERT \
1058 GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + BP_FUNC(bp))
1059
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001060#define BNX2X_MC_ASSERT_BITS \
1061 (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1062 GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1063 GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1064 GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT))
1065
1066#define BNX2X_MCP_ASSERT \
1067 GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT)
1068
1069#define BNX2X_DOORQ_ASSERT \
1070 AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT
1071
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001072#define BNX2X_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC)
1073#define BNX2X_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \
1074 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \
1075 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \
1076 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \
1077 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \
1078 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC))
1079
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001080#define HW_INTERRUT_ASSERT_SET_0 \
1081 (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \
1082 AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \
1083 AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \
1084 AEU_INPUTS_ATTN_BITS_PBF_HW_INTERRUPT)
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001085#define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001086 AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \
1087 AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \
1088 AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\
1089 AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR)
1090#define HW_INTERRUT_ASSERT_SET_1 \
1091 (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \
1092 AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \
1093 AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \
1094 AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \
1095 AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \
1096 AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \
1097 AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \
1098 AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \
1099 AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \
1100 AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \
1101 AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT)
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001102#define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR |\
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001103 AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \
1104 AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \
1105 AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \
1106 AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\
1107 AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\
1108 AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \
1109 AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \
1110 AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \
1111 AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \
1112 AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR)
1113#define HW_INTERRUT_ASSERT_SET_2 \
1114 (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \
1115 AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \
1116 AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \
1117 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\
1118 AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT)
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001119#define HW_PRTY_ASSERT_SET_2 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001120 AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \
1121 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\
1122 AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \
1123 AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \
1124 AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \
1125 AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR)
1126
1127
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001128#define MULTI_FLAGS \
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001129 (TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY | \
1130 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY | \
1131 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY | \
1132 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY | \
1133 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_ENABLE)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001134
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001135#define MULTI_MASK 0x7f
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001136
1137
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001138#define DEF_USB_FUNC_OFF (2 + 2*HC_USTORM_DEF_SB_NUM_INDICES)
1139#define DEF_CSB_FUNC_OFF (2 + 2*HC_CSTORM_DEF_SB_NUM_INDICES)
1140#define DEF_XSB_FUNC_OFF (2 + 2*HC_XSTORM_DEF_SB_NUM_INDICES)
1141#define DEF_TSB_FUNC_OFF (2 + 2*HC_TSTORM_DEF_SB_NUM_INDICES)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001142
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001143#define C_DEF_SB_SP_INDEX HC_INDEX_DEF_C_ETH_SLOW_PATH
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001144
1145#define BNX2X_SP_DSB_INDEX \
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001146(&bp->def_status_blk->c_def_status_block.index_values[C_DEF_SB_SP_INDEX])
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001147
1148
1149#define CAM_IS_INVALID(x) \
1150(x.target_table_entry.flags == TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE)
1151
1152#define CAM_INVALIDATE(x) \
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001153 (x.target_table_entry.flags = TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001154
1155
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001156/* Number of u32 elements in MC hash array */
1157#define MC_HASH_SIZE 8
1158#define MC_HASH_OFFSET(bp, i) (BAR_TSTRORM_INTMEM + \
1159 TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(BP_FUNC(bp)) + i*4)
1160
1161
1162#ifndef PXP2_REG_PXP2_INT_STS
1163#define PXP2_REG_PXP2_INT_STS PXP2_REG_PXP2_INT_STS_0
1164#endif
1165
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001166/* MISC_REG_RESET_REG - this is here for the hsi to work don't touch */
1167
1168#endif /* bnx2x.h */