blob: 1bc00dc4876c0678e1bbd78e43f0806d822ddeeb [file] [log] [blame]
Paul Walmsleyd198b512010-12-21 15:30:54 -07001/*
2 * OMAP44xx CM1 instance offset macros
3 *
Benoit Coussonad98a182011-07-09 19:15:04 -06004 * Copyright (C) 2009-2011 Texas Instruments, Inc.
Paul Walmsleyd198b512010-12-21 15:30:54 -07005 * Copyright (C) 2009-2010 Nokia Corporation
6 *
7 * Paul Walmsley (paul@pwsan.com)
8 * Rajendra Nayak (rnayak@ti.com)
9 * Benoit Cousson (b-cousson@ti.com)
10 *
11 * This file is automatically generated from the OMAP hardware databases.
12 * We respectfully ask that any modifications to this file be coordinated
13 * with the public linux-omap@vger.kernel.org mailing list and the
14 * authors above to ensure that the autogeneration scripts are kept
15 * up-to-date with the file contents.
16 *
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License version 2 as
19 * published by the Free Software Foundation.
20 *
21 * XXX This file needs to be updated to align on one of "OMAP4", "OMAP44XX",
22 * or "OMAP4430".
23 */
24
25#ifndef __ARCH_ARM_MACH_OMAP2_CM1_44XX_H
26#define __ARCH_ARM_MACH_OMAP2_CM1_44XX_H
27
28/* CM1 base address */
29#define OMAP4430_CM1_BASE 0x4a004000
30
Paul Walmsleycdb54c42010-12-21 15:30:55 -070031#define OMAP44XX_CM1_REGADDR(inst, reg) \
32 OMAP2_L4_IO_ADDRESS(OMAP4430_CM1_BASE + (inst) + (reg))
Paul Walmsleyd198b512010-12-21 15:30:54 -070033
34/* CM1 instances */
Paul Walmsleycdb54c42010-12-21 15:30:55 -070035#define OMAP4430_CM1_OCP_SOCKET_INST 0x0000
36#define OMAP4430_CM1_CKGEN_INST 0x0100
37#define OMAP4430_CM1_MPU_INST 0x0300
38#define OMAP4430_CM1_TESLA_INST 0x0400
39#define OMAP4430_CM1_ABE_INST 0x0500
40#define OMAP4430_CM1_RESTORE_INST 0x0e00
41#define OMAP4430_CM1_INSTR_INST 0x0f00
Paul Walmsleyd198b512010-12-21 15:30:54 -070042
Paul Walmsleye4156ee2010-12-21 21:05:15 -070043/* CM1 clockdomain register offsets (from instance start) */
Benoit Coussonad98a182011-07-09 19:15:04 -060044#define OMAP4430_CM1_MPU_MPU_CDOFFS 0x0000
45#define OMAP4430_CM1_TESLA_TESLA_CDOFFS 0x0000
46#define OMAP4430_CM1_ABE_ABE_CDOFFS 0x0000
Paul Walmsleye4156ee2010-12-21 21:05:15 -070047
Paul Walmsleyd198b512010-12-21 15:30:54 -070048/* CM1 */
49
50/* CM1.OCP_SOCKET_CM1 register offsets */
51#define OMAP4_REVISION_CM1_OFFSET 0x0000
Paul Walmsleycdb54c42010-12-21 15:30:55 -070052#define OMAP4430_REVISION_CM1 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_OCP_SOCKET_INST, 0x0000)
Paul Walmsleyd198b512010-12-21 15:30:54 -070053#define OMAP4_CM_CM1_PROFILING_CLKCTRL_OFFSET 0x0040
Paul Walmsleycdb54c42010-12-21 15:30:55 -070054#define OMAP4430_CM_CM1_PROFILING_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_OCP_SOCKET_INST, 0x0040)
Paul Walmsleyd198b512010-12-21 15:30:54 -070055
56/* CM1.CKGEN_CM1 register offsets */
57#define OMAP4_CM_CLKSEL_CORE_OFFSET 0x0000
Paul Walmsleycdb54c42010-12-21 15:30:55 -070058#define OMAP4430_CM_CLKSEL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0000)
Paul Walmsleyd198b512010-12-21 15:30:54 -070059#define OMAP4_CM_CLKSEL_ABE_OFFSET 0x0008
Paul Walmsleycdb54c42010-12-21 15:30:55 -070060#define OMAP4430_CM_CLKSEL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0008)
Paul Walmsleyd198b512010-12-21 15:30:54 -070061#define OMAP4_CM_DLL_CTRL_OFFSET 0x0010
Paul Walmsleycdb54c42010-12-21 15:30:55 -070062#define OMAP4430_CM_DLL_CTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0010)
Paul Walmsleyd198b512010-12-21 15:30:54 -070063#define OMAP4_CM_CLKMODE_DPLL_CORE_OFFSET 0x0020
Paul Walmsleycdb54c42010-12-21 15:30:55 -070064#define OMAP4430_CM_CLKMODE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0020)
Paul Walmsleyd198b512010-12-21 15:30:54 -070065#define OMAP4_CM_IDLEST_DPLL_CORE_OFFSET 0x0024
Paul Walmsleycdb54c42010-12-21 15:30:55 -070066#define OMAP4430_CM_IDLEST_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0024)
Paul Walmsleyd198b512010-12-21 15:30:54 -070067#define OMAP4_CM_AUTOIDLE_DPLL_CORE_OFFSET 0x0028
Paul Walmsleycdb54c42010-12-21 15:30:55 -070068#define OMAP4430_CM_AUTOIDLE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0028)
Paul Walmsleyd198b512010-12-21 15:30:54 -070069#define OMAP4_CM_CLKSEL_DPLL_CORE_OFFSET 0x002c
Paul Walmsleycdb54c42010-12-21 15:30:55 -070070#define OMAP4430_CM_CLKSEL_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x002c)
Paul Walmsleyd198b512010-12-21 15:30:54 -070071#define OMAP4_CM_DIV_M2_DPLL_CORE_OFFSET 0x0030
Paul Walmsleycdb54c42010-12-21 15:30:55 -070072#define OMAP4430_CM_DIV_M2_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0030)
Paul Walmsleyd198b512010-12-21 15:30:54 -070073#define OMAP4_CM_DIV_M3_DPLL_CORE_OFFSET 0x0034
Paul Walmsleycdb54c42010-12-21 15:30:55 -070074#define OMAP4430_CM_DIV_M3_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0034)
Paul Walmsleyd198b512010-12-21 15:30:54 -070075#define OMAP4_CM_DIV_M4_DPLL_CORE_OFFSET 0x0038
Paul Walmsleycdb54c42010-12-21 15:30:55 -070076#define OMAP4430_CM_DIV_M4_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0038)
Paul Walmsleyd198b512010-12-21 15:30:54 -070077#define OMAP4_CM_DIV_M5_DPLL_CORE_OFFSET 0x003c
Paul Walmsleycdb54c42010-12-21 15:30:55 -070078#define OMAP4430_CM_DIV_M5_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x003c)
Paul Walmsleyd198b512010-12-21 15:30:54 -070079#define OMAP4_CM_DIV_M6_DPLL_CORE_OFFSET 0x0040
Paul Walmsleycdb54c42010-12-21 15:30:55 -070080#define OMAP4430_CM_DIV_M6_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0040)
Paul Walmsleyd198b512010-12-21 15:30:54 -070081#define OMAP4_CM_DIV_M7_DPLL_CORE_OFFSET 0x0044
Paul Walmsleycdb54c42010-12-21 15:30:55 -070082#define OMAP4430_CM_DIV_M7_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0044)
Paul Walmsleyd198b512010-12-21 15:30:54 -070083#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET 0x0048
Paul Walmsleycdb54c42010-12-21 15:30:55 -070084#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0048)
Benoit Coussonad98a182011-07-09 19:15:04 -060085#define OMAP4_CM_SSC_MODFREQDIV_DPLL_CORE_OFFSET 0x004c
86#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x004c)
Paul Walmsleyd198b512010-12-21 15:30:54 -070087#define OMAP4_CM_EMU_OVERRIDE_DPLL_CORE_OFFSET 0x0050
Paul Walmsleycdb54c42010-12-21 15:30:55 -070088#define OMAP4430_CM_EMU_OVERRIDE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0050)
Paul Walmsleyd198b512010-12-21 15:30:54 -070089#define OMAP4_CM_CLKMODE_DPLL_MPU_OFFSET 0x0060
Paul Walmsleycdb54c42010-12-21 15:30:55 -070090#define OMAP4430_CM_CLKMODE_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0060)
Paul Walmsleyd198b512010-12-21 15:30:54 -070091#define OMAP4_CM_IDLEST_DPLL_MPU_OFFSET 0x0064
Paul Walmsleycdb54c42010-12-21 15:30:55 -070092#define OMAP4430_CM_IDLEST_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0064)
Paul Walmsleyd198b512010-12-21 15:30:54 -070093#define OMAP4_CM_AUTOIDLE_DPLL_MPU_OFFSET 0x0068
Paul Walmsleycdb54c42010-12-21 15:30:55 -070094#define OMAP4430_CM_AUTOIDLE_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0068)
Paul Walmsleyd198b512010-12-21 15:30:54 -070095#define OMAP4_CM_CLKSEL_DPLL_MPU_OFFSET 0x006c
Paul Walmsleycdb54c42010-12-21 15:30:55 -070096#define OMAP4430_CM_CLKSEL_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x006c)
Paul Walmsleyd198b512010-12-21 15:30:54 -070097#define OMAP4_CM_DIV_M2_DPLL_MPU_OFFSET 0x0070
Paul Walmsleycdb54c42010-12-21 15:30:55 -070098#define OMAP4430_CM_DIV_M2_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0070)
Paul Walmsleyd198b512010-12-21 15:30:54 -070099#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET 0x0088
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700100#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0088)
Benoit Coussonad98a182011-07-09 19:15:04 -0600101#define OMAP4_CM_SSC_MODFREQDIV_DPLL_MPU_OFFSET 0x008c
102#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x008c)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700103#define OMAP4_CM_BYPCLK_DPLL_MPU_OFFSET 0x009c
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700104#define OMAP4430_CM_BYPCLK_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x009c)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700105#define OMAP4_CM_CLKMODE_DPLL_IVA_OFFSET 0x00a0
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700106#define OMAP4430_CM_CLKMODE_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00a0)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700107#define OMAP4_CM_IDLEST_DPLL_IVA_OFFSET 0x00a4
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700108#define OMAP4430_CM_IDLEST_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00a4)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700109#define OMAP4_CM_AUTOIDLE_DPLL_IVA_OFFSET 0x00a8
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700110#define OMAP4430_CM_AUTOIDLE_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00a8)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700111#define OMAP4_CM_CLKSEL_DPLL_IVA_OFFSET 0x00ac
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700112#define OMAP4430_CM_CLKSEL_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00ac)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700113#define OMAP4_CM_DIV_M4_DPLL_IVA_OFFSET 0x00b8
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700114#define OMAP4430_CM_DIV_M4_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00b8)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700115#define OMAP4_CM_DIV_M5_DPLL_IVA_OFFSET 0x00bc
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700116#define OMAP4430_CM_DIV_M5_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00bc)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700117#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_IVA_OFFSET 0x00c8
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700118#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00c8)
Benoit Coussonad98a182011-07-09 19:15:04 -0600119#define OMAP4_CM_SSC_MODFREQDIV_DPLL_IVA_OFFSET 0x00cc
120#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00cc)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700121#define OMAP4_CM_BYPCLK_DPLL_IVA_OFFSET 0x00dc
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700122#define OMAP4430_CM_BYPCLK_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00dc)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700123#define OMAP4_CM_CLKMODE_DPLL_ABE_OFFSET 0x00e0
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700124#define OMAP4430_CM_CLKMODE_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00e0)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700125#define OMAP4_CM_IDLEST_DPLL_ABE_OFFSET 0x00e4
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700126#define OMAP4430_CM_IDLEST_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00e4)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700127#define OMAP4_CM_AUTOIDLE_DPLL_ABE_OFFSET 0x00e8
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700128#define OMAP4430_CM_AUTOIDLE_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00e8)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700129#define OMAP4_CM_CLKSEL_DPLL_ABE_OFFSET 0x00ec
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700130#define OMAP4430_CM_CLKSEL_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00ec)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700131#define OMAP4_CM_DIV_M2_DPLL_ABE_OFFSET 0x00f0
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700132#define OMAP4430_CM_DIV_M2_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00f0)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700133#define OMAP4_CM_DIV_M3_DPLL_ABE_OFFSET 0x00f4
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700134#define OMAP4430_CM_DIV_M3_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00f4)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700135#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_ABE_OFFSET 0x0108
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700136#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0108)
Benoit Coussonad98a182011-07-09 19:15:04 -0600137#define OMAP4_CM_SSC_MODFREQDIV_DPLL_ABE_OFFSET 0x010c
138#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x010c)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700139#define OMAP4_CM_CLKMODE_DPLL_DDRPHY_OFFSET 0x0120
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700140#define OMAP4430_CM_CLKMODE_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0120)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700141#define OMAP4_CM_IDLEST_DPLL_DDRPHY_OFFSET 0x0124
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700142#define OMAP4430_CM_IDLEST_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0124)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700143#define OMAP4_CM_AUTOIDLE_DPLL_DDRPHY_OFFSET 0x0128
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700144#define OMAP4430_CM_AUTOIDLE_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0128)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700145#define OMAP4_CM_CLKSEL_DPLL_DDRPHY_OFFSET 0x012c
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700146#define OMAP4430_CM_CLKSEL_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x012c)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700147#define OMAP4_CM_DIV_M2_DPLL_DDRPHY_OFFSET 0x0130
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700148#define OMAP4430_CM_DIV_M2_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0130)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700149#define OMAP4_CM_DIV_M4_DPLL_DDRPHY_OFFSET 0x0138
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700150#define OMAP4430_CM_DIV_M4_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0138)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700151#define OMAP4_CM_DIV_M5_DPLL_DDRPHY_OFFSET 0x013c
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700152#define OMAP4430_CM_DIV_M5_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x013c)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700153#define OMAP4_CM_DIV_M6_DPLL_DDRPHY_OFFSET 0x0140
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700154#define OMAP4430_CM_DIV_M6_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0140)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700155#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_DDRPHY_OFFSET 0x0148
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700156#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0148)
Benoit Coussonad98a182011-07-09 19:15:04 -0600157#define OMAP4_CM_SSC_MODFREQDIV_DPLL_DDRPHY_OFFSET 0x014c
158#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x014c)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700159#define OMAP4_CM_SHADOW_FREQ_CONFIG1_OFFSET 0x0160
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700160#define OMAP4430_CM_SHADOW_FREQ_CONFIG1 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0160)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700161#define OMAP4_CM_SHADOW_FREQ_CONFIG2_OFFSET 0x0164
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700162#define OMAP4430_CM_SHADOW_FREQ_CONFIG2 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0164)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700163#define OMAP4_CM_DYN_DEP_PRESCAL_OFFSET 0x0170
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700164#define OMAP4430_CM_DYN_DEP_PRESCAL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0170)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700165#define OMAP4_CM_RESTORE_ST_OFFSET 0x0180
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700166#define OMAP4430_CM_RESTORE_ST OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0180)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700167
168/* CM1.MPU_CM1 register offsets */
169#define OMAP4_CM_MPU_CLKSTCTRL_OFFSET 0x0000
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700170#define OMAP4430_CM_MPU_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0000)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700171#define OMAP4_CM_MPU_STATICDEP_OFFSET 0x0004
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700172#define OMAP4430_CM_MPU_STATICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0004)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700173#define OMAP4_CM_MPU_DYNAMICDEP_OFFSET 0x0008
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700174#define OMAP4430_CM_MPU_DYNAMICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0008)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700175#define OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET 0x0020
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700176#define OMAP4430_CM_MPU_MPU_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0020)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700177
178/* CM1.TESLA_CM1 register offsets */
179#define OMAP4_CM_TESLA_CLKSTCTRL_OFFSET 0x0000
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700180#define OMAP4430_CM_TESLA_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0000)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700181#define OMAP4_CM_TESLA_STATICDEP_OFFSET 0x0004
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700182#define OMAP4430_CM_TESLA_STATICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0004)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700183#define OMAP4_CM_TESLA_DYNAMICDEP_OFFSET 0x0008
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700184#define OMAP4430_CM_TESLA_DYNAMICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0008)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700185#define OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET 0x0020
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700186#define OMAP4430_CM_TESLA_TESLA_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0020)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700187
188/* CM1.ABE_CM1 register offsets */
189#define OMAP4_CM1_ABE_CLKSTCTRL_OFFSET 0x0000
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700190#define OMAP4430_CM1_ABE_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0000)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700191#define OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET 0x0020
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700192#define OMAP4430_CM1_ABE_L4ABE_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0020)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700193#define OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET 0x0028
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700194#define OMAP4430_CM1_ABE_AESS_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0028)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700195#define OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET 0x0030
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700196#define OMAP4430_CM1_ABE_PDM_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0030)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700197#define OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET 0x0038
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700198#define OMAP4430_CM1_ABE_DMIC_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0038)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700199#define OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET 0x0040
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700200#define OMAP4430_CM1_ABE_MCASP_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0040)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700201#define OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET 0x0048
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700202#define OMAP4430_CM1_ABE_MCBSP1_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0048)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700203#define OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET 0x0050
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700204#define OMAP4430_CM1_ABE_MCBSP2_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0050)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700205#define OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET 0x0058
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700206#define OMAP4430_CM1_ABE_MCBSP3_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0058)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700207#define OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET 0x0060
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700208#define OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0060)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700209#define OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET 0x0068
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700210#define OMAP4430_CM1_ABE_TIMER5_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0068)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700211#define OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET 0x0070
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700212#define OMAP4430_CM1_ABE_TIMER6_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0070)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700213#define OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET 0x0078
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700214#define OMAP4430_CM1_ABE_TIMER7_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0078)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700215#define OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET 0x0080
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700216#define OMAP4430_CM1_ABE_TIMER8_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0080)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700217#define OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET 0x0088
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700218#define OMAP4430_CM1_ABE_WDT3_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0088)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700219
Paul Walmsley2ace8312010-12-21 21:05:14 -0700220/* Function prototypes */
221extern u32 omap4_cm1_read_inst_reg(s16 inst, u16 idx);
222extern void omap4_cm1_write_inst_reg(u32 val, s16 inst, u16 idx);
223extern u32 omap4_cm1_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
224
Paul Walmsleyd198b512010-12-21 15:30:54 -0700225#endif