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Paul Walmsleyd198b512010-12-21 15:30:54 -07001/*
2 * OMAP44xx CM2 instance offset macros
3 *
Benoit Coussonad98a182011-07-09 19:15:04 -06004 * Copyright (C) 2009-2011 Texas Instruments, Inc.
Paul Walmsleyd198b512010-12-21 15:30:54 -07005 * Copyright (C) 2009-2010 Nokia Corporation
6 *
7 * Paul Walmsley (paul@pwsan.com)
8 * Rajendra Nayak (rnayak@ti.com)
9 * Benoit Cousson (b-cousson@ti.com)
10 *
11 * This file is automatically generated from the OMAP hardware databases.
12 * We respectfully ask that any modifications to this file be coordinated
13 * with the public linux-omap@vger.kernel.org mailing list and the
14 * authors above to ensure that the autogeneration scripts are kept
15 * up-to-date with the file contents.
16 *
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License version 2 as
19 * published by the Free Software Foundation.
20 *
21 * XXX This file needs to be updated to align on one of "OMAP4", "OMAP44XX",
22 * or "OMAP4430".
23 */
24
25#ifndef __ARCH_ARM_MACH_OMAP2_CM2_44XX_H
26#define __ARCH_ARM_MACH_OMAP2_CM2_44XX_H
27
28/* CM2 base address */
29#define OMAP4430_CM2_BASE 0x4a008000
30
Paul Walmsleycdb54c42010-12-21 15:30:55 -070031#define OMAP44XX_CM2_REGADDR(inst, reg) \
32 OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE + (inst) + (reg))
Paul Walmsleyd198b512010-12-21 15:30:54 -070033
34/* CM2 instances */
Paul Walmsleycdb54c42010-12-21 15:30:55 -070035#define OMAP4430_CM2_OCP_SOCKET_INST 0x0000
36#define OMAP4430_CM2_CKGEN_INST 0x0100
37#define OMAP4430_CM2_ALWAYS_ON_INST 0x0600
38#define OMAP4430_CM2_CORE_INST 0x0700
39#define OMAP4430_CM2_IVAHD_INST 0x0f00
40#define OMAP4430_CM2_CAM_INST 0x1000
41#define OMAP4430_CM2_DSS_INST 0x1100
42#define OMAP4430_CM2_GFX_INST 0x1200
Benoit Coussonad98a182011-07-09 19:15:04 -060043#define OMAP4430_CM2_L3INIT_INST 0x1300
Paul Walmsleycdb54c42010-12-21 15:30:55 -070044#define OMAP4430_CM2_L4PER_INST 0x1400
Benoit Coussonad98a182011-07-09 19:15:04 -060045#define OMAP4430_CM2_CEFUSE_INST 0x1600
Paul Walmsleycdb54c42010-12-21 15:30:55 -070046#define OMAP4430_CM2_RESTORE_INST 0x1e00
47#define OMAP4430_CM2_INSTR_INST 0x1f00
Paul Walmsleyd198b512010-12-21 15:30:54 -070048
Paul Walmsleye4156ee2010-12-21 21:05:15 -070049/* CM2 clockdomain register offsets (from instance start) */
50#define OMAP4430_CM2_ALWAYS_ON_ALWON_CDOFFS 0x0000
51#define OMAP4430_CM2_CORE_L3_1_CDOFFS 0x0000
52#define OMAP4430_CM2_CORE_L3_2_CDOFFS 0x0100
53#define OMAP4430_CM2_CORE_DUCATI_CDOFFS 0x0200
54#define OMAP4430_CM2_CORE_SDMA_CDOFFS 0x0300
55#define OMAP4430_CM2_CORE_MEMIF_CDOFFS 0x0400
56#define OMAP4430_CM2_CORE_D2D_CDOFFS 0x0500
57#define OMAP4430_CM2_CORE_L4CFG_CDOFFS 0x0600
58#define OMAP4430_CM2_CORE_L3INSTR_CDOFFS 0x0700
59#define OMAP4430_CM2_IVAHD_IVAHD_CDOFFS 0x0000
60#define OMAP4430_CM2_CAM_CAM_CDOFFS 0x0000
61#define OMAP4430_CM2_DSS_DSS_CDOFFS 0x0000
62#define OMAP4430_CM2_GFX_GFX_CDOFFS 0x0000
63#define OMAP4430_CM2_L3INIT_L3INIT_CDOFFS 0x0000
64#define OMAP4430_CM2_L4PER_L4PER_CDOFFS 0x0000
65#define OMAP4430_CM2_L4PER_L4SEC_CDOFFS 0x0180
66#define OMAP4430_CM2_CEFUSE_CEFUSE_CDOFFS 0x0000
67
Paul Walmsleyd198b512010-12-21 15:30:54 -070068/* CM2 */
69
70/* CM2.OCP_SOCKET_CM2 register offsets */
71#define OMAP4_REVISION_CM2_OFFSET 0x0000
Paul Walmsleycdb54c42010-12-21 15:30:55 -070072#define OMAP4430_REVISION_CM2 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_OCP_SOCKET_INST, 0x0000)
Paul Walmsleyd198b512010-12-21 15:30:54 -070073#define OMAP4_CM_CM2_PROFILING_CLKCTRL_OFFSET 0x0040
Paul Walmsleycdb54c42010-12-21 15:30:55 -070074#define OMAP4430_CM_CM2_PROFILING_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_OCP_SOCKET_INST, 0x0040)
Paul Walmsleyd198b512010-12-21 15:30:54 -070075
76/* CM2.CKGEN_CM2 register offsets */
77#define OMAP4_CM_CLKSEL_DUCATI_ISS_ROOT_OFFSET 0x0000
Paul Walmsleycdb54c42010-12-21 15:30:55 -070078#define OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0000)
Paul Walmsleyd198b512010-12-21 15:30:54 -070079#define OMAP4_CM_CLKSEL_USB_60MHZ_OFFSET 0x0004
Paul Walmsleycdb54c42010-12-21 15:30:55 -070080#define OMAP4430_CM_CLKSEL_USB_60MHZ OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0004)
Paul Walmsleyd198b512010-12-21 15:30:54 -070081#define OMAP4_CM_SCALE_FCLK_OFFSET 0x0008
Paul Walmsleycdb54c42010-12-21 15:30:55 -070082#define OMAP4430_CM_SCALE_FCLK OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0008)
Paul Walmsleyd198b512010-12-21 15:30:54 -070083#define OMAP4_CM_CORE_DVFS_PERF1_OFFSET 0x0010
Paul Walmsleycdb54c42010-12-21 15:30:55 -070084#define OMAP4430_CM_CORE_DVFS_PERF1 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0010)
Paul Walmsleyd198b512010-12-21 15:30:54 -070085#define OMAP4_CM_CORE_DVFS_PERF2_OFFSET 0x0014
Paul Walmsleycdb54c42010-12-21 15:30:55 -070086#define OMAP4430_CM_CORE_DVFS_PERF2 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0014)
Paul Walmsleyd198b512010-12-21 15:30:54 -070087#define OMAP4_CM_CORE_DVFS_PERF3_OFFSET 0x0018
Paul Walmsleycdb54c42010-12-21 15:30:55 -070088#define OMAP4430_CM_CORE_DVFS_PERF3 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0018)
Paul Walmsleyd198b512010-12-21 15:30:54 -070089#define OMAP4_CM_CORE_DVFS_PERF4_OFFSET 0x001c
Paul Walmsleycdb54c42010-12-21 15:30:55 -070090#define OMAP4430_CM_CORE_DVFS_PERF4 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x001c)
Paul Walmsleyd198b512010-12-21 15:30:54 -070091#define OMAP4_CM_CORE_DVFS_CURRENT_OFFSET 0x0024
Paul Walmsleycdb54c42010-12-21 15:30:55 -070092#define OMAP4430_CM_CORE_DVFS_CURRENT OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0024)
Paul Walmsleyd198b512010-12-21 15:30:54 -070093#define OMAP4_CM_IVA_DVFS_PERF_TESLA_OFFSET 0x0028
Paul Walmsleycdb54c42010-12-21 15:30:55 -070094#define OMAP4430_CM_IVA_DVFS_PERF_TESLA OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0028)
Paul Walmsleyd198b512010-12-21 15:30:54 -070095#define OMAP4_CM_IVA_DVFS_PERF_IVAHD_OFFSET 0x002c
Paul Walmsleycdb54c42010-12-21 15:30:55 -070096#define OMAP4430_CM_IVA_DVFS_PERF_IVAHD OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x002c)
Paul Walmsleyd198b512010-12-21 15:30:54 -070097#define OMAP4_CM_IVA_DVFS_PERF_ABE_OFFSET 0x0030
Paul Walmsleycdb54c42010-12-21 15:30:55 -070098#define OMAP4430_CM_IVA_DVFS_PERF_ABE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0030)
Paul Walmsleyd198b512010-12-21 15:30:54 -070099#define OMAP4_CM_IVA_DVFS_CURRENT_OFFSET 0x0038
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700100#define OMAP4430_CM_IVA_DVFS_CURRENT OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0038)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700101#define OMAP4_CM_CLKMODE_DPLL_PER_OFFSET 0x0040
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700102#define OMAP4430_CM_CLKMODE_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0040)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700103#define OMAP4_CM_IDLEST_DPLL_PER_OFFSET 0x0044
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700104#define OMAP4430_CM_IDLEST_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0044)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700105#define OMAP4_CM_AUTOIDLE_DPLL_PER_OFFSET 0x0048
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700106#define OMAP4430_CM_AUTOIDLE_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0048)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700107#define OMAP4_CM_CLKSEL_DPLL_PER_OFFSET 0x004c
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700108#define OMAP4430_CM_CLKSEL_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x004c)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700109#define OMAP4_CM_DIV_M2_DPLL_PER_OFFSET 0x0050
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700110#define OMAP4430_CM_DIV_M2_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0050)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700111#define OMAP4_CM_DIV_M3_DPLL_PER_OFFSET 0x0054
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700112#define OMAP4430_CM_DIV_M3_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0054)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700113#define OMAP4_CM_DIV_M4_DPLL_PER_OFFSET 0x0058
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700114#define OMAP4430_CM_DIV_M4_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0058)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700115#define OMAP4_CM_DIV_M5_DPLL_PER_OFFSET 0x005c
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700116#define OMAP4430_CM_DIV_M5_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x005c)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700117#define OMAP4_CM_DIV_M6_DPLL_PER_OFFSET 0x0060
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700118#define OMAP4430_CM_DIV_M6_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0060)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700119#define OMAP4_CM_DIV_M7_DPLL_PER_OFFSET 0x0064
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700120#define OMAP4430_CM_DIV_M7_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0064)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700121#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_PER_OFFSET 0x0068
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700122#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0068)
Benoit Coussonad98a182011-07-09 19:15:04 -0600123#define OMAP4_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET 0x006c
124#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x006c)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700125#define OMAP4_CM_CLKMODE_DPLL_USB_OFFSET 0x0080
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700126#define OMAP4430_CM_CLKMODE_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0080)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700127#define OMAP4_CM_IDLEST_DPLL_USB_OFFSET 0x0084
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700128#define OMAP4430_CM_IDLEST_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0084)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700129#define OMAP4_CM_AUTOIDLE_DPLL_USB_OFFSET 0x0088
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700130#define OMAP4430_CM_AUTOIDLE_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0088)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700131#define OMAP4_CM_CLKSEL_DPLL_USB_OFFSET 0x008c
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700132#define OMAP4430_CM_CLKSEL_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x008c)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700133#define OMAP4_CM_DIV_M2_DPLL_USB_OFFSET 0x0090
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700134#define OMAP4430_CM_DIV_M2_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0090)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700135#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_USB_OFFSET 0x00a8
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700136#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00a8)
Benoit Coussonad98a182011-07-09 19:15:04 -0600137#define OMAP4_CM_SSC_MODFREQDIV_DPLL_USB_OFFSET 0x00ac
138#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00ac)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700139#define OMAP4_CM_CLKDCOLDO_DPLL_USB_OFFSET 0x00b4
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700140#define OMAP4430_CM_CLKDCOLDO_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00b4)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700141#define OMAP4_CM_CLKMODE_DPLL_UNIPRO_OFFSET 0x00c0
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700142#define OMAP4430_CM_CLKMODE_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00c0)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700143#define OMAP4_CM_IDLEST_DPLL_UNIPRO_OFFSET 0x00c4
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700144#define OMAP4430_CM_IDLEST_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00c4)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700145#define OMAP4_CM_AUTOIDLE_DPLL_UNIPRO_OFFSET 0x00c8
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700146#define OMAP4430_CM_AUTOIDLE_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00c8)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700147#define OMAP4_CM_CLKSEL_DPLL_UNIPRO_OFFSET 0x00cc
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700148#define OMAP4430_CM_CLKSEL_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00cc)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700149#define OMAP4_CM_DIV_M2_DPLL_UNIPRO_OFFSET 0x00d0
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700150#define OMAP4430_CM_DIV_M2_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00d0)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700151#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_UNIPRO_OFFSET 0x00e8
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700152#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00e8)
Benoit Coussonad98a182011-07-09 19:15:04 -0600153#define OMAP4_CM_SSC_MODFREQDIV_DPLL_UNIPRO_OFFSET 0x00ec
154#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00ec)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700155
156/* CM2.ALWAYS_ON_CM2 register offsets */
157#define OMAP4_CM_ALWON_CLKSTCTRL_OFFSET 0x0000
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700158#define OMAP4430_CM_ALWON_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0000)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700159#define OMAP4_CM_ALWON_MDMINTC_CLKCTRL_OFFSET 0x0020
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700160#define OMAP4430_CM_ALWON_MDMINTC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0020)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700161#define OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET 0x0028
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700162#define OMAP4430_CM_ALWON_SR_MPU_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0028)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700163#define OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET 0x0030
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700164#define OMAP4430_CM_ALWON_SR_IVA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0030)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700165#define OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET 0x0038
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700166#define OMAP4430_CM_ALWON_SR_CORE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0038)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700167#define OMAP4_CM_ALWON_USBPHY_CLKCTRL_OFFSET 0x0040
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700168#define OMAP4430_CM_ALWON_USBPHY_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0040)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700169
170/* CM2.CORE_CM2 register offsets */
171#define OMAP4_CM_L3_1_CLKSTCTRL_OFFSET 0x0000
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700172#define OMAP4430_CM_L3_1_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0000)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700173#define OMAP4_CM_L3_1_DYNAMICDEP_OFFSET 0x0008
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700174#define OMAP4430_CM_L3_1_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0008)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700175#define OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET 0x0020
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700176#define OMAP4430_CM_L3_1_L3_1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0020)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700177#define OMAP4_CM_L3_2_CLKSTCTRL_OFFSET 0x0100
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700178#define OMAP4430_CM_L3_2_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0100)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700179#define OMAP4_CM_L3_2_DYNAMICDEP_OFFSET 0x0108
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700180#define OMAP4430_CM_L3_2_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0108)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700181#define OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET 0x0120
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700182#define OMAP4430_CM_L3_2_L3_2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0120)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700183#define OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET 0x0128
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700184#define OMAP4430_CM_L3_2_GPMC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0128)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700185#define OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET 0x0130
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700186#define OMAP4430_CM_L3_2_OCMC_RAM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0130)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700187#define OMAP4_CM_DUCATI_CLKSTCTRL_OFFSET 0x0200
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700188#define OMAP4430_CM_DUCATI_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0200)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700189#define OMAP4_CM_DUCATI_STATICDEP_OFFSET 0x0204
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700190#define OMAP4430_CM_DUCATI_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0204)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700191#define OMAP4_CM_DUCATI_DYNAMICDEP_OFFSET 0x0208
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700192#define OMAP4430_CM_DUCATI_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0208)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700193#define OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET 0x0220
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700194#define OMAP4430_CM_DUCATI_DUCATI_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0220)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700195#define OMAP4_CM_SDMA_CLKSTCTRL_OFFSET 0x0300
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700196#define OMAP4430_CM_SDMA_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0300)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700197#define OMAP4_CM_SDMA_STATICDEP_OFFSET 0x0304
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700198#define OMAP4430_CM_SDMA_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0304)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700199#define OMAP4_CM_SDMA_DYNAMICDEP_OFFSET 0x0308
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700200#define OMAP4430_CM_SDMA_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0308)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700201#define OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET 0x0320
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700202#define OMAP4430_CM_SDMA_SDMA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0320)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700203#define OMAP4_CM_MEMIF_CLKSTCTRL_OFFSET 0x0400
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700204#define OMAP4430_CM_MEMIF_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0400)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700205#define OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET 0x0420
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700206#define OMAP4430_CM_MEMIF_DMM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0420)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700207#define OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET 0x0428
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700208#define OMAP4430_CM_MEMIF_EMIF_FW_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0428)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700209#define OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET 0x0430
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700210#define OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0430)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700211#define OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET 0x0438
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700212#define OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0438)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700213#define OMAP4_CM_MEMIF_DLL_CLKCTRL_OFFSET 0x0440
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700214#define OMAP4430_CM_MEMIF_DLL_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0440)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700215#define OMAP4_CM_MEMIF_EMIF_H1_CLKCTRL_OFFSET 0x0450
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700216#define OMAP4430_CM_MEMIF_EMIF_H1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0450)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700217#define OMAP4_CM_MEMIF_EMIF_H2_CLKCTRL_OFFSET 0x0458
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700218#define OMAP4430_CM_MEMIF_EMIF_H2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0458)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700219#define OMAP4_CM_MEMIF_DLL_H_CLKCTRL_OFFSET 0x0460
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700220#define OMAP4430_CM_MEMIF_DLL_H_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0460)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700221#define OMAP4_CM_D2D_CLKSTCTRL_OFFSET 0x0500
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700222#define OMAP4430_CM_D2D_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0500)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700223#define OMAP4_CM_D2D_STATICDEP_OFFSET 0x0504
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700224#define OMAP4430_CM_D2D_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0504)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700225#define OMAP4_CM_D2D_DYNAMICDEP_OFFSET 0x0508
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700226#define OMAP4430_CM_D2D_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0508)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700227#define OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET 0x0520
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700228#define OMAP4430_CM_D2D_SAD2D_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0520)
Benoit Coussonad98a182011-07-09 19:15:04 -0600229#define OMAP4_CM_D2D_MODEM_ICR_CLKCTRL_OFFSET 0x0528
230#define OMAP4430_CM_D2D_MODEM_ICR_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0528)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700231#define OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET 0x0530
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700232#define OMAP4430_CM_D2D_SAD2D_FW_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0530)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700233#define OMAP4_CM_L4CFG_CLKSTCTRL_OFFSET 0x0600
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700234#define OMAP4430_CM_L4CFG_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0600)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700235#define OMAP4_CM_L4CFG_DYNAMICDEP_OFFSET 0x0608
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700236#define OMAP4430_CM_L4CFG_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0608)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700237#define OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET 0x0620
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700238#define OMAP4430_CM_L4CFG_L4_CFG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0620)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700239#define OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET 0x0628
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700240#define OMAP4430_CM_L4CFG_HW_SEM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0628)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700241#define OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET 0x0630
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700242#define OMAP4430_CM_L4CFG_MAILBOX_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0630)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700243#define OMAP4_CM_L4CFG_SAR_ROM_CLKCTRL_OFFSET 0x0638
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700244#define OMAP4430_CM_L4CFG_SAR_ROM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0638)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700245#define OMAP4_CM_L3INSTR_CLKSTCTRL_OFFSET 0x0700
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700246#define OMAP4430_CM_L3INSTR_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0700)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700247#define OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET 0x0720
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700248#define OMAP4430_CM_L3INSTR_L3_3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0720)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700249#define OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET 0x0728
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700250#define OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0728)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700251#define OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET 0x0740
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700252#define OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0740)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700253
254/* CM2.IVAHD_CM2 register offsets */
255#define OMAP4_CM_IVAHD_CLKSTCTRL_OFFSET 0x0000
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700256#define OMAP4430_CM_IVAHD_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_INST, 0x0000)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700257#define OMAP4_CM_IVAHD_STATICDEP_OFFSET 0x0004
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700258#define OMAP4430_CM_IVAHD_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_INST, 0x0004)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700259#define OMAP4_CM_IVAHD_DYNAMICDEP_OFFSET 0x0008
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700260#define OMAP4430_CM_IVAHD_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_INST, 0x0008)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700261#define OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET 0x0020
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700262#define OMAP4430_CM_IVAHD_IVAHD_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_INST, 0x0020)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700263#define OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET 0x0028
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700264#define OMAP4430_CM_IVAHD_SL2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_INST, 0x0028)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700265
266/* CM2.CAM_CM2 register offsets */
267#define OMAP4_CM_CAM_CLKSTCTRL_OFFSET 0x0000
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700268#define OMAP4430_CM_CAM_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_INST, 0x0000)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700269#define OMAP4_CM_CAM_STATICDEP_OFFSET 0x0004
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700270#define OMAP4430_CM_CAM_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_INST, 0x0004)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700271#define OMAP4_CM_CAM_DYNAMICDEP_OFFSET 0x0008
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700272#define OMAP4430_CM_CAM_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_INST, 0x0008)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700273#define OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET 0x0020
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700274#define OMAP4430_CM_CAM_ISS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_INST, 0x0020)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700275#define OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET 0x0028
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700276#define OMAP4430_CM_CAM_FDIF_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_INST, 0x0028)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700277
278/* CM2.DSS_CM2 register offsets */
279#define OMAP4_CM_DSS_CLKSTCTRL_OFFSET 0x0000
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700280#define OMAP4430_CM_DSS_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_INST, 0x0000)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700281#define OMAP4_CM_DSS_STATICDEP_OFFSET 0x0004
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700282#define OMAP4430_CM_DSS_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_INST, 0x0004)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700283#define OMAP4_CM_DSS_DYNAMICDEP_OFFSET 0x0008
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700284#define OMAP4430_CM_DSS_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_INST, 0x0008)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700285#define OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET 0x0020
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700286#define OMAP4430_CM_DSS_DSS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_INST, 0x0020)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700287#define OMAP4_CM_DSS_DEISS_CLKCTRL_OFFSET 0x0028
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700288#define OMAP4430_CM_DSS_DEISS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_INST, 0x0028)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700289
290/* CM2.GFX_CM2 register offsets */
291#define OMAP4_CM_GFX_CLKSTCTRL_OFFSET 0x0000
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700292#define OMAP4430_CM_GFX_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_INST, 0x0000)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700293#define OMAP4_CM_GFX_STATICDEP_OFFSET 0x0004
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700294#define OMAP4430_CM_GFX_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_INST, 0x0004)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700295#define OMAP4_CM_GFX_DYNAMICDEP_OFFSET 0x0008
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700296#define OMAP4430_CM_GFX_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_INST, 0x0008)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700297#define OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET 0x0020
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700298#define OMAP4430_CM_GFX_GFX_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_INST, 0x0020)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700299
300/* CM2.L3INIT_CM2 register offsets */
301#define OMAP4_CM_L3INIT_CLKSTCTRL_OFFSET 0x0000
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700302#define OMAP4430_CM_L3INIT_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0000)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700303#define OMAP4_CM_L3INIT_STATICDEP_OFFSET 0x0004
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700304#define OMAP4430_CM_L3INIT_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0004)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700305#define OMAP4_CM_L3INIT_DYNAMICDEP_OFFSET 0x0008
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700306#define OMAP4430_CM_L3INIT_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0008)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700307#define OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET 0x0028
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700308#define OMAP4430_CM_L3INIT_MMC1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0028)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700309#define OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET 0x0030
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700310#define OMAP4430_CM_L3INIT_MMC2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0030)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700311#define OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET 0x0038
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700312#define OMAP4430_CM_L3INIT_HSI_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0038)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700313#define OMAP4_CM_L3INIT_UNIPRO1_CLKCTRL_OFFSET 0x0040
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700314#define OMAP4430_CM_L3INIT_UNIPRO1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0040)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700315#define OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET 0x0058
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700316#define OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0058)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700317#define OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET 0x0060
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700318#define OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0060)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700319#define OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET 0x0068
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700320#define OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0068)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700321#define OMAP4_CM_L3INIT_P1500_CLKCTRL_OFFSET 0x0078
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700322#define OMAP4430_CM_L3INIT_P1500_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0078)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700323#define OMAP4_CM_L3INIT_EMAC_CLKCTRL_OFFSET 0x0080
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700324#define OMAP4430_CM_L3INIT_EMAC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0080)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700325#define OMAP4_CM_L3INIT_SATA_CLKCTRL_OFFSET 0x0088
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700326#define OMAP4430_CM_L3INIT_SATA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0088)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700327#define OMAP4_CM_L3INIT_TPPSS_CLKCTRL_OFFSET 0x0090
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700328#define OMAP4430_CM_L3INIT_TPPSS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0090)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700329#define OMAP4_CM_L3INIT_PCIESS_CLKCTRL_OFFSET 0x0098
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700330#define OMAP4430_CM_L3INIT_PCIESS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0098)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700331#define OMAP4_CM_L3INIT_CCPTX_CLKCTRL_OFFSET 0x00a8
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700332#define OMAP4430_CM_L3INIT_CCPTX_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x00a8)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700333#define OMAP4_CM_L3INIT_XHPI_CLKCTRL_OFFSET 0x00c0
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700334#define OMAP4430_CM_L3INIT_XHPI_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x00c0)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700335#define OMAP4_CM_L3INIT_MMC6_CLKCTRL_OFFSET 0x00c8
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700336#define OMAP4430_CM_L3INIT_MMC6_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x00c8)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700337#define OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET 0x00d0
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700338#define OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x00d0)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700339#define OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET 0x00e0
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700340#define OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x00e0)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700341
342/* CM2.L4PER_CM2 register offsets */
343#define OMAP4_CM_L4PER_CLKSTCTRL_OFFSET 0x0000
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700344#define OMAP4430_CM_L4PER_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0000)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700345#define OMAP4_CM_L4PER_DYNAMICDEP_OFFSET 0x0008
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700346#define OMAP4430_CM_L4PER_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0008)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700347#define OMAP4_CM_L4PER_ADC_CLKCTRL_OFFSET 0x0020
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700348#define OMAP4430_CM_L4PER_ADC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0020)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700349#define OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET 0x0028
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700350#define OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0028)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700351#define OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET 0x0030
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700352#define OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0030)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700353#define OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET 0x0038
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700354#define OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0038)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700355#define OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET 0x0040
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700356#define OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0040)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700357#define OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET 0x0048
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700358#define OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0048)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700359#define OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET 0x0050
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700360#define OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0050)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700361#define OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET 0x0058
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700362#define OMAP4430_CM_L4PER_ELM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0058)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700363#define OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET 0x0060
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700364#define OMAP4430_CM_L4PER_GPIO2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0060)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700365#define OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET 0x0068
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700366#define OMAP4430_CM_L4PER_GPIO3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0068)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700367#define OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET 0x0070
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700368#define OMAP4430_CM_L4PER_GPIO4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0070)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700369#define OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET 0x0078
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700370#define OMAP4430_CM_L4PER_GPIO5_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0078)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700371#define OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET 0x0080
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700372#define OMAP4430_CM_L4PER_GPIO6_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0080)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700373#define OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET 0x0088
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700374#define OMAP4430_CM_L4PER_HDQ1W_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0088)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700375#define OMAP4_CM_L4PER_HECC1_CLKCTRL_OFFSET 0x0090
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700376#define OMAP4430_CM_L4PER_HECC1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0090)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700377#define OMAP4_CM_L4PER_HECC2_CLKCTRL_OFFSET 0x0098
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700378#define OMAP4430_CM_L4PER_HECC2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0098)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700379#define OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET 0x00a0
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700380#define OMAP4430_CM_L4PER_I2C1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00a0)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700381#define OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET 0x00a8
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700382#define OMAP4430_CM_L4PER_I2C2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00a8)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700383#define OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET 0x00b0
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700384#define OMAP4430_CM_L4PER_I2C3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00b0)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700385#define OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET 0x00b8
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700386#define OMAP4430_CM_L4PER_I2C4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00b8)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700387#define OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET 0x00c0
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700388#define OMAP4430_CM_L4PER_L4PER_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00c0)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700389#define OMAP4_CM_L4PER_MCASP2_CLKCTRL_OFFSET 0x00d0
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700390#define OMAP4430_CM_L4PER_MCASP2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00d0)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700391#define OMAP4_CM_L4PER_MCASP3_CLKCTRL_OFFSET 0x00d8
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700392#define OMAP4430_CM_L4PER_MCASP3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00d8)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700393#define OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET 0x00e0
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700394#define OMAP4430_CM_L4PER_MCBSP4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00e0)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700395#define OMAP4_CM_L4PER_MGATE_CLKCTRL_OFFSET 0x00e8
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700396#define OMAP4430_CM_L4PER_MGATE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00e8)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700397#define OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET 0x00f0
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700398#define OMAP4430_CM_L4PER_MCSPI1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00f0)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700399#define OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET 0x00f8
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700400#define OMAP4430_CM_L4PER_MCSPI2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00f8)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700401#define OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET 0x0100
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700402#define OMAP4430_CM_L4PER_MCSPI3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0100)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700403#define OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET 0x0108
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700404#define OMAP4430_CM_L4PER_MCSPI4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0108)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700405#define OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET 0x0120
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700406#define OMAP4430_CM_L4PER_MMCSD3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0120)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700407#define OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET 0x0128
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700408#define OMAP4430_CM_L4PER_MMCSD4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0128)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700409#define OMAP4_CM_L4PER_MSPROHG_CLKCTRL_OFFSET 0x0130
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700410#define OMAP4430_CM_L4PER_MSPROHG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0130)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700411#define OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET 0x0138
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700412#define OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0138)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700413#define OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET 0x0140
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700414#define OMAP4430_CM_L4PER_UART1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0140)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700415#define OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET 0x0148
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700416#define OMAP4430_CM_L4PER_UART2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0148)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700417#define OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET 0x0150
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700418#define OMAP4430_CM_L4PER_UART3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0150)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700419#define OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET 0x0158
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700420#define OMAP4430_CM_L4PER_UART4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0158)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700421#define OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET 0x0160
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700422#define OMAP4430_CM_L4PER_MMCSD5_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0160)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700423#define OMAP4_CM_L4PER_I2C5_CLKCTRL_OFFSET 0x0168
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700424#define OMAP4430_CM_L4PER_I2C5_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0168)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700425#define OMAP4_CM_L4SEC_CLKSTCTRL_OFFSET 0x0180
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700426#define OMAP4430_CM_L4SEC_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0180)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700427#define OMAP4_CM_L4SEC_STATICDEP_OFFSET 0x0184
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700428#define OMAP4430_CM_L4SEC_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0184)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700429#define OMAP4_CM_L4SEC_DYNAMICDEP_OFFSET 0x0188
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700430#define OMAP4430_CM_L4SEC_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0188)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700431#define OMAP4_CM_L4SEC_AES1_CLKCTRL_OFFSET 0x01a0
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700432#define OMAP4430_CM_L4SEC_AES1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01a0)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700433#define OMAP4_CM_L4SEC_AES2_CLKCTRL_OFFSET 0x01a8
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700434#define OMAP4430_CM_L4SEC_AES2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01a8)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700435#define OMAP4_CM_L4SEC_DES3DES_CLKCTRL_OFFSET 0x01b0
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700436#define OMAP4430_CM_L4SEC_DES3DES_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01b0)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700437#define OMAP4_CM_L4SEC_PKAEIP29_CLKCTRL_OFFSET 0x01b8
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700438#define OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01b8)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700439#define OMAP4_CM_L4SEC_RNG_CLKCTRL_OFFSET 0x01c0
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700440#define OMAP4430_CM_L4SEC_RNG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01c0)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700441#define OMAP4_CM_L4SEC_SHA2MD51_CLKCTRL_OFFSET 0x01c8
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700442#define OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01c8)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700443#define OMAP4_CM_L4SEC_CRYPTODMA_CLKCTRL_OFFSET 0x01d8
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700444#define OMAP4430_CM_L4SEC_CRYPTODMA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01d8)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700445
446/* CM2.CEFUSE_CM2 register offsets */
447#define OMAP4_CM_CEFUSE_CLKSTCTRL_OFFSET 0x0000
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700448#define OMAP4430_CM_CEFUSE_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_INST, 0x0000)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700449#define OMAP4_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET 0x0020
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700450#define OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_INST, 0x0020)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700451
Paul Walmsley2ace8312010-12-21 21:05:14 -0700452/* Function prototypes */
453extern u32 omap4_cm2_read_inst_reg(s16 inst, u16 idx);
454extern void omap4_cm2_write_inst_reg(u32 val, s16 inst, u16 idx);
455extern u32 omap4_cm2_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
456
Paul Walmsleyd198b512010-12-21 15:30:54 -0700457#endif