Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 1 | /* |
Shannon Nelson | 43d6e36 | 2007-10-16 01:27:39 -0700 | [diff] [blame] | 2 | * Intel I/OAT DMA Linux driver |
Maciej Sosnowski | 211a22c | 2009-02-26 11:05:43 +0100 | [diff] [blame] | 3 | * Copyright(c) 2004 - 2009 Intel Corporation. |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify it |
Shannon Nelson | 43d6e36 | 2007-10-16 01:27:39 -0700 | [diff] [blame] | 6 | * under the terms and conditions of the GNU General Public License, |
| 7 | * version 2, as published by the Free Software Foundation. |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 8 | * |
| 9 | * This program is distributed in the hope that it will be useful, but WITHOUT |
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 12 | * more details. |
| 13 | * |
| 14 | * You should have received a copy of the GNU General Public License along with |
Shannon Nelson | 43d6e36 | 2007-10-16 01:27:39 -0700 | [diff] [blame] | 15 | * this program; if not, write to the Free Software Foundation, Inc., |
| 16 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 17 | * |
Shannon Nelson | 43d6e36 | 2007-10-16 01:27:39 -0700 | [diff] [blame] | 18 | * The full GNU General Public License is included in this distribution in |
| 19 | * the file called "COPYING". |
| 20 | * |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 21 | */ |
| 22 | |
| 23 | /* |
| 24 | * This driver supports an Intel I/OAT DMA engine, which does asynchronous |
| 25 | * copy operations. |
| 26 | */ |
| 27 | |
| 28 | #include <linux/init.h> |
| 29 | #include <linux/module.h> |
| 30 | #include <linux/pci.h> |
| 31 | #include <linux/interrupt.h> |
| 32 | #include <linux/dmaengine.h> |
| 33 | #include <linux/delay.h> |
David S. Miller | 6b00c92 | 2006-05-23 17:37:58 -0700 | [diff] [blame] | 34 | #include <linux/dma-mapping.h> |
Maciej Sosnowski | 09177e8 | 2008-07-22 10:07:33 -0700 | [diff] [blame] | 35 | #include <linux/workqueue.h> |
Venki Pallipadi | 3ad0b02 | 2008-10-22 16:34:52 -0700 | [diff] [blame] | 36 | #include <linux/i7300_idle.h> |
Dan Williams | 584ec22 | 2009-07-28 14:32:12 -0700 | [diff] [blame] | 37 | #include "dma.h" |
| 38 | #include "registers.h" |
| 39 | #include "hw.h" |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 40 | |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 41 | int ioat_pending_level = 4; |
Shannon Nelson | 7bb67c1 | 2007-11-14 16:59:51 -0800 | [diff] [blame] | 42 | module_param(ioat_pending_level, int, 0644); |
| 43 | MODULE_PARM_DESC(ioat_pending_level, |
| 44 | "high-water mark for pushing ioat descriptors (default: 4)"); |
| 45 | |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 46 | /* internal functions */ |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 47 | static void ioat1_cleanup(struct ioat_dma_chan *ioat); |
| 48 | static void ioat1_dma_start_null_desc(struct ioat_dma_chan *ioat); |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 49 | |
| 50 | /** |
| 51 | * ioat_dma_do_interrupt - handler used for single vector interrupt mode |
| 52 | * @irq: interrupt id |
| 53 | * @data: interrupt data |
| 54 | */ |
| 55 | static irqreturn_t ioat_dma_do_interrupt(int irq, void *data) |
| 56 | { |
| 57 | struct ioatdma_device *instance = data; |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 58 | struct ioat_chan_common *chan; |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 59 | unsigned long attnstatus; |
| 60 | int bit; |
| 61 | u8 intrctrl; |
| 62 | |
| 63 | intrctrl = readb(instance->reg_base + IOAT_INTRCTRL_OFFSET); |
| 64 | |
| 65 | if (!(intrctrl & IOAT_INTRCTRL_MASTER_INT_EN)) |
| 66 | return IRQ_NONE; |
| 67 | |
| 68 | if (!(intrctrl & IOAT_INTRCTRL_INT_STATUS)) { |
| 69 | writeb(intrctrl, instance->reg_base + IOAT_INTRCTRL_OFFSET); |
| 70 | return IRQ_NONE; |
| 71 | } |
| 72 | |
| 73 | attnstatus = readl(instance->reg_base + IOAT_ATTNSTATUS_OFFSET); |
| 74 | for_each_bit(bit, &attnstatus, BITS_PER_LONG) { |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 75 | chan = ioat_chan_by_index(instance, bit); |
| 76 | tasklet_schedule(&chan->cleanup_task); |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 77 | } |
| 78 | |
| 79 | writeb(intrctrl, instance->reg_base + IOAT_INTRCTRL_OFFSET); |
| 80 | return IRQ_HANDLED; |
| 81 | } |
| 82 | |
| 83 | /** |
| 84 | * ioat_dma_do_interrupt_msix - handler used for vector-per-channel interrupt mode |
| 85 | * @irq: interrupt id |
| 86 | * @data: interrupt data |
| 87 | */ |
| 88 | static irqreturn_t ioat_dma_do_interrupt_msix(int irq, void *data) |
| 89 | { |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 90 | struct ioat_chan_common *chan = data; |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 91 | |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 92 | tasklet_schedule(&chan->cleanup_task); |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 93 | |
| 94 | return IRQ_HANDLED; |
| 95 | } |
| 96 | |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 97 | static void ioat1_cleanup_tasklet(unsigned long data); |
| 98 | |
| 99 | /* common channel initialization */ |
| 100 | void ioat_init_channel(struct ioatdma_device *device, |
| 101 | struct ioat_chan_common *chan, int idx, |
| 102 | work_func_t work_fn, void (*tasklet)(unsigned long), |
| 103 | unsigned long tasklet_data) |
| 104 | { |
| 105 | struct dma_device *dma = &device->common; |
| 106 | |
| 107 | chan->device = device; |
| 108 | chan->reg_base = device->reg_base + (0x80 * (idx + 1)); |
| 109 | INIT_DELAYED_WORK(&chan->work, work_fn); |
| 110 | spin_lock_init(&chan->cleanup_lock); |
| 111 | chan->common.device = dma; |
| 112 | list_add_tail(&chan->common.device_node, &dma->channels); |
| 113 | device->idx[idx] = chan; |
| 114 | tasklet_init(&chan->cleanup_task, tasklet, tasklet_data); |
| 115 | tasklet_disable(&chan->cleanup_task); |
| 116 | } |
| 117 | |
| 118 | static void ioat1_reset_part2(struct work_struct *work); |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 119 | |
| 120 | /** |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 121 | * ioat1_dma_enumerate_channels - find and initialize the device's channels |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 122 | * @device: the device to be enumerated |
| 123 | */ |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 124 | static int ioat1_enumerate_channels(struct ioatdma_device *device) |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 125 | { |
| 126 | u8 xfercap_scale; |
| 127 | u32 xfercap; |
| 128 | int i; |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 129 | struct ioat_dma_chan *ioat; |
Dan Williams | e6c0b69 | 2009-09-08 17:29:44 -0700 | [diff] [blame] | 130 | struct device *dev = &device->pdev->dev; |
Dan Williams | f2427e2 | 2009-07-28 14:42:38 -0700 | [diff] [blame] | 131 | struct dma_device *dma = &device->common; |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 132 | |
Dan Williams | f2427e2 | 2009-07-28 14:42:38 -0700 | [diff] [blame] | 133 | INIT_LIST_HEAD(&dma->channels); |
| 134 | dma->chancnt = readb(device->reg_base + IOAT_CHANCNT_OFFSET); |
Chris Leech | e382881 | 2007-03-08 09:57:35 -0800 | [diff] [blame] | 135 | xfercap_scale = readb(device->reg_base + IOAT_XFERCAP_OFFSET); |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 136 | xfercap = (xfercap_scale == 0 ? -1 : (1UL << xfercap_scale)); |
Dan Williams | 6df9183 | 2009-09-08 12:00:55 -0700 | [diff] [blame] | 137 | dev_dbg(dev, "%s: xfercap = %d\n", __func__, xfercap); |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 138 | |
Venki Pallipadi | f371be6 | 2008-10-23 15:39:06 -0700 | [diff] [blame] | 139 | #ifdef CONFIG_I7300_IDLE_IOAT_CHANNEL |
Dan Williams | f2427e2 | 2009-07-28 14:42:38 -0700 | [diff] [blame] | 140 | if (i7300_idle_platform_probe(NULL, NULL, 1) == 0) |
| 141 | dma->chancnt--; |
Andy Henroid | 27471fd | 2008-10-09 11:45:22 -0700 | [diff] [blame] | 142 | #endif |
Dan Williams | f2427e2 | 2009-07-28 14:42:38 -0700 | [diff] [blame] | 143 | for (i = 0; i < dma->chancnt; i++) { |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 144 | ioat = devm_kzalloc(dev, sizeof(*ioat), GFP_KERNEL); |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 145 | if (!ioat) |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 146 | break; |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 147 | |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 148 | ioat_init_channel(device, &ioat->base, i, |
| 149 | ioat1_reset_part2, |
| 150 | ioat1_cleanup_tasklet, |
| 151 | (unsigned long) ioat); |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 152 | ioat->xfercap = xfercap; |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 153 | spin_lock_init(&ioat->desc_lock); |
| 154 | INIT_LIST_HEAD(&ioat->free_desc); |
| 155 | INIT_LIST_HEAD(&ioat->used_desc); |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 156 | } |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 157 | dma->chancnt = i; |
| 158 | return i; |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 159 | } |
| 160 | |
Shannon Nelson | 711924b | 2007-12-17 16:20:08 -0800 | [diff] [blame] | 161 | /** |
| 162 | * ioat_dma_memcpy_issue_pending - push potentially unrecognized appended |
| 163 | * descriptors to hw |
| 164 | * @chan: DMA channel handle |
| 165 | */ |
Dan Williams | bc3c702 | 2009-07-28 14:33:42 -0700 | [diff] [blame] | 166 | static inline void |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 167 | __ioat1_dma_memcpy_issue_pending(struct ioat_dma_chan *ioat) |
Shannon Nelson | 711924b | 2007-12-17 16:20:08 -0800 | [diff] [blame] | 168 | { |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 169 | void __iomem *reg_base = ioat->base.reg_base; |
| 170 | |
Dan Williams | 6df9183 | 2009-09-08 12:00:55 -0700 | [diff] [blame] | 171 | dev_dbg(to_dev(&ioat->base), "%s: pending: %d\n", |
| 172 | __func__, ioat->pending); |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 173 | ioat->pending = 0; |
| 174 | writeb(IOAT_CHANCMD_APPEND, reg_base + IOAT1_CHANCMD_OFFSET); |
Shannon Nelson | 711924b | 2007-12-17 16:20:08 -0800 | [diff] [blame] | 175 | } |
| 176 | |
| 177 | static void ioat1_dma_memcpy_issue_pending(struct dma_chan *chan) |
| 178 | { |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 179 | struct ioat_dma_chan *ioat = to_ioat_chan(chan); |
Shannon Nelson | 711924b | 2007-12-17 16:20:08 -0800 | [diff] [blame] | 180 | |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 181 | if (ioat->pending > 0) { |
| 182 | spin_lock_bh(&ioat->desc_lock); |
| 183 | __ioat1_dma_memcpy_issue_pending(ioat); |
| 184 | spin_unlock_bh(&ioat->desc_lock); |
Shannon Nelson | 711924b | 2007-12-17 16:20:08 -0800 | [diff] [blame] | 185 | } |
| 186 | } |
| 187 | |
Maciej Sosnowski | 09177e8 | 2008-07-22 10:07:33 -0700 | [diff] [blame] | 188 | /** |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 189 | * ioat1_reset_part2 - reinit the channel after a reset |
Maciej Sosnowski | 09177e8 | 2008-07-22 10:07:33 -0700 | [diff] [blame] | 190 | */ |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 191 | static void ioat1_reset_part2(struct work_struct *work) |
Maciej Sosnowski | 09177e8 | 2008-07-22 10:07:33 -0700 | [diff] [blame] | 192 | { |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 193 | struct ioat_chan_common *chan; |
| 194 | struct ioat_dma_chan *ioat; |
Maciej Sosnowski | 09177e8 | 2008-07-22 10:07:33 -0700 | [diff] [blame] | 195 | struct ioat_desc_sw *desc; |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 196 | int dmacount; |
| 197 | bool start_null = false; |
Maciej Sosnowski | 09177e8 | 2008-07-22 10:07:33 -0700 | [diff] [blame] | 198 | |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 199 | chan = container_of(work, struct ioat_chan_common, work.work); |
| 200 | ioat = container_of(chan, struct ioat_dma_chan, base); |
| 201 | spin_lock_bh(&chan->cleanup_lock); |
| 202 | spin_lock_bh(&ioat->desc_lock); |
Maciej Sosnowski | 09177e8 | 2008-07-22 10:07:33 -0700 | [diff] [blame] | 203 | |
Dan Williams | 4fb9b9e | 2009-09-08 12:01:04 -0700 | [diff] [blame^] | 204 | *chan->completion = 0; |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 205 | ioat->pending = 0; |
Maciej Sosnowski | 09177e8 | 2008-07-22 10:07:33 -0700 | [diff] [blame] | 206 | |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 207 | /* count the descriptors waiting */ |
| 208 | dmacount = 0; |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 209 | if (ioat->used_desc.prev) { |
| 210 | desc = to_ioat_desc(ioat->used_desc.prev); |
Maciej Sosnowski | 09177e8 | 2008-07-22 10:07:33 -0700 | [diff] [blame] | 211 | do { |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 212 | dmacount++; |
Maciej Sosnowski | 09177e8 | 2008-07-22 10:07:33 -0700 | [diff] [blame] | 213 | desc = to_ioat_desc(desc->node.next); |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 214 | } while (&desc->node != ioat->used_desc.next); |
Maciej Sosnowski | 09177e8 | 2008-07-22 10:07:33 -0700 | [diff] [blame] | 215 | } |
| 216 | |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 217 | if (dmacount) { |
| 218 | /* |
| 219 | * write the new starting descriptor address |
| 220 | * this puts channel engine into ARMED state |
| 221 | */ |
| 222 | desc = to_ioat_desc(ioat->used_desc.prev); |
Dan Williams | bc3c702 | 2009-07-28 14:33:42 -0700 | [diff] [blame] | 223 | writel(((u64) desc->txd.phys) & 0x00000000FFFFFFFF, |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 224 | chan->reg_base + IOAT1_CHAINADDR_OFFSET_LOW); |
Dan Williams | bc3c702 | 2009-07-28 14:33:42 -0700 | [diff] [blame] | 225 | writel(((u64) desc->txd.phys) >> 32, |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 226 | chan->reg_base + IOAT1_CHAINADDR_OFFSET_HIGH); |
Maciej Sosnowski | 09177e8 | 2008-07-22 10:07:33 -0700 | [diff] [blame] | 227 | |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 228 | writeb(IOAT_CHANCMD_START, chan->reg_base |
| 229 | + IOAT_CHANCMD_OFFSET(chan->device->version)); |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 230 | } else |
| 231 | start_null = true; |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 232 | spin_unlock_bh(&ioat->desc_lock); |
| 233 | spin_unlock_bh(&chan->cleanup_lock); |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 234 | |
| 235 | dev_err(to_dev(chan), |
| 236 | "chan%d reset - %d descs waiting, %d total desc\n", |
| 237 | chan_num(chan), dmacount, ioat->desccount); |
| 238 | |
| 239 | if (start_null) |
| 240 | ioat1_dma_start_null_desc(ioat); |
Maciej Sosnowski | 09177e8 | 2008-07-22 10:07:33 -0700 | [diff] [blame] | 241 | } |
| 242 | |
| 243 | /** |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 244 | * ioat1_reset_channel - restart a channel |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 245 | * @ioat: IOAT DMA channel handle |
Maciej Sosnowski | 09177e8 | 2008-07-22 10:07:33 -0700 | [diff] [blame] | 246 | */ |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 247 | static void ioat1_reset_channel(struct ioat_dma_chan *ioat) |
Maciej Sosnowski | 09177e8 | 2008-07-22 10:07:33 -0700 | [diff] [blame] | 248 | { |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 249 | struct ioat_chan_common *chan = &ioat->base; |
| 250 | void __iomem *reg_base = chan->reg_base; |
Maciej Sosnowski | 09177e8 | 2008-07-22 10:07:33 -0700 | [diff] [blame] | 251 | u32 chansts, chanerr; |
| 252 | |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 253 | if (!ioat->used_desc.prev) |
Maciej Sosnowski | 09177e8 | 2008-07-22 10:07:33 -0700 | [diff] [blame] | 254 | return; |
| 255 | |
Dan Williams | 6df9183 | 2009-09-08 12:00:55 -0700 | [diff] [blame] | 256 | dev_dbg(to_dev(chan), "%s\n", __func__); |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 257 | chanerr = readl(reg_base + IOAT_CHANERR_OFFSET); |
Dan Williams | 4fb9b9e | 2009-09-08 12:01:04 -0700 | [diff] [blame^] | 258 | chansts = *chan->completion & IOAT_CHANSTS_DMA_TRANSFER_STATUS; |
Maciej Sosnowski | 09177e8 | 2008-07-22 10:07:33 -0700 | [diff] [blame] | 259 | if (chanerr) { |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 260 | dev_err(to_dev(chan), |
Maciej Sosnowski | 09177e8 | 2008-07-22 10:07:33 -0700 | [diff] [blame] | 261 | "chan%d, CHANSTS = 0x%08x CHANERR = 0x%04x, clearing\n", |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 262 | chan_num(chan), chansts, chanerr); |
| 263 | writel(chanerr, reg_base + IOAT_CHANERR_OFFSET); |
Maciej Sosnowski | 09177e8 | 2008-07-22 10:07:33 -0700 | [diff] [blame] | 264 | } |
| 265 | |
| 266 | /* |
| 267 | * whack it upside the head with a reset |
| 268 | * and wait for things to settle out. |
| 269 | * force the pending count to a really big negative |
| 270 | * to make sure no one forces an issue_pending |
| 271 | * while we're waiting. |
| 272 | */ |
| 273 | |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 274 | spin_lock_bh(&ioat->desc_lock); |
| 275 | ioat->pending = INT_MIN; |
Maciej Sosnowski | 09177e8 | 2008-07-22 10:07:33 -0700 | [diff] [blame] | 276 | writeb(IOAT_CHANCMD_RESET, |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 277 | reg_base + IOAT_CHANCMD_OFFSET(chan->device->version)); |
| 278 | spin_unlock_bh(&ioat->desc_lock); |
Maciej Sosnowski | 09177e8 | 2008-07-22 10:07:33 -0700 | [diff] [blame] | 279 | |
| 280 | /* schedule the 2nd half instead of sleeping a long time */ |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 281 | schedule_delayed_work(&chan->work, RESET_DELAY); |
Maciej Sosnowski | 09177e8 | 2008-07-22 10:07:33 -0700 | [diff] [blame] | 282 | } |
| 283 | |
| 284 | /** |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 285 | * ioat1_chan_watchdog - watch for stuck channels |
Maciej Sosnowski | 09177e8 | 2008-07-22 10:07:33 -0700 | [diff] [blame] | 286 | */ |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 287 | static void ioat1_chan_watchdog(struct work_struct *work) |
Maciej Sosnowski | 09177e8 | 2008-07-22 10:07:33 -0700 | [diff] [blame] | 288 | { |
| 289 | struct ioatdma_device *device = |
| 290 | container_of(work, struct ioatdma_device, work.work); |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 291 | struct ioat_dma_chan *ioat; |
| 292 | struct ioat_chan_common *chan; |
Maciej Sosnowski | 09177e8 | 2008-07-22 10:07:33 -0700 | [diff] [blame] | 293 | int i; |
Dan Williams | 4fb9b9e | 2009-09-08 12:01:04 -0700 | [diff] [blame^] | 294 | u64 completion; |
| 295 | u32 completion_low; |
Maciej Sosnowski | 09177e8 | 2008-07-22 10:07:33 -0700 | [diff] [blame] | 296 | unsigned long compl_desc_addr_hw; |
| 297 | |
| 298 | for (i = 0; i < device->common.chancnt; i++) { |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 299 | chan = ioat_chan_by_index(device, i); |
| 300 | ioat = container_of(chan, struct ioat_dma_chan, base); |
Maciej Sosnowski | 09177e8 | 2008-07-22 10:07:33 -0700 | [diff] [blame] | 301 | |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 302 | if (/* have we started processing anything yet */ |
| 303 | chan->last_completion |
| 304 | /* have we completed any since last watchdog cycle? */ |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 305 | && (chan->last_completion == chan->watchdog_completion) |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 306 | /* has TCP stuck on one cookie since last watchdog? */ |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 307 | && (chan->watchdog_tcp_cookie == chan->watchdog_last_tcp_cookie) |
| 308 | && (chan->watchdog_tcp_cookie != chan->completed_cookie) |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 309 | /* is there something in the chain to be processed? */ |
| 310 | /* CB1 chain always has at least the last one processed */ |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 311 | && (ioat->used_desc.prev != ioat->used_desc.next) |
| 312 | && ioat->pending == 0) { |
Maciej Sosnowski | 09177e8 | 2008-07-22 10:07:33 -0700 | [diff] [blame] | 313 | |
| 314 | /* |
| 315 | * check CHANSTS register for completed |
| 316 | * descriptor address. |
| 317 | * if it is different than completion writeback, |
| 318 | * it is not zero |
| 319 | * and it has changed since the last watchdog |
| 320 | * we can assume that channel |
| 321 | * is still working correctly |
| 322 | * and the problem is in completion writeback. |
| 323 | * update completion writeback |
| 324 | * with actual CHANSTS value |
| 325 | * else |
| 326 | * try resetting the channel |
| 327 | */ |
| 328 | |
Dan Williams | 4fb9b9e | 2009-09-08 12:01:04 -0700 | [diff] [blame^] | 329 | /* we need to read the low address first as this |
| 330 | * causes the chipset to latch the upper bits |
| 331 | * for the subsequent read |
| 332 | */ |
| 333 | completion_low = readl(chan->reg_base + |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 334 | IOAT_CHANSTS_OFFSET_LOW(chan->device->version)); |
Dan Williams | 4fb9b9e | 2009-09-08 12:01:04 -0700 | [diff] [blame^] | 335 | completion = readl(chan->reg_base + |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 336 | IOAT_CHANSTS_OFFSET_HIGH(chan->device->version)); |
Dan Williams | 4fb9b9e | 2009-09-08 12:01:04 -0700 | [diff] [blame^] | 337 | completion <<= 32; |
| 338 | completion |= completion_low; |
| 339 | compl_desc_addr_hw = completion & |
| 340 | IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR; |
Maciej Sosnowski | 09177e8 | 2008-07-22 10:07:33 -0700 | [diff] [blame] | 341 | |
| 342 | if ((compl_desc_addr_hw != 0) |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 343 | && (compl_desc_addr_hw != chan->watchdog_completion) |
| 344 | && (compl_desc_addr_hw != chan->last_compl_desc_addr_hw)) { |
| 345 | chan->last_compl_desc_addr_hw = compl_desc_addr_hw; |
Dan Williams | 4fb9b9e | 2009-09-08 12:01:04 -0700 | [diff] [blame^] | 346 | *chan->completion = completion; |
Maciej Sosnowski | 09177e8 | 2008-07-22 10:07:33 -0700 | [diff] [blame] | 347 | } else { |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 348 | ioat1_reset_channel(ioat); |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 349 | chan->watchdog_completion = 0; |
| 350 | chan->last_compl_desc_addr_hw = 0; |
Maciej Sosnowski | 09177e8 | 2008-07-22 10:07:33 -0700 | [diff] [blame] | 351 | } |
Maciej Sosnowski | 09177e8 | 2008-07-22 10:07:33 -0700 | [diff] [blame] | 352 | } else { |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 353 | chan->last_compl_desc_addr_hw = 0; |
| 354 | chan->watchdog_completion = chan->last_completion; |
Maciej Sosnowski | 09177e8 | 2008-07-22 10:07:33 -0700 | [diff] [blame] | 355 | } |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 356 | |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 357 | chan->watchdog_last_tcp_cookie = chan->watchdog_tcp_cookie; |
Maciej Sosnowski | 09177e8 | 2008-07-22 10:07:33 -0700 | [diff] [blame] | 358 | } |
| 359 | |
| 360 | schedule_delayed_work(&device->work, WATCHDOG_DELAY); |
| 361 | } |
| 362 | |
Shannon Nelson | 7bb67c1 | 2007-11-14 16:59:51 -0800 | [diff] [blame] | 363 | static dma_cookie_t ioat1_tx_submit(struct dma_async_tx_descriptor *tx) |
Dan Williams | 7405f74 | 2007-01-02 11:10:43 -0700 | [diff] [blame] | 364 | { |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 365 | struct dma_chan *c = tx->chan; |
| 366 | struct ioat_dma_chan *ioat = to_ioat_chan(c); |
Dan Williams | a0587bc | 2009-07-28 14:44:04 -0700 | [diff] [blame] | 367 | struct ioat_desc_sw *desc = tx_to_ioat_desc(tx); |
| 368 | struct ioat_desc_sw *first; |
| 369 | struct ioat_desc_sw *chain_tail; |
Dan Williams | 7405f74 | 2007-01-02 11:10:43 -0700 | [diff] [blame] | 370 | dma_cookie_t cookie; |
Shannon Nelson | 7f2b291 | 2007-10-18 03:07:14 -0700 | [diff] [blame] | 371 | |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 372 | spin_lock_bh(&ioat->desc_lock); |
Dan Williams | 7405f74 | 2007-01-02 11:10:43 -0700 | [diff] [blame] | 373 | /* cookie incr and addition to used_list must be atomic */ |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 374 | cookie = c->cookie; |
Dan Williams | 7405f74 | 2007-01-02 11:10:43 -0700 | [diff] [blame] | 375 | cookie++; |
| 376 | if (cookie < 0) |
| 377 | cookie = 1; |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 378 | c->cookie = cookie; |
| 379 | tx->cookie = cookie; |
Dan Williams | 6df9183 | 2009-09-08 12:00:55 -0700 | [diff] [blame] | 380 | dev_dbg(to_dev(&ioat->base), "%s: cookie: %d\n", __func__, cookie); |
Dan Williams | 7405f74 | 2007-01-02 11:10:43 -0700 | [diff] [blame] | 381 | |
| 382 | /* write address into NextDescriptor field of last desc in chain */ |
Dan Williams | a0587bc | 2009-07-28 14:44:04 -0700 | [diff] [blame] | 383 | first = to_ioat_desc(tx->tx_list.next); |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 384 | chain_tail = to_ioat_desc(ioat->used_desc.prev); |
Dan Williams | a0587bc | 2009-07-28 14:44:04 -0700 | [diff] [blame] | 385 | /* make descriptor updates globally visible before chaining */ |
| 386 | wmb(); |
| 387 | chain_tail->hw->next = first->txd.phys; |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 388 | list_splice_tail_init(&tx->tx_list, &ioat->used_desc); |
Dan Williams | 6df9183 | 2009-09-08 12:00:55 -0700 | [diff] [blame] | 389 | dump_desc_dbg(ioat, chain_tail); |
| 390 | dump_desc_dbg(ioat, first); |
Dan Williams | 7405f74 | 2007-01-02 11:10:43 -0700 | [diff] [blame] | 391 | |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 392 | ioat->pending += desc->tx_cnt; |
| 393 | if (ioat->pending >= ioat_pending_level) |
| 394 | __ioat1_dma_memcpy_issue_pending(ioat); |
| 395 | spin_unlock_bh(&ioat->desc_lock); |
Dan Williams | 7405f74 | 2007-01-02 11:10:43 -0700 | [diff] [blame] | 396 | |
Dan Williams | 7405f74 | 2007-01-02 11:10:43 -0700 | [diff] [blame] | 397 | return cookie; |
| 398 | } |
| 399 | |
Shannon Nelson | 7bb67c1 | 2007-11-14 16:59:51 -0800 | [diff] [blame] | 400 | /** |
| 401 | * ioat_dma_alloc_descriptor - allocate and return a sw and hw descriptor pair |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 402 | * @ioat: the channel supplying the memory pool for the descriptors |
Shannon Nelson | 7bb67c1 | 2007-11-14 16:59:51 -0800 | [diff] [blame] | 403 | * @flags: allocation flags |
| 404 | */ |
Dan Williams | bc3c702 | 2009-07-28 14:33:42 -0700 | [diff] [blame] | 405 | static struct ioat_desc_sw * |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 406 | ioat_dma_alloc_descriptor(struct ioat_dma_chan *ioat, gfp_t flags) |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 407 | { |
| 408 | struct ioat_dma_descriptor *desc; |
| 409 | struct ioat_desc_sw *desc_sw; |
Shannon Nelson | 8ab8956 | 2007-10-16 01:27:39 -0700 | [diff] [blame] | 410 | struct ioatdma_device *ioatdma_device; |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 411 | dma_addr_t phys; |
| 412 | |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 413 | ioatdma_device = ioat->base.device; |
Shannon Nelson | 8ab8956 | 2007-10-16 01:27:39 -0700 | [diff] [blame] | 414 | desc = pci_pool_alloc(ioatdma_device->dma_pool, flags, &phys); |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 415 | if (unlikely(!desc)) |
| 416 | return NULL; |
| 417 | |
| 418 | desc_sw = kzalloc(sizeof(*desc_sw), flags); |
| 419 | if (unlikely(!desc_sw)) { |
Shannon Nelson | 8ab8956 | 2007-10-16 01:27:39 -0700 | [diff] [blame] | 420 | pci_pool_free(ioatdma_device->dma_pool, desc, phys); |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 421 | return NULL; |
| 422 | } |
| 423 | |
| 424 | memset(desc, 0, sizeof(*desc)); |
Shannon Nelson | 7bb67c1 | 2007-11-14 16:59:51 -0800 | [diff] [blame] | 425 | |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 426 | dma_async_tx_descriptor_init(&desc_sw->txd, &ioat->base.common); |
| 427 | desc_sw->txd.tx_submit = ioat1_tx_submit; |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 428 | desc_sw->hw = desc; |
Dan Williams | bc3c702 | 2009-07-28 14:33:42 -0700 | [diff] [blame] | 429 | desc_sw->txd.phys = phys; |
Dan Williams | 6df9183 | 2009-09-08 12:00:55 -0700 | [diff] [blame] | 430 | set_desc_id(desc_sw, -1); |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 431 | |
| 432 | return desc_sw; |
| 433 | } |
| 434 | |
Shannon Nelson | 7bb67c1 | 2007-11-14 16:59:51 -0800 | [diff] [blame] | 435 | static int ioat_initial_desc_count = 256; |
| 436 | module_param(ioat_initial_desc_count, int, 0644); |
| 437 | MODULE_PARM_DESC(ioat_initial_desc_count, |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 438 | "ioat1: initial descriptors per channel (default: 256)"); |
Shannon Nelson | 7bb67c1 | 2007-11-14 16:59:51 -0800 | [diff] [blame] | 439 | /** |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 440 | * ioat1_dma_alloc_chan_resources - returns the number of allocated descriptors |
Shannon Nelson | 7bb67c1 | 2007-11-14 16:59:51 -0800 | [diff] [blame] | 441 | * @chan: the channel to be filled out |
| 442 | */ |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 443 | static int ioat1_dma_alloc_chan_resources(struct dma_chan *c) |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 444 | { |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 445 | struct ioat_dma_chan *ioat = to_ioat_chan(c); |
| 446 | struct ioat_chan_common *chan = &ioat->base; |
Shannon Nelson | 711924b | 2007-12-17 16:20:08 -0800 | [diff] [blame] | 447 | struct ioat_desc_sw *desc; |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 448 | u16 chanctrl; |
| 449 | u32 chanerr; |
| 450 | int i; |
| 451 | LIST_HEAD(tmp_list); |
| 452 | |
Shannon Nelson | e422397 | 2007-08-24 23:02:53 -0700 | [diff] [blame] | 453 | /* have we already been set up? */ |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 454 | if (!list_empty(&ioat->free_desc)) |
| 455 | return ioat->desccount; |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 456 | |
Shannon Nelson | 43d6e36 | 2007-10-16 01:27:39 -0700 | [diff] [blame] | 457 | /* Setup register to interrupt and write completion status on error */ |
Shannon Nelson | e422397 | 2007-08-24 23:02:53 -0700 | [diff] [blame] | 458 | chanctrl = IOAT_CHANCTRL_ERR_INT_EN | |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 459 | IOAT_CHANCTRL_ANY_ERR_ABORT_EN | |
| 460 | IOAT_CHANCTRL_ERR_COMPLETION_EN; |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 461 | writew(chanctrl, chan->reg_base + IOAT_CHANCTRL_OFFSET); |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 462 | |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 463 | chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET); |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 464 | if (chanerr) { |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 465 | dev_err(to_dev(chan), "CHANERR = %x, clearing\n", chanerr); |
| 466 | writel(chanerr, chan->reg_base + IOAT_CHANERR_OFFSET); |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 467 | } |
| 468 | |
| 469 | /* Allocate descriptors */ |
Shannon Nelson | 7bb67c1 | 2007-11-14 16:59:51 -0800 | [diff] [blame] | 470 | for (i = 0; i < ioat_initial_desc_count; i++) { |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 471 | desc = ioat_dma_alloc_descriptor(ioat, GFP_KERNEL); |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 472 | if (!desc) { |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 473 | dev_err(to_dev(chan), "Only %d initial descriptors\n", i); |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 474 | break; |
| 475 | } |
Dan Williams | 6df9183 | 2009-09-08 12:00:55 -0700 | [diff] [blame] | 476 | set_desc_id(desc, i); |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 477 | list_add_tail(&desc->node, &tmp_list); |
| 478 | } |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 479 | spin_lock_bh(&ioat->desc_lock); |
| 480 | ioat->desccount = i; |
| 481 | list_splice(&tmp_list, &ioat->free_desc); |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 482 | spin_unlock_bh(&ioat->desc_lock); |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 483 | |
| 484 | /* allocate a completion writeback area */ |
| 485 | /* doing 2 32bit writes to mmio since 1 64b write doesn't work */ |
Dan Williams | 4fb9b9e | 2009-09-08 12:01:04 -0700 | [diff] [blame^] | 486 | chan->completion = pci_pool_alloc(chan->device->completion_pool, |
| 487 | GFP_KERNEL, &chan->completion_dma); |
| 488 | memset(chan->completion, 0, sizeof(*chan->completion)); |
| 489 | writel(((u64) chan->completion_dma) & 0x00000000FFFFFFFF, |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 490 | chan->reg_base + IOAT_CHANCMP_OFFSET_LOW); |
Dan Williams | 4fb9b9e | 2009-09-08 12:01:04 -0700 | [diff] [blame^] | 491 | writel(((u64) chan->completion_dma) >> 32, |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 492 | chan->reg_base + IOAT_CHANCMP_OFFSET_HIGH); |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 493 | |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 494 | tasklet_enable(&chan->cleanup_task); |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 495 | ioat1_dma_start_null_desc(ioat); /* give chain to dma device */ |
Dan Williams | 6df9183 | 2009-09-08 12:00:55 -0700 | [diff] [blame] | 496 | dev_dbg(to_dev(chan), "%s: allocated %d descriptors\n", |
| 497 | __func__, ioat->desccount); |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 498 | return ioat->desccount; |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 499 | } |
| 500 | |
Shannon Nelson | 7bb67c1 | 2007-11-14 16:59:51 -0800 | [diff] [blame] | 501 | /** |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 502 | * ioat1_dma_free_chan_resources - release all the descriptors |
Shannon Nelson | 7bb67c1 | 2007-11-14 16:59:51 -0800 | [diff] [blame] | 503 | * @chan: the channel to be cleaned |
| 504 | */ |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 505 | static void ioat1_dma_free_chan_resources(struct dma_chan *c) |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 506 | { |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 507 | struct ioat_dma_chan *ioat = to_ioat_chan(c); |
| 508 | struct ioat_chan_common *chan = &ioat->base; |
| 509 | struct ioatdma_device *ioatdma_device = chan->device; |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 510 | struct ioat_desc_sw *desc, *_desc; |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 511 | int in_use_descs = 0; |
| 512 | |
Maciej Sosnowski | c3d4f44 | 2008-11-07 01:45:52 +0000 | [diff] [blame] | 513 | /* Before freeing channel resources first check |
| 514 | * if they have been previously allocated for this channel. |
| 515 | */ |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 516 | if (ioat->desccount == 0) |
Maciej Sosnowski | c3d4f44 | 2008-11-07 01:45:52 +0000 | [diff] [blame] | 517 | return; |
| 518 | |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 519 | tasklet_disable(&chan->cleanup_task); |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 520 | ioat1_cleanup(ioat); |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 521 | |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 522 | /* Delay 100ms after reset to allow internal DMA logic to quiesce |
| 523 | * before removing DMA descriptor resources. |
| 524 | */ |
Shannon Nelson | 7bb67c1 | 2007-11-14 16:59:51 -0800 | [diff] [blame] | 525 | writeb(IOAT_CHANCMD_RESET, |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 526 | chan->reg_base + IOAT_CHANCMD_OFFSET(chan->device->version)); |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 527 | mdelay(100); |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 528 | |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 529 | spin_lock_bh(&ioat->desc_lock); |
Dan Williams | 6df9183 | 2009-09-08 12:00:55 -0700 | [diff] [blame] | 530 | list_for_each_entry_safe(desc, _desc, &ioat->used_desc, node) { |
| 531 | dev_dbg(to_dev(chan), "%s: freeing %d from used list\n", |
| 532 | __func__, desc_id(desc)); |
| 533 | dump_desc_dbg(ioat, desc); |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 534 | in_use_descs++; |
| 535 | list_del(&desc->node); |
Shannon Nelson | 8ab8956 | 2007-10-16 01:27:39 -0700 | [diff] [blame] | 536 | pci_pool_free(ioatdma_device->dma_pool, desc->hw, |
Dan Williams | bc3c702 | 2009-07-28 14:33:42 -0700 | [diff] [blame] | 537 | desc->txd.phys); |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 538 | kfree(desc); |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 539 | } |
| 540 | list_for_each_entry_safe(desc, _desc, |
| 541 | &ioat->free_desc, node) { |
| 542 | list_del(&desc->node); |
| 543 | pci_pool_free(ioatdma_device->dma_pool, desc->hw, |
| 544 | desc->txd.phys); |
| 545 | kfree(desc); |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 546 | } |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 547 | spin_unlock_bh(&ioat->desc_lock); |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 548 | |
Shannon Nelson | 8ab8956 | 2007-10-16 01:27:39 -0700 | [diff] [blame] | 549 | pci_pool_free(ioatdma_device->completion_pool, |
Dan Williams | 4fb9b9e | 2009-09-08 12:01:04 -0700 | [diff] [blame^] | 550 | chan->completion, |
| 551 | chan->completion_dma); |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 552 | |
| 553 | /* one is ok since we left it on there on purpose */ |
| 554 | if (in_use_descs > 1) |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 555 | dev_err(to_dev(chan), "Freeing %d in use descriptors!\n", |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 556 | in_use_descs - 1); |
| 557 | |
Dan Williams | 4fb9b9e | 2009-09-08 12:01:04 -0700 | [diff] [blame^] | 558 | chan->last_completion = 0; |
| 559 | chan->completion_dma = 0; |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 560 | chan->watchdog_completion = 0; |
| 561 | chan->last_compl_desc_addr_hw = 0; |
| 562 | chan->watchdog_tcp_cookie = chan->watchdog_last_tcp_cookie = 0; |
| 563 | ioat->pending = 0; |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 564 | ioat->desccount = 0; |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 565 | } |
Shannon Nelson | 7f2b291 | 2007-10-18 03:07:14 -0700 | [diff] [blame] | 566 | |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 567 | /** |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 568 | * ioat1_dma_get_next_descriptor - return the next available descriptor |
| 569 | * @ioat: IOAT DMA channel handle |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 570 | * |
| 571 | * Gets the next descriptor from the chain, and must be called with the |
| 572 | * channel's desc_lock held. Allocates more descriptors if the channel |
| 573 | * has run out. |
| 574 | */ |
Shannon Nelson | 7f2b291 | 2007-10-18 03:07:14 -0700 | [diff] [blame] | 575 | static struct ioat_desc_sw * |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 576 | ioat1_dma_get_next_descriptor(struct ioat_dma_chan *ioat) |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 577 | { |
Shannon Nelson | 711924b | 2007-12-17 16:20:08 -0800 | [diff] [blame] | 578 | struct ioat_desc_sw *new; |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 579 | |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 580 | if (!list_empty(&ioat->free_desc)) { |
| 581 | new = to_ioat_desc(ioat->free_desc.next); |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 582 | list_del(&new->node); |
| 583 | } else { |
| 584 | /* try to get another desc */ |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 585 | new = ioat_dma_alloc_descriptor(ioat, GFP_ATOMIC); |
Shannon Nelson | 711924b | 2007-12-17 16:20:08 -0800 | [diff] [blame] | 586 | if (!new) { |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 587 | dev_err(to_dev(&ioat->base), "alloc failed\n"); |
Shannon Nelson | 711924b | 2007-12-17 16:20:08 -0800 | [diff] [blame] | 588 | return NULL; |
| 589 | } |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 590 | } |
Dan Williams | 6df9183 | 2009-09-08 12:00:55 -0700 | [diff] [blame] | 591 | dev_dbg(to_dev(&ioat->base), "%s: allocated: %d\n", |
| 592 | __func__, desc_id(new)); |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 593 | prefetch(new->hw); |
| 594 | return new; |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 595 | } |
| 596 | |
Dan Williams | bc3c702 | 2009-07-28 14:33:42 -0700 | [diff] [blame] | 597 | static struct dma_async_tx_descriptor * |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 598 | ioat1_dma_prep_memcpy(struct dma_chan *c, dma_addr_t dma_dest, |
Dan Williams | bc3c702 | 2009-07-28 14:33:42 -0700 | [diff] [blame] | 599 | dma_addr_t dma_src, size_t len, unsigned long flags) |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 600 | { |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 601 | struct ioat_dma_chan *ioat = to_ioat_chan(c); |
Dan Williams | a0587bc | 2009-07-28 14:44:04 -0700 | [diff] [blame] | 602 | struct ioat_desc_sw *desc; |
| 603 | size_t copy; |
| 604 | LIST_HEAD(chain); |
| 605 | dma_addr_t src = dma_src; |
| 606 | dma_addr_t dest = dma_dest; |
| 607 | size_t total_len = len; |
| 608 | struct ioat_dma_descriptor *hw = NULL; |
| 609 | int tx_cnt = 0; |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 610 | |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 611 | spin_lock_bh(&ioat->desc_lock); |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 612 | desc = ioat1_dma_get_next_descriptor(ioat); |
Dan Williams | a0587bc | 2009-07-28 14:44:04 -0700 | [diff] [blame] | 613 | do { |
| 614 | if (!desc) |
| 615 | break; |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 616 | |
Dan Williams | a0587bc | 2009-07-28 14:44:04 -0700 | [diff] [blame] | 617 | tx_cnt++; |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 618 | copy = min_t(size_t, len, ioat->xfercap); |
Dan Williams | a0587bc | 2009-07-28 14:44:04 -0700 | [diff] [blame] | 619 | |
| 620 | hw = desc->hw; |
| 621 | hw->size = copy; |
| 622 | hw->ctl = 0; |
| 623 | hw->src_addr = src; |
| 624 | hw->dst_addr = dest; |
| 625 | |
| 626 | list_add_tail(&desc->node, &chain); |
| 627 | |
| 628 | len -= copy; |
| 629 | dest += copy; |
| 630 | src += copy; |
| 631 | if (len) { |
| 632 | struct ioat_desc_sw *next; |
| 633 | |
| 634 | async_tx_ack(&desc->txd); |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 635 | next = ioat1_dma_get_next_descriptor(ioat); |
Dan Williams | a0587bc | 2009-07-28 14:44:04 -0700 | [diff] [blame] | 636 | hw->next = next ? next->txd.phys : 0; |
Dan Williams | 6df9183 | 2009-09-08 12:00:55 -0700 | [diff] [blame] | 637 | dump_desc_dbg(ioat, desc); |
Dan Williams | a0587bc | 2009-07-28 14:44:04 -0700 | [diff] [blame] | 638 | desc = next; |
| 639 | } else |
| 640 | hw->next = 0; |
| 641 | } while (len); |
| 642 | |
| 643 | if (!desc) { |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 644 | struct ioat_chan_common *chan = &ioat->base; |
| 645 | |
| 646 | dev_err(to_dev(chan), |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 647 | "chan%d - get_next_desc failed\n", chan_num(chan)); |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 648 | list_splice(&chain, &ioat->free_desc); |
| 649 | spin_unlock_bh(&ioat->desc_lock); |
Shannon Nelson | 711924b | 2007-12-17 16:20:08 -0800 | [diff] [blame] | 650 | return NULL; |
Maciej Sosnowski | 09177e8 | 2008-07-22 10:07:33 -0700 | [diff] [blame] | 651 | } |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 652 | spin_unlock_bh(&ioat->desc_lock); |
Dan Williams | a0587bc | 2009-07-28 14:44:04 -0700 | [diff] [blame] | 653 | |
| 654 | desc->txd.flags = flags; |
| 655 | desc->tx_cnt = tx_cnt; |
Dan Williams | a0587bc | 2009-07-28 14:44:04 -0700 | [diff] [blame] | 656 | desc->len = total_len; |
| 657 | list_splice(&chain, &desc->txd.tx_list); |
| 658 | hw->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT); |
| 659 | hw->ctl_f.compl_write = 1; |
Dan Williams | 6df9183 | 2009-09-08 12:00:55 -0700 | [diff] [blame] | 660 | dump_desc_dbg(ioat, desc); |
Dan Williams | a0587bc | 2009-07-28 14:44:04 -0700 | [diff] [blame] | 661 | |
| 662 | return &desc->txd; |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 663 | } |
| 664 | |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 665 | static void ioat1_cleanup_tasklet(unsigned long data) |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 666 | { |
| 667 | struct ioat_dma_chan *chan = (void *)data; |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 668 | ioat1_cleanup(chan); |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 669 | writew(IOAT_CHANCTRL_INT_DISABLE, |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 670 | chan->base.reg_base + IOAT_CHANCTRL_OFFSET); |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 671 | } |
| 672 | |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 673 | static void ioat_unmap(struct pci_dev *pdev, dma_addr_t addr, size_t len, |
| 674 | int direction, enum dma_ctrl_flags flags, bool dst) |
Dan Williams | e1d181e | 2008-07-04 00:13:40 -0700 | [diff] [blame] | 675 | { |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 676 | if ((dst && (flags & DMA_COMPL_DEST_UNMAP_SINGLE)) || |
| 677 | (!dst && (flags & DMA_COMPL_SRC_UNMAP_SINGLE))) |
| 678 | pci_unmap_single(pdev, addr, len, direction); |
| 679 | else |
| 680 | pci_unmap_page(pdev, addr, len, direction); |
Dan Williams | e1d181e | 2008-07-04 00:13:40 -0700 | [diff] [blame] | 681 | } |
| 682 | |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 683 | |
| 684 | void ioat_dma_unmap(struct ioat_chan_common *chan, enum dma_ctrl_flags flags, |
| 685 | size_t len, struct ioat_dma_descriptor *hw) |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 686 | { |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 687 | struct pci_dev *pdev = chan->device->pdev; |
| 688 | size_t offset = len - hw->size; |
| 689 | |
| 690 | if (!(flags & DMA_COMPL_SKIP_DEST_UNMAP)) |
| 691 | ioat_unmap(pdev, hw->dst_addr - offset, len, |
| 692 | PCI_DMA_FROMDEVICE, flags, 1); |
| 693 | |
| 694 | if (!(flags & DMA_COMPL_SKIP_SRC_UNMAP)) |
| 695 | ioat_unmap(pdev, hw->src_addr - offset, len, |
| 696 | PCI_DMA_TODEVICE, flags, 0); |
| 697 | } |
| 698 | |
| 699 | unsigned long ioat_get_current_completion(struct ioat_chan_common *chan) |
| 700 | { |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 701 | unsigned long phys_complete; |
Dan Williams | 4fb9b9e | 2009-09-08 12:01:04 -0700 | [diff] [blame^] | 702 | u64 completion; |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 703 | |
Dan Williams | 4fb9b9e | 2009-09-08 12:01:04 -0700 | [diff] [blame^] | 704 | completion = *chan->completion; |
| 705 | phys_complete = completion & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR; |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 706 | |
Dan Williams | 6df9183 | 2009-09-08 12:00:55 -0700 | [diff] [blame] | 707 | dev_dbg(to_dev(chan), "%s: phys_complete: %#llx\n", __func__, |
| 708 | (unsigned long long) phys_complete); |
| 709 | |
Dan Williams | 4fb9b9e | 2009-09-08 12:01:04 -0700 | [diff] [blame^] | 710 | if ((completion & IOAT_CHANSTS_DMA_TRANSFER_STATUS) == |
Shannon Nelson | 43d6e36 | 2007-10-16 01:27:39 -0700 | [diff] [blame] | 711 | IOAT_CHANSTS_DMA_TRANSFER_STATUS_HALTED) { |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 712 | dev_err(to_dev(chan), "Channel halted, chanerr = %x\n", |
| 713 | readl(chan->reg_base + IOAT_CHANERR_OFFSET)); |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 714 | |
| 715 | /* TODO do something to salvage the situation */ |
| 716 | } |
| 717 | |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 718 | return phys_complete; |
| 719 | } |
| 720 | |
| 721 | /** |
| 722 | * ioat1_cleanup - cleanup up finished descriptors |
| 723 | * @chan: ioat channel to be cleaned up |
| 724 | */ |
| 725 | static void ioat1_cleanup(struct ioat_dma_chan *ioat) |
| 726 | { |
| 727 | struct ioat_chan_common *chan = &ioat->base; |
| 728 | unsigned long phys_complete; |
| 729 | struct ioat_desc_sw *desc, *_desc; |
| 730 | dma_cookie_t cookie = 0; |
| 731 | struct dma_async_tx_descriptor *tx; |
| 732 | |
Dan Williams | 4fb9b9e | 2009-09-08 12:01:04 -0700 | [diff] [blame^] | 733 | prefetch(chan->completion); |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 734 | |
| 735 | if (!spin_trylock_bh(&chan->cleanup_lock)) |
| 736 | return; |
| 737 | |
| 738 | phys_complete = ioat_get_current_completion(chan); |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 739 | if (phys_complete == chan->last_completion) { |
| 740 | spin_unlock_bh(&chan->cleanup_lock); |
Maciej Sosnowski | 09177e8 | 2008-07-22 10:07:33 -0700 | [diff] [blame] | 741 | /* |
| 742 | * perhaps we're stuck so hard that the watchdog can't go off? |
| 743 | * try to catch it after 2 seconds |
| 744 | */ |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 745 | if (time_after(jiffies, |
| 746 | chan->last_completion_time + HZ*WATCHDOG_DELAY)) { |
| 747 | ioat1_chan_watchdog(&(chan->device->work.work)); |
| 748 | chan->last_completion_time = jiffies; |
Maciej Sosnowski | 09177e8 | 2008-07-22 10:07:33 -0700 | [diff] [blame] | 749 | } |
| 750 | return; |
| 751 | } |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 752 | chan->last_completion_time = jiffies; |
Maciej Sosnowski | 09177e8 | 2008-07-22 10:07:33 -0700 | [diff] [blame] | 753 | |
| 754 | cookie = 0; |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 755 | if (!spin_trylock_bh(&ioat->desc_lock)) { |
| 756 | spin_unlock_bh(&chan->cleanup_lock); |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 757 | return; |
| 758 | } |
| 759 | |
Dan Williams | 6df9183 | 2009-09-08 12:00:55 -0700 | [diff] [blame] | 760 | dev_dbg(to_dev(chan), "%s: phys_complete: %lx\n", |
| 761 | __func__, phys_complete); |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 762 | list_for_each_entry_safe(desc, _desc, &ioat->used_desc, node) { |
Dan Williams | bc3c702 | 2009-07-28 14:33:42 -0700 | [diff] [blame] | 763 | tx = &desc->txd; |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 764 | /* |
| 765 | * Incoming DMA requests may use multiple descriptors, |
| 766 | * due to exceeding xfercap, perhaps. If so, only the |
| 767 | * last one will have a cookie, and require unmapping. |
| 768 | */ |
Dan Williams | 6df9183 | 2009-09-08 12:00:55 -0700 | [diff] [blame] | 769 | dump_desc_dbg(ioat, desc); |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 770 | if (tx->cookie) { |
| 771 | cookie = tx->cookie; |
| 772 | ioat_dma_unmap(chan, tx->flags, desc->len, desc->hw); |
| 773 | if (tx->callback) { |
| 774 | tx->callback(tx->callback_param); |
| 775 | tx->callback = NULL; |
Shannon Nelson | 7bb67c1 | 2007-11-14 16:59:51 -0800 | [diff] [blame] | 776 | } |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 777 | } |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 778 | |
| 779 | if (tx->phys != phys_complete) { |
| 780 | /* |
| 781 | * a completed entry, but not the last, so clean |
| 782 | * up if the client is done with the descriptor |
| 783 | */ |
| 784 | if (async_tx_test_ack(tx)) |
| 785 | list_move_tail(&desc->node, &ioat->free_desc); |
| 786 | else |
| 787 | tx->cookie = 0; |
| 788 | } else { |
| 789 | /* |
| 790 | * last used desc. Do not remove, so we can |
| 791 | * append from it, but don't look at it next |
| 792 | * time, either |
| 793 | */ |
| 794 | tx->cookie = 0; |
| 795 | |
| 796 | /* TODO check status bits? */ |
| 797 | break; |
| 798 | } |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 799 | } |
| 800 | |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 801 | spin_unlock_bh(&ioat->desc_lock); |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 802 | |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 803 | chan->last_completion = phys_complete; |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 804 | if (cookie != 0) |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 805 | chan->completed_cookie = cookie; |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 806 | |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 807 | spin_unlock_bh(&chan->cleanup_lock); |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 808 | } |
| 809 | |
Dan Williams | bc3c702 | 2009-07-28 14:33:42 -0700 | [diff] [blame] | 810 | static enum dma_status |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 811 | ioat1_dma_is_complete(struct dma_chan *c, dma_cookie_t cookie, |
| 812 | dma_cookie_t *done, dma_cookie_t *used) |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 813 | { |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 814 | struct ioat_dma_chan *ioat = to_ioat_chan(c); |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 815 | |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 816 | if (ioat_is_complete(c, cookie, done, used) == DMA_SUCCESS) |
| 817 | return DMA_SUCCESS; |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 818 | |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 819 | ioat1_cleanup(ioat); |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 820 | |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 821 | return ioat_is_complete(c, cookie, done, used); |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 822 | } |
| 823 | |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 824 | static void ioat1_dma_start_null_desc(struct ioat_dma_chan *ioat) |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 825 | { |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 826 | struct ioat_chan_common *chan = &ioat->base; |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 827 | struct ioat_desc_sw *desc; |
Dan Williams | c7984f4 | 2009-07-28 14:44:04 -0700 | [diff] [blame] | 828 | struct ioat_dma_descriptor *hw; |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 829 | |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 830 | spin_lock_bh(&ioat->desc_lock); |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 831 | |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 832 | desc = ioat1_dma_get_next_descriptor(ioat); |
Maciej Sosnowski | 7f1b358 | 2008-07-22 17:30:57 -0700 | [diff] [blame] | 833 | |
| 834 | if (!desc) { |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 835 | dev_err(to_dev(chan), |
Maciej Sosnowski | 7f1b358 | 2008-07-22 17:30:57 -0700 | [diff] [blame] | 836 | "Unable to start null desc - get next desc failed\n"); |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 837 | spin_unlock_bh(&ioat->desc_lock); |
Maciej Sosnowski | 7f1b358 | 2008-07-22 17:30:57 -0700 | [diff] [blame] | 838 | return; |
| 839 | } |
| 840 | |
Dan Williams | c7984f4 | 2009-07-28 14:44:04 -0700 | [diff] [blame] | 841 | hw = desc->hw; |
| 842 | hw->ctl = 0; |
| 843 | hw->ctl_f.null = 1; |
| 844 | hw->ctl_f.int_en = 1; |
| 845 | hw->ctl_f.compl_write = 1; |
Maciej Sosnowski | 7f1b358 | 2008-07-22 17:30:57 -0700 | [diff] [blame] | 846 | /* set size to non-zero value (channel returns error when size is 0) */ |
Dan Williams | c7984f4 | 2009-07-28 14:44:04 -0700 | [diff] [blame] | 847 | hw->size = NULL_DESC_BUFFER_SIZE; |
| 848 | hw->src_addr = 0; |
| 849 | hw->dst_addr = 0; |
Dan Williams | bc3c702 | 2009-07-28 14:33:42 -0700 | [diff] [blame] | 850 | async_tx_ack(&desc->txd); |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 851 | hw->next = 0; |
| 852 | list_add_tail(&desc->node, &ioat->used_desc); |
Dan Williams | 6df9183 | 2009-09-08 12:00:55 -0700 | [diff] [blame] | 853 | dump_desc_dbg(ioat, desc); |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 854 | |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 855 | writel(((u64) desc->txd.phys) & 0x00000000FFFFFFFF, |
| 856 | chan->reg_base + IOAT1_CHAINADDR_OFFSET_LOW); |
| 857 | writel(((u64) desc->txd.phys) >> 32, |
| 858 | chan->reg_base + IOAT1_CHAINADDR_OFFSET_HIGH); |
Shannon Nelson | 7bb67c1 | 2007-11-14 16:59:51 -0800 | [diff] [blame] | 859 | |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 860 | writeb(IOAT_CHANCMD_START, chan->reg_base |
| 861 | + IOAT_CHANCMD_OFFSET(chan->device->version)); |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 862 | spin_unlock_bh(&ioat->desc_lock); |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 863 | } |
| 864 | |
| 865 | /* |
| 866 | * Perform a IOAT transaction to verify the HW works. |
| 867 | */ |
| 868 | #define IOAT_TEST_SIZE 2000 |
| 869 | |
Shannon Nelson | 9521843 | 2007-10-18 03:07:15 -0700 | [diff] [blame] | 870 | static void ioat_dma_test_callback(void *dma_async_param) |
| 871 | { |
Dan Williams | b9bdcbb | 2009-01-06 11:38:22 -0700 | [diff] [blame] | 872 | struct completion *cmp = dma_async_param; |
| 873 | |
| 874 | complete(cmp); |
Shannon Nelson | 9521843 | 2007-10-18 03:07:15 -0700 | [diff] [blame] | 875 | } |
| 876 | |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 877 | /** |
| 878 | * ioat_dma_self_test - Perform a IOAT transaction to verify the HW works. |
| 879 | * @device: device to be tested |
| 880 | */ |
| 881 | static int ioat_dma_self_test(struct ioatdma_device *device) |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 882 | { |
| 883 | int i; |
| 884 | u8 *src; |
| 885 | u8 *dest; |
Dan Williams | bc3c702 | 2009-07-28 14:33:42 -0700 | [diff] [blame] | 886 | struct dma_device *dma = &device->common; |
| 887 | struct device *dev = &device->pdev->dev; |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 888 | struct dma_chan *dma_chan; |
Shannon Nelson | 711924b | 2007-12-17 16:20:08 -0800 | [diff] [blame] | 889 | struct dma_async_tx_descriptor *tx; |
Dan Williams | 0036731 | 2008-02-02 19:49:57 -0700 | [diff] [blame] | 890 | dma_addr_t dma_dest, dma_src; |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 891 | dma_cookie_t cookie; |
| 892 | int err = 0; |
Dan Williams | b9bdcbb | 2009-01-06 11:38:22 -0700 | [diff] [blame] | 893 | struct completion cmp; |
Dan Williams | 0c33e1c | 2009-03-02 13:31:35 -0700 | [diff] [blame] | 894 | unsigned long tmo; |
Maciej Sosnowski | 4f005db | 2009-04-23 12:31:51 +0200 | [diff] [blame] | 895 | unsigned long flags; |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 896 | |
Christoph Lameter | e94b176 | 2006-12-06 20:33:17 -0800 | [diff] [blame] | 897 | src = kzalloc(sizeof(u8) * IOAT_TEST_SIZE, GFP_KERNEL); |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 898 | if (!src) |
| 899 | return -ENOMEM; |
Christoph Lameter | e94b176 | 2006-12-06 20:33:17 -0800 | [diff] [blame] | 900 | dest = kzalloc(sizeof(u8) * IOAT_TEST_SIZE, GFP_KERNEL); |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 901 | if (!dest) { |
| 902 | kfree(src); |
| 903 | return -ENOMEM; |
| 904 | } |
| 905 | |
| 906 | /* Fill in src buffer */ |
| 907 | for (i = 0; i < IOAT_TEST_SIZE; i++) |
| 908 | src[i] = (u8)i; |
| 909 | |
| 910 | /* Start copy, using first DMA channel */ |
Dan Williams | bc3c702 | 2009-07-28 14:33:42 -0700 | [diff] [blame] | 911 | dma_chan = container_of(dma->channels.next, struct dma_chan, |
Shannon Nelson | 43d6e36 | 2007-10-16 01:27:39 -0700 | [diff] [blame] | 912 | device_node); |
Dan Williams | bc3c702 | 2009-07-28 14:33:42 -0700 | [diff] [blame] | 913 | if (dma->device_alloc_chan_resources(dma_chan) < 1) { |
| 914 | dev_err(dev, "selftest cannot allocate chan resource\n"); |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 915 | err = -ENODEV; |
| 916 | goto out; |
| 917 | } |
| 918 | |
Dan Williams | bc3c702 | 2009-07-28 14:33:42 -0700 | [diff] [blame] | 919 | dma_src = dma_map_single(dev, src, IOAT_TEST_SIZE, DMA_TO_DEVICE); |
| 920 | dma_dest = dma_map_single(dev, dest, IOAT_TEST_SIZE, DMA_FROM_DEVICE); |
Dan Williams | a6a39ca | 2009-07-28 14:44:05 -0700 | [diff] [blame] | 921 | flags = DMA_COMPL_SRC_UNMAP_SINGLE | DMA_COMPL_DEST_UNMAP_SINGLE | |
| 922 | DMA_PREP_INTERRUPT; |
Dan Williams | 0036731 | 2008-02-02 19:49:57 -0700 | [diff] [blame] | 923 | tx = device->common.device_prep_dma_memcpy(dma_chan, dma_dest, dma_src, |
Maciej Sosnowski | 4f005db | 2009-04-23 12:31:51 +0200 | [diff] [blame] | 924 | IOAT_TEST_SIZE, flags); |
Shannon Nelson | 5149fd0 | 2007-10-18 03:07:13 -0700 | [diff] [blame] | 925 | if (!tx) { |
Dan Williams | bc3c702 | 2009-07-28 14:33:42 -0700 | [diff] [blame] | 926 | dev_err(dev, "Self-test prep failed, disabling\n"); |
Shannon Nelson | 5149fd0 | 2007-10-18 03:07:13 -0700 | [diff] [blame] | 927 | err = -ENODEV; |
| 928 | goto free_resources; |
| 929 | } |
| 930 | |
Dan Williams | 7405f74 | 2007-01-02 11:10:43 -0700 | [diff] [blame] | 931 | async_tx_ack(tx); |
Dan Williams | b9bdcbb | 2009-01-06 11:38:22 -0700 | [diff] [blame] | 932 | init_completion(&cmp); |
Shannon Nelson | 9521843 | 2007-10-18 03:07:15 -0700 | [diff] [blame] | 933 | tx->callback = ioat_dma_test_callback; |
Dan Williams | b9bdcbb | 2009-01-06 11:38:22 -0700 | [diff] [blame] | 934 | tx->callback_param = &cmp; |
Shannon Nelson | 7bb67c1 | 2007-11-14 16:59:51 -0800 | [diff] [blame] | 935 | cookie = tx->tx_submit(tx); |
Shannon Nelson | 7f2b291 | 2007-10-18 03:07:14 -0700 | [diff] [blame] | 936 | if (cookie < 0) { |
Dan Williams | bc3c702 | 2009-07-28 14:33:42 -0700 | [diff] [blame] | 937 | dev_err(dev, "Self-test setup failed, disabling\n"); |
Shannon Nelson | 7f2b291 | 2007-10-18 03:07:14 -0700 | [diff] [blame] | 938 | err = -ENODEV; |
| 939 | goto free_resources; |
| 940 | } |
Dan Williams | bc3c702 | 2009-07-28 14:33:42 -0700 | [diff] [blame] | 941 | dma->device_issue_pending(dma_chan); |
Dan Williams | 532d3b1 | 2008-12-03 17:16:55 -0700 | [diff] [blame] | 942 | |
Dan Williams | 0c33e1c | 2009-03-02 13:31:35 -0700 | [diff] [blame] | 943 | tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000)); |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 944 | |
Dan Williams | 0c33e1c | 2009-03-02 13:31:35 -0700 | [diff] [blame] | 945 | if (tmo == 0 || |
Dan Williams | bc3c702 | 2009-07-28 14:33:42 -0700 | [diff] [blame] | 946 | dma->device_is_tx_complete(dma_chan, cookie, NULL, NULL) |
Shannon Nelson | 7bb67c1 | 2007-11-14 16:59:51 -0800 | [diff] [blame] | 947 | != DMA_SUCCESS) { |
Dan Williams | bc3c702 | 2009-07-28 14:33:42 -0700 | [diff] [blame] | 948 | dev_err(dev, "Self-test copy timed out, disabling\n"); |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 949 | err = -ENODEV; |
| 950 | goto free_resources; |
| 951 | } |
| 952 | if (memcmp(src, dest, IOAT_TEST_SIZE)) { |
Dan Williams | bc3c702 | 2009-07-28 14:33:42 -0700 | [diff] [blame] | 953 | dev_err(dev, "Self-test copy failed compare, disabling\n"); |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 954 | err = -ENODEV; |
| 955 | goto free_resources; |
| 956 | } |
| 957 | |
| 958 | free_resources: |
Dan Williams | bc3c702 | 2009-07-28 14:33:42 -0700 | [diff] [blame] | 959 | dma->device_free_chan_resources(dma_chan); |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 960 | out: |
| 961 | kfree(src); |
| 962 | kfree(dest); |
| 963 | return err; |
| 964 | } |
| 965 | |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 966 | static char ioat_interrupt_style[32] = "msix"; |
| 967 | module_param_string(ioat_interrupt_style, ioat_interrupt_style, |
| 968 | sizeof(ioat_interrupt_style), 0644); |
| 969 | MODULE_PARM_DESC(ioat_interrupt_style, |
| 970 | "set ioat interrupt style: msix (default), " |
| 971 | "msix-single-vector, msi, intx)"); |
| 972 | |
| 973 | /** |
| 974 | * ioat_dma_setup_interrupts - setup interrupt handler |
| 975 | * @device: ioat device |
| 976 | */ |
| 977 | static int ioat_dma_setup_interrupts(struct ioatdma_device *device) |
| 978 | { |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 979 | struct ioat_chan_common *chan; |
Dan Williams | e6c0b69 | 2009-09-08 17:29:44 -0700 | [diff] [blame] | 980 | struct pci_dev *pdev = device->pdev; |
| 981 | struct device *dev = &pdev->dev; |
| 982 | struct msix_entry *msix; |
| 983 | int i, j, msixcnt; |
| 984 | int err = -EINVAL; |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 985 | u8 intrctrl = 0; |
| 986 | |
| 987 | if (!strcmp(ioat_interrupt_style, "msix")) |
| 988 | goto msix; |
| 989 | if (!strcmp(ioat_interrupt_style, "msix-single-vector")) |
| 990 | goto msix_single_vector; |
| 991 | if (!strcmp(ioat_interrupt_style, "msi")) |
| 992 | goto msi; |
| 993 | if (!strcmp(ioat_interrupt_style, "intx")) |
| 994 | goto intx; |
Dan Williams | e6c0b69 | 2009-09-08 17:29:44 -0700 | [diff] [blame] | 995 | dev_err(dev, "invalid ioat_interrupt_style %s\n", ioat_interrupt_style); |
Shannon Nelson | 5149fd0 | 2007-10-18 03:07:13 -0700 | [diff] [blame] | 996 | goto err_no_irq; |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 997 | |
| 998 | msix: |
| 999 | /* The number of MSI-X vectors should equal the number of channels */ |
| 1000 | msixcnt = device->common.chancnt; |
| 1001 | for (i = 0; i < msixcnt; i++) |
| 1002 | device->msix_entries[i].entry = i; |
| 1003 | |
Dan Williams | e6c0b69 | 2009-09-08 17:29:44 -0700 | [diff] [blame] | 1004 | err = pci_enable_msix(pdev, device->msix_entries, msixcnt); |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 1005 | if (err < 0) |
| 1006 | goto msi; |
| 1007 | if (err > 0) |
| 1008 | goto msix_single_vector; |
| 1009 | |
| 1010 | for (i = 0; i < msixcnt; i++) { |
Dan Williams | e6c0b69 | 2009-09-08 17:29:44 -0700 | [diff] [blame] | 1011 | msix = &device->msix_entries[i]; |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 1012 | chan = ioat_chan_by_index(device, i); |
Dan Williams | e6c0b69 | 2009-09-08 17:29:44 -0700 | [diff] [blame] | 1013 | err = devm_request_irq(dev, msix->vector, |
| 1014 | ioat_dma_do_interrupt_msix, 0, |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 1015 | "ioat-msix", chan); |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 1016 | if (err) { |
| 1017 | for (j = 0; j < i; j++) { |
Dan Williams | e6c0b69 | 2009-09-08 17:29:44 -0700 | [diff] [blame] | 1018 | msix = &device->msix_entries[j]; |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 1019 | chan = ioat_chan_by_index(device, j); |
| 1020 | devm_free_irq(dev, msix->vector, chan); |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 1021 | } |
| 1022 | goto msix_single_vector; |
| 1023 | } |
| 1024 | } |
| 1025 | intrctrl |= IOAT_INTRCTRL_MSIX_VECTOR_CONTROL; |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 1026 | goto done; |
| 1027 | |
| 1028 | msix_single_vector: |
Dan Williams | e6c0b69 | 2009-09-08 17:29:44 -0700 | [diff] [blame] | 1029 | msix = &device->msix_entries[0]; |
| 1030 | msix->entry = 0; |
| 1031 | err = pci_enable_msix(pdev, device->msix_entries, 1); |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 1032 | if (err) |
| 1033 | goto msi; |
| 1034 | |
Dan Williams | e6c0b69 | 2009-09-08 17:29:44 -0700 | [diff] [blame] | 1035 | err = devm_request_irq(dev, msix->vector, ioat_dma_do_interrupt, 0, |
| 1036 | "ioat-msix", device); |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 1037 | if (err) { |
Dan Williams | e6c0b69 | 2009-09-08 17:29:44 -0700 | [diff] [blame] | 1038 | pci_disable_msix(pdev); |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 1039 | goto msi; |
| 1040 | } |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 1041 | goto done; |
| 1042 | |
| 1043 | msi: |
Dan Williams | e6c0b69 | 2009-09-08 17:29:44 -0700 | [diff] [blame] | 1044 | err = pci_enable_msi(pdev); |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 1045 | if (err) |
| 1046 | goto intx; |
| 1047 | |
Dan Williams | e6c0b69 | 2009-09-08 17:29:44 -0700 | [diff] [blame] | 1048 | err = devm_request_irq(dev, pdev->irq, ioat_dma_do_interrupt, 0, |
| 1049 | "ioat-msi", device); |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 1050 | if (err) { |
Dan Williams | e6c0b69 | 2009-09-08 17:29:44 -0700 | [diff] [blame] | 1051 | pci_disable_msi(pdev); |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 1052 | goto intx; |
| 1053 | } |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 1054 | goto done; |
| 1055 | |
| 1056 | intx: |
Dan Williams | e6c0b69 | 2009-09-08 17:29:44 -0700 | [diff] [blame] | 1057 | err = devm_request_irq(dev, pdev->irq, ioat_dma_do_interrupt, |
| 1058 | IRQF_SHARED, "ioat-intx", device); |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 1059 | if (err) |
| 1060 | goto err_no_irq; |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 1061 | |
| 1062 | done: |
Dan Williams | f2427e2 | 2009-07-28 14:42:38 -0700 | [diff] [blame] | 1063 | if (device->intr_quirk) |
| 1064 | device->intr_quirk(device); |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 1065 | intrctrl |= IOAT_INTRCTRL_MASTER_INT_EN; |
| 1066 | writeb(intrctrl, device->reg_base + IOAT_INTRCTRL_OFFSET); |
| 1067 | return 0; |
| 1068 | |
| 1069 | err_no_irq: |
| 1070 | /* Disable all interrupt generation */ |
| 1071 | writeb(0, device->reg_base + IOAT_INTRCTRL_OFFSET); |
Dan Williams | e6c0b69 | 2009-09-08 17:29:44 -0700 | [diff] [blame] | 1072 | dev_err(dev, "no usable interrupts\n"); |
| 1073 | return err; |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 1074 | } |
| 1075 | |
Dan Williams | e6c0b69 | 2009-09-08 17:29:44 -0700 | [diff] [blame] | 1076 | static void ioat_disable_interrupts(struct ioatdma_device *device) |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 1077 | { |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 1078 | /* Disable all interrupt generation */ |
| 1079 | writeb(0, device->reg_base + IOAT_INTRCTRL_OFFSET); |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 1080 | } |
| 1081 | |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 1082 | int ioat_probe(struct ioatdma_device *device) |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 1083 | { |
Dan Williams | f2427e2 | 2009-07-28 14:42:38 -0700 | [diff] [blame] | 1084 | int err = -ENODEV; |
| 1085 | struct dma_device *dma = &device->common; |
| 1086 | struct pci_dev *pdev = device->pdev; |
Dan Williams | e6c0b69 | 2009-09-08 17:29:44 -0700 | [diff] [blame] | 1087 | struct device *dev = &pdev->dev; |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 1088 | |
| 1089 | /* DMA coherent memory pool for DMA descriptor allocations */ |
| 1090 | device->dma_pool = pci_pool_create("dma_desc_pool", pdev, |
Shannon Nelson | 8ab8956 | 2007-10-16 01:27:39 -0700 | [diff] [blame] | 1091 | sizeof(struct ioat_dma_descriptor), |
| 1092 | 64, 0); |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 1093 | if (!device->dma_pool) { |
| 1094 | err = -ENOMEM; |
| 1095 | goto err_dma_pool; |
| 1096 | } |
| 1097 | |
Shannon Nelson | 43d6e36 | 2007-10-16 01:27:39 -0700 | [diff] [blame] | 1098 | device->completion_pool = pci_pool_create("completion_pool", pdev, |
| 1099 | sizeof(u64), SMP_CACHE_BYTES, |
| 1100 | SMP_CACHE_BYTES); |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 1101 | |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 1102 | if (!device->completion_pool) { |
| 1103 | err = -ENOMEM; |
| 1104 | goto err_completion_pool; |
| 1105 | } |
| 1106 | |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 1107 | device->enumerate_channels(device); |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 1108 | |
Dan Williams | f2427e2 | 2009-07-28 14:42:38 -0700 | [diff] [blame] | 1109 | dma_cap_set(DMA_MEMCPY, dma->cap_mask); |
Dan Williams | f2427e2 | 2009-07-28 14:42:38 -0700 | [diff] [blame] | 1110 | dma->dev = &pdev->dev; |
Shannon Nelson | 7bb67c1 | 2007-11-14 16:59:51 -0800 | [diff] [blame] | 1111 | |
Dan Williams | e6c0b69 | 2009-09-08 17:29:44 -0700 | [diff] [blame] | 1112 | dev_err(dev, "Intel(R) I/OAT DMA Engine found," |
Shannon Nelson | 5149fd0 | 2007-10-18 03:07:13 -0700 | [diff] [blame] | 1113 | " %d channels, device version 0x%02x, driver version %s\n", |
Dan Williams | bc3c702 | 2009-07-28 14:33:42 -0700 | [diff] [blame] | 1114 | dma->chancnt, device->version, IOAT_DMA_VERSION); |
Shannon Nelson | 8ab8956 | 2007-10-16 01:27:39 -0700 | [diff] [blame] | 1115 | |
Dan Williams | bc3c702 | 2009-07-28 14:33:42 -0700 | [diff] [blame] | 1116 | if (!dma->chancnt) { |
Dan Williams | e6c0b69 | 2009-09-08 17:29:44 -0700 | [diff] [blame] | 1117 | dev_err(dev, "Intel(R) I/OAT DMA Engine problem found: " |
Maciej Sosnowski | 8b794b1 | 2009-02-26 11:04:54 +0100 | [diff] [blame] | 1118 | "zero channels detected\n"); |
| 1119 | goto err_setup_interrupts; |
| 1120 | } |
| 1121 | |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 1122 | err = ioat_dma_setup_interrupts(device); |
Shannon Nelson | 8ab8956 | 2007-10-16 01:27:39 -0700 | [diff] [blame] | 1123 | if (err) |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 1124 | goto err_setup_interrupts; |
Shannon Nelson | 8ab8956 | 2007-10-16 01:27:39 -0700 | [diff] [blame] | 1125 | |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 1126 | err = ioat_dma_self_test(device); |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 1127 | if (err) |
| 1128 | goto err_self_test; |
| 1129 | |
Dan Williams | f2427e2 | 2009-07-28 14:42:38 -0700 | [diff] [blame] | 1130 | return 0; |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 1131 | |
| 1132 | err_self_test: |
Dan Williams | e6c0b69 | 2009-09-08 17:29:44 -0700 | [diff] [blame] | 1133 | ioat_disable_interrupts(device); |
Shannon Nelson | 3e03745 | 2007-10-16 01:27:40 -0700 | [diff] [blame] | 1134 | err_setup_interrupts: |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 1135 | pci_pool_destroy(device->completion_pool); |
| 1136 | err_completion_pool: |
| 1137 | pci_pool_destroy(device->dma_pool); |
| 1138 | err_dma_pool: |
Dan Williams | f2427e2 | 2009-07-28 14:42:38 -0700 | [diff] [blame] | 1139 | return err; |
| 1140 | } |
| 1141 | |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 1142 | int ioat_register(struct ioatdma_device *device) |
Dan Williams | f2427e2 | 2009-07-28 14:42:38 -0700 | [diff] [blame] | 1143 | { |
| 1144 | int err = dma_async_device_register(&device->common); |
| 1145 | |
| 1146 | if (err) { |
| 1147 | ioat_disable_interrupts(device); |
| 1148 | pci_pool_destroy(device->completion_pool); |
| 1149 | pci_pool_destroy(device->dma_pool); |
| 1150 | } |
| 1151 | |
| 1152 | return err; |
| 1153 | } |
| 1154 | |
| 1155 | /* ioat1_intr_quirk - fix up dma ctrl register to enable / disable msi */ |
| 1156 | static void ioat1_intr_quirk(struct ioatdma_device *device) |
| 1157 | { |
| 1158 | struct pci_dev *pdev = device->pdev; |
| 1159 | u32 dmactrl; |
| 1160 | |
| 1161 | pci_read_config_dword(pdev, IOAT_PCI_DMACTRL_OFFSET, &dmactrl); |
| 1162 | if (pdev->msi_enabled) |
| 1163 | dmactrl |= IOAT_PCI_DMACTRL_MSI_EN; |
| 1164 | else |
| 1165 | dmactrl &= ~IOAT_PCI_DMACTRL_MSI_EN; |
| 1166 | pci_write_config_dword(pdev, IOAT_PCI_DMACTRL_OFFSET, dmactrl); |
| 1167 | } |
| 1168 | |
| 1169 | int ioat1_dma_probe(struct ioatdma_device *device, int dca) |
| 1170 | { |
| 1171 | struct pci_dev *pdev = device->pdev; |
| 1172 | struct dma_device *dma; |
| 1173 | int err; |
| 1174 | |
| 1175 | device->intr_quirk = ioat1_intr_quirk; |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 1176 | device->enumerate_channels = ioat1_enumerate_channels; |
Dan Williams | f2427e2 | 2009-07-28 14:42:38 -0700 | [diff] [blame] | 1177 | dma = &device->common; |
| 1178 | dma->device_prep_dma_memcpy = ioat1_dma_prep_memcpy; |
| 1179 | dma->device_issue_pending = ioat1_dma_memcpy_issue_pending; |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 1180 | dma->device_alloc_chan_resources = ioat1_dma_alloc_chan_resources; |
| 1181 | dma->device_free_chan_resources = ioat1_dma_free_chan_resources; |
| 1182 | dma->device_is_tx_complete = ioat1_dma_is_complete; |
Dan Williams | f2427e2 | 2009-07-28 14:42:38 -0700 | [diff] [blame] | 1183 | |
| 1184 | err = ioat_probe(device); |
| 1185 | if (err) |
| 1186 | return err; |
| 1187 | ioat_set_tcp_copy_break(4096); |
| 1188 | err = ioat_register(device); |
| 1189 | if (err) |
| 1190 | return err; |
| 1191 | if (dca) |
| 1192 | device->dca = ioat_dca_init(pdev, device->reg_base); |
| 1193 | |
Dan Williams | 5cbafa6 | 2009-08-26 13:01:44 -0700 | [diff] [blame] | 1194 | INIT_DELAYED_WORK(&device->work, ioat1_chan_watchdog); |
Dan Williams | f2427e2 | 2009-07-28 14:42:38 -0700 | [diff] [blame] | 1195 | schedule_delayed_work(&device->work, WATCHDOG_DELAY); |
| 1196 | |
| 1197 | return err; |
| 1198 | } |
| 1199 | |
Shannon Nelson | 8ab8956 | 2007-10-16 01:27:39 -0700 | [diff] [blame] | 1200 | void ioat_dma_remove(struct ioatdma_device *device) |
Dan Aloni | 428ed60 | 2007-03-08 09:57:36 -0800 | [diff] [blame] | 1201 | { |
Dan Williams | bc3c702 | 2009-07-28 14:33:42 -0700 | [diff] [blame] | 1202 | struct dma_device *dma = &device->common; |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 1203 | |
Maciej Sosnowski | 2b8a6bf | 2009-02-26 11:05:07 +0100 | [diff] [blame] | 1204 | if (device->version != IOAT_VER_3_0) |
| 1205 | cancel_delayed_work(&device->work); |
| 1206 | |
Dan Williams | e6c0b69 | 2009-09-08 17:29:44 -0700 | [diff] [blame] | 1207 | ioat_disable_interrupts(device); |
Shannon Nelson | 8ab8956 | 2007-10-16 01:27:39 -0700 | [diff] [blame] | 1208 | |
Dan Williams | bc3c702 | 2009-07-28 14:33:42 -0700 | [diff] [blame] | 1209 | dma_async_device_unregister(dma); |
Shannon Nelson | dfe2299 | 2007-10-18 03:07:13 -0700 | [diff] [blame] | 1210 | |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 1211 | pci_pool_destroy(device->dma_pool); |
| 1212 | pci_pool_destroy(device->completion_pool); |
Shannon Nelson | 8ab8956 | 2007-10-16 01:27:39 -0700 | [diff] [blame] | 1213 | |
Dan Williams | dcbc853 | 2009-07-28 14:44:50 -0700 | [diff] [blame] | 1214 | INIT_LIST_HEAD(&dma->channels); |
Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 1215 | } |