blob: 4e5931cabfa2a53f7f3290e803b76d41b51a55a9 [file] [log] [blame]
Grant Likelyca632f52011-06-06 01:16:30 -06001/*
Jassi Brar230d42d2009-11-30 07:39:42 +00002 * Copyright (C) 2009 Samsung Electronics Ltd.
3 * Jaswinder Singh <jassi.brar@samsung.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
Jassi Brar230d42d2009-11-30 07:39:42 +000014 */
15
16#include <linux/init.h>
17#include <linux/module.h>
Mark Brownc2573122011-11-10 10:57:32 +000018#include <linux/interrupt.h>
Jassi Brar230d42d2009-11-30 07:39:42 +000019#include <linux/delay.h>
20#include <linux/clk.h>
21#include <linux/dma-mapping.h>
Arnd Bergmann78843722013-04-11 22:42:03 +020022#include <linux/dmaengine.h>
Jassi Brar230d42d2009-11-30 07:39:42 +000023#include <linux/platform_device.h>
Mark Brownb97b6622011-12-04 00:58:06 +000024#include <linux/pm_runtime.h>
Jassi Brar230d42d2009-11-30 07:39:42 +000025#include <linux/spi/spi.h>
Thomas Abraham1c20c202012-07-13 07:15:14 +090026#include <linux/gpio.h>
Thomas Abraham2b908072012-07-13 07:15:15 +090027#include <linux/of.h>
28#include <linux/of_gpio.h>
Jassi Brar230d42d2009-11-30 07:39:42 +000029
Arnd Bergmann436d42c2012-08-24 15:22:12 +020030#include <linux/platform_data/spi-s3c64xx.h>
Jassi Brar230d42d2009-11-30 07:39:42 +000031
Padmavathi Vennabf77cba2014-11-06 15:21:49 +053032#define MAX_SPI_PORTS 6
Girish K S7e995552013-05-20 12:21:32 +053033#define S3C64XX_SPI_QUIRK_POLL (1 << 0)
Padmavathi Vennabf77cba2014-11-06 15:21:49 +053034#define S3C64XX_SPI_QUIRK_CS_AUTO (1 << 1)
Heiner Kallweit483867e2015-09-03 22:39:36 +020035#define AUTOSUSPEND_TIMEOUT 2000
Thomas Abrahama5238e32012-07-13 07:15:14 +090036
Jassi Brar230d42d2009-11-30 07:39:42 +000037/* Registers and bit-fields */
38
39#define S3C64XX_SPI_CH_CFG 0x00
40#define S3C64XX_SPI_CLK_CFG 0x04
41#define S3C64XX_SPI_MODE_CFG 0x08
42#define S3C64XX_SPI_SLAVE_SEL 0x0C
43#define S3C64XX_SPI_INT_EN 0x10
44#define S3C64XX_SPI_STATUS 0x14
45#define S3C64XX_SPI_TX_DATA 0x18
46#define S3C64XX_SPI_RX_DATA 0x1C
47#define S3C64XX_SPI_PACKET_CNT 0x20
48#define S3C64XX_SPI_PENDING_CLR 0x24
49#define S3C64XX_SPI_SWAP_CFG 0x28
50#define S3C64XX_SPI_FB_CLK 0x2C
51
52#define S3C64XX_SPI_CH_HS_EN (1<<6) /* High Speed Enable */
53#define S3C64XX_SPI_CH_SW_RST (1<<5)
54#define S3C64XX_SPI_CH_SLAVE (1<<4)
55#define S3C64XX_SPI_CPOL_L (1<<3)
56#define S3C64XX_SPI_CPHA_B (1<<2)
57#define S3C64XX_SPI_CH_RXCH_ON (1<<1)
58#define S3C64XX_SPI_CH_TXCH_ON (1<<0)
59
60#define S3C64XX_SPI_CLKSEL_SRCMSK (3<<9)
61#define S3C64XX_SPI_CLKSEL_SRCSHFT 9
62#define S3C64XX_SPI_ENCLK_ENABLE (1<<8)
Jingoo Han75bf3362013-01-31 15:25:01 +090063#define S3C64XX_SPI_PSR_MASK 0xff
Jassi Brar230d42d2009-11-30 07:39:42 +000064
65#define S3C64XX_SPI_MODE_CH_TSZ_BYTE (0<<29)
66#define S3C64XX_SPI_MODE_CH_TSZ_HALFWORD (1<<29)
67#define S3C64XX_SPI_MODE_CH_TSZ_WORD (2<<29)
68#define S3C64XX_SPI_MODE_CH_TSZ_MASK (3<<29)
69#define S3C64XX_SPI_MODE_BUS_TSZ_BYTE (0<<17)
70#define S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD (1<<17)
71#define S3C64XX_SPI_MODE_BUS_TSZ_WORD (2<<17)
72#define S3C64XX_SPI_MODE_BUS_TSZ_MASK (3<<17)
73#define S3C64XX_SPI_MODE_RXDMA_ON (1<<2)
74#define S3C64XX_SPI_MODE_TXDMA_ON (1<<1)
75#define S3C64XX_SPI_MODE_4BURST (1<<0)
76
77#define S3C64XX_SPI_SLAVE_AUTO (1<<1)
78#define S3C64XX_SPI_SLAVE_SIG_INACT (1<<0)
Padmavathi Vennabf77cba2014-11-06 15:21:49 +053079#define S3C64XX_SPI_SLAVE_NSC_CNT_2 (2<<4)
Jassi Brar230d42d2009-11-30 07:39:42 +000080
Jassi Brar230d42d2009-11-30 07:39:42 +000081#define S3C64XX_SPI_INT_TRAILING_EN (1<<6)
82#define S3C64XX_SPI_INT_RX_OVERRUN_EN (1<<5)
83#define S3C64XX_SPI_INT_RX_UNDERRUN_EN (1<<4)
84#define S3C64XX_SPI_INT_TX_OVERRUN_EN (1<<3)
85#define S3C64XX_SPI_INT_TX_UNDERRUN_EN (1<<2)
86#define S3C64XX_SPI_INT_RX_FIFORDY_EN (1<<1)
87#define S3C64XX_SPI_INT_TX_FIFORDY_EN (1<<0)
88
89#define S3C64XX_SPI_ST_RX_OVERRUN_ERR (1<<5)
90#define S3C64XX_SPI_ST_RX_UNDERRUN_ERR (1<<4)
91#define S3C64XX_SPI_ST_TX_OVERRUN_ERR (1<<3)
92#define S3C64XX_SPI_ST_TX_UNDERRUN_ERR (1<<2)
93#define S3C64XX_SPI_ST_RX_FIFORDY (1<<1)
94#define S3C64XX_SPI_ST_TX_FIFORDY (1<<0)
95
96#define S3C64XX_SPI_PACKET_CNT_EN (1<<16)
97
98#define S3C64XX_SPI_PND_TX_UNDERRUN_CLR (1<<4)
99#define S3C64XX_SPI_PND_TX_OVERRUN_CLR (1<<3)
100#define S3C64XX_SPI_PND_RX_UNDERRUN_CLR (1<<2)
101#define S3C64XX_SPI_PND_RX_OVERRUN_CLR (1<<1)
102#define S3C64XX_SPI_PND_TRAILING_CLR (1<<0)
103
104#define S3C64XX_SPI_SWAP_RX_HALF_WORD (1<<7)
105#define S3C64XX_SPI_SWAP_RX_BYTE (1<<6)
106#define S3C64XX_SPI_SWAP_RX_BIT (1<<5)
107#define S3C64XX_SPI_SWAP_RX_EN (1<<4)
108#define S3C64XX_SPI_SWAP_TX_HALF_WORD (1<<3)
109#define S3C64XX_SPI_SWAP_TX_BYTE (1<<2)
110#define S3C64XX_SPI_SWAP_TX_BIT (1<<1)
111#define S3C64XX_SPI_SWAP_TX_EN (1<<0)
112
113#define S3C64XX_SPI_FBCLK_MSK (3<<0)
114
Thomas Abrahama5238e32012-07-13 07:15:14 +0900115#define FIFO_LVL_MASK(i) ((i)->port_conf->fifo_lvl_mask[i->port_id])
116#define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & \
117 (1 << (i)->port_conf->tx_st_done)) ? 1 : 0)
118#define TX_FIFO_LVL(v, i) (((v) >> 6) & FIFO_LVL_MASK(i))
119#define RX_FIFO_LVL(v, i) (((v) >> (i)->port_conf->rx_lvl_offset) & \
120 FIFO_LVL_MASK(i))
Jassi Brar230d42d2009-11-30 07:39:42 +0000121
122#define S3C64XX_SPI_MAX_TRAILCNT 0x3ff
123#define S3C64XX_SPI_TRAILCNT_OFF 19
124
125#define S3C64XX_SPI_TRAILCNT S3C64XX_SPI_MAX_TRAILCNT
126
127#define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
Girish K S7e995552013-05-20 12:21:32 +0530128#define is_polling(x) (x->port_conf->quirks & S3C64XX_SPI_QUIRK_POLL)
Jassi Brar230d42d2009-11-30 07:39:42 +0000129
Jassi Brar230d42d2009-11-30 07:39:42 +0000130#define RXBUSY (1<<2)
131#define TXBUSY (1<<3)
132
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900133struct s3c64xx_spi_dma_data {
Arnd Bergmann78843722013-04-11 22:42:03 +0200134 struct dma_chan *ch;
Arnd Bergmannc10356b2012-04-30 16:31:27 +0000135 enum dma_transfer_direction direction;
Arnd Bergmann78843722013-04-11 22:42:03 +0200136 unsigned int dmach;
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900137};
138
Jassi Brar230d42d2009-11-30 07:39:42 +0000139/**
Thomas Abrahama5238e32012-07-13 07:15:14 +0900140 * struct s3c64xx_spi_info - SPI Controller hardware info
141 * @fifo_lvl_mask: Bit-mask for {TX|RX}_FIFO_LVL bits in SPI_STATUS register.
142 * @rx_lvl_offset: Bit offset of RX_FIFO_LVL bits in SPI_STATUS regiter.
143 * @tx_st_done: Bit offset of TX_DONE bit in SPI_STATUS regiter.
144 * @high_speed: True, if the controller supports HIGH_SPEED_EN bit.
145 * @clk_from_cmu: True, if the controller does not include a clock mux and
146 * prescaler unit.
147 *
148 * The Samsung s3c64xx SPI controller are used on various Samsung SoC's but
149 * differ in some aspects such as the size of the fifo and spi bus clock
150 * setup. Such differences are specified to the driver using this structure
151 * which is provided as driver data to the driver.
152 */
153struct s3c64xx_spi_port_config {
154 int fifo_lvl_mask[MAX_SPI_PORTS];
155 int rx_lvl_offset;
156 int tx_st_done;
Girish K S7e995552013-05-20 12:21:32 +0530157 int quirks;
Thomas Abrahama5238e32012-07-13 07:15:14 +0900158 bool high_speed;
159 bool clk_from_cmu;
160};
161
162/**
Jassi Brar230d42d2009-11-30 07:39:42 +0000163 * struct s3c64xx_spi_driver_data - Runtime info holder for SPI driver.
164 * @clk: Pointer to the spi clock.
Jassi Brarb0d5d6e2010-01-20 13:49:44 -0700165 * @src_clk: Pointer to the clock used to generate SPI signals.
Jassi Brar230d42d2009-11-30 07:39:42 +0000166 * @master: Pointer to the SPI Protocol master.
Jassi Brar230d42d2009-11-30 07:39:42 +0000167 * @cntrlr_info: Platform specific data for the controller this driver manages.
168 * @tgl_spi: Pointer to the last CS left untoggled by the cs_change hint.
Jassi Brar230d42d2009-11-30 07:39:42 +0000169 * @lock: Controller specific lock.
170 * @state: Set of FLAGS to indicate status.
171 * @rx_dmach: Controller's DMA channel for Rx.
172 * @tx_dmach: Controller's DMA channel for Tx.
173 * @sfr_start: BUS address of SPI controller regs.
174 * @regs: Pointer to ioremap'ed controller registers.
Mark Brownc2573122011-11-10 10:57:32 +0000175 * @irq: interrupt
Jassi Brar230d42d2009-11-30 07:39:42 +0000176 * @xfer_completion: To indicate completion of xfer task.
177 * @cur_mode: Stores the active configuration of the controller.
178 * @cur_bpw: Stores the active bits per word settings.
179 * @cur_speed: Stores the active xfer clock speed.
180 */
181struct s3c64xx_spi_driver_data {
182 void __iomem *regs;
183 struct clk *clk;
Jassi Brarb0d5d6e2010-01-20 13:49:44 -0700184 struct clk *src_clk;
Jassi Brar230d42d2009-11-30 07:39:42 +0000185 struct platform_device *pdev;
186 struct spi_master *master;
Jassi Brarad7de722010-01-20 13:49:44 -0700187 struct s3c64xx_spi_info *cntrlr_info;
Jassi Brar230d42d2009-11-30 07:39:42 +0000188 struct spi_device *tgl_spi;
Jassi Brar230d42d2009-11-30 07:39:42 +0000189 spinlock_t lock;
Jassi Brar230d42d2009-11-30 07:39:42 +0000190 unsigned long sfr_start;
191 struct completion xfer_completion;
192 unsigned state;
193 unsigned cur_mode, cur_bpw;
194 unsigned cur_speed;
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900195 struct s3c64xx_spi_dma_data rx_dma;
196 struct s3c64xx_spi_dma_data tx_dma;
Thomas Abrahama5238e32012-07-13 07:15:14 +0900197 struct s3c64xx_spi_port_config *port_conf;
198 unsigned int port_id;
Jassi Brar230d42d2009-11-30 07:39:42 +0000199};
200
Jassi Brar230d42d2009-11-30 07:39:42 +0000201static void flush_fifo(struct s3c64xx_spi_driver_data *sdd)
202{
Jassi Brar230d42d2009-11-30 07:39:42 +0000203 void __iomem *regs = sdd->regs;
204 unsigned long loops;
205 u32 val;
206
207 writel(0, regs + S3C64XX_SPI_PACKET_CNT);
208
209 val = readl(regs + S3C64XX_SPI_CH_CFG);
Kyoungil Kim7d859ff2012-05-23 21:29:51 +0900210 val &= ~(S3C64XX_SPI_CH_RXCH_ON | S3C64XX_SPI_CH_TXCH_ON);
211 writel(val, regs + S3C64XX_SPI_CH_CFG);
212
213 val = readl(regs + S3C64XX_SPI_CH_CFG);
Jassi Brar230d42d2009-11-30 07:39:42 +0000214 val |= S3C64XX_SPI_CH_SW_RST;
215 val &= ~S3C64XX_SPI_CH_HS_EN;
216 writel(val, regs + S3C64XX_SPI_CH_CFG);
217
218 /* Flush TxFIFO*/
219 loops = msecs_to_loops(1);
220 do {
221 val = readl(regs + S3C64XX_SPI_STATUS);
Thomas Abrahama5238e32012-07-13 07:15:14 +0900222 } while (TX_FIFO_LVL(val, sdd) && loops--);
Jassi Brar230d42d2009-11-30 07:39:42 +0000223
Mark Brownbe7852a2010-08-23 17:40:56 +0100224 if (loops == 0)
225 dev_warn(&sdd->pdev->dev, "Timed out flushing TX FIFO\n");
226
Jassi Brar230d42d2009-11-30 07:39:42 +0000227 /* Flush RxFIFO*/
228 loops = msecs_to_loops(1);
229 do {
230 val = readl(regs + S3C64XX_SPI_STATUS);
Thomas Abrahama5238e32012-07-13 07:15:14 +0900231 if (RX_FIFO_LVL(val, sdd))
Jassi Brar230d42d2009-11-30 07:39:42 +0000232 readl(regs + S3C64XX_SPI_RX_DATA);
233 else
234 break;
235 } while (loops--);
236
Mark Brownbe7852a2010-08-23 17:40:56 +0100237 if (loops == 0)
238 dev_warn(&sdd->pdev->dev, "Timed out flushing RX FIFO\n");
239
Jassi Brar230d42d2009-11-30 07:39:42 +0000240 val = readl(regs + S3C64XX_SPI_CH_CFG);
241 val &= ~S3C64XX_SPI_CH_SW_RST;
242 writel(val, regs + S3C64XX_SPI_CH_CFG);
243
244 val = readl(regs + S3C64XX_SPI_MODE_CFG);
245 val &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
246 writel(val, regs + S3C64XX_SPI_MODE_CFG);
Jassi Brar230d42d2009-11-30 07:39:42 +0000247}
248
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900249static void s3c64xx_spi_dmacb(void *data)
Boojin Kim39d3e802011-09-02 09:44:41 +0900250{
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900251 struct s3c64xx_spi_driver_data *sdd;
252 struct s3c64xx_spi_dma_data *dma = data;
Boojin Kim39d3e802011-09-02 09:44:41 +0900253 unsigned long flags;
254
Kyoungil Kim054ebcc2012-03-10 09:48:46 +0900255 if (dma->direction == DMA_DEV_TO_MEM)
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900256 sdd = container_of(data,
257 struct s3c64xx_spi_driver_data, rx_dma);
258 else
259 sdd = container_of(data,
260 struct s3c64xx_spi_driver_data, tx_dma);
261
Boojin Kim39d3e802011-09-02 09:44:41 +0900262 spin_lock_irqsave(&sdd->lock, flags);
263
Kyoungil Kim054ebcc2012-03-10 09:48:46 +0900264 if (dma->direction == DMA_DEV_TO_MEM) {
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900265 sdd->state &= ~RXBUSY;
266 if (!(sdd->state & TXBUSY))
267 complete(&sdd->xfer_completion);
268 } else {
269 sdd->state &= ~TXBUSY;
270 if (!(sdd->state & RXBUSY))
271 complete(&sdd->xfer_completion);
272 }
Boojin Kim39d3e802011-09-02 09:44:41 +0900273
274 spin_unlock_irqrestore(&sdd->lock, flags);
275}
276
Arnd Bergmann78843722013-04-11 22:42:03 +0200277static void prepare_dma(struct s3c64xx_spi_dma_data *dma,
Mark Brown6ad45a22014-02-02 13:47:47 +0000278 struct sg_table *sgt)
Arnd Bergmann78843722013-04-11 22:42:03 +0200279{
280 struct s3c64xx_spi_driver_data *sdd;
281 struct dma_slave_config config;
Arnd Bergmann78843722013-04-11 22:42:03 +0200282 struct dma_async_tx_descriptor *desc;
283
Tomasz Figab1a8e782013-08-11 02:33:28 +0200284 memset(&config, 0, sizeof(config));
285
Arnd Bergmann78843722013-04-11 22:42:03 +0200286 if (dma->direction == DMA_DEV_TO_MEM) {
287 sdd = container_of((void *)dma,
288 struct s3c64xx_spi_driver_data, rx_dma);
289 config.direction = dma->direction;
290 config.src_addr = sdd->sfr_start + S3C64XX_SPI_RX_DATA;
291 config.src_addr_width = sdd->cur_bpw / 8;
292 config.src_maxburst = 1;
293 dmaengine_slave_config(dma->ch, &config);
294 } else {
295 sdd = container_of((void *)dma,
296 struct s3c64xx_spi_driver_data, tx_dma);
297 config.direction = dma->direction;
298 config.dst_addr = sdd->sfr_start + S3C64XX_SPI_TX_DATA;
299 config.dst_addr_width = sdd->cur_bpw / 8;
300 config.dst_maxburst = 1;
301 dmaengine_slave_config(dma->ch, &config);
302 }
303
Mark Brown6ad45a22014-02-02 13:47:47 +0000304 desc = dmaengine_prep_slave_sg(dma->ch, sgt->sgl, sgt->nents,
305 dma->direction, DMA_PREP_INTERRUPT);
Arnd Bergmann78843722013-04-11 22:42:03 +0200306
307 desc->callback = s3c64xx_spi_dmacb;
308 desc->callback_param = dma;
309
310 dmaengine_submit(desc);
311 dma_async_issue_pending(dma->ch);
312}
313
314static int s3c64xx_spi_prepare_transfer(struct spi_master *spi)
315{
316 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
317 dma_filter_fn filter = sdd->cntrlr_info->filter;
318 struct device *dev = &sdd->pdev->dev;
319 dma_cap_mask_t mask;
Mark Brownfb9d0442013-04-18 18:12:00 +0100320 int ret;
Arnd Bergmann78843722013-04-11 22:42:03 +0200321
Mark Brownc12f9642013-08-13 19:03:01 +0100322 if (!is_polling(sdd)) {
323 dma_cap_zero(mask);
324 dma_cap_set(DMA_SLAVE, mask);
Girish K Sd96760f2013-06-27 12:26:53 +0530325
Mark Brownc12f9642013-08-13 19:03:01 +0100326 /* Acquire DMA channels */
327 sdd->rx_dma.ch = dma_request_slave_channel_compat(mask, filter,
Andre Przywara0744ea22015-02-23 12:30:46 +0000328 (void *)(long)sdd->rx_dma.dmach, dev, "rx");
Mark Brownc12f9642013-08-13 19:03:01 +0100329 if (!sdd->rx_dma.ch) {
330 dev_err(dev, "Failed to get RX DMA channel\n");
331 ret = -EBUSY;
332 goto out;
333 }
Mark Brown3f295882014-01-16 12:25:46 +0000334 spi->dma_rx = sdd->rx_dma.ch;
Arnd Bergmann78843722013-04-11 22:42:03 +0200335
Mark Brownc12f9642013-08-13 19:03:01 +0100336 sdd->tx_dma.ch = dma_request_slave_channel_compat(mask, filter,
Andre Przywara0744ea22015-02-23 12:30:46 +0000337 (void *)(long)sdd->tx_dma.dmach, dev, "tx");
Mark Brownc12f9642013-08-13 19:03:01 +0100338 if (!sdd->tx_dma.ch) {
339 dev_err(dev, "Failed to get TX DMA channel\n");
340 ret = -EBUSY;
341 goto out_rx;
342 }
Mark Brown3f295882014-01-16 12:25:46 +0000343 spi->dma_tx = sdd->tx_dma.ch;
Mark Brownfb9d0442013-04-18 18:12:00 +0100344 }
345
Arnd Bergmann78843722013-04-11 22:42:03 +0200346 return 0;
Mark Brownfb9d0442013-04-18 18:12:00 +0100347
Mark Brownfb9d0442013-04-18 18:12:00 +0100348out_rx:
349 dma_release_channel(sdd->rx_dma.ch);
350out:
351 return ret;
Arnd Bergmann78843722013-04-11 22:42:03 +0200352}
353
354static int s3c64xx_spi_unprepare_transfer(struct spi_master *spi)
355{
356 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
357
358 /* Free DMA channels */
Girish K S7e995552013-05-20 12:21:32 +0530359 if (!is_polling(sdd)) {
360 dma_release_channel(sdd->rx_dma.ch);
361 dma_release_channel(sdd->tx_dma.ch);
362 }
Arnd Bergmann78843722013-04-11 22:42:03 +0200363
Arnd Bergmann78843722013-04-11 22:42:03 +0200364 return 0;
365}
366
Mark Brown3f295882014-01-16 12:25:46 +0000367static bool s3c64xx_spi_can_dma(struct spi_master *master,
368 struct spi_device *spi,
369 struct spi_transfer *xfer)
370{
371 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
372
373 return xfer->len > (FIFO_LVL_MASK(sdd) >> 1) + 1;
374}
375
Jassi Brar230d42d2009-11-30 07:39:42 +0000376static void enable_datapath(struct s3c64xx_spi_driver_data *sdd,
377 struct spi_device *spi,
378 struct spi_transfer *xfer, int dma_mode)
379{
Jassi Brar230d42d2009-11-30 07:39:42 +0000380 void __iomem *regs = sdd->regs;
381 u32 modecfg, chcfg;
382
383 modecfg = readl(regs + S3C64XX_SPI_MODE_CFG);
384 modecfg &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
385
386 chcfg = readl(regs + S3C64XX_SPI_CH_CFG);
387 chcfg &= ~S3C64XX_SPI_CH_TXCH_ON;
388
389 if (dma_mode) {
390 chcfg &= ~S3C64XX_SPI_CH_RXCH_ON;
391 } else {
392 /* Always shift in data in FIFO, even if xfer is Tx only,
393 * this helps setting PCKT_CNT value for generating clocks
394 * as exactly needed.
395 */
396 chcfg |= S3C64XX_SPI_CH_RXCH_ON;
397 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
398 | S3C64XX_SPI_PACKET_CNT_EN,
399 regs + S3C64XX_SPI_PACKET_CNT);
400 }
401
402 if (xfer->tx_buf != NULL) {
403 sdd->state |= TXBUSY;
404 chcfg |= S3C64XX_SPI_CH_TXCH_ON;
405 if (dma_mode) {
406 modecfg |= S3C64XX_SPI_MODE_TXDMA_ON;
Mark Brown6ad45a22014-02-02 13:47:47 +0000407 prepare_dma(&sdd->tx_dma, &xfer->tx_sg);
Jassi Brar230d42d2009-11-30 07:39:42 +0000408 } else {
Jassi Brar0c92ecf2010-09-29 17:31:33 +0900409 switch (sdd->cur_bpw) {
410 case 32:
411 iowrite32_rep(regs + S3C64XX_SPI_TX_DATA,
412 xfer->tx_buf, xfer->len / 4);
413 break;
414 case 16:
415 iowrite16_rep(regs + S3C64XX_SPI_TX_DATA,
416 xfer->tx_buf, xfer->len / 2);
417 break;
418 default:
419 iowrite8_rep(regs + S3C64XX_SPI_TX_DATA,
420 xfer->tx_buf, xfer->len);
421 break;
422 }
Jassi Brar230d42d2009-11-30 07:39:42 +0000423 }
424 }
425
426 if (xfer->rx_buf != NULL) {
427 sdd->state |= RXBUSY;
428
Thomas Abrahama5238e32012-07-13 07:15:14 +0900429 if (sdd->port_conf->high_speed && sdd->cur_speed >= 30000000UL
Jassi Brar230d42d2009-11-30 07:39:42 +0000430 && !(sdd->cur_mode & SPI_CPHA))
431 chcfg |= S3C64XX_SPI_CH_HS_EN;
432
433 if (dma_mode) {
434 modecfg |= S3C64XX_SPI_MODE_RXDMA_ON;
435 chcfg |= S3C64XX_SPI_CH_RXCH_ON;
436 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
437 | S3C64XX_SPI_PACKET_CNT_EN,
438 regs + S3C64XX_SPI_PACKET_CNT);
Mark Brown6ad45a22014-02-02 13:47:47 +0000439 prepare_dma(&sdd->rx_dma, &xfer->rx_sg);
Jassi Brar230d42d2009-11-30 07:39:42 +0000440 }
441 }
442
443 writel(modecfg, regs + S3C64XX_SPI_MODE_CFG);
444 writel(chcfg, regs + S3C64XX_SPI_CH_CFG);
445}
446
Mark Brown79617072013-06-19 19:12:39 +0100447static u32 s3c64xx_spi_wait_for_timeout(struct s3c64xx_spi_driver_data *sdd,
Girish K S7e995552013-05-20 12:21:32 +0530448 int timeout_ms)
449{
450 void __iomem *regs = sdd->regs;
451 unsigned long val = 1;
452 u32 status;
453
454 /* max fifo depth available */
455 u32 max_fifo = (FIFO_LVL_MASK(sdd) >> 1) + 1;
456
457 if (timeout_ms)
458 val = msecs_to_loops(timeout_ms);
459
460 do {
461 status = readl(regs + S3C64XX_SPI_STATUS);
462 } while (RX_FIFO_LVL(status, sdd) < max_fifo && --val);
463
464 /* return the actual received data length */
465 return RX_FIFO_LVL(status, sdd);
Jassi Brar230d42d2009-11-30 07:39:42 +0000466}
467
Mark Brown3700c6e2014-01-24 20:05:43 +0000468static int wait_for_dma(struct s3c64xx_spi_driver_data *sdd,
469 struct spi_transfer *xfer)
Jassi Brar230d42d2009-11-30 07:39:42 +0000470{
Jassi Brar230d42d2009-11-30 07:39:42 +0000471 void __iomem *regs = sdd->regs;
472 unsigned long val;
Mark Brown3700c6e2014-01-24 20:05:43 +0000473 u32 status;
Jassi Brar230d42d2009-11-30 07:39:42 +0000474 int ms;
475
476 /* millisecs to xfer 'len' bytes @ 'cur_speed' */
477 ms = xfer->len * 8 * 1000 / sdd->cur_speed;
Mark Brown9d8f86b2010-09-07 16:37:52 +0100478 ms += 10; /* some tolerance */
Jassi Brar230d42d2009-11-30 07:39:42 +0000479
Mark Brown3700c6e2014-01-24 20:05:43 +0000480 val = msecs_to_jiffies(ms) + 10;
481 val = wait_for_completion_timeout(&sdd->xfer_completion, val);
482
483 /*
484 * If the previous xfer was completed within timeout, then
485 * proceed further else return -EIO.
486 * DmaTx returns after simply writing data in the FIFO,
487 * w/o waiting for real transmission on the bus to finish.
488 * DmaRx returns only after Dma read data from FIFO which
489 * needs bus transmission to finish, so we don't worry if
490 * Xfer involved Rx(with or without Tx).
491 */
492 if (val && !xfer->rx_buf) {
493 val = msecs_to_loops(10);
494 status = readl(regs + S3C64XX_SPI_STATUS);
495 while ((TX_FIFO_LVL(status, sdd)
496 || !S3C64XX_SPI_ST_TX_DONE(status, sdd))
497 && --val) {
498 cpu_relax();
Jassi Brarc3f139b2010-09-03 10:36:46 +0900499 status = readl(regs + S3C64XX_SPI_STATUS);
Jassi Brar230d42d2009-11-30 07:39:42 +0000500 }
Girish K S7e995552013-05-20 12:21:32 +0530501
Mark Brown3700c6e2014-01-24 20:05:43 +0000502 }
Girish K S7e995552013-05-20 12:21:32 +0530503
Mark Brown3700c6e2014-01-24 20:05:43 +0000504 /* If timed out while checking rx/tx status return error */
505 if (!val)
506 return -EIO;
507
508 return 0;
509}
510
511static int wait_for_pio(struct s3c64xx_spi_driver_data *sdd,
512 struct spi_transfer *xfer)
513{
514 void __iomem *regs = sdd->regs;
515 unsigned long val;
516 u32 status;
517 int loops;
518 u32 cpy_len;
519 u8 *buf;
520 int ms;
521
522 /* millisecs to xfer 'len' bytes @ 'cur_speed' */
523 ms = xfer->len * 8 * 1000 / sdd->cur_speed;
524 ms += 10; /* some tolerance */
525
526 val = msecs_to_loops(ms);
527 do {
528 status = readl(regs + S3C64XX_SPI_STATUS);
529 } while (RX_FIFO_LVL(status, sdd) < xfer->len && --val);
530
531
532 /* If it was only Tx */
533 if (!xfer->rx_buf) {
534 sdd->state &= ~TXBUSY;
535 return 0;
536 }
537
538 /*
539 * If the receive length is bigger than the controller fifo
540 * size, calculate the loops and read the fifo as many times.
541 * loops = length / max fifo size (calculated by using the
542 * fifo mask).
543 * For any size less than the fifo size the below code is
544 * executed atleast once.
545 */
546 loops = xfer->len / ((FIFO_LVL_MASK(sdd) >> 1) + 1);
547 buf = xfer->rx_buf;
548 do {
549 /* wait for data to be received in the fifo */
550 cpy_len = s3c64xx_spi_wait_for_timeout(sdd,
551 (loops ? ms : 0));
552
553 switch (sdd->cur_bpw) {
554 case 32:
555 ioread32_rep(regs + S3C64XX_SPI_RX_DATA,
556 buf, cpy_len / 4);
557 break;
558 case 16:
559 ioread16_rep(regs + S3C64XX_SPI_RX_DATA,
560 buf, cpy_len / 2);
561 break;
562 default:
563 ioread8_rep(regs + S3C64XX_SPI_RX_DATA,
564 buf, cpy_len);
565 break;
Jassi Brar230d42d2009-11-30 07:39:42 +0000566 }
567
Mark Brown3700c6e2014-01-24 20:05:43 +0000568 buf = buf + cpy_len;
569 } while (loops--);
570 sdd->state &= ~RXBUSY;
Jassi Brar230d42d2009-11-30 07:39:42 +0000571
572 return 0;
573}
574
Jassi Brar230d42d2009-11-30 07:39:42 +0000575static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)
576{
Jassi Brar230d42d2009-11-30 07:39:42 +0000577 void __iomem *regs = sdd->regs;
578 u32 val;
579
580 /* Disable Clock */
Thomas Abrahama5238e32012-07-13 07:15:14 +0900581 if (sdd->port_conf->clk_from_cmu) {
Thomas Abraham9f667bf2012-10-03 08:30:12 +0900582 clk_disable_unprepare(sdd->src_clk);
Jassi Brarb42a81c2010-09-29 17:31:33 +0900583 } else {
584 val = readl(regs + S3C64XX_SPI_CLK_CFG);
585 val &= ~S3C64XX_SPI_ENCLK_ENABLE;
586 writel(val, regs + S3C64XX_SPI_CLK_CFG);
587 }
Jassi Brar230d42d2009-11-30 07:39:42 +0000588
589 /* Set Polarity and Phase */
590 val = readl(regs + S3C64XX_SPI_CH_CFG);
591 val &= ~(S3C64XX_SPI_CH_SLAVE |
592 S3C64XX_SPI_CPOL_L |
593 S3C64XX_SPI_CPHA_B);
594
595 if (sdd->cur_mode & SPI_CPOL)
596 val |= S3C64XX_SPI_CPOL_L;
597
598 if (sdd->cur_mode & SPI_CPHA)
599 val |= S3C64XX_SPI_CPHA_B;
600
601 writel(val, regs + S3C64XX_SPI_CH_CFG);
602
603 /* Set Channel & DMA Mode */
604 val = readl(regs + S3C64XX_SPI_MODE_CFG);
605 val &= ~(S3C64XX_SPI_MODE_BUS_TSZ_MASK
606 | S3C64XX_SPI_MODE_CH_TSZ_MASK);
607
608 switch (sdd->cur_bpw) {
609 case 32:
610 val |= S3C64XX_SPI_MODE_BUS_TSZ_WORD;
Jassi Brar0c92ecf2010-09-29 17:31:33 +0900611 val |= S3C64XX_SPI_MODE_CH_TSZ_WORD;
Jassi Brar230d42d2009-11-30 07:39:42 +0000612 break;
613 case 16:
614 val |= S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD;
Jassi Brar0c92ecf2010-09-29 17:31:33 +0900615 val |= S3C64XX_SPI_MODE_CH_TSZ_HALFWORD;
Jassi Brar230d42d2009-11-30 07:39:42 +0000616 break;
617 default:
618 val |= S3C64XX_SPI_MODE_BUS_TSZ_BYTE;
Jassi Brar0c92ecf2010-09-29 17:31:33 +0900619 val |= S3C64XX_SPI_MODE_CH_TSZ_BYTE;
Jassi Brar230d42d2009-11-30 07:39:42 +0000620 break;
621 }
Jassi Brar230d42d2009-11-30 07:39:42 +0000622
623 writel(val, regs + S3C64XX_SPI_MODE_CFG);
624
Thomas Abrahama5238e32012-07-13 07:15:14 +0900625 if (sdd->port_conf->clk_from_cmu) {
Jassi Brarb42a81c2010-09-29 17:31:33 +0900626 /* Configure Clock */
627 /* There is half-multiplier before the SPI */
628 clk_set_rate(sdd->src_clk, sdd->cur_speed * 2);
629 /* Enable Clock */
Thomas Abraham9f667bf2012-10-03 08:30:12 +0900630 clk_prepare_enable(sdd->src_clk);
Jassi Brarb42a81c2010-09-29 17:31:33 +0900631 } else {
632 /* Configure Clock */
633 val = readl(regs + S3C64XX_SPI_CLK_CFG);
634 val &= ~S3C64XX_SPI_PSR_MASK;
635 val |= ((clk_get_rate(sdd->src_clk) / sdd->cur_speed / 2 - 1)
636 & S3C64XX_SPI_PSR_MASK);
637 writel(val, regs + S3C64XX_SPI_CLK_CFG);
Jassi Brar230d42d2009-11-30 07:39:42 +0000638
Jassi Brarb42a81c2010-09-29 17:31:33 +0900639 /* Enable Clock */
640 val = readl(regs + S3C64XX_SPI_CLK_CFG);
641 val |= S3C64XX_SPI_ENCLK_ENABLE;
642 writel(val, regs + S3C64XX_SPI_CLK_CFG);
643 }
Jassi Brar230d42d2009-11-30 07:39:42 +0000644}
645
Jassi Brar230d42d2009-11-30 07:39:42 +0000646#define XFER_DMAADDR_INVALID DMA_BIT_MASK(32)
647
Mark Brown6bb9c0e2013-10-05 00:42:58 +0100648static int s3c64xx_spi_prepare_message(struct spi_master *master,
649 struct spi_message *msg)
Jassi Brar230d42d2009-11-30 07:39:42 +0000650{
Mark Brownad2a99a2012-02-15 14:48:32 -0800651 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
Jassi Brar230d42d2009-11-30 07:39:42 +0000652 struct spi_device *spi = msg->spi;
653 struct s3c64xx_spi_csinfo *cs = spi->controller_data;
Jassi Brar230d42d2009-11-30 07:39:42 +0000654
655 /* If Master's(controller) state differs from that needed by Slave */
656 if (sdd->cur_speed != spi->max_speed_hz
657 || sdd->cur_mode != spi->mode
658 || sdd->cur_bpw != spi->bits_per_word) {
659 sdd->cur_bpw = spi->bits_per_word;
660 sdd->cur_speed = spi->max_speed_hz;
661 sdd->cur_mode = spi->mode;
662 s3c64xx_spi_config(sdd);
663 }
664
Jassi Brar230d42d2009-11-30 07:39:42 +0000665 /* Configure feedback delay */
666 writel(cs->fb_delay & 0x3, sdd->regs + S3C64XX_SPI_FB_CLK);
667
Mark Brown6bb9c0e2013-10-05 00:42:58 +0100668 return 0;
669}
Jassi Brar230d42d2009-11-30 07:39:42 +0000670
Mark Brown0732a9d2013-10-05 11:51:14 +0100671static int s3c64xx_spi_transfer_one(struct spi_master *master,
672 struct spi_device *spi,
673 struct spi_transfer *xfer)
Mark Brown6bb9c0e2013-10-05 00:42:58 +0100674{
675 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
Mark Brown0732a9d2013-10-05 11:51:14 +0100676 int status;
Mark Brown6bb9c0e2013-10-05 00:42:58 +0100677 u32 speed;
678 u8 bpw;
Mark Brown0732a9d2013-10-05 11:51:14 +0100679 unsigned long flags;
680 int use_dma;
Jassi Brar230d42d2009-11-30 07:39:42 +0000681
Geert Uytterhoeven3e83c192014-01-12 14:07:50 +0100682 reinit_completion(&sdd->xfer_completion);
Jassi Brar230d42d2009-11-30 07:39:42 +0000683
Mark Brown0732a9d2013-10-05 11:51:14 +0100684 /* Only BPW and Speed may change across transfers */
685 bpw = xfer->bits_per_word;
686 speed = xfer->speed_hz ? : spi->max_speed_hz;
Jassi Brar230d42d2009-11-30 07:39:42 +0000687
Mark Brown0732a9d2013-10-05 11:51:14 +0100688 if (bpw != sdd->cur_bpw || speed != sdd->cur_speed) {
689 sdd->cur_bpw = bpw;
690 sdd->cur_speed = speed;
691 s3c64xx_spi_config(sdd);
692 }
693
694 /* Polling method for xfers not bigger than FIFO capacity */
695 use_dma = 0;
696 if (!is_polling(sdd) &&
697 (sdd->rx_dma.ch && sdd->tx_dma.ch &&
698 (xfer->len > ((FIFO_LVL_MASK(sdd) >> 1) + 1))))
699 use_dma = 1;
700
701 spin_lock_irqsave(&sdd->lock, flags);
702
703 /* Pending only which is to be done */
704 sdd->state &= ~RXBUSY;
705 sdd->state &= ~TXBUSY;
706
707 enable_datapath(sdd, spi, xfer, use_dma);
708
709 /* Start the signals */
Padmavathi Vennabf77cba2014-11-06 15:21:49 +0530710 if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO))
711 writel(0, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
712 else
713 writel(readl(sdd->regs + S3C64XX_SPI_SLAVE_SEL)
714 | S3C64XX_SPI_SLAVE_AUTO | S3C64XX_SPI_SLAVE_NSC_CNT_2,
715 sdd->regs + S3C64XX_SPI_SLAVE_SEL);
Mark Brown0732a9d2013-10-05 11:51:14 +0100716
Mark Brown0732a9d2013-10-05 11:51:14 +0100717 spin_unlock_irqrestore(&sdd->lock, flags);
718
Mark Brown3700c6e2014-01-24 20:05:43 +0000719 if (use_dma)
720 status = wait_for_dma(sdd, xfer);
721 else
722 status = wait_for_pio(sdd, xfer);
Mark Brown0732a9d2013-10-05 11:51:14 +0100723
724 if (status) {
725 dev_err(&spi->dev, "I/O Error: rx-%d tx-%d res:rx-%c tx-%c len-%d\n",
726 xfer->rx_buf ? 1 : 0, xfer->tx_buf ? 1 : 0,
727 (sdd->state & RXBUSY) ? 'f' : 'p',
728 (sdd->state & TXBUSY) ? 'f' : 'p',
729 xfer->len);
730
731 if (use_dma) {
732 if (xfer->tx_buf != NULL
733 && (sdd->state & TXBUSY))
Mark Brown1b5e1b62014-02-07 12:39:22 +0000734 dmaengine_terminate_all(sdd->tx_dma.ch);
Mark Brown0732a9d2013-10-05 11:51:14 +0100735 if (xfer->rx_buf != NULL
736 && (sdd->state & RXBUSY))
Mark Brown1b5e1b62014-02-07 12:39:22 +0000737 dmaengine_terminate_all(sdd->rx_dma.ch);
Jassi Brar0c92ecf2010-09-29 17:31:33 +0900738 }
Mark Brown8c09daa2013-09-27 19:56:31 +0100739 } else {
Jassi Brar230d42d2009-11-30 07:39:42 +0000740 flush_fifo(sdd);
741 }
742
Mark Brown0732a9d2013-10-05 11:51:14 +0100743 return status;
Jassi Brar230d42d2009-11-30 07:39:42 +0000744}
745
Thomas Abraham2b908072012-07-13 07:15:15 +0900746static struct s3c64xx_spi_csinfo *s3c64xx_get_slave_ctrldata(
Thomas Abraham2b908072012-07-13 07:15:15 +0900747 struct spi_device *spi)
748{
749 struct s3c64xx_spi_csinfo *cs;
Arnd Bergmann4732cc62012-08-04 11:18:20 +0000750 struct device_node *slave_np, *data_np = NULL;
Thomas Abraham2b908072012-07-13 07:15:15 +0900751 u32 fb_delay = 0;
752
753 slave_np = spi->dev.of_node;
754 if (!slave_np) {
755 dev_err(&spi->dev, "device node not found\n");
756 return ERR_PTR(-EINVAL);
757 }
758
Srinivas Kandagatla06455bb2012-09-18 08:10:49 +0100759 data_np = of_get_child_by_name(slave_np, "controller-data");
Thomas Abraham2b908072012-07-13 07:15:15 +0900760 if (!data_np) {
761 dev_err(&spi->dev, "child node 'controller-data' not found\n");
762 return ERR_PTR(-EINVAL);
763 }
764
765 cs = kzalloc(sizeof(*cs), GFP_KERNEL);
766 if (!cs) {
Srinivas Kandagatla06455bb2012-09-18 08:10:49 +0100767 of_node_put(data_np);
Thomas Abraham2b908072012-07-13 07:15:15 +0900768 return ERR_PTR(-ENOMEM);
769 }
770
Thomas Abraham2b908072012-07-13 07:15:15 +0900771 of_property_read_u32(data_np, "samsung,spi-feedback-delay", &fb_delay);
772 cs->fb_delay = fb_delay;
Srinivas Kandagatla06455bb2012-09-18 08:10:49 +0100773 of_node_put(data_np);
Thomas Abraham2b908072012-07-13 07:15:15 +0900774 return cs;
775}
776
Jassi Brar230d42d2009-11-30 07:39:42 +0000777/*
778 * Here we only check the validity of requested configuration
779 * and save the configuration in a local data-structure.
780 * The controller is actually configured only just before we
781 * get a message to transfer.
782 */
783static int s3c64xx_spi_setup(struct spi_device *spi)
784{
785 struct s3c64xx_spi_csinfo *cs = spi->controller_data;
786 struct s3c64xx_spi_driver_data *sdd;
Jassi Brarad7de722010-01-20 13:49:44 -0700787 struct s3c64xx_spi_info *sci;
Thomas Abraham2b908072012-07-13 07:15:15 +0900788 int err;
Jassi Brar230d42d2009-11-30 07:39:42 +0000789
Thomas Abraham2b908072012-07-13 07:15:15 +0900790 sdd = spi_master_get_devdata(spi->master);
Naveen Krishna Chatradhi306972c2014-07-16 17:19:08 +0200791 if (spi->dev.of_node) {
Matthias Brugger5c725b32013-03-26 10:27:35 +0100792 cs = s3c64xx_get_slave_ctrldata(spi);
Thomas Abraham2b908072012-07-13 07:15:15 +0900793 spi->controller_data = cs;
Naveen Krishna Chatradhi306972c2014-07-16 17:19:08 +0200794 } else if (cs) {
795 /* On non-DT platforms the SPI core will set spi->cs_gpio
796 * to -ENOENT. The GPIO pin used to drive the chip select
797 * is defined by using platform data so spi->cs_gpio value
798 * has to be override to have the proper GPIO pin number.
799 */
800 spi->cs_gpio = cs->line;
Thomas Abraham2b908072012-07-13 07:15:15 +0900801 }
802
803 if (IS_ERR_OR_NULL(cs)) {
Jassi Brar230d42d2009-11-30 07:39:42 +0000804 dev_err(&spi->dev, "No CS for SPI(%d)\n", spi->chip_select);
805 return -ENODEV;
806 }
807
Tomasz Figa01498712013-08-11 02:33:29 +0200808 if (!spi_get_ctldata(spi)) {
Naveen Krishna Chatradhi306972c2014-07-16 17:19:08 +0200809 if (gpio_is_valid(spi->cs_gpio)) {
810 err = gpio_request_one(spi->cs_gpio, GPIOF_OUT_INIT_HIGH,
811 dev_name(&spi->dev));
812 if (err) {
813 dev_err(&spi->dev,
814 "Failed to get /CS gpio [%d]: %d\n",
815 spi->cs_gpio, err);
816 goto err_gpio_req;
817 }
Thomas Abraham1c20c202012-07-13 07:15:14 +0900818 }
Thomas Abraham1c20c202012-07-13 07:15:14 +0900819
Girish K S3146bee2013-06-21 11:26:12 +0530820 spi_set_ctldata(spi, cs);
Tomasz Figa01498712013-08-11 02:33:29 +0200821 }
Girish K S3146bee2013-06-21 11:26:12 +0530822
Jassi Brar230d42d2009-11-30 07:39:42 +0000823 sci = sdd->cntrlr_info;
824
Mark Brownb97b6622011-12-04 00:58:06 +0000825 pm_runtime_get_sync(&sdd->pdev->dev);
826
Jassi Brar230d42d2009-11-30 07:39:42 +0000827 /* Check if we can provide the requested rate */
Thomas Abrahama5238e32012-07-13 07:15:14 +0900828 if (!sdd->port_conf->clk_from_cmu) {
Jassi Brarb42a81c2010-09-29 17:31:33 +0900829 u32 psr, speed;
Jassi Brar230d42d2009-11-30 07:39:42 +0000830
Jassi Brarb42a81c2010-09-29 17:31:33 +0900831 /* Max possible */
832 speed = clk_get_rate(sdd->src_clk) / 2 / (0 + 1);
Jassi Brar230d42d2009-11-30 07:39:42 +0000833
Jassi Brarb42a81c2010-09-29 17:31:33 +0900834 if (spi->max_speed_hz > speed)
835 spi->max_speed_hz = speed;
Jassi Brar230d42d2009-11-30 07:39:42 +0000836
Jassi Brarb42a81c2010-09-29 17:31:33 +0900837 psr = clk_get_rate(sdd->src_clk) / 2 / spi->max_speed_hz - 1;
838 psr &= S3C64XX_SPI_PSR_MASK;
839 if (psr == S3C64XX_SPI_PSR_MASK)
840 psr--;
841
842 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1);
843 if (spi->max_speed_hz < speed) {
844 if (psr+1 < S3C64XX_SPI_PSR_MASK) {
845 psr++;
846 } else {
847 err = -EINVAL;
848 goto setup_exit;
849 }
Jassi Brar230d42d2009-11-30 07:39:42 +0000850 }
Jassi Brar230d42d2009-11-30 07:39:42 +0000851
Jassi Brarb42a81c2010-09-29 17:31:33 +0900852 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1);
Thomas Abraham2b908072012-07-13 07:15:15 +0900853 if (spi->max_speed_hz >= speed) {
Jassi Brarb42a81c2010-09-29 17:31:33 +0900854 spi->max_speed_hz = speed;
Thomas Abraham2b908072012-07-13 07:15:15 +0900855 } else {
Mark Browne1b0f0d2012-12-20 18:27:31 +0000856 dev_err(&spi->dev, "Can't set %dHz transfer speed\n",
857 spi->max_speed_hz);
Jassi Brarb42a81c2010-09-29 17:31:33 +0900858 err = -EINVAL;
Thomas Abraham2b908072012-07-13 07:15:15 +0900859 goto setup_exit;
860 }
Jassi Brarb42a81c2010-09-29 17:31:33 +0900861 }
Jassi Brar230d42d2009-11-30 07:39:42 +0000862
Heiner Kallweit483867e2015-09-03 22:39:36 +0200863 pm_runtime_mark_last_busy(&sdd->pdev->dev);
864 pm_runtime_put_autosuspend(&sdd->pdev->dev);
Padmavathi Vennabf77cba2014-11-06 15:21:49 +0530865 if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO))
866 writel(S3C64XX_SPI_SLAVE_SIG_INACT, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
Thomas Abraham2b908072012-07-13 07:15:15 +0900867 return 0;
Mark Brownb97b6622011-12-04 00:58:06 +0000868
Jassi Brar230d42d2009-11-30 07:39:42 +0000869setup_exit:
Heiner Kallweit483867e2015-09-03 22:39:36 +0200870 pm_runtime_mark_last_busy(&sdd->pdev->dev);
871 pm_runtime_put_autosuspend(&sdd->pdev->dev);
Jassi Brar230d42d2009-11-30 07:39:42 +0000872 /* setup() returns with device de-selected */
Padmavathi Vennabf77cba2014-11-06 15:21:49 +0530873 if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO))
874 writel(S3C64XX_SPI_SLAVE_SIG_INACT, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
Jassi Brar230d42d2009-11-30 07:39:42 +0000875
Naveen Krishna Chatradhi306972c2014-07-16 17:19:08 +0200876 if (gpio_is_valid(spi->cs_gpio))
877 gpio_free(spi->cs_gpio);
Thomas Abraham2b908072012-07-13 07:15:15 +0900878 spi_set_ctldata(spi, NULL);
879
880err_gpio_req:
Sylwester Nawrocki5bee3b92012-09-13 16:31:30 +0200881 if (spi->dev.of_node)
882 kfree(cs);
Thomas Abraham2b908072012-07-13 07:15:15 +0900883
Jassi Brar230d42d2009-11-30 07:39:42 +0000884 return err;
885}
886
Thomas Abraham1c20c202012-07-13 07:15:14 +0900887static void s3c64xx_spi_cleanup(struct spi_device *spi)
888{
889 struct s3c64xx_spi_csinfo *cs = spi_get_ctldata(spi);
890
Naveen Krishna Chatradhi306972c2014-07-16 17:19:08 +0200891 if (gpio_is_valid(spi->cs_gpio)) {
Mark Browndd97e262013-09-27 18:58:55 +0100892 gpio_free(spi->cs_gpio);
Thomas Abraham2b908072012-07-13 07:15:15 +0900893 if (spi->dev.of_node)
894 kfree(cs);
Naveen Krishna Chatradhi306972c2014-07-16 17:19:08 +0200895 else {
896 /* On non-DT platforms, the SPI core sets
897 * spi->cs_gpio to -ENOENT and .setup()
898 * overrides it with the GPIO pin value
899 * passed using platform data.
900 */
901 spi->cs_gpio = -ENOENT;
902 }
Thomas Abraham2b908072012-07-13 07:15:15 +0900903 }
Naveen Krishna Chatradhi306972c2014-07-16 17:19:08 +0200904
Thomas Abraham1c20c202012-07-13 07:15:14 +0900905 spi_set_ctldata(spi, NULL);
906}
907
Mark Brownc2573122011-11-10 10:57:32 +0000908static irqreturn_t s3c64xx_spi_irq(int irq, void *data)
909{
910 struct s3c64xx_spi_driver_data *sdd = data;
911 struct spi_master *spi = sdd->master;
Girish K S375981f2013-03-13 12:13:30 +0530912 unsigned int val, clr = 0;
Mark Brownc2573122011-11-10 10:57:32 +0000913
Girish K S375981f2013-03-13 12:13:30 +0530914 val = readl(sdd->regs + S3C64XX_SPI_STATUS);
Mark Brownc2573122011-11-10 10:57:32 +0000915
Girish K S375981f2013-03-13 12:13:30 +0530916 if (val & S3C64XX_SPI_ST_RX_OVERRUN_ERR) {
917 clr = S3C64XX_SPI_PND_RX_OVERRUN_CLR;
Mark Brownc2573122011-11-10 10:57:32 +0000918 dev_err(&spi->dev, "RX overrun\n");
Girish K S375981f2013-03-13 12:13:30 +0530919 }
920 if (val & S3C64XX_SPI_ST_RX_UNDERRUN_ERR) {
921 clr |= S3C64XX_SPI_PND_RX_UNDERRUN_CLR;
Mark Brownc2573122011-11-10 10:57:32 +0000922 dev_err(&spi->dev, "RX underrun\n");
Girish K S375981f2013-03-13 12:13:30 +0530923 }
924 if (val & S3C64XX_SPI_ST_TX_OVERRUN_ERR) {
925 clr |= S3C64XX_SPI_PND_TX_OVERRUN_CLR;
Mark Brownc2573122011-11-10 10:57:32 +0000926 dev_err(&spi->dev, "TX overrun\n");
Girish K S375981f2013-03-13 12:13:30 +0530927 }
928 if (val & S3C64XX_SPI_ST_TX_UNDERRUN_ERR) {
929 clr |= S3C64XX_SPI_PND_TX_UNDERRUN_CLR;
Mark Brownc2573122011-11-10 10:57:32 +0000930 dev_err(&spi->dev, "TX underrun\n");
Girish K S375981f2013-03-13 12:13:30 +0530931 }
932
933 /* Clear the pending irq by setting and then clearing it */
934 writel(clr, sdd->regs + S3C64XX_SPI_PENDING_CLR);
935 writel(0, sdd->regs + S3C64XX_SPI_PENDING_CLR);
Mark Brownc2573122011-11-10 10:57:32 +0000936
937 return IRQ_HANDLED;
938}
939
Jassi Brar230d42d2009-11-30 07:39:42 +0000940static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd, int channel)
941{
Jassi Brarad7de722010-01-20 13:49:44 -0700942 struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
Jassi Brar230d42d2009-11-30 07:39:42 +0000943 void __iomem *regs = sdd->regs;
944 unsigned int val;
945
946 sdd->cur_speed = 0;
947
Padmavathi Vennabf77cba2014-11-06 15:21:49 +0530948 if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO))
949 writel(S3C64XX_SPI_SLAVE_SIG_INACT, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
Jassi Brar230d42d2009-11-30 07:39:42 +0000950
951 /* Disable Interrupts - we use Polling if not DMA mode */
952 writel(0, regs + S3C64XX_SPI_INT_EN);
953
Thomas Abrahama5238e32012-07-13 07:15:14 +0900954 if (!sdd->port_conf->clk_from_cmu)
Jassi Brarb42a81c2010-09-29 17:31:33 +0900955 writel(sci->src_clk_nr << S3C64XX_SPI_CLKSEL_SRCSHFT,
Jassi Brar230d42d2009-11-30 07:39:42 +0000956 regs + S3C64XX_SPI_CLK_CFG);
957 writel(0, regs + S3C64XX_SPI_MODE_CFG);
958 writel(0, regs + S3C64XX_SPI_PACKET_CNT);
959
Girish K S375981f2013-03-13 12:13:30 +0530960 /* Clear any irq pending bits, should set and clear the bits */
961 val = S3C64XX_SPI_PND_RX_OVERRUN_CLR |
962 S3C64XX_SPI_PND_RX_UNDERRUN_CLR |
963 S3C64XX_SPI_PND_TX_OVERRUN_CLR |
964 S3C64XX_SPI_PND_TX_UNDERRUN_CLR;
965 writel(val, regs + S3C64XX_SPI_PENDING_CLR);
966 writel(0, regs + S3C64XX_SPI_PENDING_CLR);
Jassi Brar230d42d2009-11-30 07:39:42 +0000967
968 writel(0, regs + S3C64XX_SPI_SWAP_CFG);
969
970 val = readl(regs + S3C64XX_SPI_MODE_CFG);
971 val &= ~S3C64XX_SPI_MODE_4BURST;
972 val &= ~(S3C64XX_SPI_MAX_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
973 val |= (S3C64XX_SPI_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
974 writel(val, regs + S3C64XX_SPI_MODE_CFG);
975
976 flush_fifo(sdd);
977}
978
Thomas Abraham2b908072012-07-13 07:15:15 +0900979#ifdef CONFIG_OF
Jingoo Han75bf3362013-01-31 15:25:01 +0900980static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev)
Thomas Abraham2b908072012-07-13 07:15:15 +0900981{
982 struct s3c64xx_spi_info *sci;
983 u32 temp;
984
985 sci = devm_kzalloc(dev, sizeof(*sci), GFP_KERNEL);
Jingoo Han1273eb02014-04-29 17:20:20 +0900986 if (!sci)
Thomas Abraham2b908072012-07-13 07:15:15 +0900987 return ERR_PTR(-ENOMEM);
Thomas Abraham2b908072012-07-13 07:15:15 +0900988
989 if (of_property_read_u32(dev->of_node, "samsung,spi-src-clk", &temp)) {
Jingoo Han75bf3362013-01-31 15:25:01 +0900990 dev_warn(dev, "spi bus clock parent not specified, using clock at index 0 as parent\n");
Thomas Abraham2b908072012-07-13 07:15:15 +0900991 sci->src_clk_nr = 0;
992 } else {
993 sci->src_clk_nr = temp;
994 }
995
996 if (of_property_read_u32(dev->of_node, "num-cs", &temp)) {
Jingoo Han75bf3362013-01-31 15:25:01 +0900997 dev_warn(dev, "number of chip select lines not specified, assuming 1 chip select line\n");
Thomas Abraham2b908072012-07-13 07:15:15 +0900998 sci->num_cs = 1;
999 } else {
1000 sci->num_cs = temp;
1001 }
1002
1003 return sci;
1004}
1005#else
1006static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev)
1007{
Jingoo Han8074cf02013-07-30 16:58:59 +09001008 return dev_get_platdata(dev);
Thomas Abraham2b908072012-07-13 07:15:15 +09001009}
Thomas Abraham2b908072012-07-13 07:15:15 +09001010#endif
1011
1012static const struct of_device_id s3c64xx_spi_dt_match[];
1013
Thomas Abrahama5238e32012-07-13 07:15:14 +09001014static inline struct s3c64xx_spi_port_config *s3c64xx_spi_get_port_config(
1015 struct platform_device *pdev)
1016{
Thomas Abraham2b908072012-07-13 07:15:15 +09001017#ifdef CONFIG_OF
1018 if (pdev->dev.of_node) {
1019 const struct of_device_id *match;
1020 match = of_match_node(s3c64xx_spi_dt_match, pdev->dev.of_node);
1021 return (struct s3c64xx_spi_port_config *)match->data;
1022 }
1023#endif
Thomas Abrahama5238e32012-07-13 07:15:14 +09001024 return (struct s3c64xx_spi_port_config *)
1025 platform_get_device_id(pdev)->driver_data;
1026}
1027
Grant Likely2deff8d2013-02-05 13:27:35 +00001028static int s3c64xx_spi_probe(struct platform_device *pdev)
Jassi Brar230d42d2009-11-30 07:39:42 +00001029{
Thomas Abraham2b908072012-07-13 07:15:15 +09001030 struct resource *mem_res;
Padmavathi Vennab5be04d2013-01-18 17:17:03 +05301031 struct resource *res;
Jassi Brar230d42d2009-11-30 07:39:42 +00001032 struct s3c64xx_spi_driver_data *sdd;
Jingoo Han8074cf02013-07-30 16:58:59 +09001033 struct s3c64xx_spi_info *sci = dev_get_platdata(&pdev->dev);
Jassi Brar230d42d2009-11-30 07:39:42 +00001034 struct spi_master *master;
Mark Brownc2573122011-11-10 10:57:32 +00001035 int ret, irq;
Padmavathi Vennaa24d8502011-11-02 20:04:19 +09001036 char clk_name[16];
Jassi Brar230d42d2009-11-30 07:39:42 +00001037
Thomas Abraham2b908072012-07-13 07:15:15 +09001038 if (!sci && pdev->dev.of_node) {
1039 sci = s3c64xx_spi_parse_dt(&pdev->dev);
1040 if (IS_ERR(sci))
1041 return PTR_ERR(sci);
Jassi Brar230d42d2009-11-30 07:39:42 +00001042 }
1043
Thomas Abraham2b908072012-07-13 07:15:15 +09001044 if (!sci) {
Jassi Brar230d42d2009-11-30 07:39:42 +00001045 dev_err(&pdev->dev, "platform_data missing!\n");
1046 return -ENODEV;
1047 }
1048
Jassi Brar230d42d2009-11-30 07:39:42 +00001049 mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1050 if (mem_res == NULL) {
1051 dev_err(&pdev->dev, "Unable to get SPI MEM resource\n");
1052 return -ENXIO;
1053 }
1054
Mark Brownc2573122011-11-10 10:57:32 +00001055 irq = platform_get_irq(pdev, 0);
1056 if (irq < 0) {
1057 dev_warn(&pdev->dev, "Failed to get IRQ: %d\n", irq);
1058 return irq;
1059 }
1060
Jassi Brar230d42d2009-11-30 07:39:42 +00001061 master = spi_alloc_master(&pdev->dev,
1062 sizeof(struct s3c64xx_spi_driver_data));
1063 if (master == NULL) {
1064 dev_err(&pdev->dev, "Unable to allocate SPI Master\n");
1065 return -ENOMEM;
1066 }
1067
Jassi Brar230d42d2009-11-30 07:39:42 +00001068 platform_set_drvdata(pdev, master);
1069
1070 sdd = spi_master_get_devdata(master);
Thomas Abrahama5238e32012-07-13 07:15:14 +09001071 sdd->port_conf = s3c64xx_spi_get_port_config(pdev);
Jassi Brar230d42d2009-11-30 07:39:42 +00001072 sdd->master = master;
1073 sdd->cntrlr_info = sci;
1074 sdd->pdev = pdev;
1075 sdd->sfr_start = mem_res->start;
Thomas Abraham2b908072012-07-13 07:15:15 +09001076 if (pdev->dev.of_node) {
1077 ret = of_alias_get_id(pdev->dev.of_node, "spi");
1078 if (ret < 0) {
Jingoo Han75bf3362013-01-31 15:25:01 +09001079 dev_err(&pdev->dev, "failed to get alias id, errno %d\n",
1080 ret);
Thomas Abraham2b908072012-07-13 07:15:15 +09001081 goto err0;
1082 }
1083 sdd->port_id = ret;
1084 } else {
1085 sdd->port_id = pdev->id;
1086 }
Jassi Brar230d42d2009-11-30 07:39:42 +00001087
1088 sdd->cur_bpw = 8;
1089
Padmavathi Vennab5be04d2013-01-18 17:17:03 +05301090 if (!sdd->pdev->dev.of_node) {
1091 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1092 if (!res) {
Jingoo Handb0606e2013-07-15 15:11:57 +09001093 dev_warn(&pdev->dev, "Unable to get SPI tx dma resource. Switching to poll mode\n");
Girish K S7e995552013-05-20 12:21:32 +05301094 sdd->port_conf->quirks = S3C64XX_SPI_QUIRK_POLL;
1095 } else
1096 sdd->tx_dma.dmach = res->start;
Thomas Abraham2b908072012-07-13 07:15:15 +09001097
Padmavathi Vennab5be04d2013-01-18 17:17:03 +05301098 res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
1099 if (!res) {
Jingoo Handb0606e2013-07-15 15:11:57 +09001100 dev_warn(&pdev->dev, "Unable to get SPI rx dma resource. Switching to poll mode\n");
Girish K S7e995552013-05-20 12:21:32 +05301101 sdd->port_conf->quirks = S3C64XX_SPI_QUIRK_POLL;
1102 } else
1103 sdd->rx_dma.dmach = res->start;
Padmavathi Vennab5be04d2013-01-18 17:17:03 +05301104 }
1105
1106 sdd->tx_dma.direction = DMA_MEM_TO_DEV;
1107 sdd->rx_dma.direction = DMA_DEV_TO_MEM;
Thomas Abraham2b908072012-07-13 07:15:15 +09001108
1109 master->dev.of_node = pdev->dev.of_node;
Thomas Abrahama5238e32012-07-13 07:15:14 +09001110 master->bus_num = sdd->port_id;
Jassi Brar230d42d2009-11-30 07:39:42 +00001111 master->setup = s3c64xx_spi_setup;
Thomas Abraham1c20c202012-07-13 07:15:14 +09001112 master->cleanup = s3c64xx_spi_cleanup;
Mark Brownad2a99a2012-02-15 14:48:32 -08001113 master->prepare_transfer_hardware = s3c64xx_spi_prepare_transfer;
Mark Brown6bb9c0e2013-10-05 00:42:58 +01001114 master->prepare_message = s3c64xx_spi_prepare_message;
Mark Brown0732a9d2013-10-05 11:51:14 +01001115 master->transfer_one = s3c64xx_spi_transfer_one;
Mark Brownad2a99a2012-02-15 14:48:32 -08001116 master->unprepare_transfer_hardware = s3c64xx_spi_unprepare_transfer;
Jassi Brar230d42d2009-11-30 07:39:42 +00001117 master->num_chipselect = sci->num_cs;
1118 master->dma_alignment = 8;
Stephen Warren24778be2013-05-21 20:36:35 -06001119 master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) |
1120 SPI_BPW_MASK(8);
Jassi Brar230d42d2009-11-30 07:39:42 +00001121 /* the spi->mode bits understood by this driver: */
1122 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
Mark Brownfc0f81b2013-07-28 15:24:54 +01001123 master->auto_runtime_pm = true;
Mark Brown3f295882014-01-16 12:25:46 +00001124 if (!is_polling(sdd))
1125 master->can_dma = s3c64xx_spi_can_dma;
Jassi Brar230d42d2009-11-30 07:39:42 +00001126
Thierry Redingb0ee5602013-01-21 11:09:18 +01001127 sdd->regs = devm_ioremap_resource(&pdev->dev, mem_res);
1128 if (IS_ERR(sdd->regs)) {
1129 ret = PTR_ERR(sdd->regs);
Jingoo Han4eb77002013-01-10 11:04:21 +09001130 goto err0;
Jassi Brar230d42d2009-11-30 07:39:42 +00001131 }
1132
Thomas Abraham00ab5392013-04-15 20:42:57 -07001133 if (sci->cfg_gpio && sci->cfg_gpio()) {
Jassi Brar230d42d2009-11-30 07:39:42 +00001134 dev_err(&pdev->dev, "Unable to config gpio\n");
1135 ret = -EBUSY;
Jingoo Han4eb77002013-01-10 11:04:21 +09001136 goto err0;
Jassi Brar230d42d2009-11-30 07:39:42 +00001137 }
1138
1139 /* Setup clocks */
Jingoo Han4eb77002013-01-10 11:04:21 +09001140 sdd->clk = devm_clk_get(&pdev->dev, "spi");
Jassi Brar230d42d2009-11-30 07:39:42 +00001141 if (IS_ERR(sdd->clk)) {
1142 dev_err(&pdev->dev, "Unable to acquire clock 'spi'\n");
1143 ret = PTR_ERR(sdd->clk);
Thomas Abraham00ab5392013-04-15 20:42:57 -07001144 goto err0;
Jassi Brar230d42d2009-11-30 07:39:42 +00001145 }
1146
Thomas Abraham9f667bf2012-10-03 08:30:12 +09001147 if (clk_prepare_enable(sdd->clk)) {
Jassi Brar230d42d2009-11-30 07:39:42 +00001148 dev_err(&pdev->dev, "Couldn't enable clock 'spi'\n");
1149 ret = -EBUSY;
Thomas Abraham00ab5392013-04-15 20:42:57 -07001150 goto err0;
Jassi Brar230d42d2009-11-30 07:39:42 +00001151 }
1152
Padmavathi Vennaa24d8502011-11-02 20:04:19 +09001153 sprintf(clk_name, "spi_busclk%d", sci->src_clk_nr);
Jingoo Han4eb77002013-01-10 11:04:21 +09001154 sdd->src_clk = devm_clk_get(&pdev->dev, clk_name);
Jassi Brarb0d5d6e2010-01-20 13:49:44 -07001155 if (IS_ERR(sdd->src_clk)) {
Jassi Brar230d42d2009-11-30 07:39:42 +00001156 dev_err(&pdev->dev,
Padmavathi Vennaa24d8502011-11-02 20:04:19 +09001157 "Unable to acquire clock '%s'\n", clk_name);
Jassi Brarb0d5d6e2010-01-20 13:49:44 -07001158 ret = PTR_ERR(sdd->src_clk);
Jingoo Han4eb77002013-01-10 11:04:21 +09001159 goto err2;
Jassi Brar230d42d2009-11-30 07:39:42 +00001160 }
1161
Thomas Abraham9f667bf2012-10-03 08:30:12 +09001162 if (clk_prepare_enable(sdd->src_clk)) {
Padmavathi Vennaa24d8502011-11-02 20:04:19 +09001163 dev_err(&pdev->dev, "Couldn't enable clock '%s'\n", clk_name);
Jassi Brar230d42d2009-11-30 07:39:42 +00001164 ret = -EBUSY;
Jingoo Han4eb77002013-01-10 11:04:21 +09001165 goto err2;
Jassi Brar230d42d2009-11-30 07:39:42 +00001166 }
1167
Heiner Kallweit483867e2015-09-03 22:39:36 +02001168 pm_runtime_set_autosuspend_delay(&pdev->dev, AUTOSUSPEND_TIMEOUT);
1169 pm_runtime_use_autosuspend(&pdev->dev);
1170 pm_runtime_set_active(&pdev->dev);
1171 pm_runtime_enable(&pdev->dev);
1172 pm_runtime_get_sync(&pdev->dev);
1173
Jassi Brar230d42d2009-11-30 07:39:42 +00001174 /* Setup Deufult Mode */
Thomas Abrahama5238e32012-07-13 07:15:14 +09001175 s3c64xx_spi_hwinit(sdd, sdd->port_id);
Jassi Brar230d42d2009-11-30 07:39:42 +00001176
1177 spin_lock_init(&sdd->lock);
1178 init_completion(&sdd->xfer_completion);
Jassi Brar230d42d2009-11-30 07:39:42 +00001179
Jingoo Han4eb77002013-01-10 11:04:21 +09001180 ret = devm_request_irq(&pdev->dev, irq, s3c64xx_spi_irq, 0,
1181 "spi-s3c64xx", sdd);
Mark Brownc2573122011-11-10 10:57:32 +00001182 if (ret != 0) {
1183 dev_err(&pdev->dev, "Failed to request IRQ %d: %d\n",
1184 irq, ret);
Jingoo Han4eb77002013-01-10 11:04:21 +09001185 goto err3;
Mark Brownc2573122011-11-10 10:57:32 +00001186 }
1187
1188 writel(S3C64XX_SPI_INT_RX_OVERRUN_EN | S3C64XX_SPI_INT_RX_UNDERRUN_EN |
1189 S3C64XX_SPI_INT_TX_OVERRUN_EN | S3C64XX_SPI_INT_TX_UNDERRUN_EN,
1190 sdd->regs + S3C64XX_SPI_INT_EN);
1191
Mark Brown91800f02013-08-31 18:55:53 +01001192 ret = devm_spi_register_master(&pdev->dev, master);
1193 if (ret != 0) {
1194 dev_err(&pdev->dev, "cannot register SPI master: %d\n", ret);
Heiner Kallweit483867e2015-09-03 22:39:36 +02001195 goto err3;
Jassi Brar230d42d2009-11-30 07:39:42 +00001196 }
1197
Jingoo Han75bf3362013-01-31 15:25:01 +09001198 dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d with %d Slaves attached\n",
Thomas Abrahama5238e32012-07-13 07:15:14 +09001199 sdd->port_id, master->num_chipselect);
Michal Suchaneked425dc2015-07-24 17:36:49 +02001200 dev_dbg(&pdev->dev, "\tIOmem=[%pR]\tFIFO %dbytes\tDMA=[Rx-%d, Tx-%d]\n",
1201 mem_res, (FIFO_LVL_MASK(sdd) >> 1) + 1,
Boojin Kim82ab8cd2011-09-02 09:44:42 +09001202 sdd->rx_dma.dmach, sdd->tx_dma.dmach);
Jassi Brar230d42d2009-11-30 07:39:42 +00001203
Heiner Kallweit483867e2015-09-03 22:39:36 +02001204 pm_runtime_mark_last_busy(&pdev->dev);
1205 pm_runtime_put_autosuspend(&pdev->dev);
1206
Jassi Brar230d42d2009-11-30 07:39:42 +00001207 return 0;
1208
Heiner Kallweit483867e2015-09-03 22:39:36 +02001209err3:
1210 pm_runtime_put_noidle(&pdev->dev);
Heiner Kallweit3c863792015-09-03 22:38:46 +02001211 pm_runtime_disable(&pdev->dev);
1212 pm_runtime_set_suspended(&pdev->dev);
Heiner Kallweit483867e2015-09-03 22:39:36 +02001213
Jingoo Han4eb77002013-01-10 11:04:21 +09001214 clk_disable_unprepare(sdd->src_clk);
1215err2:
1216 clk_disable_unprepare(sdd->clk);
Jassi Brar230d42d2009-11-30 07:39:42 +00001217err0:
Jassi Brar230d42d2009-11-30 07:39:42 +00001218 spi_master_put(master);
1219
1220 return ret;
1221}
1222
1223static int s3c64xx_spi_remove(struct platform_device *pdev)
1224{
1225 struct spi_master *master = spi_master_get(platform_get_drvdata(pdev));
1226 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
Jassi Brar230d42d2009-11-30 07:39:42 +00001227
Mark Brownb97b6622011-12-04 00:58:06 +00001228 pm_runtime_disable(&pdev->dev);
1229
Mark Brownc2573122011-11-10 10:57:32 +00001230 writel(0, sdd->regs + S3C64XX_SPI_INT_EN);
1231
Thomas Abraham9f667bf2012-10-03 08:30:12 +09001232 clk_disable_unprepare(sdd->src_clk);
Jassi Brar230d42d2009-11-30 07:39:42 +00001233
Thomas Abraham9f667bf2012-10-03 08:30:12 +09001234 clk_disable_unprepare(sdd->clk);
Jassi Brar230d42d2009-11-30 07:39:42 +00001235
Jassi Brar230d42d2009-11-30 07:39:42 +00001236 return 0;
1237}
1238
Jingoo Han997230d2013-03-22 02:09:08 +00001239#ifdef CONFIG_PM_SLEEP
Mark Browne25d0bf2011-12-04 00:36:18 +00001240static int s3c64xx_spi_suspend(struct device *dev)
Jassi Brar230d42d2009-11-30 07:39:42 +00001241{
Guenter Roeck9a2a5242012-08-16 20:14:25 -07001242 struct spi_master *master = dev_get_drvdata(dev);
Jassi Brar230d42d2009-11-30 07:39:42 +00001243 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
Jassi Brar230d42d2009-11-30 07:39:42 +00001244
Krzysztof Kozlowski347de6b2013-10-21 15:42:49 +02001245 int ret = spi_master_suspend(master);
1246 if (ret)
1247 return ret;
Jassi Brar230d42d2009-11-30 07:39:42 +00001248
Heiner Kallweit4fcd9b92015-09-03 22:40:11 +02001249 ret = pm_runtime_force_suspend(dev);
1250 if (ret < 0)
1251 return ret;
Jassi Brar230d42d2009-11-30 07:39:42 +00001252
1253 sdd->cur_speed = 0; /* Output Clock is stopped */
1254
1255 return 0;
1256}
1257
Mark Browne25d0bf2011-12-04 00:36:18 +00001258static int s3c64xx_spi_resume(struct device *dev)
Jassi Brar230d42d2009-11-30 07:39:42 +00001259{
Guenter Roeck9a2a5242012-08-16 20:14:25 -07001260 struct spi_master *master = dev_get_drvdata(dev);
Jassi Brar230d42d2009-11-30 07:39:42 +00001261 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
Jassi Brarad7de722010-01-20 13:49:44 -07001262 struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
Heiner Kallweit4fcd9b92015-09-03 22:40:11 +02001263 int ret;
Jassi Brar230d42d2009-11-30 07:39:42 +00001264
Thomas Abraham00ab5392013-04-15 20:42:57 -07001265 if (sci->cfg_gpio)
Thomas Abraham2b908072012-07-13 07:15:15 +09001266 sci->cfg_gpio();
Jassi Brar230d42d2009-11-30 07:39:42 +00001267
Heiner Kallweit4fcd9b92015-09-03 22:40:11 +02001268 ret = pm_runtime_force_resume(dev);
1269 if (ret < 0)
1270 return ret;
Jassi Brar230d42d2009-11-30 07:39:42 +00001271
Thomas Abrahama5238e32012-07-13 07:15:14 +09001272 s3c64xx_spi_hwinit(sdd, sdd->port_id);
Jassi Brar230d42d2009-11-30 07:39:42 +00001273
Krzysztof Kozlowski347de6b2013-10-21 15:42:49 +02001274 return spi_master_resume(master);
Jassi Brar230d42d2009-11-30 07:39:42 +00001275}
Jingoo Han997230d2013-03-22 02:09:08 +00001276#endif /* CONFIG_PM_SLEEP */
Jassi Brar230d42d2009-11-30 07:39:42 +00001277
Rafael J. Wysockiec833052014-12-13 00:41:15 +01001278#ifdef CONFIG_PM
Mark Brownb97b6622011-12-04 00:58:06 +00001279static int s3c64xx_spi_runtime_suspend(struct device *dev)
1280{
Guenter Roeck9a2a5242012-08-16 20:14:25 -07001281 struct spi_master *master = dev_get_drvdata(dev);
Mark Brownb97b6622011-12-04 00:58:06 +00001282 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1283
Thomas Abraham9f667bf2012-10-03 08:30:12 +09001284 clk_disable_unprepare(sdd->clk);
1285 clk_disable_unprepare(sdd->src_clk);
Mark Brownb97b6622011-12-04 00:58:06 +00001286
1287 return 0;
1288}
1289
1290static int s3c64xx_spi_runtime_resume(struct device *dev)
1291{
Guenter Roeck9a2a5242012-08-16 20:14:25 -07001292 struct spi_master *master = dev_get_drvdata(dev);
Mark Brownb97b6622011-12-04 00:58:06 +00001293 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
Mark Brown8b06d5b2013-09-27 18:44:53 +01001294 int ret;
Mark Brownb97b6622011-12-04 00:58:06 +00001295
Mark Brown8b06d5b2013-09-27 18:44:53 +01001296 ret = clk_prepare_enable(sdd->src_clk);
1297 if (ret != 0)
1298 return ret;
1299
1300 ret = clk_prepare_enable(sdd->clk);
1301 if (ret != 0) {
1302 clk_disable_unprepare(sdd->src_clk);
1303 return ret;
1304 }
Mark Brownb97b6622011-12-04 00:58:06 +00001305
1306 return 0;
1307}
Rafael J. Wysockiec833052014-12-13 00:41:15 +01001308#endif /* CONFIG_PM */
Mark Brownb97b6622011-12-04 00:58:06 +00001309
Mark Browne25d0bf2011-12-04 00:36:18 +00001310static const struct dev_pm_ops s3c64xx_spi_pm = {
1311 SET_SYSTEM_SLEEP_PM_OPS(s3c64xx_spi_suspend, s3c64xx_spi_resume)
Mark Brownb97b6622011-12-04 00:58:06 +00001312 SET_RUNTIME_PM_OPS(s3c64xx_spi_runtime_suspend,
1313 s3c64xx_spi_runtime_resume, NULL)
Mark Browne25d0bf2011-12-04 00:36:18 +00001314};
1315
Sachin Kamat10ce0472012-08-03 10:08:12 +05301316static struct s3c64xx_spi_port_config s3c2443_spi_port_config = {
Thomas Abrahama5238e32012-07-13 07:15:14 +09001317 .fifo_lvl_mask = { 0x7f },
1318 .rx_lvl_offset = 13,
1319 .tx_st_done = 21,
1320 .high_speed = true,
1321};
1322
Sachin Kamat10ce0472012-08-03 10:08:12 +05301323static struct s3c64xx_spi_port_config s3c6410_spi_port_config = {
Thomas Abrahama5238e32012-07-13 07:15:14 +09001324 .fifo_lvl_mask = { 0x7f, 0x7F },
1325 .rx_lvl_offset = 13,
1326 .tx_st_done = 21,
1327};
1328
Sachin Kamat10ce0472012-08-03 10:08:12 +05301329static struct s3c64xx_spi_port_config s5pv210_spi_port_config = {
Thomas Abrahama5238e32012-07-13 07:15:14 +09001330 .fifo_lvl_mask = { 0x1ff, 0x7F },
1331 .rx_lvl_offset = 15,
1332 .tx_st_done = 25,
1333 .high_speed = true,
1334};
1335
Sachin Kamat10ce0472012-08-03 10:08:12 +05301336static struct s3c64xx_spi_port_config exynos4_spi_port_config = {
Thomas Abrahama5238e32012-07-13 07:15:14 +09001337 .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F },
1338 .rx_lvl_offset = 15,
1339 .tx_st_done = 25,
1340 .high_speed = true,
1341 .clk_from_cmu = true,
1342};
1343
Girish K Sbff82032013-06-21 11:26:13 +05301344static struct s3c64xx_spi_port_config exynos5440_spi_port_config = {
1345 .fifo_lvl_mask = { 0x1ff },
1346 .rx_lvl_offset = 15,
1347 .tx_st_done = 25,
1348 .high_speed = true,
1349 .clk_from_cmu = true,
1350 .quirks = S3C64XX_SPI_QUIRK_POLL,
1351};
1352
Padmavathi Vennabf77cba2014-11-06 15:21:49 +05301353static struct s3c64xx_spi_port_config exynos7_spi_port_config = {
1354 .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F, 0x7F, 0x7F, 0x1ff},
1355 .rx_lvl_offset = 15,
1356 .tx_st_done = 25,
1357 .high_speed = true,
1358 .clk_from_cmu = true,
1359 .quirks = S3C64XX_SPI_QUIRK_CS_AUTO,
1360};
1361
Krzysztof Kozlowski23f6d392015-05-02 00:44:06 +09001362static const struct platform_device_id s3c64xx_spi_driver_ids[] = {
Thomas Abrahama5238e32012-07-13 07:15:14 +09001363 {
1364 .name = "s3c2443-spi",
1365 .driver_data = (kernel_ulong_t)&s3c2443_spi_port_config,
1366 }, {
1367 .name = "s3c6410-spi",
1368 .driver_data = (kernel_ulong_t)&s3c6410_spi_port_config,
1369 }, {
Thomas Abrahama5238e32012-07-13 07:15:14 +09001370 .name = "s5pv210-spi",
1371 .driver_data = (kernel_ulong_t)&s5pv210_spi_port_config,
1372 }, {
1373 .name = "exynos4210-spi",
1374 .driver_data = (kernel_ulong_t)&exynos4_spi_port_config,
1375 },
1376 { },
1377};
1378
Thomas Abraham2b908072012-07-13 07:15:15 +09001379static const struct of_device_id s3c64xx_spi_dt_match[] = {
Mateusz Krawczuka3b924d2013-09-23 11:45:45 +02001380 { .compatible = "samsung,s3c2443-spi",
1381 .data = (void *)&s3c2443_spi_port_config,
1382 },
1383 { .compatible = "samsung,s3c6410-spi",
1384 .data = (void *)&s3c6410_spi_port_config,
1385 },
Mateusz Krawczuka3b924d2013-09-23 11:45:45 +02001386 { .compatible = "samsung,s5pv210-spi",
1387 .data = (void *)&s5pv210_spi_port_config,
1388 },
Thomas Abraham2b908072012-07-13 07:15:15 +09001389 { .compatible = "samsung,exynos4210-spi",
1390 .data = (void *)&exynos4_spi_port_config,
1391 },
Girish K Sbff82032013-06-21 11:26:13 +05301392 { .compatible = "samsung,exynos5440-spi",
1393 .data = (void *)&exynos5440_spi_port_config,
1394 },
Padmavathi Vennabf77cba2014-11-06 15:21:49 +05301395 { .compatible = "samsung,exynos7-spi",
1396 .data = (void *)&exynos7_spi_port_config,
1397 },
Thomas Abraham2b908072012-07-13 07:15:15 +09001398 { },
1399};
1400MODULE_DEVICE_TABLE(of, s3c64xx_spi_dt_match);
Thomas Abraham2b908072012-07-13 07:15:15 +09001401
Jassi Brar230d42d2009-11-30 07:39:42 +00001402static struct platform_driver s3c64xx_spi_driver = {
1403 .driver = {
1404 .name = "s3c64xx-spi",
Mark Browne25d0bf2011-12-04 00:36:18 +00001405 .pm = &s3c64xx_spi_pm,
Thomas Abraham2b908072012-07-13 07:15:15 +09001406 .of_match_table = of_match_ptr(s3c64xx_spi_dt_match),
Jassi Brar230d42d2009-11-30 07:39:42 +00001407 },
Lukasz Czerwinski50c959f2013-09-09 16:09:25 +02001408 .probe = s3c64xx_spi_probe,
Jassi Brar230d42d2009-11-30 07:39:42 +00001409 .remove = s3c64xx_spi_remove,
Thomas Abrahama5238e32012-07-13 07:15:14 +09001410 .id_table = s3c64xx_spi_driver_ids,
Jassi Brar230d42d2009-11-30 07:39:42 +00001411};
1412MODULE_ALIAS("platform:s3c64xx-spi");
1413
Lukasz Czerwinski50c959f2013-09-09 16:09:25 +02001414module_platform_driver(s3c64xx_spi_driver);
Jassi Brar230d42d2009-11-30 07:39:42 +00001415
1416MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>");
1417MODULE_DESCRIPTION("S3C64XX SPI Controller Driver");
1418MODULE_LICENSE("GPL");