blob: 28be7415a1989b55b5e848c72e3b2e2f43a08edd [file] [log] [blame]
Sascha Haueraecfbdb2012-09-21 10:07:49 +02001/*
2 * Copyright (c) 2010 Sascha Hauer <s.hauer@pengutronix.de>
3 * Copyright (C) 2005-2009 Freescale Semiconductor, Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * for more details.
14 */
15#include <linux/module.h>
16#include <linux/export.h>
17#include <linux/types.h>
Philipp Zabel6c641552013-03-28 17:35:21 +010018#include <linux/reset.h>
Sascha Haueraecfbdb2012-09-21 10:07:49 +020019#include <linux/platform_device.h>
20#include <linux/err.h>
21#include <linux/spinlock.h>
22#include <linux/delay.h>
23#include <linux/interrupt.h>
24#include <linux/io.h>
25#include <linux/clk.h>
26#include <linux/list.h>
27#include <linux/irq.h>
Catalin Marinasde88cbb2013-01-18 15:31:37 +000028#include <linux/irqchip/chained_irq.h>
Philipp Zabelb7287662013-06-21 10:27:39 +020029#include <linux/irqdomain.h>
Sascha Haueraecfbdb2012-09-21 10:07:49 +020030#include <linux/of_device.h>
Sascha Haueraecfbdb2012-09-21 10:07:49 +020031
Philipp Zabel7cb17792013-10-10 16:18:38 +020032#include <drm/drm_fourcc.h>
33
Philipp Zabel39b90042013-09-30 16:13:39 +020034#include <video/imx-ipu-v3.h>
Sascha Haueraecfbdb2012-09-21 10:07:49 +020035#include "ipu-prv.h"
36
37static inline u32 ipu_cm_read(struct ipu_soc *ipu, unsigned offset)
38{
39 return readl(ipu->cm_reg + offset);
40}
41
42static inline void ipu_cm_write(struct ipu_soc *ipu, u32 value, unsigned offset)
43{
44 writel(value, ipu->cm_reg + offset);
45}
46
Sascha Haueraecfbdb2012-09-21 10:07:49 +020047void ipu_srm_dp_sync_update(struct ipu_soc *ipu)
48{
49 u32 val;
50
51 val = ipu_cm_read(ipu, IPU_SRM_PRI2);
52 val |= 0x8;
53 ipu_cm_write(ipu, val, IPU_SRM_PRI2);
54}
55EXPORT_SYMBOL_GPL(ipu_srm_dp_sync_update);
56
Philipp Zabel7cb17792013-10-10 16:18:38 +020057enum ipu_color_space ipu_drm_fourcc_to_colorspace(u32 drm_fourcc)
58{
59 switch (drm_fourcc) {
60 case DRM_FORMAT_RGB565:
61 case DRM_FORMAT_BGR565:
62 case DRM_FORMAT_RGB888:
63 case DRM_FORMAT_BGR888:
64 case DRM_FORMAT_XRGB8888:
65 case DRM_FORMAT_XBGR8888:
66 case DRM_FORMAT_RGBX8888:
67 case DRM_FORMAT_BGRX8888:
68 case DRM_FORMAT_ARGB8888:
69 case DRM_FORMAT_ABGR8888:
70 case DRM_FORMAT_RGBA8888:
71 case DRM_FORMAT_BGRA8888:
72 return IPUV3_COLORSPACE_RGB;
73 case DRM_FORMAT_YUYV:
74 case DRM_FORMAT_UYVY:
75 case DRM_FORMAT_YUV420:
76 case DRM_FORMAT_YVU420:
77 return IPUV3_COLORSPACE_YUV;
78 default:
79 return IPUV3_COLORSPACE_UNKNOWN;
80 }
81}
82EXPORT_SYMBOL_GPL(ipu_drm_fourcc_to_colorspace);
83
Sascha Haueraecfbdb2012-09-21 10:07:49 +020084enum ipu_color_space ipu_pixelformat_to_colorspace(u32 pixelformat)
85{
86 switch (pixelformat) {
87 case V4L2_PIX_FMT_YUV420:
Philipp Zabeld3e4e612012-11-12 16:29:00 +010088 case V4L2_PIX_FMT_YVU420:
Sascha Haueraecfbdb2012-09-21 10:07:49 +020089 case V4L2_PIX_FMT_UYVY:
Michael Olbrichc096ae12012-11-12 16:28:59 +010090 case V4L2_PIX_FMT_YUYV:
Sascha Haueraecfbdb2012-09-21 10:07:49 +020091 return IPUV3_COLORSPACE_YUV;
92 case V4L2_PIX_FMT_RGB32:
93 case V4L2_PIX_FMT_BGR32:
94 case V4L2_PIX_FMT_RGB24:
95 case V4L2_PIX_FMT_BGR24:
96 case V4L2_PIX_FMT_RGB565:
97 return IPUV3_COLORSPACE_RGB;
98 default:
99 return IPUV3_COLORSPACE_UNKNOWN;
100 }
101}
102EXPORT_SYMBOL_GPL(ipu_pixelformat_to_colorspace);
103
Steve Longerbeam4cea9402014-06-25 18:05:38 -0700104bool ipu_pixelformat_is_planar(u32 pixelformat)
105{
106 switch (pixelformat) {
107 case V4L2_PIX_FMT_YUV420:
108 case V4L2_PIX_FMT_YVU420:
109 return true;
110 }
111
112 return false;
113}
114EXPORT_SYMBOL_GPL(ipu_pixelformat_is_planar);
115
Steve Longerbeamae0e9702014-06-25 18:05:36 -0700116enum ipu_color_space ipu_mbus_code_to_colorspace(u32 mbus_code)
117{
118 switch (mbus_code & 0xf000) {
119 case 0x1000:
120 return IPUV3_COLORSPACE_RGB;
121 case 0x2000:
122 return IPUV3_COLORSPACE_YUV;
123 default:
124 return IPUV3_COLORSPACE_UNKNOWN;
125 }
126}
127EXPORT_SYMBOL_GPL(ipu_mbus_code_to_colorspace);
128
Steve Longerbeam6930afd2014-06-25 18:05:43 -0700129int ipu_stride_to_bytes(u32 pixel_stride, u32 pixelformat)
130{
131 switch (pixelformat) {
132 case V4L2_PIX_FMT_YUV420:
133 case V4L2_PIX_FMT_YVU420:
134 /*
135 * for the planar YUV formats, the stride passed to
136 * cpmem must be the stride in bytes of the Y plane.
137 * And all the planar YUV formats have an 8-bit
138 * Y component.
139 */
140 return (8 * pixel_stride) >> 3;
141 case V4L2_PIX_FMT_RGB565:
142 case V4L2_PIX_FMT_YUYV:
143 case V4L2_PIX_FMT_UYVY:
144 return (16 * pixel_stride) >> 3;
145 case V4L2_PIX_FMT_BGR24:
146 case V4L2_PIX_FMT_RGB24:
147 return (24 * pixel_stride) >> 3;
148 case V4L2_PIX_FMT_BGR32:
149 case V4L2_PIX_FMT_RGB32:
150 return (32 * pixel_stride) >> 3;
151 default:
152 break;
153 }
154
155 return -EINVAL;
156}
157EXPORT_SYMBOL_GPL(ipu_stride_to_bytes);
158
Steve Longerbeamf835f382014-06-25 18:05:37 -0700159int ipu_degrees_to_rot_mode(enum ipu_rotate_mode *mode, int degrees,
160 bool hflip, bool vflip)
161{
162 u32 r90, vf, hf;
163
164 switch (degrees) {
165 case 0:
166 vf = hf = r90 = 0;
167 break;
168 case 90:
169 vf = hf = 0;
170 r90 = 1;
171 break;
172 case 180:
173 vf = hf = 1;
174 r90 = 0;
175 break;
176 case 270:
177 vf = hf = r90 = 1;
178 break;
179 default:
180 return -EINVAL;
181 }
182
183 hf ^= (u32)hflip;
184 vf ^= (u32)vflip;
185
186 *mode = (enum ipu_rotate_mode)((r90 << 2) | (hf << 1) | vf);
187 return 0;
188}
189EXPORT_SYMBOL_GPL(ipu_degrees_to_rot_mode);
190
191int ipu_rot_mode_to_degrees(int *degrees, enum ipu_rotate_mode mode,
192 bool hflip, bool vflip)
193{
194 u32 r90, vf, hf;
195
196 r90 = ((u32)mode >> 2) & 0x1;
197 hf = ((u32)mode >> 1) & 0x1;
198 vf = ((u32)mode >> 0) & 0x1;
199 hf ^= (u32)hflip;
200 vf ^= (u32)vflip;
201
202 switch ((enum ipu_rotate_mode)((r90 << 2) | (hf << 1) | vf)) {
203 case IPU_ROTATE_NONE:
204 *degrees = 0;
205 break;
206 case IPU_ROTATE_90_RIGHT:
207 *degrees = 90;
208 break;
209 case IPU_ROTATE_180:
210 *degrees = 180;
211 break;
212 case IPU_ROTATE_90_LEFT:
213 *degrees = 270;
214 break;
215 default:
216 return -EINVAL;
217 }
218
219 return 0;
220}
221EXPORT_SYMBOL_GPL(ipu_rot_mode_to_degrees);
222
Sascha Haueraecfbdb2012-09-21 10:07:49 +0200223struct ipuv3_channel *ipu_idmac_get(struct ipu_soc *ipu, unsigned num)
224{
225 struct ipuv3_channel *channel;
226
227 dev_dbg(ipu->dev, "%s %d\n", __func__, num);
228
229 if (num > 63)
230 return ERR_PTR(-ENODEV);
231
232 mutex_lock(&ipu->channel_lock);
233
234 channel = &ipu->channel[num];
235
236 if (channel->busy) {
237 channel = ERR_PTR(-EBUSY);
238 goto out;
239 }
240
Valentina Manea89bc5be2013-10-25 11:52:20 +0300241 channel->busy = true;
Sascha Haueraecfbdb2012-09-21 10:07:49 +0200242 channel->num = num;
243
244out:
245 mutex_unlock(&ipu->channel_lock);
246
247 return channel;
248}
249EXPORT_SYMBOL_GPL(ipu_idmac_get);
250
251void ipu_idmac_put(struct ipuv3_channel *channel)
252{
253 struct ipu_soc *ipu = channel->ipu;
254
255 dev_dbg(ipu->dev, "%s %d\n", __func__, channel->num);
256
257 mutex_lock(&ipu->channel_lock);
258
Valentina Manea89bc5be2013-10-25 11:52:20 +0300259 channel->busy = false;
Sascha Haueraecfbdb2012-09-21 10:07:49 +0200260
261 mutex_unlock(&ipu->channel_lock);
262}
263EXPORT_SYMBOL_GPL(ipu_idmac_put);
264
Steve Longerbeamaa52f572014-06-25 18:05:40 -0700265#define idma_mask(ch) (1 << ((ch) & 0x1f))
Sascha Haueraecfbdb2012-09-21 10:07:49 +0200266
Steve Longerbeame7268c62014-06-25 18:05:42 -0700267/*
268 * This is an undocumented feature, a write one to a channel bit in
269 * IPU_CHA_CUR_BUF and IPU_CHA_TRIPLE_CUR_BUF will reset the channel's
270 * internal current buffer pointer so that transfers start from buffer
271 * 0 on the next channel enable (that's the theory anyway, the imx6 TRM
272 * only says these are read-only registers). This operation is required
273 * for channel linking to work correctly, for instance video capture
274 * pipelines that carry out image rotations will fail after the first
275 * streaming unless this function is called for each channel before
276 * re-enabling the channels.
277 */
278static void __ipu_idmac_reset_current_buffer(struct ipuv3_channel *channel)
279{
280 struct ipu_soc *ipu = channel->ipu;
281 unsigned int chno = channel->num;
282
283 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_CUR_BUF(chno));
284}
285
Sascha Haueraecfbdb2012-09-21 10:07:49 +0200286void ipu_idmac_set_double_buffer(struct ipuv3_channel *channel,
287 bool doublebuffer)
288{
289 struct ipu_soc *ipu = channel->ipu;
290 unsigned long flags;
291 u32 reg;
292
293 spin_lock_irqsave(&ipu->lock, flags);
294
295 reg = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(channel->num));
296 if (doublebuffer)
297 reg |= idma_mask(channel->num);
298 else
299 reg &= ~idma_mask(channel->num);
300 ipu_cm_write(ipu, reg, IPU_CHA_DB_MODE_SEL(channel->num));
301
Steve Longerbeame7268c62014-06-25 18:05:42 -0700302 __ipu_idmac_reset_current_buffer(channel);
303
Sascha Haueraecfbdb2012-09-21 10:07:49 +0200304 spin_unlock_irqrestore(&ipu->lock, flags);
305}
306EXPORT_SYMBOL_GPL(ipu_idmac_set_double_buffer);
307
Steve Longerbeam4fd1a072014-06-25 18:05:45 -0700308static const struct {
309 int chnum;
310 u32 reg;
311 int shift;
312} idmac_lock_en_info[] = {
313 { .chnum = 5, .reg = IDMAC_CH_LOCK_EN_1, .shift = 0, },
314 { .chnum = 11, .reg = IDMAC_CH_LOCK_EN_1, .shift = 2, },
315 { .chnum = 12, .reg = IDMAC_CH_LOCK_EN_1, .shift = 4, },
316 { .chnum = 14, .reg = IDMAC_CH_LOCK_EN_1, .shift = 6, },
317 { .chnum = 15, .reg = IDMAC_CH_LOCK_EN_1, .shift = 8, },
318 { .chnum = 20, .reg = IDMAC_CH_LOCK_EN_1, .shift = 10, },
319 { .chnum = 21, .reg = IDMAC_CH_LOCK_EN_1, .shift = 12, },
320 { .chnum = 22, .reg = IDMAC_CH_LOCK_EN_1, .shift = 14, },
321 { .chnum = 23, .reg = IDMAC_CH_LOCK_EN_1, .shift = 16, },
322 { .chnum = 27, .reg = IDMAC_CH_LOCK_EN_1, .shift = 18, },
323 { .chnum = 28, .reg = IDMAC_CH_LOCK_EN_1, .shift = 20, },
324 { .chnum = 45, .reg = IDMAC_CH_LOCK_EN_2, .shift = 0, },
325 { .chnum = 46, .reg = IDMAC_CH_LOCK_EN_2, .shift = 2, },
326 { .chnum = 47, .reg = IDMAC_CH_LOCK_EN_2, .shift = 4, },
327 { .chnum = 48, .reg = IDMAC_CH_LOCK_EN_2, .shift = 6, },
328 { .chnum = 49, .reg = IDMAC_CH_LOCK_EN_2, .shift = 8, },
329 { .chnum = 50, .reg = IDMAC_CH_LOCK_EN_2, .shift = 10, },
330};
331
332int ipu_idmac_lock_enable(struct ipuv3_channel *channel, int num_bursts)
333{
334 struct ipu_soc *ipu = channel->ipu;
335 unsigned long flags;
336 u32 bursts, regval;
337 int i;
338
339 switch (num_bursts) {
340 case 0:
341 case 1:
342 bursts = 0x00; /* locking disabled */
343 break;
344 case 2:
345 bursts = 0x01;
346 break;
347 case 4:
348 bursts = 0x02;
349 break;
350 case 8:
351 bursts = 0x03;
352 break;
353 default:
354 return -EINVAL;
355 }
356
357 for (i = 0; i < ARRAY_SIZE(idmac_lock_en_info); i++) {
358 if (channel->num == idmac_lock_en_info[i].chnum)
359 break;
360 }
361 if (i >= ARRAY_SIZE(idmac_lock_en_info))
362 return -EINVAL;
363
364 spin_lock_irqsave(&ipu->lock, flags);
365
366 regval = ipu_idmac_read(ipu, idmac_lock_en_info[i].reg);
367 regval &= ~(0x03 << idmac_lock_en_info[i].shift);
368 regval |= (bursts << idmac_lock_en_info[i].shift);
369 ipu_idmac_write(ipu, regval, idmac_lock_en_info[i].reg);
370
371 spin_unlock_irqrestore(&ipu->lock, flags);
372
373 return 0;
374}
375EXPORT_SYMBOL_GPL(ipu_idmac_lock_enable);
376
Sascha Haueraecfbdb2012-09-21 10:07:49 +0200377int ipu_module_enable(struct ipu_soc *ipu, u32 mask)
378{
379 unsigned long lock_flags;
380 u32 val;
381
382 spin_lock_irqsave(&ipu->lock, lock_flags);
383
384 val = ipu_cm_read(ipu, IPU_DISP_GEN);
385
386 if (mask & IPU_CONF_DI0_EN)
387 val |= IPU_DI0_COUNTER_RELEASE;
388 if (mask & IPU_CONF_DI1_EN)
389 val |= IPU_DI1_COUNTER_RELEASE;
390
391 ipu_cm_write(ipu, val, IPU_DISP_GEN);
392
393 val = ipu_cm_read(ipu, IPU_CONF);
394 val |= mask;
395 ipu_cm_write(ipu, val, IPU_CONF);
396
397 spin_unlock_irqrestore(&ipu->lock, lock_flags);
398
399 return 0;
400}
401EXPORT_SYMBOL_GPL(ipu_module_enable);
402
403int ipu_module_disable(struct ipu_soc *ipu, u32 mask)
404{
405 unsigned long lock_flags;
406 u32 val;
407
408 spin_lock_irqsave(&ipu->lock, lock_flags);
409
410 val = ipu_cm_read(ipu, IPU_CONF);
411 val &= ~mask;
412 ipu_cm_write(ipu, val, IPU_CONF);
413
414 val = ipu_cm_read(ipu, IPU_DISP_GEN);
415
416 if (mask & IPU_CONF_DI0_EN)
417 val &= ~IPU_DI0_COUNTER_RELEASE;
418 if (mask & IPU_CONF_DI1_EN)
419 val &= ~IPU_DI1_COUNTER_RELEASE;
420
421 ipu_cm_write(ipu, val, IPU_DISP_GEN);
422
423 spin_unlock_irqrestore(&ipu->lock, lock_flags);
424
425 return 0;
426}
427EXPORT_SYMBOL_GPL(ipu_module_disable);
428
Philipp Zabele9046092012-05-16 17:28:29 +0200429int ipu_idmac_get_current_buffer(struct ipuv3_channel *channel)
430{
431 struct ipu_soc *ipu = channel->ipu;
432 unsigned int chno = channel->num;
433
434 return (ipu_cm_read(ipu, IPU_CHA_CUR_BUF(chno)) & idma_mask(chno)) ? 1 : 0;
435}
436EXPORT_SYMBOL_GPL(ipu_idmac_get_current_buffer);
437
Steve Longerbeamaa52f572014-06-25 18:05:40 -0700438bool ipu_idmac_buffer_is_ready(struct ipuv3_channel *channel, u32 buf_num)
439{
440 struct ipu_soc *ipu = channel->ipu;
441 unsigned long flags;
442 u32 reg = 0;
443
444 spin_lock_irqsave(&ipu->lock, flags);
445 switch (buf_num) {
446 case 0:
447 reg = ipu_cm_read(ipu, IPU_CHA_BUF0_RDY(channel->num));
448 break;
449 case 1:
450 reg = ipu_cm_read(ipu, IPU_CHA_BUF1_RDY(channel->num));
451 break;
452 case 2:
453 reg = ipu_cm_read(ipu, IPU_CHA_BUF2_RDY(channel->num));
454 break;
455 }
456 spin_unlock_irqrestore(&ipu->lock, flags);
457
458 return ((reg & idma_mask(channel->num)) != 0);
459}
460EXPORT_SYMBOL_GPL(ipu_idmac_buffer_is_ready);
461
Sascha Haueraecfbdb2012-09-21 10:07:49 +0200462void ipu_idmac_select_buffer(struct ipuv3_channel *channel, u32 buf_num)
463{
464 struct ipu_soc *ipu = channel->ipu;
465 unsigned int chno = channel->num;
466 unsigned long flags;
467
468 spin_lock_irqsave(&ipu->lock, flags);
469
470 /* Mark buffer as ready. */
471 if (buf_num == 0)
472 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF0_RDY(chno));
473 else
474 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF1_RDY(chno));
475
476 spin_unlock_irqrestore(&ipu->lock, flags);
477}
478EXPORT_SYMBOL_GPL(ipu_idmac_select_buffer);
479
Steve Longerbeambce6f082014-06-25 18:05:41 -0700480void ipu_idmac_clear_buffer(struct ipuv3_channel *channel, u32 buf_num)
481{
482 struct ipu_soc *ipu = channel->ipu;
483 unsigned int chno = channel->num;
484 unsigned long flags;
485
486 spin_lock_irqsave(&ipu->lock, flags);
487
488 ipu_cm_write(ipu, 0xF0300000, IPU_GPR); /* write one to clear */
489 switch (buf_num) {
490 case 0:
491 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF0_RDY(chno));
492 break;
493 case 1:
494 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF1_RDY(chno));
495 break;
496 case 2:
497 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF2_RDY(chno));
498 break;
499 default:
500 break;
501 }
502 ipu_cm_write(ipu, 0x0, IPU_GPR); /* write one to set */
503
504 spin_unlock_irqrestore(&ipu->lock, flags);
505}
506EXPORT_SYMBOL_GPL(ipu_idmac_clear_buffer);
507
Sascha Haueraecfbdb2012-09-21 10:07:49 +0200508int ipu_idmac_enable_channel(struct ipuv3_channel *channel)
509{
510 struct ipu_soc *ipu = channel->ipu;
511 u32 val;
512 unsigned long flags;
513
514 spin_lock_irqsave(&ipu->lock, flags);
515
516 val = ipu_idmac_read(ipu, IDMAC_CHA_EN(channel->num));
517 val |= idma_mask(channel->num);
518 ipu_idmac_write(ipu, val, IDMAC_CHA_EN(channel->num));
519
520 spin_unlock_irqrestore(&ipu->lock, flags);
521
522 return 0;
523}
524EXPORT_SYMBOL_GPL(ipu_idmac_enable_channel);
525
Philipp Zabel17075502014-04-14 23:53:17 +0200526bool ipu_idmac_channel_busy(struct ipu_soc *ipu, unsigned int chno)
527{
528 return (ipu_idmac_read(ipu, IDMAC_CHA_BUSY(chno)) & idma_mask(chno));
529}
530EXPORT_SYMBOL_GPL(ipu_idmac_channel_busy);
531
Sascha Hauerfb822a32013-10-10 16:18:41 +0200532int ipu_idmac_wait_busy(struct ipuv3_channel *channel, int ms)
533{
534 struct ipu_soc *ipu = channel->ipu;
535 unsigned long timeout;
536
537 timeout = jiffies + msecs_to_jiffies(ms);
538 while (ipu_idmac_read(ipu, IDMAC_CHA_BUSY(channel->num)) &
539 idma_mask(channel->num)) {
540 if (time_after(jiffies, timeout))
541 return -ETIMEDOUT;
542 cpu_relax();
543 }
544
545 return 0;
546}
547EXPORT_SYMBOL_GPL(ipu_idmac_wait_busy);
548
Philipp Zabel17075502014-04-14 23:53:17 +0200549int ipu_wait_interrupt(struct ipu_soc *ipu, int irq, int ms)
550{
551 unsigned long timeout;
552
553 timeout = jiffies + msecs_to_jiffies(ms);
554 ipu_cm_write(ipu, BIT(irq % 32), IPU_INT_STAT(irq / 32));
555 while (!(ipu_cm_read(ipu, IPU_INT_STAT(irq / 32) & BIT(irq % 32)))) {
556 if (time_after(jiffies, timeout))
557 return -ETIMEDOUT;
558 cpu_relax();
559 }
560
561 return 0;
562}
563EXPORT_SYMBOL_GPL(ipu_wait_interrupt);
564
Sascha Haueraecfbdb2012-09-21 10:07:49 +0200565int ipu_idmac_disable_channel(struct ipuv3_channel *channel)
566{
567 struct ipu_soc *ipu = channel->ipu;
568 u32 val;
569 unsigned long flags;
Sascha Haueraecfbdb2012-09-21 10:07:49 +0200570
571 spin_lock_irqsave(&ipu->lock, flags);
572
573 /* Disable DMA channel(s) */
574 val = ipu_idmac_read(ipu, IDMAC_CHA_EN(channel->num));
575 val &= ~idma_mask(channel->num);
576 ipu_idmac_write(ipu, val, IDMAC_CHA_EN(channel->num));
577
Steve Longerbeame7268c62014-06-25 18:05:42 -0700578 __ipu_idmac_reset_current_buffer(channel);
579
Sascha Haueraecfbdb2012-09-21 10:07:49 +0200580 /* Set channel buffers NOT to be ready */
581 ipu_cm_write(ipu, 0xf0000000, IPU_GPR); /* write one to clear */
582
583 if (ipu_cm_read(ipu, IPU_CHA_BUF0_RDY(channel->num)) &
584 idma_mask(channel->num)) {
585 ipu_cm_write(ipu, idma_mask(channel->num),
586 IPU_CHA_BUF0_RDY(channel->num));
587 }
588
589 if (ipu_cm_read(ipu, IPU_CHA_BUF1_RDY(channel->num)) &
590 idma_mask(channel->num)) {
591 ipu_cm_write(ipu, idma_mask(channel->num),
592 IPU_CHA_BUF1_RDY(channel->num));
593 }
594
595 ipu_cm_write(ipu, 0x0, IPU_GPR); /* write one to set */
596
597 /* Reset the double buffer */
598 val = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(channel->num));
599 val &= ~idma_mask(channel->num);
600 ipu_cm_write(ipu, val, IPU_CHA_DB_MODE_SEL(channel->num));
601
602 spin_unlock_irqrestore(&ipu->lock, flags);
603
604 return 0;
605}
606EXPORT_SYMBOL_GPL(ipu_idmac_disable_channel);
607
Steve Longerbeam2bcf5772014-06-25 18:05:44 -0700608/*
609 * The imx6 rev. D TRM says that enabling the WM feature will increase
610 * a channel's priority. Refer to Table 36-8 Calculated priority value.
611 * The sub-module that is the sink or source for the channel must enable
612 * watermark signal for this to take effect (SMFC_WM for instance).
613 */
614void ipu_idmac_enable_watermark(struct ipuv3_channel *channel, bool enable)
615{
616 struct ipu_soc *ipu = channel->ipu;
617 unsigned long flags;
618 u32 val;
619
620 spin_lock_irqsave(&ipu->lock, flags);
621
622 val = ipu_idmac_read(ipu, IDMAC_WM_EN(channel->num));
623 if (enable)
624 val |= 1 << (channel->num % 32);
625 else
626 val &= ~(1 << (channel->num % 32));
627 ipu_idmac_write(ipu, val, IDMAC_WM_EN(channel->num));
628
629 spin_unlock_irqrestore(&ipu->lock, flags);
630}
631EXPORT_SYMBOL_GPL(ipu_idmac_enable_watermark);
632
Philipp Zabel6c641552013-03-28 17:35:21 +0100633static int ipu_memory_reset(struct ipu_soc *ipu)
Sascha Haueraecfbdb2012-09-21 10:07:49 +0200634{
635 unsigned long timeout;
636
637 ipu_cm_write(ipu, 0x807FFFFF, IPU_MEM_RST);
638
639 timeout = jiffies + msecs_to_jiffies(1000);
640 while (ipu_cm_read(ipu, IPU_MEM_RST) & 0x80000000) {
641 if (time_after(jiffies, timeout))
642 return -ETIME;
643 cpu_relax();
644 }
645
Sascha Haueraecfbdb2012-09-21 10:07:49 +0200646 return 0;
647}
648
Steve Longerbeamba079752014-06-25 18:05:30 -0700649/*
650 * Set the source mux for the given CSI. Selects either parallel or
651 * MIPI CSI2 sources.
652 */
653void ipu_set_csi_src_mux(struct ipu_soc *ipu, int csi_id, bool mipi_csi2)
654{
655 unsigned long flags;
656 u32 val, mask;
657
658 mask = (csi_id == 1) ? IPU_CONF_CSI1_DATA_SOURCE :
659 IPU_CONF_CSI0_DATA_SOURCE;
660
661 spin_lock_irqsave(&ipu->lock, flags);
662
663 val = ipu_cm_read(ipu, IPU_CONF);
664 if (mipi_csi2)
665 val |= mask;
666 else
667 val &= ~mask;
668 ipu_cm_write(ipu, val, IPU_CONF);
669
670 spin_unlock_irqrestore(&ipu->lock, flags);
671}
672EXPORT_SYMBOL_GPL(ipu_set_csi_src_mux);
673
674/*
675 * Set the source mux for the IC. Selects either CSI[01] or the VDI.
676 */
677void ipu_set_ic_src_mux(struct ipu_soc *ipu, int csi_id, bool vdi)
678{
679 unsigned long flags;
680 u32 val;
681
682 spin_lock_irqsave(&ipu->lock, flags);
683
684 val = ipu_cm_read(ipu, IPU_CONF);
685 if (vdi) {
686 val |= IPU_CONF_IC_INPUT;
687 } else {
688 val &= ~IPU_CONF_IC_INPUT;
689 if (csi_id == 1)
690 val |= IPU_CONF_CSI_SEL;
691 else
692 val &= ~IPU_CONF_CSI_SEL;
693 }
694 ipu_cm_write(ipu, val, IPU_CONF);
695
696 spin_unlock_irqrestore(&ipu->lock, flags);
697}
698EXPORT_SYMBOL_GPL(ipu_set_ic_src_mux);
699
Sascha Haueraecfbdb2012-09-21 10:07:49 +0200700struct ipu_devtype {
701 const char *name;
702 unsigned long cm_ofs;
703 unsigned long cpmem_ofs;
704 unsigned long srm_ofs;
705 unsigned long tpm_ofs;
Steve Longerbeam2ffd48f2014-08-19 10:52:40 -0700706 unsigned long csi0_ofs;
707 unsigned long csi1_ofs;
Steve Longerbeam1aa8ea02014-08-11 13:04:50 +0200708 unsigned long ic_ofs;
Sascha Haueraecfbdb2012-09-21 10:07:49 +0200709 unsigned long disp0_ofs;
710 unsigned long disp1_ofs;
711 unsigned long dc_tmpl_ofs;
712 unsigned long vdi_ofs;
713 enum ipuv3_type type;
714};
715
716static struct ipu_devtype ipu_type_imx51 = {
717 .name = "IPUv3EX",
718 .cm_ofs = 0x1e000000,
719 .cpmem_ofs = 0x1f000000,
720 .srm_ofs = 0x1f040000,
721 .tpm_ofs = 0x1f060000,
Steve Longerbeam2ffd48f2014-08-19 10:52:40 -0700722 .csi0_ofs = 0x1f030000,
723 .csi1_ofs = 0x1f038000,
Steve Longerbeam1aa8ea02014-08-11 13:04:50 +0200724 .ic_ofs = 0x1f020000,
Sascha Haueraecfbdb2012-09-21 10:07:49 +0200725 .disp0_ofs = 0x1e040000,
726 .disp1_ofs = 0x1e048000,
727 .dc_tmpl_ofs = 0x1f080000,
728 .vdi_ofs = 0x1e068000,
729 .type = IPUV3EX,
730};
731
732static struct ipu_devtype ipu_type_imx53 = {
733 .name = "IPUv3M",
734 .cm_ofs = 0x06000000,
735 .cpmem_ofs = 0x07000000,
736 .srm_ofs = 0x07040000,
737 .tpm_ofs = 0x07060000,
Steve Longerbeam2ffd48f2014-08-19 10:52:40 -0700738 .csi0_ofs = 0x07030000,
739 .csi1_ofs = 0x07038000,
Steve Longerbeam1aa8ea02014-08-11 13:04:50 +0200740 .ic_ofs = 0x07020000,
Sascha Haueraecfbdb2012-09-21 10:07:49 +0200741 .disp0_ofs = 0x06040000,
742 .disp1_ofs = 0x06048000,
743 .dc_tmpl_ofs = 0x07080000,
744 .vdi_ofs = 0x06068000,
745 .type = IPUV3M,
746};
747
748static struct ipu_devtype ipu_type_imx6q = {
749 .name = "IPUv3H",
750 .cm_ofs = 0x00200000,
751 .cpmem_ofs = 0x00300000,
752 .srm_ofs = 0x00340000,
753 .tpm_ofs = 0x00360000,
Steve Longerbeam2ffd48f2014-08-19 10:52:40 -0700754 .csi0_ofs = 0x00230000,
755 .csi1_ofs = 0x00238000,
Steve Longerbeam1aa8ea02014-08-11 13:04:50 +0200756 .ic_ofs = 0x00220000,
Sascha Haueraecfbdb2012-09-21 10:07:49 +0200757 .disp0_ofs = 0x00240000,
758 .disp1_ofs = 0x00248000,
759 .dc_tmpl_ofs = 0x00380000,
760 .vdi_ofs = 0x00268000,
761 .type = IPUV3H,
762};
763
764static const struct of_device_id imx_ipu_dt_ids[] = {
765 { .compatible = "fsl,imx51-ipu", .data = &ipu_type_imx51, },
766 { .compatible = "fsl,imx53-ipu", .data = &ipu_type_imx53, },
767 { .compatible = "fsl,imx6q-ipu", .data = &ipu_type_imx6q, },
768 { /* sentinel */ }
769};
770MODULE_DEVICE_TABLE(of, imx_ipu_dt_ids);
771
772static int ipu_submodules_init(struct ipu_soc *ipu,
773 struct platform_device *pdev, unsigned long ipu_base,
774 struct clk *ipu_clk)
775{
776 char *unit;
777 int ret;
778 struct device *dev = &pdev->dev;
779 const struct ipu_devtype *devtype = ipu->devtype;
780
Steve Longerbeam7d2691d2014-06-25 18:05:47 -0700781 ret = ipu_cpmem_init(ipu, dev, ipu_base + devtype->cpmem_ofs);
782 if (ret) {
783 unit = "cpmem";
784 goto err_cpmem;
785 }
786
Steve Longerbeam2ffd48f2014-08-19 10:52:40 -0700787 ret = ipu_csi_init(ipu, dev, 0, ipu_base + devtype->csi0_ofs,
788 IPU_CONF_CSI0_EN, ipu_clk);
789 if (ret) {
790 unit = "csi0";
791 goto err_csi_0;
792 }
793
794 ret = ipu_csi_init(ipu, dev, 1, ipu_base + devtype->csi1_ofs,
795 IPU_CONF_CSI1_EN, ipu_clk);
796 if (ret) {
797 unit = "csi1";
798 goto err_csi_1;
799 }
800
Steve Longerbeam1aa8ea02014-08-11 13:04:50 +0200801 ret = ipu_ic_init(ipu, dev,
802 ipu_base + devtype->ic_ofs,
803 ipu_base + devtype->tpm_ofs);
804 if (ret) {
805 unit = "ic";
806 goto err_ic;
807 }
808
Sascha Haueraecfbdb2012-09-21 10:07:49 +0200809 ret = ipu_di_init(ipu, dev, 0, ipu_base + devtype->disp0_ofs,
Steve Longerbeam1aa8ea02014-08-11 13:04:50 +0200810 IPU_CONF_DI0_EN, ipu_clk);
Sascha Haueraecfbdb2012-09-21 10:07:49 +0200811 if (ret) {
812 unit = "di0";
813 goto err_di_0;
814 }
815
816 ret = ipu_di_init(ipu, dev, 1, ipu_base + devtype->disp1_ofs,
817 IPU_CONF_DI1_EN, ipu_clk);
818 if (ret) {
819 unit = "di1";
820 goto err_di_1;
821 }
822
823 ret = ipu_dc_init(ipu, dev, ipu_base + devtype->cm_ofs +
824 IPU_CM_DC_REG_OFS, ipu_base + devtype->dc_tmpl_ofs);
825 if (ret) {
826 unit = "dc_template";
827 goto err_dc;
828 }
829
830 ret = ipu_dmfc_init(ipu, dev, ipu_base +
831 devtype->cm_ofs + IPU_CM_DMFC_REG_OFS, ipu_clk);
832 if (ret) {
833 unit = "dmfc";
834 goto err_dmfc;
835 }
836
837 ret = ipu_dp_init(ipu, dev, ipu_base + devtype->srm_ofs);
838 if (ret) {
839 unit = "dp";
840 goto err_dp;
841 }
842
Philipp Zabel35de9252012-05-09 16:59:01 +0200843 ret = ipu_smfc_init(ipu, dev, ipu_base +
844 devtype->cm_ofs + IPU_CM_SMFC_REG_OFS);
845 if (ret) {
846 unit = "smfc";
847 goto err_smfc;
848 }
849
Sascha Haueraecfbdb2012-09-21 10:07:49 +0200850 return 0;
851
Philipp Zabel35de9252012-05-09 16:59:01 +0200852err_smfc:
853 ipu_dp_exit(ipu);
Sascha Haueraecfbdb2012-09-21 10:07:49 +0200854err_dp:
855 ipu_dmfc_exit(ipu);
856err_dmfc:
857 ipu_dc_exit(ipu);
858err_dc:
859 ipu_di_exit(ipu, 1);
860err_di_1:
861 ipu_di_exit(ipu, 0);
862err_di_0:
Steve Longerbeam1aa8ea02014-08-11 13:04:50 +0200863 ipu_ic_exit(ipu);
864err_ic:
Steve Longerbeam2ffd48f2014-08-19 10:52:40 -0700865 ipu_csi_exit(ipu, 1);
866err_csi_1:
867 ipu_csi_exit(ipu, 0);
868err_csi_0:
Steve Longerbeam7d2691d2014-06-25 18:05:47 -0700869 ipu_cpmem_exit(ipu);
870err_cpmem:
Sascha Haueraecfbdb2012-09-21 10:07:49 +0200871 dev_err(&pdev->dev, "init %s failed with %d\n", unit, ret);
872 return ret;
873}
874
875static void ipu_irq_handle(struct ipu_soc *ipu, const int *regs, int num_regs)
876{
877 unsigned long status;
Philipp Zabelb7287662013-06-21 10:27:39 +0200878 int i, bit, irq;
Sascha Haueraecfbdb2012-09-21 10:07:49 +0200879
880 for (i = 0; i < num_regs; i++) {
881
882 status = ipu_cm_read(ipu, IPU_INT_STAT(regs[i]));
883 status &= ipu_cm_read(ipu, IPU_INT_CTRL(regs[i]));
884
Philipp Zabelb7287662013-06-21 10:27:39 +0200885 for_each_set_bit(bit, &status, 32) {
Antoine Schweitzer-Chaput838201a2014-04-18 23:20:06 +0200886 irq = irq_linear_revmap(ipu->domain,
887 regs[i] * 32 + bit);
Philipp Zabelb7287662013-06-21 10:27:39 +0200888 if (irq)
889 generic_handle_irq(irq);
890 }
Sascha Haueraecfbdb2012-09-21 10:07:49 +0200891 }
892}
893
894static void ipu_irq_handler(unsigned int irq, struct irq_desc *desc)
895{
896 struct ipu_soc *ipu = irq_desc_get_handler_data(desc);
897 const int int_reg[] = { 0, 1, 2, 3, 10, 11, 12, 13, 14};
898 struct irq_chip *chip = irq_get_chip(irq);
899
900 chained_irq_enter(chip, desc);
901
902 ipu_irq_handle(ipu, int_reg, ARRAY_SIZE(int_reg));
903
904 chained_irq_exit(chip, desc);
905}
906
907static void ipu_err_irq_handler(unsigned int irq, struct irq_desc *desc)
908{
909 struct ipu_soc *ipu = irq_desc_get_handler_data(desc);
910 const int int_reg[] = { 4, 5, 8, 9};
911 struct irq_chip *chip = irq_get_chip(irq);
912
913 chained_irq_enter(chip, desc);
914
915 ipu_irq_handle(ipu, int_reg, ARRAY_SIZE(int_reg));
916
917 chained_irq_exit(chip, desc);
918}
919
Philipp Zabel861a50c2014-04-14 23:53:16 +0200920int ipu_map_irq(struct ipu_soc *ipu, int irq)
921{
922 int virq;
923
924 virq = irq_linear_revmap(ipu->domain, irq);
925 if (!virq)
926 virq = irq_create_mapping(ipu->domain, irq);
927
928 return virq;
929}
930EXPORT_SYMBOL_GPL(ipu_map_irq);
931
Sascha Haueraecfbdb2012-09-21 10:07:49 +0200932int ipu_idmac_channel_irq(struct ipu_soc *ipu, struct ipuv3_channel *channel,
933 enum ipu_channel_irq irq_type)
934{
Philipp Zabel861a50c2014-04-14 23:53:16 +0200935 return ipu_map_irq(ipu, irq_type + channel->num);
Sascha Haueraecfbdb2012-09-21 10:07:49 +0200936}
937EXPORT_SYMBOL_GPL(ipu_idmac_channel_irq);
938
939static void ipu_submodules_exit(struct ipu_soc *ipu)
940{
Philipp Zabel35de9252012-05-09 16:59:01 +0200941 ipu_smfc_exit(ipu);
Sascha Haueraecfbdb2012-09-21 10:07:49 +0200942 ipu_dp_exit(ipu);
943 ipu_dmfc_exit(ipu);
944 ipu_dc_exit(ipu);
945 ipu_di_exit(ipu, 1);
946 ipu_di_exit(ipu, 0);
Steve Longerbeam1aa8ea02014-08-11 13:04:50 +0200947 ipu_ic_exit(ipu);
Steve Longerbeam2ffd48f2014-08-19 10:52:40 -0700948 ipu_csi_exit(ipu, 1);
949 ipu_csi_exit(ipu, 0);
Steve Longerbeam7d2691d2014-06-25 18:05:47 -0700950 ipu_cpmem_exit(ipu);
Sascha Haueraecfbdb2012-09-21 10:07:49 +0200951}
952
953static int platform_remove_devices_fn(struct device *dev, void *unused)
954{
955 struct platform_device *pdev = to_platform_device(dev);
956
957 platform_device_unregister(pdev);
958
959 return 0;
960}
961
962static void platform_device_unregister_children(struct platform_device *pdev)
963{
964 device_for_each_child(&pdev->dev, NULL, platform_remove_devices_fn);
965}
966
967struct ipu_platform_reg {
968 struct ipu_client_platformdata pdata;
969 const char *name;
Philipp Zabeld6ca8ca2012-05-23 17:08:19 +0200970 int reg_offset;
Sascha Haueraecfbdb2012-09-21 10:07:49 +0200971};
972
973static const struct ipu_platform_reg client_reg[] = {
974 {
975 .pdata = {
976 .di = 0,
977 .dc = 5,
978 .dp = IPU_DP_FLOW_SYNC_BG,
979 .dma[0] = IPUV3_CHANNEL_MEM_BG_SYNC,
Philipp Zabelb8d181e2013-10-10 16:18:45 +0200980 .dma[1] = IPUV3_CHANNEL_MEM_FG_SYNC,
Sascha Haueraecfbdb2012-09-21 10:07:49 +0200981 },
982 .name = "imx-ipuv3-crtc",
983 }, {
984 .pdata = {
985 .di = 1,
986 .dc = 1,
987 .dp = -EINVAL,
988 .dma[0] = IPUV3_CHANNEL_MEM_DC_SYNC,
989 .dma[1] = -EINVAL,
990 },
991 .name = "imx-ipuv3-crtc",
Philipp Zabeld6ca8ca2012-05-23 17:08:19 +0200992 }, {
993 .pdata = {
994 .csi = 0,
995 .dma[0] = IPUV3_CHANNEL_CSI0,
996 .dma[1] = -EINVAL,
997 },
998 .reg_offset = IPU_CM_CSI0_REG_OFS,
999 .name = "imx-ipuv3-camera",
1000 }, {
1001 .pdata = {
1002 .csi = 1,
1003 .dma[0] = IPUV3_CHANNEL_CSI1,
1004 .dma[1] = -EINVAL,
1005 },
1006 .reg_offset = IPU_CM_CSI1_REG_OFS,
1007 .name = "imx-ipuv3-camera",
Sascha Haueraecfbdb2012-09-21 10:07:49 +02001008 },
1009};
1010
Russell King4ae078d2013-12-16 11:34:25 +00001011static DEFINE_MUTEX(ipu_client_id_mutex);
Sascha Haueraecfbdb2012-09-21 10:07:49 +02001012static int ipu_client_id;
1013
Philipp Zabeld6ca8ca2012-05-23 17:08:19 +02001014static int ipu_add_client_devices(struct ipu_soc *ipu, unsigned long ipu_base)
Sascha Haueraecfbdb2012-09-21 10:07:49 +02001015{
Russell King4ae078d2013-12-16 11:34:25 +00001016 struct device *dev = ipu->dev;
1017 unsigned i;
1018 int id, ret;
1019
1020 mutex_lock(&ipu_client_id_mutex);
1021 id = ipu_client_id;
1022 ipu_client_id += ARRAY_SIZE(client_reg);
1023 mutex_unlock(&ipu_client_id_mutex);
Sascha Haueraecfbdb2012-09-21 10:07:49 +02001024
1025 for (i = 0; i < ARRAY_SIZE(client_reg); i++) {
1026 const struct ipu_platform_reg *reg = &client_reg[i];
Russell King4ae078d2013-12-16 11:34:25 +00001027 struct platform_device *pdev;
Philipp Zabeld6ca8ca2012-05-23 17:08:19 +02001028 struct resource res;
Russell King4ae078d2013-12-16 11:34:25 +00001029
Philipp Zabeld6ca8ca2012-05-23 17:08:19 +02001030 if (reg->reg_offset) {
1031 memset(&res, 0, sizeof(res));
1032 res.flags = IORESOURCE_MEM;
1033 res.start = ipu_base + ipu->devtype->cm_ofs + reg->reg_offset;
1034 res.end = res.start + PAGE_SIZE - 1;
1035 pdev = platform_device_register_resndata(dev, reg->name,
1036 id++, &res, 1, &reg->pdata, sizeof(reg->pdata));
1037 } else {
1038 pdev = platform_device_register_data(dev, reg->name,
1039 id++, &reg->pdata, sizeof(reg->pdata));
1040 }
Russell King4ae078d2013-12-16 11:34:25 +00001041
1042 if (IS_ERR(pdev))
Sascha Haueraecfbdb2012-09-21 10:07:49 +02001043 goto err_register;
1044 }
1045
1046 return 0;
1047
1048err_register:
Russell King4ae078d2013-12-16 11:34:25 +00001049 platform_device_unregister_children(to_platform_device(dev));
Sascha Haueraecfbdb2012-09-21 10:07:49 +02001050
1051 return ret;
1052}
1053
Philipp Zabelb7287662013-06-21 10:27:39 +02001054
Sascha Haueraecfbdb2012-09-21 10:07:49 +02001055static int ipu_irq_init(struct ipu_soc *ipu)
1056{
Philipp Zabel379cdec2013-06-21 14:52:17 +02001057 struct irq_chip_generic *gc;
1058 struct irq_chip_type *ct;
Philipp Zabel37f85b262013-06-21 14:52:18 +02001059 unsigned long unused[IPU_NUM_IRQS / 32] = {
1060 0x400100d0, 0xffe000fd,
1061 0x400100d0, 0xffe000fd,
1062 0x400100d0, 0xffe000fd,
1063 0x4077ffff, 0xffe7e1fd,
1064 0x23fffffe, 0x8880fff0,
1065 0xf98fe7d0, 0xfff81fff,
1066 0x400100d0, 0xffe000fd,
1067 0x00000000,
1068 };
Philipp Zabel379cdec2013-06-21 14:52:17 +02001069 int ret, i;
1070
Philipp Zabelb7287662013-06-21 10:27:39 +02001071 ipu->domain = irq_domain_add_linear(ipu->dev->of_node, IPU_NUM_IRQS,
Philipp Zabel379cdec2013-06-21 14:52:17 +02001072 &irq_generic_chip_ops, ipu);
Philipp Zabelb7287662013-06-21 10:27:39 +02001073 if (!ipu->domain) {
1074 dev_err(ipu->dev, "failed to add irq domain\n");
1075 return -ENODEV;
Sascha Haueraecfbdb2012-09-21 10:07:49 +02001076 }
1077
Philipp Zabel379cdec2013-06-21 14:52:17 +02001078 ret = irq_alloc_domain_generic_chips(ipu->domain, 32, 1, "IPU",
Antoine Schweitzer-Chaput838201a2014-04-18 23:20:06 +02001079 handle_level_irq, 0,
1080 IRQF_VALID, 0);
Philipp Zabel379cdec2013-06-21 14:52:17 +02001081 if (ret < 0) {
1082 dev_err(ipu->dev, "failed to alloc generic irq chips\n");
1083 irq_domain_remove(ipu->domain);
1084 return ret;
1085 }
1086
1087 for (i = 0; i < IPU_NUM_IRQS; i += 32) {
1088 gc = irq_get_domain_generic_chip(ipu->domain, i);
1089 gc->reg_base = ipu->cm_reg;
Philipp Zabel37f85b262013-06-21 14:52:18 +02001090 gc->unused = unused[i / 32];
Philipp Zabel379cdec2013-06-21 14:52:17 +02001091 ct = gc->chip_types;
1092 ct->chip.irq_ack = irq_gc_ack_set_bit;
1093 ct->chip.irq_mask = irq_gc_mask_clr_bit;
1094 ct->chip.irq_unmask = irq_gc_mask_set_bit;
1095 ct->regs.ack = IPU_INT_STAT(i / 32);
1096 ct->regs.mask = IPU_INT_CTRL(i / 32);
1097 }
1098
Sascha Haueraecfbdb2012-09-21 10:07:49 +02001099 irq_set_chained_handler(ipu->irq_sync, ipu_irq_handler);
1100 irq_set_handler_data(ipu->irq_sync, ipu);
1101 irq_set_chained_handler(ipu->irq_err, ipu_err_irq_handler);
1102 irq_set_handler_data(ipu->irq_err, ipu);
1103
1104 return 0;
1105}
1106
1107static void ipu_irq_exit(struct ipu_soc *ipu)
1108{
Philipp Zabelb7287662013-06-21 10:27:39 +02001109 int i, irq;
Sascha Haueraecfbdb2012-09-21 10:07:49 +02001110
1111 irq_set_chained_handler(ipu->irq_err, NULL);
1112 irq_set_handler_data(ipu->irq_err, NULL);
1113 irq_set_chained_handler(ipu->irq_sync, NULL);
1114 irq_set_handler_data(ipu->irq_sync, NULL);
1115
Philipp Zabel379cdec2013-06-21 14:52:17 +02001116 /* TODO: remove irq_domain_generic_chips */
1117
Philipp Zabelb7287662013-06-21 10:27:39 +02001118 for (i = 0; i < IPU_NUM_IRQS; i++) {
1119 irq = irq_linear_revmap(ipu->domain, i);
1120 if (irq)
1121 irq_dispose_mapping(irq);
Sascha Haueraecfbdb2012-09-21 10:07:49 +02001122 }
1123
Philipp Zabelb7287662013-06-21 10:27:39 +02001124 irq_domain_remove(ipu->domain);
Sascha Haueraecfbdb2012-09-21 10:07:49 +02001125}
1126
Bill Pembertonc4aabf82012-11-19 13:22:11 -05001127static int ipu_probe(struct platform_device *pdev)
Sascha Haueraecfbdb2012-09-21 10:07:49 +02001128{
1129 const struct of_device_id *of_id =
1130 of_match_device(imx_ipu_dt_ids, &pdev->dev);
1131 struct ipu_soc *ipu;
1132 struct resource *res;
1133 unsigned long ipu_base;
1134 int i, ret, irq_sync, irq_err;
1135 const struct ipu_devtype *devtype;
1136
1137 devtype = of_id->data;
1138
Sascha Haueraecfbdb2012-09-21 10:07:49 +02001139 irq_sync = platform_get_irq(pdev, 0);
1140 irq_err = platform_get_irq(pdev, 1);
1141 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1142
Fabio Estevamfd563db2012-10-24 21:36:46 -02001143 dev_dbg(&pdev->dev, "irq_sync: %d irq_err: %d\n",
Sascha Haueraecfbdb2012-09-21 10:07:49 +02001144 irq_sync, irq_err);
1145
1146 if (!res || irq_sync < 0 || irq_err < 0)
1147 return -ENODEV;
1148
1149 ipu_base = res->start;
1150
1151 ipu = devm_kzalloc(&pdev->dev, sizeof(*ipu), GFP_KERNEL);
1152 if (!ipu)
1153 return -ENODEV;
1154
1155 for (i = 0; i < 64; i++)
1156 ipu->channel[i].ipu = ipu;
1157 ipu->devtype = devtype;
1158 ipu->ipu_type = devtype->type;
1159
1160 spin_lock_init(&ipu->lock);
1161 mutex_init(&ipu->channel_lock);
1162
Fabio Estevamfd563db2012-10-24 21:36:46 -02001163 dev_dbg(&pdev->dev, "cm_reg: 0x%08lx\n",
Sascha Haueraecfbdb2012-09-21 10:07:49 +02001164 ipu_base + devtype->cm_ofs);
Fabio Estevamfd563db2012-10-24 21:36:46 -02001165 dev_dbg(&pdev->dev, "idmac: 0x%08lx\n",
Sascha Haueraecfbdb2012-09-21 10:07:49 +02001166 ipu_base + devtype->cm_ofs + IPU_CM_IDMAC_REG_OFS);
Fabio Estevamfd563db2012-10-24 21:36:46 -02001167 dev_dbg(&pdev->dev, "cpmem: 0x%08lx\n",
Sascha Haueraecfbdb2012-09-21 10:07:49 +02001168 ipu_base + devtype->cpmem_ofs);
Steve Longerbeam2ffd48f2014-08-19 10:52:40 -07001169 dev_dbg(&pdev->dev, "csi0: 0x%08lx\n",
1170 ipu_base + devtype->csi0_ofs);
1171 dev_dbg(&pdev->dev, "csi1: 0x%08lx\n",
1172 ipu_base + devtype->csi1_ofs);
Steve Longerbeam1aa8ea02014-08-11 13:04:50 +02001173 dev_dbg(&pdev->dev, "ic: 0x%08lx\n",
1174 ipu_base + devtype->ic_ofs);
Fabio Estevamfd563db2012-10-24 21:36:46 -02001175 dev_dbg(&pdev->dev, "disp0: 0x%08lx\n",
Sascha Haueraecfbdb2012-09-21 10:07:49 +02001176 ipu_base + devtype->disp0_ofs);
Fabio Estevamfd563db2012-10-24 21:36:46 -02001177 dev_dbg(&pdev->dev, "disp1: 0x%08lx\n",
Sascha Haueraecfbdb2012-09-21 10:07:49 +02001178 ipu_base + devtype->disp1_ofs);
Fabio Estevamfd563db2012-10-24 21:36:46 -02001179 dev_dbg(&pdev->dev, "srm: 0x%08lx\n",
Sascha Haueraecfbdb2012-09-21 10:07:49 +02001180 ipu_base + devtype->srm_ofs);
Fabio Estevamfd563db2012-10-24 21:36:46 -02001181 dev_dbg(&pdev->dev, "tpm: 0x%08lx\n",
Sascha Haueraecfbdb2012-09-21 10:07:49 +02001182 ipu_base + devtype->tpm_ofs);
Fabio Estevamfd563db2012-10-24 21:36:46 -02001183 dev_dbg(&pdev->dev, "dc: 0x%08lx\n",
Sascha Haueraecfbdb2012-09-21 10:07:49 +02001184 ipu_base + devtype->cm_ofs + IPU_CM_DC_REG_OFS);
Fabio Estevamfd563db2012-10-24 21:36:46 -02001185 dev_dbg(&pdev->dev, "ic: 0x%08lx\n",
Sascha Haueraecfbdb2012-09-21 10:07:49 +02001186 ipu_base + devtype->cm_ofs + IPU_CM_IC_REG_OFS);
Fabio Estevamfd563db2012-10-24 21:36:46 -02001187 dev_dbg(&pdev->dev, "dmfc: 0x%08lx\n",
Sascha Haueraecfbdb2012-09-21 10:07:49 +02001188 ipu_base + devtype->cm_ofs + IPU_CM_DMFC_REG_OFS);
Fabio Estevamfd563db2012-10-24 21:36:46 -02001189 dev_dbg(&pdev->dev, "vdi: 0x%08lx\n",
Sascha Haueraecfbdb2012-09-21 10:07:49 +02001190 ipu_base + devtype->vdi_ofs);
1191
1192 ipu->cm_reg = devm_ioremap(&pdev->dev,
1193 ipu_base + devtype->cm_ofs, PAGE_SIZE);
1194 ipu->idmac_reg = devm_ioremap(&pdev->dev,
1195 ipu_base + devtype->cm_ofs + IPU_CM_IDMAC_REG_OFS,
1196 PAGE_SIZE);
Sascha Haueraecfbdb2012-09-21 10:07:49 +02001197
Steve Longerbeam7d2691d2014-06-25 18:05:47 -07001198 if (!ipu->cm_reg || !ipu->idmac_reg)
Fabio Estevambe798b22013-07-20 18:22:09 -03001199 return -ENOMEM;
Sascha Haueraecfbdb2012-09-21 10:07:49 +02001200
1201 ipu->clk = devm_clk_get(&pdev->dev, "bus");
1202 if (IS_ERR(ipu->clk)) {
1203 ret = PTR_ERR(ipu->clk);
1204 dev_err(&pdev->dev, "clk_get failed with %d", ret);
Fabio Estevambe798b22013-07-20 18:22:09 -03001205 return ret;
Sascha Haueraecfbdb2012-09-21 10:07:49 +02001206 }
1207
1208 platform_set_drvdata(pdev, ipu);
1209
Fabio Estevam62645a22013-07-20 18:22:10 -03001210 ret = clk_prepare_enable(ipu->clk);
1211 if (ret) {
1212 dev_err(&pdev->dev, "clk_prepare_enable failed: %d\n", ret);
1213 return ret;
1214 }
Sascha Haueraecfbdb2012-09-21 10:07:49 +02001215
1216 ipu->dev = &pdev->dev;
1217 ipu->irq_sync = irq_sync;
1218 ipu->irq_err = irq_err;
1219
1220 ret = ipu_irq_init(ipu);
1221 if (ret)
1222 goto out_failed_irq;
1223
Philipp Zabel6c641552013-03-28 17:35:21 +01001224 ret = device_reset(&pdev->dev);
1225 if (ret) {
1226 dev_err(&pdev->dev, "failed to reset: %d\n", ret);
1227 goto out_failed_reset;
1228 }
1229 ret = ipu_memory_reset(ipu);
Lothar Waßmann4d27b2c2012-12-25 15:58:37 +01001230 if (ret)
1231 goto out_failed_reset;
Sascha Haueraecfbdb2012-09-21 10:07:49 +02001232
1233 /* Set MCU_T to divide MCU access window into 2 */
1234 ipu_cm_write(ipu, 0x00400000L | (IPU_MCU_T_DEFAULT << 18),
1235 IPU_DISP_GEN);
1236
1237 ret = ipu_submodules_init(ipu, pdev, ipu_base, ipu->clk);
1238 if (ret)
1239 goto failed_submodules_init;
1240
Philipp Zabeld6ca8ca2012-05-23 17:08:19 +02001241 ret = ipu_add_client_devices(ipu, ipu_base);
Sascha Haueraecfbdb2012-09-21 10:07:49 +02001242 if (ret) {
1243 dev_err(&pdev->dev, "adding client devices failed with %d\n",
1244 ret);
1245 goto failed_add_clients;
1246 }
1247
Fabio Estevam9c2c4382012-10-24 21:36:47 -02001248 dev_info(&pdev->dev, "%s probed\n", devtype->name);
1249
Sascha Haueraecfbdb2012-09-21 10:07:49 +02001250 return 0;
1251
1252failed_add_clients:
1253 ipu_submodules_exit(ipu);
1254failed_submodules_init:
Lothar Waßmann4d27b2c2012-12-25 15:58:37 +01001255out_failed_reset:
Philipp Zabel6c641552013-03-28 17:35:21 +01001256 ipu_irq_exit(ipu);
Sascha Haueraecfbdb2012-09-21 10:07:49 +02001257out_failed_irq:
1258 clk_disable_unprepare(ipu->clk);
Sascha Haueraecfbdb2012-09-21 10:07:49 +02001259 return ret;
1260}
1261
Bill Pemberton8aa1be42012-11-19 13:26:38 -05001262static int ipu_remove(struct platform_device *pdev)
Sascha Haueraecfbdb2012-09-21 10:07:49 +02001263{
1264 struct ipu_soc *ipu = platform_get_drvdata(pdev);
Sascha Haueraecfbdb2012-09-21 10:07:49 +02001265
1266 platform_device_unregister_children(pdev);
1267 ipu_submodules_exit(ipu);
1268 ipu_irq_exit(ipu);
1269
1270 clk_disable_unprepare(ipu->clk);
1271
1272 return 0;
1273}
1274
1275static struct platform_driver imx_ipu_driver = {
1276 .driver = {
1277 .name = "imx-ipuv3",
1278 .of_match_table = imx_ipu_dt_ids,
1279 },
1280 .probe = ipu_probe,
Bill Pemberton99c28f12012-11-19 13:20:51 -05001281 .remove = ipu_remove,
Sascha Haueraecfbdb2012-09-21 10:07:49 +02001282};
1283
1284module_platform_driver(imx_ipu_driver);
1285
Fabio Estevam10f22682013-07-20 18:22:11 -03001286MODULE_ALIAS("platform:imx-ipuv3");
Sascha Haueraecfbdb2012-09-21 10:07:49 +02001287MODULE_DESCRIPTION("i.MX IPU v3 driver");
1288MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
1289MODULE_LICENSE("GPL");