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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07002 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
3 * Portions Copyright (C) 2001 Sun Microsystems, Inc.
4 * Portions Copyright (C) 2003 Red Hat Inc
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02005 * Portions Copyright (C) 2007 Bartlomiej Zolnierkiewicz
Sergei Shtylyov59c8d042009-04-18 17:42:19 +02006 * Portions Copyright (C) 2005-2009 MontaVista Software, Inc.
Linus Torvalds1da177e2005-04-16 15:20:36 -07007 *
8 * Thanks to HighPoint Technologies for their assistance, and hardware.
9 * Special Thanks to Jon Burchmore in SanDiego for the deep pockets, his
10 * donation of an ABit BP6 mainboard, processor, and memory acellerated
11 * development and support.
12 *
Alan Coxb39b01f2005-06-27 15:24:27 -070013 *
Sergei Shtylyov836c0062006-12-13 00:35:47 -080014 * HighPoint has its own drivers (open source except for the RAID part)
Justin P. Mattock631dd1a2010-10-18 11:03:14 +020015 * available from http://www.highpoint-tech.com/USA_new/service_support.htm
Sergei Shtylyov836c0062006-12-13 00:35:47 -080016 * This may be useful to anyone wanting to work on this driver, however do not
17 * trust them too much since the code tends to become less and less meaningful
18 * as the time passes... :-/
Alan Coxb39b01f2005-06-27 15:24:27 -070019 *
Linus Torvalds1da177e2005-04-16 15:20:36 -070020 * Note that final HPT370 support was done by force extraction of GPL.
21 *
22 * - add function for getting/setting power status of drive
23 * - the HPT370's state machine can get confused. reset it before each dma
24 * xfer to prevent that from happening.
25 * - reset state engine whenever we get an error.
26 * - check for busmaster state at end of dma.
27 * - use new highpoint timings.
28 * - detect bus speed using highpoint register.
29 * - use pll if we don't have a clock table. added a 66MHz table that's
30 * just 2x the 33MHz table.
31 * - removed turnaround. NOTE: we never want to switch between pll and
32 * pci clocks as the chip can glitch in those cases. the highpoint
33 * approved workaround slows everything down too much to be useful. in
34 * addition, we would have to serialize access to each chip.
35 * Adrian Sun <a.sun@sun.com>
36 *
37 * add drive timings for 66MHz PCI bus,
38 * fix ATA Cable signal detection, fix incorrect /proc info
39 * add /proc display for per-drive PIO/DMA/UDMA mode and
40 * per-channel ATA-33/66 Cable detect.
41 * Duncan Laurie <void@sun.com>
42 *
43 * fixup /proc output for multiple controllers
44 * Tim Hockin <thockin@sun.com>
45 *
46 * On hpt366:
47 * Reset the hpt366 on error, reset on dma
48 * Fix disabling Fast Interrupt hpt366.
49 * Mike Waychison <crlf@sun.com>
50 *
51 * Added support for 372N clocking and clock switching. The 372N needs
52 * different clocks on read/write. This requires overloading rw_disk and
53 * other deeply crazy things. Thanks to <http://www.hoerstreich.de> for
54 * keeping me sane.
Alan Coxccd32e22008-11-02 21:40:08 +010055 * Alan Cox <alan@lxorguk.ukuu.org.uk>
Linus Torvalds1da177e2005-04-16 15:20:36 -070056 *
Sergei Shtylyov836c0062006-12-13 00:35:47 -080057 * - fix the clock turnaround code: it was writing to the wrong ports when
58 * called for the secondary channel, caching the current clock mode per-
59 * channel caused the cached register value to get out of sync with the
60 * actual one, the channels weren't serialized, the turnaround shouldn't
61 * be done on 66 MHz PCI bus
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +010062 * - disable UltraATA/100 for HPT370 by default as the 33 MHz clock being used
63 * does not allow for this speed anyway
64 * - avoid touching disabled channels (e.g. HPT371/N are single channel chips,
65 * their primary channel is kind of virtual, it isn't tied to any pins)
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -080066 * - fix/remove bad/unused timing tables and use one set of tables for the whole
67 * HPT37x chip family; save space by introducing the separate transfer mode
68 * table in which the mode lookup is done
Sergei Shtylyov26c068d2006-12-13 00:35:52 -080069 * - use f_CNT value saved by the HighPoint BIOS as reading it directly gives
Sergei Shtylyov72931362007-09-11 22:28:35 +020070 * the wrong PCI frequency since DPLL has already been calibrated by BIOS;
71 * read it only from the function 0 of HPT374 chips
Sergei Shtylyov33b18a62006-12-13 00:35:50 -080072 * - fix the hotswap code: it caused RESET- to glitch when tristating the bus,
73 * and for HPT36x the obsolete HDIO_TRISTATE_HWIF handler was called instead
Sergei Shtylyov73d1dd92006-12-13 00:35:51 -080074 * - pass to init_chipset() handlers a copy of the IDE PCI device structure as
75 * they tamper with its fields
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +010076 * - pass to the init_setup handlers a copy of the ide_pci_device_t structure
77 * since they may tamper with its fields
Sergei Shtylyov90778572007-02-07 18:17:51 +010078 * - prefix the driver startup messages with the real chip name
79 * - claim the extra 240 bytes of I/O space for all chips
Sergei Shtylyov2648e5d2007-07-09 23:17:55 +020080 * - optimize the UltraDMA filtering and the drive list lookup code
Sergei Shtylyovb4586712007-02-07 18:17:54 +010081 * - use pci_get_slot() to get to the function 1 of HPT36x/374
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +010082 * - cache offset of the channel's misc. control registers (MCRs) being used
83 * throughout the driver
84 * - only touch the relevant MCR when detecting the cable type on HPT374's
85 * function 1
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +010086 * - rename all the register related variables consistently
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +010087 * - move all the interrupt twiddling code from the speedproc handlers into
88 * init_hwif_hpt366(), also grouping all the DMA related code together there
Sergei Shtylyov866664d2008-01-25 22:17:05 +010089 * - merge HPT36x/HPT37x speedproc handlers, fix PIO timing register mask and
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +010090 * separate the UltraDMA and MWDMA masks there to avoid changing PIO timings
91 * when setting an UltraDMA mode
92 * - fix hpt3xx_tune_drive() to set the PIO mode requested, not always select
93 * the best possible one
Sergei Shtylyov4bf63de2007-02-07 18:18:13 +010094 * - clean up DMA timeout handling for HPT370
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +010095 * - switch to using the enumeration type to differ between the numerous chip
96 * variants, matching PCI device/revision ID with the chip type early, at the
97 * init_setup stage
98 * - extend the hpt_info structure to hold the DPLL and PCI clock frequencies,
99 * stop duplicating it for each channel by storing the pointer in the pci_dev
100 * structure: first, at the init_setup stage, point it to a static "template"
101 * with only the chip type and its specific base DPLL frequency, the highest
Sergei Shtylyov2648e5d2007-07-09 23:17:55 +0200102 * UltraDMA mode, and the chip settings table pointer filled, then, at the
103 * init_chipset stage, allocate per-chip instance and fill it with the rest
104 * of the necessary information
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100105 * - get rid of the constant thresholds in the HPT37x PCI clock detection code,
106 * switch to calculating PCI clock frequency based on the chip's base DPLL
107 * frequency
108 * - switch to using the DPLL clock and enable UltraATA/133 mode by default on
Sergei Shtylyov278978e2007-06-08 15:14:32 +0200109 * anything newer than HPT370/A (except HPT374 that is not capable of this
110 * mode according to the manual)
Sergei Shtylyov6273d262007-02-07 18:18:20 +0100111 * - fold PCI clock detection and DPLL setup code into init_chipset_hpt366(),
112 * also fixing the interchanged 25/40 MHz PCI clock cases for HPT36x chips;
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100113 * unify HPT36x/37x timing setup code and the speedproc handlers by joining
114 * the register setting lists into the table indexed by the clock selected
Sergei Shtylyov2648e5d2007-07-09 23:17:55 +0200115 * - set the correct hwif->ultra_mask for each individual chip
Sergei Shtylyovb4e44362007-10-11 23:53:58 +0200116 * - add Ultra and MW DMA mode filtering for the HPT37[24] based SATA cards
Sergei Shtylyovc018f1e2009-04-18 17:42:19 +0200117 * - stop resetting HPT370's state machine before each DMA transfer as that has
118 * caused more harm than good
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100119 * Sergei Shtylyov, <sshtylyov@ru.mvista.com> or <source@mvista.com>
Linus Torvalds1da177e2005-04-16 15:20:36 -0700120 */
121
Linus Torvalds1da177e2005-04-16 15:20:36 -0700122#include <linux/types.h>
123#include <linux/module.h>
124#include <linux/kernel.h>
125#include <linux/delay.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -0700126#include <linux/blkdev.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -0700127#include <linux/interrupt.h>
128#include <linux/pci.h>
129#include <linux/init.h>
130#include <linux/ide.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +0900131#include <linux/slab.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -0700132
133#include <asm/uaccess.h>
134#include <asm/io.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -0700135
Bartlomiej Zolnierkiewiczced3ec82008-07-24 22:53:32 +0200136#define DRV_NAME "hpt366"
137
Linus Torvalds1da177e2005-04-16 15:20:36 -0700138/* various tuning parameters */
Sergei Shtylyovc018f1e2009-04-18 17:42:19 +0200139#undef HPT_RESET_STATE_ENGINE
Sergei Shtylyov836c0062006-12-13 00:35:47 -0800140#undef HPT_DELAY_INTERRUPT
Linus Torvalds1da177e2005-04-16 15:20:36 -0700141
Linus Torvalds1da177e2005-04-16 15:20:36 -0700142static const char *bad_ata100_5[] = {
143 "IBM-DTLA-307075",
144 "IBM-DTLA-307060",
145 "IBM-DTLA-307045",
146 "IBM-DTLA-307030",
147 "IBM-DTLA-307020",
148 "IBM-DTLA-307015",
149 "IBM-DTLA-305040",
150 "IBM-DTLA-305030",
151 "IBM-DTLA-305020",
152 "IC35L010AVER07-0",
153 "IC35L020AVER07-0",
154 "IC35L030AVER07-0",
155 "IC35L040AVER07-0",
156 "IC35L060AVER07-0",
157 "WDC AC310200R",
158 NULL
159};
160
161static const char *bad_ata66_4[] = {
162 "IBM-DTLA-307075",
163 "IBM-DTLA-307060",
164 "IBM-DTLA-307045",
165 "IBM-DTLA-307030",
166 "IBM-DTLA-307020",
167 "IBM-DTLA-307015",
168 "IBM-DTLA-305040",
169 "IBM-DTLA-305030",
170 "IBM-DTLA-305020",
171 "IC35L010AVER07-0",
172 "IC35L020AVER07-0",
173 "IC35L030AVER07-0",
174 "IC35L040AVER07-0",
175 "IC35L060AVER07-0",
176 "WDC AC310200R",
Sergei Shtylyov783353b2007-07-03 22:28:35 +0200177 "MAXTOR STM3320620A",
Linus Torvalds1da177e2005-04-16 15:20:36 -0700178 NULL
179};
180
181static const char *bad_ata66_3[] = {
182 "WDC AC310200R",
183 NULL
184};
185
186static const char *bad_ata33[] = {
187 "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
188 "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
189 "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
190 "Maxtor 90510D4",
191 "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
192 "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
193 "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
194 NULL
195};
196
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800197static u8 xfer_speeds[] = {
198 XFER_UDMA_6,
199 XFER_UDMA_5,
200 XFER_UDMA_4,
201 XFER_UDMA_3,
202 XFER_UDMA_2,
203 XFER_UDMA_1,
204 XFER_UDMA_0,
205
206 XFER_MW_DMA_2,
207 XFER_MW_DMA_1,
208 XFER_MW_DMA_0,
209
210 XFER_PIO_4,
211 XFER_PIO_3,
212 XFER_PIO_2,
213 XFER_PIO_1,
214 XFER_PIO_0
Linus Torvalds1da177e2005-04-16 15:20:36 -0700215};
216
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800217/* Key for bus clock timings
218 * 36x 37x
219 * bits bits
220 * 0:3 0:3 data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA.
221 * cycles = value + 1
222 * 4:7 4:8 data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA.
223 * cycles = value + 1
224 * 8:11 9:12 cmd_high_time. Inactive time of DIOW_/DIOR_ during task file
225 * register access.
226 * 12:15 13:17 cmd_low_time. Active time of DIOW_/DIOR_ during task file
227 * register access.
228 * 16:18 18:20 udma_cycle_time. Clock cycles for UDMA xfer.
229 * - 21 CLK frequency: 0=ATA clock, 1=dual ATA clock.
230 * 19:21 22:24 pre_high_time. Time to initialize the 1st cycle for PIO and
231 * MW DMA xfer.
232 * 22:24 25:27 cmd_pre_high_time. Time to initialize the 1st PIO cycle for
233 * task file register access.
234 * 28 28 UDMA enable.
235 * 29 29 DMA enable.
236 * 30 30 PIO MST enable. If set, the chip is in bus master mode during
237 * PIO xfer.
238 * 31 31 FIFO enable.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700239 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700240
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800241static u32 forty_base_hpt36x[] = {
242 /* XFER_UDMA_6 */ 0x900fd943,
243 /* XFER_UDMA_5 */ 0x900fd943,
244 /* XFER_UDMA_4 */ 0x900fd943,
245 /* XFER_UDMA_3 */ 0x900ad943,
246 /* XFER_UDMA_2 */ 0x900bd943,
247 /* XFER_UDMA_1 */ 0x9008d943,
248 /* XFER_UDMA_0 */ 0x9008d943,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700249
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800250 /* XFER_MW_DMA_2 */ 0xa008d943,
251 /* XFER_MW_DMA_1 */ 0xa010d955,
252 /* XFER_MW_DMA_0 */ 0xa010d9fc,
253
254 /* XFER_PIO_4 */ 0xc008d963,
255 /* XFER_PIO_3 */ 0xc010d974,
256 /* XFER_PIO_2 */ 0xc010d997,
257 /* XFER_PIO_1 */ 0xc010d9c7,
258 /* XFER_PIO_0 */ 0xc018d9d9
Linus Torvalds1da177e2005-04-16 15:20:36 -0700259};
260
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800261static u32 thirty_three_base_hpt36x[] = {
262 /* XFER_UDMA_6 */ 0x90c9a731,
263 /* XFER_UDMA_5 */ 0x90c9a731,
264 /* XFER_UDMA_4 */ 0x90c9a731,
265 /* XFER_UDMA_3 */ 0x90cfa731,
266 /* XFER_UDMA_2 */ 0x90caa731,
267 /* XFER_UDMA_1 */ 0x90cba731,
268 /* XFER_UDMA_0 */ 0x90c8a731,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700269
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800270 /* XFER_MW_DMA_2 */ 0xa0c8a731,
271 /* XFER_MW_DMA_1 */ 0xa0c8a732, /* 0xa0c8a733 */
272 /* XFER_MW_DMA_0 */ 0xa0c8a797,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700273
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800274 /* XFER_PIO_4 */ 0xc0c8a731,
275 /* XFER_PIO_3 */ 0xc0c8a742,
276 /* XFER_PIO_2 */ 0xc0d0a753,
277 /* XFER_PIO_1 */ 0xc0d0a7a3, /* 0xc0d0a793 */
278 /* XFER_PIO_0 */ 0xc0d0a7aa /* 0xc0d0a7a7 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700279};
280
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800281static u32 twenty_five_base_hpt36x[] = {
282 /* XFER_UDMA_6 */ 0x90c98521,
283 /* XFER_UDMA_5 */ 0x90c98521,
284 /* XFER_UDMA_4 */ 0x90c98521,
285 /* XFER_UDMA_3 */ 0x90cf8521,
286 /* XFER_UDMA_2 */ 0x90cf8521,
287 /* XFER_UDMA_1 */ 0x90cb8521,
288 /* XFER_UDMA_0 */ 0x90cb8521,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700289
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800290 /* XFER_MW_DMA_2 */ 0xa0ca8521,
291 /* XFER_MW_DMA_1 */ 0xa0ca8532,
292 /* XFER_MW_DMA_0 */ 0xa0ca8575,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700293
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800294 /* XFER_PIO_4 */ 0xc0ca8521,
295 /* XFER_PIO_3 */ 0xc0ca8532,
296 /* XFER_PIO_2 */ 0xc0ca8542,
297 /* XFER_PIO_1 */ 0xc0d08572,
298 /* XFER_PIO_0 */ 0xc0d08585
Linus Torvalds1da177e2005-04-16 15:20:36 -0700299};
300
Sergei Shtylyov809b53c2007-12-12 23:31:58 +0100301/*
302 * The following are the new timing tables with PIO mode data/taskfile transfer
303 * overclocking fixed...
304 */
305
306/* This table is taken from the HPT370 data manual rev. 1.02 */
307static u32 thirty_three_base_hpt37x[] = {
308 /* XFER_UDMA_6 */ 0x16455031, /* 0x16655031 ?? */
309 /* XFER_UDMA_5 */ 0x16455031,
310 /* XFER_UDMA_4 */ 0x16455031,
311 /* XFER_UDMA_3 */ 0x166d5031,
312 /* XFER_UDMA_2 */ 0x16495031,
313 /* XFER_UDMA_1 */ 0x164d5033,
314 /* XFER_UDMA_0 */ 0x16515097,
315
316 /* XFER_MW_DMA_2 */ 0x26515031,
317 /* XFER_MW_DMA_1 */ 0x26515033,
318 /* XFER_MW_DMA_0 */ 0x26515097,
319
320 /* XFER_PIO_4 */ 0x06515021,
321 /* XFER_PIO_3 */ 0x06515022,
322 /* XFER_PIO_2 */ 0x06515033,
323 /* XFER_PIO_1 */ 0x06915065,
324 /* XFER_PIO_0 */ 0x06d1508a
325};
326
327static u32 fifty_base_hpt37x[] = {
328 /* XFER_UDMA_6 */ 0x1a861842,
329 /* XFER_UDMA_5 */ 0x1a861842,
330 /* XFER_UDMA_4 */ 0x1aae1842,
331 /* XFER_UDMA_3 */ 0x1a8e1842,
332 /* XFER_UDMA_2 */ 0x1a0e1842,
333 /* XFER_UDMA_1 */ 0x1a161854,
334 /* XFER_UDMA_0 */ 0x1a1a18ea,
335
336 /* XFER_MW_DMA_2 */ 0x2a821842,
337 /* XFER_MW_DMA_1 */ 0x2a821854,
338 /* XFER_MW_DMA_0 */ 0x2a8218ea,
339
340 /* XFER_PIO_4 */ 0x0a821842,
341 /* XFER_PIO_3 */ 0x0a821843,
342 /* XFER_PIO_2 */ 0x0a821855,
343 /* XFER_PIO_1 */ 0x0ac218a8,
344 /* XFER_PIO_0 */ 0x0b02190c
345};
346
347static u32 sixty_six_base_hpt37x[] = {
348 /* XFER_UDMA_6 */ 0x1c86fe62,
349 /* XFER_UDMA_5 */ 0x1caefe62, /* 0x1c8afe62 */
350 /* XFER_UDMA_4 */ 0x1c8afe62,
351 /* XFER_UDMA_3 */ 0x1c8efe62,
352 /* XFER_UDMA_2 */ 0x1c92fe62,
353 /* XFER_UDMA_1 */ 0x1c9afe62,
354 /* XFER_UDMA_0 */ 0x1c82fe62,
355
356 /* XFER_MW_DMA_2 */ 0x2c82fe62,
357 /* XFER_MW_DMA_1 */ 0x2c82fe66,
358 /* XFER_MW_DMA_0 */ 0x2c82ff2e,
359
360 /* XFER_PIO_4 */ 0x0c82fe62,
361 /* XFER_PIO_3 */ 0x0c82fe84,
362 /* XFER_PIO_2 */ 0x0c82fea6,
363 /* XFER_PIO_1 */ 0x0d02ff26,
364 /* XFER_PIO_0 */ 0x0d42ff7f
365};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700366
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100367#define HPT371_ALLOW_ATA133_6 1
368#define HPT302_ALLOW_ATA133_6 1
369#define HPT372_ALLOW_ATA133_6 1
Sergei Shtylyove139b0b2007-02-07 18:17:37 +0100370#define HPT370_ALLOW_ATA100_5 0
Linus Torvalds1da177e2005-04-16 15:20:36 -0700371#define HPT366_ALLOW_ATA66_4 1
372#define HPT366_ALLOW_ATA66_3 1
Linus Torvalds1da177e2005-04-16 15:20:36 -0700373
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100374/* Supported ATA clock frequencies */
375enum ata_clock {
376 ATA_CLOCK_25MHZ,
377 ATA_CLOCK_33MHZ,
378 ATA_CLOCK_40MHZ,
379 ATA_CLOCK_50MHZ,
380 ATA_CLOCK_66MHZ,
381 NUM_ATA_CLOCKS
Alan Coxb39b01f2005-06-27 15:24:27 -0700382};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700383
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100384struct hpt_timings {
385 u32 pio_mask;
386 u32 dma_mask;
387 u32 ultra_mask;
388 u32 *clock_table[NUM_ATA_CLOCKS];
389};
390
Alan Coxb39b01f2005-06-27 15:24:27 -0700391/*
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100392 * Hold all the HighPoint chip information in one place.
Alan Coxb39b01f2005-06-27 15:24:27 -0700393 */
394
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100395struct hpt_info {
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200396 char *chip_name; /* Chip name */
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100397 u8 chip_type; /* Chip type */
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200398 u8 udma_mask; /* Allowed UltraDMA modes mask. */
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100399 u8 dpll_clk; /* DPLL clock in MHz */
400 u8 pci_clk; /* PCI clock in MHz */
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100401 struct hpt_timings *timings; /* Chipset timing data */
402 u8 clock; /* ATA clock selected */
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100403};
Sergei Shtylyove139b0b2007-02-07 18:17:37 +0100404
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100405/* Supported HighPoint chips */
406enum {
407 HPT36x,
408 HPT370,
409 HPT370A,
410 HPT374,
411 HPT372,
412 HPT372A,
413 HPT302,
414 HPT371,
415 HPT372N,
416 HPT302N,
417 HPT371N
418};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700419
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100420static struct hpt_timings hpt36x_timings = {
421 .pio_mask = 0xc1f8ffff,
422 .dma_mask = 0x303800ff,
423 .ultra_mask = 0x30070000,
424 .clock_table = {
425 [ATA_CLOCK_25MHZ] = twenty_five_base_hpt36x,
426 [ATA_CLOCK_33MHZ] = thirty_three_base_hpt36x,
427 [ATA_CLOCK_40MHZ] = forty_base_hpt36x,
428 [ATA_CLOCK_50MHZ] = NULL,
429 [ATA_CLOCK_66MHZ] = NULL
430 }
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100431};
432
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100433static struct hpt_timings hpt37x_timings = {
434 .pio_mask = 0xcfc3ffff,
435 .dma_mask = 0x31c001ff,
436 .ultra_mask = 0x303c0000,
437 .clock_table = {
438 [ATA_CLOCK_25MHZ] = NULL,
439 [ATA_CLOCK_33MHZ] = thirty_three_base_hpt37x,
440 [ATA_CLOCK_40MHZ] = NULL,
441 [ATA_CLOCK_50MHZ] = fifty_base_hpt37x,
442 [ATA_CLOCK_66MHZ] = sixty_six_base_hpt37x
443 }
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100444};
445
Greg Kroah-Hartmanfe31edc2012-12-21 13:21:03 -0800446static const struct hpt_info hpt36x = {
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200447 .chip_name = "HPT36x",
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100448 .chip_type = HPT36x,
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200449 .udma_mask = HPT366_ALLOW_ATA66_3 ? (HPT366_ALLOW_ATA66_4 ? ATA_UDMA4 : ATA_UDMA3) : ATA_UDMA2,
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100450 .dpll_clk = 0, /* no DPLL */
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100451 .timings = &hpt36x_timings
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100452};
453
Greg Kroah-Hartmanfe31edc2012-12-21 13:21:03 -0800454static const struct hpt_info hpt370 = {
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200455 .chip_name = "HPT370",
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100456 .chip_type = HPT370,
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200457 .udma_mask = HPT370_ALLOW_ATA100_5 ? ATA_UDMA5 : ATA_UDMA4,
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100458 .dpll_clk = 48,
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100459 .timings = &hpt37x_timings
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100460};
461
Greg Kroah-Hartmanfe31edc2012-12-21 13:21:03 -0800462static const struct hpt_info hpt370a = {
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200463 .chip_name = "HPT370A",
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100464 .chip_type = HPT370A,
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200465 .udma_mask = HPT370_ALLOW_ATA100_5 ? ATA_UDMA5 : ATA_UDMA4,
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100466 .dpll_clk = 48,
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100467 .timings = &hpt37x_timings
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100468};
469
Greg Kroah-Hartmanfe31edc2012-12-21 13:21:03 -0800470static const struct hpt_info hpt374 = {
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200471 .chip_name = "HPT374",
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100472 .chip_type = HPT374,
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200473 .udma_mask = ATA_UDMA5,
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100474 .dpll_clk = 48,
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100475 .timings = &hpt37x_timings
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100476};
477
Greg Kroah-Hartmanfe31edc2012-12-21 13:21:03 -0800478static const struct hpt_info hpt372 = {
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200479 .chip_name = "HPT372",
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100480 .chip_type = HPT372,
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200481 .udma_mask = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100482 .dpll_clk = 55,
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100483 .timings = &hpt37x_timings
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100484};
485
Greg Kroah-Hartmanfe31edc2012-12-21 13:21:03 -0800486static const struct hpt_info hpt372a = {
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200487 .chip_name = "HPT372A",
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100488 .chip_type = HPT372A,
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200489 .udma_mask = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100490 .dpll_clk = 66,
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100491 .timings = &hpt37x_timings
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100492};
493
Greg Kroah-Hartmanfe31edc2012-12-21 13:21:03 -0800494static const struct hpt_info hpt302 = {
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200495 .chip_name = "HPT302",
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100496 .chip_type = HPT302,
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200497 .udma_mask = HPT302_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100498 .dpll_clk = 66,
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100499 .timings = &hpt37x_timings
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100500};
501
Greg Kroah-Hartmanfe31edc2012-12-21 13:21:03 -0800502static const struct hpt_info hpt371 = {
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200503 .chip_name = "HPT371",
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100504 .chip_type = HPT371,
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200505 .udma_mask = HPT371_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100506 .dpll_clk = 66,
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100507 .timings = &hpt37x_timings
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100508};
509
Greg Kroah-Hartmanfe31edc2012-12-21 13:21:03 -0800510static const struct hpt_info hpt372n = {
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200511 .chip_name = "HPT372N",
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100512 .chip_type = HPT372N,
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200513 .udma_mask = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100514 .dpll_clk = 77,
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100515 .timings = &hpt37x_timings
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100516};
517
Greg Kroah-Hartmanfe31edc2012-12-21 13:21:03 -0800518static const struct hpt_info hpt302n = {
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200519 .chip_name = "HPT302N",
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100520 .chip_type = HPT302N,
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200521 .udma_mask = HPT302_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100522 .dpll_clk = 77,
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100523 .timings = &hpt37x_timings
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100524};
525
Greg Kroah-Hartmanfe31edc2012-12-21 13:21:03 -0800526static const struct hpt_info hpt371n = {
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200527 .chip_name = "HPT371N",
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100528 .chip_type = HPT371N,
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200529 .udma_mask = HPT371_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100530 .dpll_clk = 77,
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100531 .timings = &hpt37x_timings
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100532};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700533
Sergei Shtylyove139b0b2007-02-07 18:17:37 +0100534static int check_in_drive_list(ide_drive_t *drive, const char **list)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700535{
Bartlomiej Zolnierkiewicz4dde4492008-10-10 22:39:19 +0200536 char *m = (char *)&drive->id[ATA_ID_PROD];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700537
Sergei Shtylyove139b0b2007-02-07 18:17:37 +0100538 while (*list)
Bartlomiej Zolnierkiewicz4dde4492008-10-10 22:39:19 +0200539 if (!strcmp(*list++, m))
Sergei Shtylyove139b0b2007-02-07 18:17:37 +0100540 return 1;
541 return 0;
542}
Alan Coxb39b01f2005-06-27 15:24:27 -0700543
Masoud Sharbiani62ff2ec2008-09-10 22:22:34 +0200544static struct hpt_info *hpt3xx_get_info(struct device *dev)
545{
546 struct ide_host *host = dev_get_drvdata(dev);
547 struct hpt_info *info = (struct hpt_info *)host->host_priv;
548
549 return dev == host->dev[1] ? info + 1 : info;
550}
551
Linus Torvalds1da177e2005-04-16 15:20:36 -0700552/*
Sergei Shtylyov2808b0a2007-09-11 22:28:36 +0200553 * The Marvell bridge chips used on the HighPoint SATA cards do not seem
554 * to support the UltraDMA modes 1, 2, and 3 as well as any MWDMA modes...
Linus Torvalds1da177e2005-04-16 15:20:36 -0700555 */
Bartlomiej Zolnierkiewicz2d5eaa62007-05-10 00:01:08 +0200556
557static u8 hpt3xx_udma_filter(ide_drive_t *drive)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700558{
Bartlomiej Zolnierkiewicz898ec222009-01-06 17:20:52 +0100559 ide_hwif_t *hwif = drive->hwif;
Masoud Sharbiani62ff2ec2008-09-10 22:22:34 +0200560 struct hpt_info *info = hpt3xx_get_info(hwif->dev);
Sergei Shtylyov2808b0a2007-09-11 22:28:36 +0200561 u8 mask = hwif->ultra_mask;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700562
Sergei Shtylyov2648e5d2007-07-09 23:17:55 +0200563 switch (info->chip_type) {
Sergei Shtylyov2648e5d2007-07-09 23:17:55 +0200564 case HPT36x:
565 if (!HPT366_ALLOW_ATA66_4 ||
566 check_in_drive_list(drive, bad_ata66_4))
Sergei Shtylyov2808b0a2007-09-11 22:28:36 +0200567 mask = ATA_UDMA3;
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100568
Sergei Shtylyov2648e5d2007-07-09 23:17:55 +0200569 if (!HPT366_ALLOW_ATA66_3 ||
570 check_in_drive_list(drive, bad_ata66_3))
Sergei Shtylyov2808b0a2007-09-11 22:28:36 +0200571 mask = ATA_UDMA2;
Sergei Shtylyov2648e5d2007-07-09 23:17:55 +0200572 break;
Sergei Shtylyov2808b0a2007-09-11 22:28:36 +0200573 case HPT370:
574 if (!HPT370_ALLOW_ATA100_5 ||
575 check_in_drive_list(drive, bad_ata100_5))
576 mask = ATA_UDMA4;
577 break;
578 case HPT370A:
579 if (!HPT370_ALLOW_ATA100_5 ||
580 check_in_drive_list(drive, bad_ata100_5))
581 return ATA_UDMA4;
582 case HPT372 :
583 case HPT372A:
584 case HPT372N:
585 case HPT374 :
Bartlomiej Zolnierkiewicz367d7e72008-10-10 22:39:30 +0200586 if (ata_id_is_sata(drive->id))
Sergei Shtylyov2808b0a2007-09-11 22:28:36 +0200587 mask &= ~0x0e;
588 /* Fall thru */
Sergei Shtylyov2648e5d2007-07-09 23:17:55 +0200589 default:
Sergei Shtylyov2808b0a2007-09-11 22:28:36 +0200590 return mask;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700591 }
Sergei Shtylyov2648e5d2007-07-09 23:17:55 +0200592
593 return check_in_drive_list(drive, bad_ata33) ? 0x00 : mask;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700594}
595
Sergei Shtylyovb4e44362007-10-11 23:53:58 +0200596static u8 hpt3xx_mdma_filter(ide_drive_t *drive)
597{
Bartlomiej Zolnierkiewicz898ec222009-01-06 17:20:52 +0100598 ide_hwif_t *hwif = drive->hwif;
Masoud Sharbiani62ff2ec2008-09-10 22:22:34 +0200599 struct hpt_info *info = hpt3xx_get_info(hwif->dev);
Sergei Shtylyovb4e44362007-10-11 23:53:58 +0200600
601 switch (info->chip_type) {
602 case HPT372 :
603 case HPT372A:
604 case HPT372N:
605 case HPT374 :
Bartlomiej Zolnierkiewicz367d7e72008-10-10 22:39:30 +0200606 if (ata_id_is_sata(drive->id))
Sergei Shtylyovb4e44362007-10-11 23:53:58 +0200607 return 0x00;
608 /* Fall thru */
609 default:
610 return 0x07;
611 }
612}
613
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100614static u32 get_speed_setting(u8 speed, struct hpt_info *info)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700615{
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800616 int i;
617
618 /*
619 * Lookup the transfer mode table to get the index into
620 * the timing table.
621 *
622 * NOTE: For XFER_PIO_SLOW, PIO mode 0 timings will be used.
623 */
624 for (i = 0; i < ARRAY_SIZE(xfer_speeds) - 1; i++)
625 if (xfer_speeds[i] == speed)
626 break;
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100627
628 return info->timings->clock_table[info->clock][i];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700629}
630
Bartlomiej Zolnierkiewicz87761682010-01-19 01:45:29 -0800631static void hpt3xx_set_mode(ide_hwif_t *hwif, ide_drive_t *drive)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700632{
Bartlomiej Zolnierkiewicz74811f32008-07-24 22:53:15 +0200633 struct pci_dev *dev = to_pci_dev(hwif->dev);
Masoud Sharbiani62ff2ec2008-09-10 22:22:34 +0200634 struct hpt_info *info = hpt3xx_get_info(hwif->dev);
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100635 struct hpt_timings *t = info->timings;
636 u8 itr_addr = 0x40 + (drive->dn * 4);
Sergei Shtylyov26ccb802007-02-07 18:18:11 +0100637 u32 old_itr = 0;
Bartlomiej Zolnierkiewicz87761682010-01-19 01:45:29 -0800638 const u8 speed = drive->dma_mode;
Sergei Shtylyovceb1b2c2008-01-25 22:17:04 +0100639 u32 new_itr = get_speed_setting(speed, info);
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100640 u32 itr_mask = speed < XFER_MW_DMA_0 ? t->pio_mask :
641 (speed < XFER_UDMA_0 ? t->dma_mask :
642 t->ultra_mask);
Bartlomiej Zolnierkiewicz2d5eaa62007-05-10 00:01:08 +0200643
Sergei Shtylyovceb1b2c2008-01-25 22:17:04 +0100644 pci_read_config_dword(dev, itr_addr, &old_itr);
645 new_itr = (old_itr & ~itr_mask) | (new_itr & itr_mask);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700646 /*
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100647 * Disable on-chip PIO FIFO/buffer (and PIO MST mode as well)
648 * to avoid problems handling I/O errors later
Linus Torvalds1da177e2005-04-16 15:20:36 -0700649 */
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100650 new_itr &= ~0xc0000000;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700651
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100652 pci_write_config_dword(dev, itr_addr, new_itr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700653}
654
Bartlomiej Zolnierkiewicze085b3c2010-01-19 01:44:41 -0800655static void hpt3xx_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700656{
Bartlomiej Zolnierkiewicz87761682010-01-19 01:45:29 -0800657 drive->dma_mode = drive->pio_mode;
658 hpt3xx_set_mode(hwif, drive);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700659}
660
Sergei Shtylyov26ccb802007-02-07 18:18:11 +0100661static void hpt3xx_maskproc(ide_drive_t *drive, int mask)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700662{
Bartlomiej Zolnierkiewicz898ec222009-01-06 17:20:52 +0100663 ide_hwif_t *hwif = drive->hwif;
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +0100664 struct pci_dev *dev = to_pci_dev(hwif->dev);
Masoud Sharbiani62ff2ec2008-09-10 22:22:34 +0200665 struct hpt_info *info = hpt3xx_get_info(hwif->dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700666
Bartlomiej Zolnierkiewicz734affd2009-06-07 15:37:10 +0200667 if ((drive->dev_flags & IDE_DFLAG_NIEN_QUIRK) == 0)
Sergei Shtylyovea2ac5a2008-10-17 18:09:15 +0200668 return;
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100669
Sergei Shtylyovea2ac5a2008-10-17 18:09:15 +0200670 if (info->chip_type >= HPT370) {
671 u8 scr1 = 0;
672
673 pci_read_config_byte(dev, 0x5a, &scr1);
674 if (((scr1 & 0x10) >> 4) != mask) {
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100675 if (mask)
Sergei Shtylyovea2ac5a2008-10-17 18:09:15 +0200676 scr1 |= 0x10;
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100677 else
Sergei Shtylyovea2ac5a2008-10-17 18:09:15 +0200678 scr1 &= ~0x10;
679 pci_write_config_byte(dev, 0x5a, scr1);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700680 }
Sergei Shtylyovea2ac5a2008-10-17 18:09:15 +0200681 } else if (mask)
682 disable_irq(hwif->irq);
683 else
684 enable_irq(hwif->irq);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700685}
686
Linus Torvalds1da177e2005-04-16 15:20:36 -0700687/*
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100688 * This is specific to the HPT366 UDMA chipset
Linus Torvalds1da177e2005-04-16 15:20:36 -0700689 * by HighPoint|Triones Technologies, Inc.
690 */
Sergei Shtylyov841d2a92007-07-09 23:17:54 +0200691static void hpt366_dma_lost_irq(ide_drive_t *drive)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700692{
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +0100693 struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100694 u8 mcr1 = 0, mcr3 = 0, scr1 = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700695
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100696 pci_read_config_byte(dev, 0x50, &mcr1);
697 pci_read_config_byte(dev, 0x52, &mcr3);
698 pci_read_config_byte(dev, 0x5a, &scr1);
699 printk("%s: (%s) mcr1=0x%02x, mcr3=0x%02x, scr1=0x%02x\n",
Harvey Harrisoneb639632008-04-26 22:25:20 +0200700 drive->name, __func__, mcr1, mcr3, scr1);
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100701 if (scr1 & 0x10)
702 pci_write_config_byte(dev, 0x5a, scr1 & ~0x10);
Sergei Shtylyov841d2a92007-07-09 23:17:54 +0200703 ide_dma_lost_irq(drive);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700704}
705
Sergei Shtylyov4bf63de2007-02-07 18:18:13 +0100706static void hpt370_clear_engine(ide_drive_t *drive)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700707{
Bartlomiej Zolnierkiewicz898ec222009-01-06 17:20:52 +0100708 ide_hwif_t *hwif = drive->hwif;
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +0100709 struct pci_dev *dev = to_pci_dev(hwif->dev);
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100710
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +0100711 pci_write_config_byte(dev, hwif->select_data, 0x37);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700712 udelay(10);
713}
714
Sergei Shtylyov4bf63de2007-02-07 18:18:13 +0100715static void hpt370_irq_timeout(ide_drive_t *drive)
716{
Bartlomiej Zolnierkiewicz898ec222009-01-06 17:20:52 +0100717 ide_hwif_t *hwif = drive->hwif;
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +0100718 struct pci_dev *dev = to_pci_dev(hwif->dev);
Sergei Shtylyov4bf63de2007-02-07 18:18:13 +0100719 u16 bfifo = 0;
720 u8 dma_cmd;
721
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +0100722 pci_read_config_word(dev, hwif->select_data + 2, &bfifo);
Sergei Shtylyov4bf63de2007-02-07 18:18:13 +0100723 printk(KERN_DEBUG "%s: %d bytes in FIFO\n", drive->name, bfifo & 0x1ff);
724
725 /* get DMA command mode */
Bartlomiej Zolnierkiewiczcab7f8e2008-07-23 19:55:51 +0200726 dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
Sergei Shtylyov4bf63de2007-02-07 18:18:13 +0100727 /* stop DMA */
Sergei Shtylyov59c8d042009-04-18 17:42:19 +0200728 outb(dma_cmd & ~ATA_DMA_START, hwif->dma_base + ATA_DMA_CMD);
Sergei Shtylyov4bf63de2007-02-07 18:18:13 +0100729 hpt370_clear_engine(drive);
730}
731
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +0200732static void hpt370_dma_start(ide_drive_t *drive)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700733{
734#ifdef HPT_RESET_STATE_ENGINE
735 hpt370_clear_engine(drive);
736#endif
737 ide_dma_start(drive);
738}
739
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +0200740static int hpt370_dma_end(ide_drive_t *drive)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700741{
Bartlomiej Zolnierkiewicz898ec222009-01-06 17:20:52 +0100742 ide_hwif_t *hwif = drive->hwif;
Bartlomiej Zolnierkiewiczcab7f8e2008-07-23 19:55:51 +0200743 u8 dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700744
Sergei Shtylyov59c8d042009-04-18 17:42:19 +0200745 if (dma_stat & ATA_DMA_ACTIVE) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700746 /* wait a little */
747 udelay(20);
Bartlomiej Zolnierkiewiczcab7f8e2008-07-23 19:55:51 +0200748 dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS);
Sergei Shtylyov59c8d042009-04-18 17:42:19 +0200749 if (dma_stat & ATA_DMA_ACTIVE)
Sergei Shtylyov4bf63de2007-02-07 18:18:13 +0100750 hpt370_irq_timeout(drive);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700751 }
Bartlomiej Zolnierkiewicz653bcf52008-10-13 21:39:46 +0200752 return ide_dma_end(drive);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700753}
754
Linus Torvalds1da177e2005-04-16 15:20:36 -0700755/* returns 1 if DMA IRQ issued, 0 otherwise */
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +0200756static int hpt374_dma_test_irq(ide_drive_t *drive)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700757{
Bartlomiej Zolnierkiewicz898ec222009-01-06 17:20:52 +0100758 ide_hwif_t *hwif = drive->hwif;
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +0100759 struct pci_dev *dev = to_pci_dev(hwif->dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700760 u16 bfifo = 0;
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100761 u8 dma_stat;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700762
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +0100763 pci_read_config_word(dev, hwif->select_data + 2, &bfifo);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700764 if (bfifo & 0x1FF) {
765// printk("%s: %d bytes in FIFO\n", drive->name, bfifo);
766 return 0;
767 }
768
Bartlomiej Zolnierkiewiczcab7f8e2008-07-23 19:55:51 +0200769 dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700770 /* return 1 if INTR asserted */
Sergei Shtylyov59c8d042009-04-18 17:42:19 +0200771 if (dma_stat & ATA_DMA_INTR)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700772 return 1;
773
Linus Torvalds1da177e2005-04-16 15:20:36 -0700774 return 0;
775}
776
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +0200777static int hpt374_dma_end(ide_drive_t *drive)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700778{
Bartlomiej Zolnierkiewicz898ec222009-01-06 17:20:52 +0100779 ide_hwif_t *hwif = drive->hwif;
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +0100780 struct pci_dev *dev = to_pci_dev(hwif->dev);
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100781 u8 mcr = 0, mcr_addr = hwif->select_data;
782 u8 bwsr = 0, mask = hwif->channel ? 0x02 : 0x01;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700783
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100784 pci_read_config_byte(dev, 0x6a, &bwsr);
785 pci_read_config_byte(dev, mcr_addr, &mcr);
786 if (bwsr & mask)
787 pci_write_config_byte(dev, mcr_addr, mcr | 0x30);
Bartlomiej Zolnierkiewicz653bcf52008-10-13 21:39:46 +0200788 return ide_dma_end(drive);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700789}
790
791/**
Sergei Shtylyov836c0062006-12-13 00:35:47 -0800792 * hpt3xxn_set_clock - perform clock switching dance
793 * @hwif: hwif to switch
794 * @mode: clocking mode (0x21 for write, 0x23 otherwise)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700795 *
Sergei Shtylyov836c0062006-12-13 00:35:47 -0800796 * Switch the DPLL clock on the HPT3xxN devices. This is a right mess.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700797 */
Sergei Shtylyov836c0062006-12-13 00:35:47 -0800798
799static void hpt3xxn_set_clock(ide_hwif_t *hwif, u8 mode)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700800{
Bartlomiej Zolnierkiewicz1c029fd2008-01-25 22:17:05 +0100801 unsigned long base = hwif->extra_base;
802 u8 scr2 = inb(base + 0x6b);
Sergei Shtylyov836c0062006-12-13 00:35:47 -0800803
804 if ((scr2 & 0x7f) == mode)
805 return;
806
Linus Torvalds1da177e2005-04-16 15:20:36 -0700807 /* Tristate the bus */
Bartlomiej Zolnierkiewicz1c029fd2008-01-25 22:17:05 +0100808 outb(0x80, base + 0x63);
809 outb(0x80, base + 0x67);
Sergei Shtylyov836c0062006-12-13 00:35:47 -0800810
Linus Torvalds1da177e2005-04-16 15:20:36 -0700811 /* Switch clock and reset channels */
Bartlomiej Zolnierkiewicz1c029fd2008-01-25 22:17:05 +0100812 outb(mode, base + 0x6b);
813 outb(0xc0, base + 0x69);
Sergei Shtylyov836c0062006-12-13 00:35:47 -0800814
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100815 /*
816 * Reset the state machines.
817 * NOTE: avoid accidentally enabling the disabled channels.
818 */
Bartlomiej Zolnierkiewicz1c029fd2008-01-25 22:17:05 +0100819 outb(inb(base + 0x60) | 0x32, base + 0x60);
820 outb(inb(base + 0x64) | 0x32, base + 0x64);
Sergei Shtylyov836c0062006-12-13 00:35:47 -0800821
Linus Torvalds1da177e2005-04-16 15:20:36 -0700822 /* Complete reset */
Bartlomiej Zolnierkiewicz1c029fd2008-01-25 22:17:05 +0100823 outb(0x00, base + 0x69);
Sergei Shtylyov836c0062006-12-13 00:35:47 -0800824
Linus Torvalds1da177e2005-04-16 15:20:36 -0700825 /* Reconnect channels to bus */
Bartlomiej Zolnierkiewicz1c029fd2008-01-25 22:17:05 +0100826 outb(0x00, base + 0x63);
827 outb(0x00, base + 0x67);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700828}
829
830/**
Sergei Shtylyov836c0062006-12-13 00:35:47 -0800831 * hpt3xxn_rw_disk - prepare for I/O
Linus Torvalds1da177e2005-04-16 15:20:36 -0700832 * @drive: drive for command
833 * @rq: block request structure
834 *
Sergei Shtylyov836c0062006-12-13 00:35:47 -0800835 * This is called when a disk I/O is issued to HPT3xxN.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700836 * We need it because of the clock switching.
837 */
838
Sergei Shtylyov836c0062006-12-13 00:35:47 -0800839static void hpt3xxn_rw_disk(ide_drive_t *drive, struct request *rq)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700840{
Sergei Shtylyovbbe54d72010-09-27 11:01:32 -0700841 hpt3xxn_set_clock(drive->hwif, rq_data_dir(rq) ? 0x21 : 0x23);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700842}
843
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100844/**
845 * hpt37x_calibrate_dpll - calibrate the DPLL
846 * @dev: PCI device
847 *
848 * Perform a calibration cycle on the DPLL.
849 * Returns 1 if this succeeds
850 */
Bartlomiej Zolnierkiewiczfeb22b72008-10-10 22:39:32 +0200851static int hpt37x_calibrate_dpll(struct pci_dev *dev, u16 f_low, u16 f_high)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700852{
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100853 u32 dpll = (f_high << 16) | f_low | 0x100;
854 u8 scr2;
855 int i;
Alan Coxb39b01f2005-06-27 15:24:27 -0700856
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100857 pci_write_config_dword(dev, 0x5c, dpll);
Alan Coxb39b01f2005-06-27 15:24:27 -0700858
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100859 /* Wait for oscillator ready */
860 for(i = 0; i < 0x5000; ++i) {
861 udelay(50);
862 pci_read_config_byte(dev, 0x5b, &scr2);
863 if (scr2 & 0x80)
Alan Coxb39b01f2005-06-27 15:24:27 -0700864 break;
865 }
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100866 /* See if it stays ready (we'll just bail out if it's not yet) */
867 for(i = 0; i < 0x1000; ++i) {
868 pci_read_config_byte(dev, 0x5b, &scr2);
869 /* DPLL destabilized? */
870 if(!(scr2 & 0x80))
871 return 0;
Sergei Shtylyov90778572007-02-07 18:17:51 +0100872 }
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100873 /* Turn off tuning, we have the DPLL set */
874 pci_read_config_dword (dev, 0x5c, &dpll);
875 pci_write_config_dword(dev, 0x5c, (dpll & ~0x100));
876 return 1;
Alan Coxb39b01f2005-06-27 15:24:27 -0700877}
878
Bartlomiej Zolnierkiewiczfeb22b72008-10-10 22:39:32 +0200879static void hpt3xx_disable_fast_irq(struct pci_dev *dev, u8 mcr_addr)
Bartlomiej Zolnierkiewicz17851922008-10-10 22:39:32 +0200880{
881 struct ide_host *host = pci_get_drvdata(dev);
882 struct hpt_info *info = host->host_priv + (&dev->dev == host->dev[1]);
883 u8 chip_type = info->chip_type;
884 u8 new_mcr, old_mcr = 0;
885
886 /*
887 * Disable the "fast interrupt" prediction. Don't hold off
888 * on interrupts. (== 0x01 despite what the docs say)
889 */
890 pci_read_config_byte(dev, mcr_addr + 1, &old_mcr);
891
892 if (chip_type >= HPT374)
893 new_mcr = old_mcr & ~0x07;
894 else if (chip_type >= HPT370) {
895 new_mcr = old_mcr;
896 new_mcr &= ~0x02;
897#ifdef HPT_DELAY_INTERRUPT
898 new_mcr &= ~0x01;
899#else
900 new_mcr |= 0x01;
901#endif
902 } else /* HPT366 and HPT368 */
903 new_mcr = old_mcr & ~0x80;
904
905 if (new_mcr != old_mcr)
906 pci_write_config_byte(dev, mcr_addr + 1, new_mcr);
907}
908
Bartlomiej Zolnierkiewicz2ed0ef52009-03-24 23:22:53 +0100909static int init_chipset_hpt366(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700910{
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100911 unsigned long io_base = pci_resource_start(dev, 4);
Masoud Sharbiani62ff2ec2008-09-10 22:22:34 +0200912 struct hpt_info *info = hpt3xx_get_info(&dev->dev);
Bartlomiej Zolnierkiewicza326b022008-07-24 22:53:33 +0200913 const char *name = DRV_NAME;
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100914 u8 pci_clk, dpll_clk = 0; /* PCI and DPLL clock in MHz */
Sergei Shtylyov72931362007-09-11 22:28:35 +0200915 u8 chip_type;
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100916 enum ata_clock clock;
917
Sergei Shtylyov72931362007-09-11 22:28:35 +0200918 chip_type = info->chip_type;
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100919
Alan Coxb39b01f2005-06-27 15:24:27 -0700920 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
921 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
922 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
923 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700924
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100925 /*
926 * First, try to estimate the PCI clock frequency...
927 */
Sergei Shtylyov72931362007-09-11 22:28:35 +0200928 if (chip_type >= HPT370) {
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100929 u8 scr1 = 0;
930 u16 f_cnt = 0;
931 u32 temp = 0;
Alan Coxb39b01f2005-06-27 15:24:27 -0700932
Sergei Shtylyov26ccb802007-02-07 18:18:11 +0100933 /* Interrupt force enable. */
934 pci_read_config_byte(dev, 0x5a, &scr1);
935 if (scr1 & 0x10)
936 pci_write_config_byte(dev, 0x5a, scr1 & ~0x10);
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100937
938 /*
939 * HighPoint does this for HPT372A.
940 * NOTE: This register is only writeable via I/O space.
941 */
Sergei Shtylyov72931362007-09-11 22:28:35 +0200942 if (chip_type == HPT372A)
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100943 outb(0x0e, io_base + 0x9c);
944
945 /*
946 * Default to PCI clock. Make sure MA15/16 are set to output
947 * to prevent drives having problems with 40-pin cables.
948 */
949 pci_write_config_byte(dev, 0x5b, 0x23);
950
951 /*
952 * We'll have to read f_CNT value in order to determine
953 * the PCI clock frequency according to the following ratio:
954 *
955 * f_CNT = Fpci * 192 / Fdpll
956 *
957 * First try reading the register in which the HighPoint BIOS
958 * saves f_CNT value before reprogramming the DPLL from its
959 * default setting (which differs for the various chips).
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100960 *
Sergei Shtylyov72931362007-09-11 22:28:35 +0200961 * NOTE: This register is only accessible via I/O space;
962 * HPT374 BIOS only saves it for the function 0, so we have to
963 * always read it from there -- no need to check the result of
964 * pci_get_slot() for the function 0 as the whole device has
965 * been already "pinned" (via function 1) in init_setup_hpt374()
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100966 */
Sergei Shtylyov72931362007-09-11 22:28:35 +0200967 if (chip_type == HPT374 && (PCI_FUNC(dev->devfn) & 1)) {
968 struct pci_dev *dev1 = pci_get_slot(dev->bus,
969 dev->devfn - 1);
970 unsigned long io_base = pci_resource_start(dev1, 4);
971
972 temp = inl(io_base + 0x90);
973 pci_dev_put(dev1);
974 } else
975 temp = inl(io_base + 0x90);
976
977 /*
978 * In case the signature check fails, we'll have to
979 * resort to reading the f_CNT register itself in hopes
980 * that nobody has touched the DPLL yet...
981 */
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100982 if ((temp & 0xFFFFF000) != 0xABCDE000) {
983 int i;
984
Bartlomiej Zolnierkiewicz28cfd8a2008-07-24 22:53:31 +0200985 printk(KERN_WARNING "%s %s: no clock data saved by "
986 "BIOS\n", name, pci_name(dev));
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100987
988 /* Calculate the average value of f_CNT. */
989 for (temp = i = 0; i < 128; i++) {
990 pci_read_config_word(dev, 0x78, &f_cnt);
991 temp += f_cnt & 0x1ff;
992 mdelay(1);
993 }
994 f_cnt = temp / 128;
995 } else
996 f_cnt = temp & 0x1ff;
997
998 dpll_clk = info->dpll_clk;
999 pci_clk = (f_cnt * dpll_clk) / 192;
1000
1001 /* Clamp PCI clock to bands. */
1002 if (pci_clk < 40)
1003 pci_clk = 33;
1004 else if(pci_clk < 45)
1005 pci_clk = 40;
1006 else if(pci_clk < 55)
1007 pci_clk = 50;
1008 else
1009 pci_clk = 66;
1010
Bartlomiej Zolnierkiewicz28cfd8a2008-07-24 22:53:31 +02001011 printk(KERN_INFO "%s %s: DPLL base: %d MHz, f_CNT: %d, "
1012 "assuming %d MHz PCI\n", name, pci_name(dev),
1013 dpll_clk, f_cnt, pci_clk);
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001014 } else {
1015 u32 itr1 = 0;
1016
1017 pci_read_config_dword(dev, 0x40, &itr1);
1018
1019 /* Detect PCI clock by looking at cmd_high_time. */
1020 switch((itr1 >> 8) & 0x07) {
1021 case 0x09:
1022 pci_clk = 40;
Sergei Shtylyov6273d262007-02-07 18:18:20 +01001023 break;
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001024 case 0x05:
1025 pci_clk = 25;
Sergei Shtylyov6273d262007-02-07 18:18:20 +01001026 break;
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001027 case 0x07:
1028 default:
1029 pci_clk = 33;
Sergei Shtylyov6273d262007-02-07 18:18:20 +01001030 break;
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001031 }
Sergei Shtylyov26ccb802007-02-07 18:18:11 +01001032 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001033
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001034 /* Let's assume we'll use PCI clock for the ATA clock... */
1035 switch (pci_clk) {
1036 case 25:
1037 clock = ATA_CLOCK_25MHZ;
1038 break;
1039 case 33:
1040 default:
1041 clock = ATA_CLOCK_33MHZ;
1042 break;
1043 case 40:
1044 clock = ATA_CLOCK_40MHZ;
1045 break;
1046 case 50:
1047 clock = ATA_CLOCK_50MHZ;
1048 break;
1049 case 66:
1050 clock = ATA_CLOCK_66MHZ;
1051 break;
1052 }
1053
1054 /*
1055 * Only try the DPLL if we don't have a table for the PCI clock that
1056 * we are running at for HPT370/A, always use it for anything newer...
1057 *
1058 * NOTE: Using the internal DPLL results in slow reads on 33 MHz PCI.
1059 * We also don't like using the DPLL because this causes glitches
1060 * on PRST-/SRST- when the state engine gets reset...
1061 */
Sergei Shtylyov866664d2008-01-25 22:17:05 +01001062 if (chip_type >= HPT374 || info->timings->clock_table[clock] == NULL) {
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001063 u16 f_low, delta = pci_clk < 50 ? 2 : 4;
1064 int adjust;
1065
1066 /*
1067 * Select 66 MHz DPLL clock only if UltraATA/133 mode is
1068 * supported/enabled, use 50 MHz DPLL clock otherwise...
1069 */
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001070 if (info->udma_mask == ATA_UDMA6) {
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001071 dpll_clk = 66;
1072 clock = ATA_CLOCK_66MHZ;
1073 } else if (dpll_clk) { /* HPT36x chips don't have DPLL */
1074 dpll_clk = 50;
1075 clock = ATA_CLOCK_50MHZ;
1076 }
1077
Sergei Shtylyov866664d2008-01-25 22:17:05 +01001078 if (info->timings->clock_table[clock] == NULL) {
Bartlomiej Zolnierkiewicz28cfd8a2008-07-24 22:53:31 +02001079 printk(KERN_ERR "%s %s: unknown bus timing!\n",
1080 name, pci_name(dev));
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001081 return -EIO;
1082 }
1083
1084 /* Select the DPLL clock. */
1085 pci_write_config_byte(dev, 0x5b, 0x21);
1086
1087 /*
1088 * Adjust the DPLL based upon PCI clock, enable it,
1089 * and wait for stabilization...
1090 */
1091 f_low = (pci_clk * 48) / dpll_clk;
1092
1093 for (adjust = 0; adjust < 8; adjust++) {
1094 if(hpt37x_calibrate_dpll(dev, f_low, f_low + delta))
1095 break;
1096
1097 /*
1098 * See if it'll settle at a fractionally different clock
1099 */
1100 if (adjust & 1)
1101 f_low -= adjust >> 1;
1102 else
1103 f_low += adjust >> 1;
1104 }
1105 if (adjust == 8) {
Bartlomiej Zolnierkiewicz28cfd8a2008-07-24 22:53:31 +02001106 printk(KERN_ERR "%s %s: DPLL did not stabilize!\n",
1107 name, pci_name(dev));
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001108 return -EIO;
1109 }
1110
Bartlomiej Zolnierkiewicz28cfd8a2008-07-24 22:53:31 +02001111 printk(KERN_INFO "%s %s: using %d MHz DPLL clock\n",
1112 name, pci_name(dev), dpll_clk);
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001113 } else {
1114 /* Mark the fact that we're not using the DPLL. */
1115 dpll_clk = 0;
1116
Bartlomiej Zolnierkiewicz28cfd8a2008-07-24 22:53:31 +02001117 printk(KERN_INFO "%s %s: using %d MHz PCI clock\n",
1118 name, pci_name(dev), pci_clk);
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001119 }
1120
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001121 /* Store the clock frequencies. */
1122 info->dpll_clk = dpll_clk;
1123 info->pci_clk = pci_clk;
Sergei Shtylyov866664d2008-01-25 22:17:05 +01001124 info->clock = clock;
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001125
Sergei Shtylyov72931362007-09-11 22:28:35 +02001126 if (chip_type >= HPT370) {
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001127 u8 mcr1, mcr4;
1128
1129 /*
1130 * Reset the state engines.
1131 * NOTE: Avoid accidentally enabling the disabled channels.
1132 */
1133 pci_read_config_byte (dev, 0x50, &mcr1);
1134 pci_read_config_byte (dev, 0x54, &mcr4);
1135 pci_write_config_byte(dev, 0x50, (mcr1 | 0x32));
1136 pci_write_config_byte(dev, 0x54, (mcr4 | 0x32));
1137 udelay(100);
1138 }
1139
1140 /*
1141 * On HPT371N, if ATA clock is 66 MHz we must set bit 2 in
1142 * the MISC. register to stretch the UltraDMA Tss timing.
1143 * NOTE: This register is only writeable via I/O space.
1144 */
Sergei Shtylyov72931362007-09-11 22:28:35 +02001145 if (chip_type == HPT371N && clock == ATA_CLOCK_66MHZ)
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001146 outb(inb(io_base + 0x9c) | 0x04, io_base + 0x9c);
1147
Bartlomiej Zolnierkiewicz17851922008-10-10 22:39:32 +02001148 hpt3xx_disable_fast_irq(dev, 0x50);
1149 hpt3xx_disable_fast_irq(dev, 0x54);
1150
Bartlomiej Zolnierkiewicz2ed0ef52009-03-24 23:22:53 +01001151 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001152}
1153
Bartlomiej Zolnierkiewiczf454cbe2008-08-05 18:17:04 +02001154static u8 hpt3xx_cable_detect(ide_hwif_t *hwif)
Bartlomiej Zolnierkiewiczbfa14b42008-02-02 19:56:31 +01001155{
1156 struct pci_dev *dev = to_pci_dev(hwif->dev);
Masoud Sharbiani62ff2ec2008-09-10 22:22:34 +02001157 struct hpt_info *info = hpt3xx_get_info(hwif->dev);
Bartlomiej Zolnierkiewiczbfa14b42008-02-02 19:56:31 +01001158 u8 chip_type = info->chip_type;
1159 u8 scr1 = 0, ata66 = hwif->channel ? 0x01 : 0x02;
1160
1161 /*
1162 * The HPT37x uses the CBLID pins as outputs for MA15/MA16
1163 * address lines to access an external EEPROM. To read valid
1164 * cable detect state the pins must be enabled as inputs.
1165 */
1166 if (chip_type == HPT374 && (PCI_FUNC(dev->devfn) & 1)) {
1167 /*
1168 * HPT374 PCI function 1
1169 * - set bit 15 of reg 0x52 to enable TCBLID as input
1170 * - set bit 15 of reg 0x56 to enable FCBLID as input
1171 */
1172 u8 mcr_addr = hwif->select_data + 2;
1173 u16 mcr;
1174
1175 pci_read_config_word(dev, mcr_addr, &mcr);
Sergei Shtylyov5d3f1a42010-09-27 11:00:40 -07001176 pci_write_config_word(dev, mcr_addr, mcr | 0x8000);
1177 /* Debounce, then read cable ID register */
1178 udelay(10);
Bartlomiej Zolnierkiewiczbfa14b42008-02-02 19:56:31 +01001179 pci_read_config_byte(dev, 0x5a, &scr1);
1180 pci_write_config_word(dev, mcr_addr, mcr);
1181 } else if (chip_type >= HPT370) {
1182 /*
1183 * HPT370/372 and 374 pcifn 0
1184 * - clear bit 0 of reg 0x5b to enable P/SCBLID as inputs
1185 */
1186 u8 scr2 = 0;
1187
1188 pci_read_config_byte(dev, 0x5b, &scr2);
Sergei Shtylyov5d3f1a42010-09-27 11:00:40 -07001189 pci_write_config_byte(dev, 0x5b, scr2 & ~1);
1190 /* Debounce, then read cable ID register */
1191 udelay(10);
Bartlomiej Zolnierkiewiczbfa14b42008-02-02 19:56:31 +01001192 pci_read_config_byte(dev, 0x5a, &scr1);
Sergei Shtylyov5d3f1a42010-09-27 11:00:40 -07001193 pci_write_config_byte(dev, 0x5b, scr2);
Bartlomiej Zolnierkiewiczbfa14b42008-02-02 19:56:31 +01001194 } else
1195 pci_read_config_byte(dev, 0x5a, &scr1);
1196
1197 return (scr1 & ata66) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
1198}
1199
Greg Kroah-Hartmanfe31edc2012-12-21 13:21:03 -08001200static void init_hwif_hpt366(ide_hwif_t *hwif)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001201{
Masoud Sharbiani62ff2ec2008-09-10 22:22:34 +02001202 struct hpt_info *info = hpt3xx_get_info(hwif->dev);
Sergei Shtylyov2808b0a2007-09-11 22:28:36 +02001203 u8 chip_type = info->chip_type;
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +01001204
1205 /* Cache the channel's MISC. control registers' offset */
Sergei Shtylyov2808b0a2007-09-11 22:28:36 +02001206 hwif->select_data = hwif->channel ? 0x54 : 0x50;
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +01001207
Sergei Shtylyov836c0062006-12-13 00:35:47 -08001208 /*
1209 * HPT3xxN chips have some complications:
1210 *
1211 * - on 33 MHz PCI we must clock switch
1212 * - on 66 MHz PCI we must NOT use the PCI clock
1213 */
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001214 if (chip_type >= HPT372N && info->dpll_clk && info->pci_clk < 66) {
Sergei Shtylyov836c0062006-12-13 00:35:47 -08001215 /*
1216 * Clock is shared between the channels,
1217 * so we'll have to serialize them... :-(
1218 */
Bartlomiej Zolnierkiewicz702c0262008-12-29 20:27:36 +01001219 hwif->host->host_flags |= IDE_HFLAG_SERIALIZE;
Sergei Shtylyov836c0062006-12-13 00:35:47 -08001220 hwif->rw_disk = &hpt3xxn_rw_disk;
1221 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001222}
1223
Greg Kroah-Hartmanfe31edc2012-12-21 13:21:03 -08001224static int init_dma_hpt366(ide_hwif_t *hwif,
Bartlomiej Zolnierkiewiczb123f562008-04-26 22:25:22 +02001225 const struct ide_port_info *d)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001226{
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +01001227 struct pci_dev *dev = to_pci_dev(hwif->dev);
Bartlomiej Zolnierkiewiczb123f562008-04-26 22:25:22 +02001228 unsigned long flags, base = ide_pci_dma_base(hwif, d);
1229 u8 dma_old, dma_new, masterdma = 0, slavedma = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001230
Bartlomiej Zolnierkiewiczebb00fb2008-07-23 19:55:51 +02001231 if (base == 0)
1232 return -1;
1233
1234 hwif->dma_base = base;
1235
1236 if (ide_pci_check_simplex(hwif, d) < 0)
1237 return -1;
1238
1239 if (ide_pci_set_master(dev, d->name) < 0)
Bartlomiej Zolnierkiewiczb123f562008-04-26 22:25:22 +02001240 return -1;
1241
1242 dma_old = inb(base + 2);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001243
1244 local_irq_save(flags);
1245
1246 dma_new = dma_old;
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +01001247 pci_read_config_byte(dev, hwif->channel ? 0x4b : 0x43, &masterdma);
1248 pci_read_config_byte(dev, hwif->channel ? 0x4f : 0x47, &slavedma);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001249
1250 if (masterdma & 0x30) dma_new |= 0x20;
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +01001251 if ( slavedma & 0x30) dma_new |= 0x40;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001252 if (dma_new != dma_old)
Bartlomiej Zolnierkiewiczb123f562008-04-26 22:25:22 +02001253 outb(dma_new, base + 2);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001254
1255 local_irq_restore(flags);
Bartlomiej Zolnierkiewiczb123f562008-04-26 22:25:22 +02001256
1257 printk(KERN_INFO " %s: BM-DMA at 0x%04lx-0x%04lx\n",
1258 hwif->name, base, base + 7);
1259
1260 hwif->extra_base = base + (hwif->channel ? 8 : 16);
1261
1262 if (ide_allocate_dma_engine(hwif))
1263 return -1;
1264
Bartlomiej Zolnierkiewiczb123f562008-04-26 22:25:22 +02001265 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001266}
1267
Greg Kroah-Hartmanfe31edc2012-12-21 13:21:03 -08001268static void hpt374_init(struct pci_dev *dev, struct pci_dev *dev2)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001269{
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001270 if (dev2->irq != dev->irq) {
1271 /* FIXME: we need a core pci_set_interrupt() */
1272 dev2->irq = dev->irq;
Bartlomiej Zolnierkiewiczced3ec82008-07-24 22:53:32 +02001273 printk(KERN_INFO DRV_NAME " %s: PCI config space interrupt "
Bartlomiej Zolnierkiewicz28cfd8a2008-07-24 22:53:31 +02001274 "fixed\n", pci_name(dev2));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001275 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001276}
1277
Greg Kroah-Hartmanfe31edc2012-12-21 13:21:03 -08001278static void hpt371_init(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001279{
Auke Kok44c10132007-06-08 15:46:36 -07001280 u8 mcr1 = 0;
Sergei Shtylyov90778572007-02-07 18:17:51 +01001281
Sergei Shtylyov836c0062006-12-13 00:35:47 -08001282 /*
1283 * HPT371 chips physically have only one channel, the secondary one,
1284 * but the primary channel registers do exist! Go figure...
1285 * So, we manually disable the non-existing channel here
1286 * (if the BIOS hasn't done this already).
1287 */
1288 pci_read_config_byte(dev, 0x50, &mcr1);
1289 if (mcr1 & 0x04)
Sergei Shtylyov90778572007-02-07 18:17:51 +01001290 pci_write_config_byte(dev, 0x50, mcr1 & ~0x04);
Sergei Shtylyov90778572007-02-07 18:17:51 +01001291}
1292
Greg Kroah-Hartmanfe31edc2012-12-21 13:21:03 -08001293static int hpt36x_init(struct pci_dev *dev, struct pci_dev *dev2)
Sergei Shtylyov90778572007-02-07 18:17:51 +01001294{
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001295 u8 mcr1 = 0, pin1 = 0, pin2 = 0;
Sergei Shtylyov90778572007-02-07 18:17:51 +01001296
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001297 /*
1298 * Now we'll have to force both channels enabled if
1299 * at least one of them has been enabled by BIOS...
1300 */
1301 pci_read_config_byte(dev, 0x50, &mcr1);
1302 if (mcr1 & 0x30)
1303 pci_write_config_byte(dev, 0x50, mcr1 | 0x30);
Sergei Shtylyov90778572007-02-07 18:17:51 +01001304
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001305 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin1);
1306 pci_read_config_byte(dev2, PCI_INTERRUPT_PIN, &pin2);
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001307
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001308 if (pin1 != pin2 && dev->irq == dev2->irq) {
Bartlomiej Zolnierkiewiczced3ec82008-07-24 22:53:32 +02001309 printk(KERN_INFO DRV_NAME " %s: onboard version of chipset, "
Bartlomiej Zolnierkiewicz28cfd8a2008-07-24 22:53:31 +02001310 "pin1=%d pin2=%d\n", pci_name(dev), pin1, pin2);
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001311 return 1;
1312 }
1313
1314 return 0;
Sergei Shtylyov90778572007-02-07 18:17:51 +01001315}
1316
Bartlomiej Zolnierkiewicz4db90a12008-01-25 22:17:18 +01001317#define IDE_HFLAGS_HPT3XX \
1318 (IDE_HFLAG_NO_ATAPI_DMA | \
Bartlomiej Zolnierkiewicz4db90a12008-01-25 22:17:18 +01001319 IDE_HFLAG_OFF_BOARD)
1320
Bartlomiej Zolnierkiewiczac95bee2008-04-26 22:25:14 +02001321static const struct ide_port_ops hpt3xx_port_ops = {
1322 .set_pio_mode = hpt3xx_set_pio_mode,
1323 .set_dma_mode = hpt3xx_set_mode,
Bartlomiej Zolnierkiewiczac95bee2008-04-26 22:25:14 +02001324 .maskproc = hpt3xx_maskproc,
1325 .mdma_filter = hpt3xx_mdma_filter,
1326 .udma_filter = hpt3xx_udma_filter,
1327 .cable_detect = hpt3xx_cable_detect,
1328};
1329
Bartlomiej Zolnierkiewiczf37afda2008-04-26 22:25:24 +02001330static const struct ide_dma_ops hpt37x_dma_ops = {
1331 .dma_host_set = ide_dma_host_set,
1332 .dma_setup = ide_dma_setup,
Bartlomiej Zolnierkiewiczf37afda2008-04-26 22:25:24 +02001333 .dma_start = ide_dma_start,
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +02001334 .dma_end = hpt374_dma_end,
1335 .dma_test_irq = hpt374_dma_test_irq,
Bartlomiej Zolnierkiewiczf37afda2008-04-26 22:25:24 +02001336 .dma_lost_irq = ide_dma_lost_irq,
Bartlomiej Zolnierkiewicz22117d62009-03-27 12:46:47 +01001337 .dma_timer_expiry = ide_dma_sff_timer_expiry,
Sergei Shtylyov592b5312009-01-06 17:21:02 +01001338 .dma_sff_read_status = ide_dma_sff_read_status,
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +02001339};
1340
Bartlomiej Zolnierkiewiczf37afda2008-04-26 22:25:24 +02001341static const struct ide_dma_ops hpt370_dma_ops = {
1342 .dma_host_set = ide_dma_host_set,
1343 .dma_setup = ide_dma_setup,
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +02001344 .dma_start = hpt370_dma_start,
1345 .dma_end = hpt370_dma_end,
Bartlomiej Zolnierkiewiczf37afda2008-04-26 22:25:24 +02001346 .dma_test_irq = ide_dma_test_irq,
1347 .dma_lost_irq = ide_dma_lost_irq,
Bartlomiej Zolnierkiewicz22117d62009-03-27 12:46:47 +01001348 .dma_timer_expiry = ide_dma_sff_timer_expiry,
Bartlomiej Zolnierkiewicz35c9b4d2009-03-31 20:15:19 +02001349 .dma_clear = hpt370_irq_timeout,
Sergei Shtylyov592b5312009-01-06 17:21:02 +01001350 .dma_sff_read_status = ide_dma_sff_read_status,
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +02001351};
1352
Bartlomiej Zolnierkiewiczf37afda2008-04-26 22:25:24 +02001353static const struct ide_dma_ops hpt36x_dma_ops = {
1354 .dma_host_set = ide_dma_host_set,
1355 .dma_setup = ide_dma_setup,
Bartlomiej Zolnierkiewiczf37afda2008-04-26 22:25:24 +02001356 .dma_start = ide_dma_start,
Bartlomiej Zolnierkiewicz653bcf52008-10-13 21:39:46 +02001357 .dma_end = ide_dma_end,
Bartlomiej Zolnierkiewiczf37afda2008-04-26 22:25:24 +02001358 .dma_test_irq = ide_dma_test_irq,
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +02001359 .dma_lost_irq = hpt366_dma_lost_irq,
Bartlomiej Zolnierkiewicz22117d62009-03-27 12:46:47 +01001360 .dma_timer_expiry = ide_dma_sff_timer_expiry,
Sergei Shtylyov592b5312009-01-06 17:21:02 +01001361 .dma_sff_read_status = ide_dma_sff_read_status,
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +02001362};
1363
Greg Kroah-Hartmanfe31edc2012-12-21 13:21:03 -08001364static const struct ide_port_info hpt366_chipsets[] = {
Bartlomiej Zolnierkiewiczced3ec82008-07-24 22:53:32 +02001365 { /* 0: HPT36x */
1366 .name = DRV_NAME,
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001367 .init_chipset = init_chipset_hpt366,
1368 .init_hwif = init_hwif_hpt366,
1369 .init_dma = init_dma_hpt366,
Sergei Shtylyov2648e5d2007-07-09 23:17:55 +02001370 /*
1371 * HPT36x chips have one channel per function and have
1372 * both channel enable bits located differently and visible
1373 * to both functions -- really stupid design decision... :-(
1374 * Bit 4 is for the primary channel, bit 5 for the secondary.
1375 */
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001376 .enablebits = {{0x50,0x10,0x10}, {0x54,0x04,0x04}},
Bartlomiej Zolnierkiewiczac95bee2008-04-26 22:25:14 +02001377 .port_ops = &hpt3xx_port_ops,
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +02001378 .dma_ops = &hpt36x_dma_ops,
Bartlomiej Zolnierkiewicz4db90a12008-01-25 22:17:18 +01001379 .host_flags = IDE_HFLAGS_HPT3XX | IDE_HFLAG_SINGLE,
Bartlomiej Zolnierkiewicz4099d142007-07-20 01:11:59 +02001380 .pio_mask = ATA_PIO4,
Bartlomiej Zolnierkiewicz5f8b6c32007-10-19 00:30:07 +02001381 .mwdma_mask = ATA_MWDMA2,
Bartlomiej Zolnierkiewiczced3ec82008-07-24 22:53:32 +02001382 },
1383 { /* 1: HPT3xx */
1384 .name = DRV_NAME,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001385 .init_chipset = init_chipset_hpt366,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001386 .init_hwif = init_hwif_hpt366,
1387 .init_dma = init_dma_hpt366,
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001388 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
Bartlomiej Zolnierkiewiczac95bee2008-04-26 22:25:14 +02001389 .port_ops = &hpt3xx_port_ops,
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +02001390 .dma_ops = &hpt37x_dma_ops,
Bartlomiej Zolnierkiewicz4db90a12008-01-25 22:17:18 +01001391 .host_flags = IDE_HFLAGS_HPT3XX,
Bartlomiej Zolnierkiewicz4099d142007-07-20 01:11:59 +02001392 .pio_mask = ATA_PIO4,
Bartlomiej Zolnierkiewicz5f8b6c32007-10-19 00:30:07 +02001393 .mwdma_mask = ATA_MWDMA2,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001394 }
1395};
1396
1397/**
1398 * hpt366_init_one - called when an HPT366 is found
1399 * @dev: the hpt366 device
1400 * @id: the matching pci id
1401 *
1402 * Called when the PCI registration layer (or the IDE initialization)
1403 * finds a device matching our IDE device tables.
1404 */
Greg Kroah-Hartmanfe31edc2012-12-21 13:21:03 -08001405static int hpt366_init_one(struct pci_dev *dev, const struct pci_device_id *id)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001406{
Bartlomiej Zolnierkiewicz282037f2007-10-26 20:31:15 +02001407 const struct hpt_info *info = NULL;
Bartlomiej Zolnierkiewicz74811f32008-07-24 22:53:15 +02001408 struct hpt_info *dyn_info;
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001409 struct pci_dev *dev2 = NULL;
Bartlomiej Zolnierkiewicz039788e2007-10-20 00:32:34 +02001410 struct ide_port_info d;
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001411 u8 idx = id->driver_data;
1412 u8 rev = dev->revision;
Bartlomiej Zolnierkiewicz74811f32008-07-24 22:53:15 +02001413 int ret;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001414
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001415 if ((idx == 0 || idx == 4) && (PCI_FUNC(dev->devfn) & 1))
1416 return -ENODEV;
1417
1418 switch (idx) {
1419 case 0:
1420 if (rev < 3)
1421 info = &hpt36x;
1422 else {
Sam Ravnborgb66cae72008-02-26 21:50:33 +01001423 switch (min_t(u8, rev, 6)) {
1424 case 3: info = &hpt370; break;
1425 case 4: info = &hpt370a; break;
1426 case 5: info = &hpt372; break;
1427 case 6: info = &hpt372n; break;
1428 }
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001429 idx++;
1430 }
1431 break;
1432 case 1:
1433 info = (rev > 1) ? &hpt372n : &hpt372a;
1434 break;
1435 case 2:
1436 info = (rev > 1) ? &hpt302n : &hpt302;
1437 break;
1438 case 3:
1439 hpt371_init(dev);
1440 info = (rev > 1) ? &hpt371n : &hpt371;
1441 break;
1442 case 4:
1443 info = &hpt374;
1444 break;
1445 case 5:
1446 info = &hpt372n;
1447 break;
1448 }
1449
Bartlomiej Zolnierkiewiczced3ec82008-07-24 22:53:32 +02001450 printk(KERN_INFO DRV_NAME ": %s chipset detected\n", info->chip_name);
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001451
Bartlomiej Zolnierkiewiczced3ec82008-07-24 22:53:32 +02001452 d = hpt366_chipsets[min_t(u8, idx, 1)];
1453
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001454 d.udma_mask = info->udma_mask;
1455
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +02001456 /* fixup ->dma_ops for HPT370/HPT370A */
1457 if (info == &hpt370 || info == &hpt370a)
1458 d.dma_ops = &hpt370_dma_ops;
1459
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001460 if (info == &hpt36x || info == &hpt374)
1461 dev2 = pci_get_slot(dev->bus, dev->devfn + 1);
1462
Bartlomiej Zolnierkiewicz74811f32008-07-24 22:53:15 +02001463 dyn_info = kzalloc(sizeof(*dyn_info) * (dev2 ? 2 : 1), GFP_KERNEL);
1464 if (dyn_info == NULL) {
Bartlomiej Zolnierkiewicz28cfd8a2008-07-24 22:53:31 +02001465 printk(KERN_ERR "%s %s: out of memory!\n",
1466 d.name, pci_name(dev));
Bartlomiej Zolnierkiewicz74811f32008-07-24 22:53:15 +02001467 pci_dev_put(dev2);
1468 return -ENOMEM;
1469 }
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001470
Bartlomiej Zolnierkiewicz74811f32008-07-24 22:53:15 +02001471 /*
1472 * Copy everything from a static "template" structure
1473 * to just allocated per-chip hpt_info structure.
1474 */
1475 memcpy(dyn_info, info, sizeof(*dyn_info));
1476
1477 if (dev2) {
1478 memcpy(dyn_info + 1, info, sizeof(*dyn_info));
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001479
1480 if (info == &hpt374)
1481 hpt374_init(dev, dev2);
1482 else {
1483 if (hpt36x_init(dev, dev2))
Bartlomiej Zolnierkiewicz5e71d9c2008-04-26 17:36:35 +02001484 d.host_flags &= ~IDE_HFLAG_NON_BOOTABLE;
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001485 }
1486
Bartlomiej Zolnierkiewicz74811f32008-07-24 22:53:15 +02001487 ret = ide_pci_init_two(dev, dev2, &d, dyn_info);
1488 if (ret < 0) {
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001489 pci_dev_put(dev2);
Bartlomiej Zolnierkiewicz74811f32008-07-24 22:53:15 +02001490 kfree(dyn_info);
1491 }
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001492 return ret;
1493 }
1494
Bartlomiej Zolnierkiewicz74811f32008-07-24 22:53:15 +02001495 ret = ide_pci_init_one(dev, &d, dyn_info);
1496 if (ret < 0)
1497 kfree(dyn_info);
1498
1499 return ret;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001500}
1501
Greg Kroah-Hartmanfe31edc2012-12-21 13:21:03 -08001502static void hpt366_remove(struct pci_dev *dev)
Bartlomiej Zolnierkiewicza6c43a22008-07-24 22:53:21 +02001503{
1504 struct ide_host *host = pci_get_drvdata(dev);
1505 struct ide_info *info = host->host_priv;
1506 struct pci_dev *dev2 = host->dev[1] ? to_pci_dev(host->dev[1]) : NULL;
1507
1508 ide_pci_remove(dev);
1509 pci_dev_put(dev2);
1510 kfree(info);
1511}
1512
Greg Kroah-Hartmanfe31edc2012-12-21 13:21:03 -08001513static const struct pci_device_id hpt366_pci_tbl[] = {
Bartlomiej Zolnierkiewicz9cbcc5e2007-10-16 22:29:56 +02001514 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), 0 },
1515 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372), 1 },
1516 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT302), 2 },
1517 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT371), 3 },
1518 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT374), 4 },
1519 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372N), 5 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07001520 { 0, },
1521};
1522MODULE_DEVICE_TABLE(pci, hpt366_pci_tbl);
1523
Bartlomiej Zolnierkiewicza9ab09e2008-10-13 21:39:41 +02001524static struct pci_driver hpt366_pci_driver = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001525 .name = "HPT366_IDE",
1526 .id_table = hpt366_pci_tbl,
1527 .probe = hpt366_init_one,
Greg Kroah-Hartmanfe31edc2012-12-21 13:21:03 -08001528 .remove = hpt366_remove,
Bartlomiej Zolnierkiewiczfeb22b72008-10-10 22:39:32 +02001529 .suspend = ide_pci_suspend,
1530 .resume = ide_pci_resume,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001531};
1532
Bartlomiej Zolnierkiewicz82ab1ee2007-01-27 13:46:56 +01001533static int __init hpt366_ide_init(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001534{
Bartlomiej Zolnierkiewicza9ab09e2008-10-13 21:39:41 +02001535 return ide_pci_register_driver(&hpt366_pci_driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001536}
1537
Bartlomiej Zolnierkiewicza6c43a22008-07-24 22:53:21 +02001538static void __exit hpt366_ide_exit(void)
1539{
Bartlomiej Zolnierkiewicza9ab09e2008-10-13 21:39:41 +02001540 pci_unregister_driver(&hpt366_pci_driver);
Bartlomiej Zolnierkiewicza6c43a22008-07-24 22:53:21 +02001541}
1542
Linus Torvalds1da177e2005-04-16 15:20:36 -07001543module_init(hpt366_ide_init);
Bartlomiej Zolnierkiewicza6c43a22008-07-24 22:53:21 +02001544module_exit(hpt366_ide_exit);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001545
1546MODULE_AUTHOR("Andre Hedrick");
1547MODULE_DESCRIPTION("PCI driver module for Highpoint HPT366 IDE");
1548MODULE_LICENSE("GPL");