blob: 00c41a4bde2aabb3fa2cf54f5c606bfbd9c6d8fc [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
2 */
Dave Airlie0d6aa602006-01-02 20:14:23 +11003/*
Dave Airliebc54fd12005-06-23 22:46:46 +10004 *
Linus Torvalds1da177e2005-04-16 15:20:36 -07005 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
Dave Airliebc54fd12005-06-23 22:46:46 +10007 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
Dave Airlie0d6aa602006-01-02 20:14:23 +110028 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070029
30#ifndef _I915_DRV_H_
31#define _I915_DRV_H_
32
Chris Wilsone9b73c62012-12-03 21:03:14 +000033#include <uapi/drm/i915_drm.h>
Tvrtko Ursulin93b81f52015-02-10 17:16:05 +000034#include <uapi/drm/drm_fourcc.h>
Chris Wilsone9b73c62012-12-03 21:03:14 +000035
Jani Nikulae23ceb82015-12-16 15:04:18 +020036#include <drm/drmP.h>
Joonas Lahtinenc838d712015-12-18 13:08:15 +020037#include "i915_params.h"
Jesse Barnes585fb112008-07-29 11:54:06 -070038#include "i915_reg.h"
Jesse Barnes79e53942008-11-07 14:24:08 -080039#include "intel_bios.h"
Zou Nan hai8187a2b2010-05-21 09:08:55 +080040#include "intel_ringbuffer.h"
Oscar Mateob20385f2014-07-24 17:04:10 +010041#include "intel_lrc.h"
Ben Widawsky0260c422014-03-22 22:47:21 -070042#include "i915_gem_gtt.h"
Oscar Mateo564ddb22014-08-21 11:40:54 +010043#include "i915_gem_render_state.h"
Keith Packard0839ccb2008-10-30 19:38:48 -070044#include <linux/io-mapping.h>
Chris Wilsonf899fc62010-07-20 15:44:45 -070045#include <linux/i2c.h>
Daniel Vetterc167a6f2012-02-28 00:43:09 +010046#include <linux/i2c-algo-bit.h>
Daniel Vetter0ade6382010-08-24 22:18:41 +020047#include <drm/intel-gtt.h>
Daniel Vetterba8286f2014-09-11 07:43:25 +020048#include <drm/drm_legacy.h> /* for struct drm_dma_handle */
Daniel Vetterd9fc9412014-09-23 15:46:53 +020049#include <drm/drm_gem.h>
Matthew Garrettaaa6fd22011-08-12 12:11:33 +020050#include <linux/backlight.h>
Chris Wilson5cc9ed42014-05-16 14:22:37 +010051#include <linux/hashtable.h>
Ben Widawsky2911a352012-04-05 14:47:36 -070052#include <linux/intel-iommu.h>
Daniel Vetter742cbee2012-04-27 15:17:39 +020053#include <linux/kref.h>
Daniel Vetter9ee32fea2012-12-01 13:53:48 +010054#include <linux/pm_qos.h>
Alex Dai33a732f2015-08-12 15:43:36 +010055#include "intel_guc.h"
Ander Conselvan de Oliveiraac7f11c2016-03-08 17:46:19 +020056#include "intel_dpll_mgr.h"
Jesse Barnes585fb112008-07-29 11:54:06 -070057
Linus Torvalds1da177e2005-04-16 15:20:36 -070058/* General customization:
59 */
60
Linus Torvalds1da177e2005-04-16 15:20:36 -070061#define DRIVER_NAME "i915"
62#define DRIVER_DESC "Intel Graphics"
Daniel Vetter359d22432016-03-14 08:16:51 +010063#define DRIVER_DATE "20160314"
Linus Torvalds1da177e2005-04-16 15:20:36 -070064
Mika Kuoppalac883ef12014-10-28 17:32:30 +020065#undef WARN_ON
Daniel Vetter5f77eeb2014-12-08 16:40:10 +010066/* Many gcc seem to no see through this and fall over :( */
67#if 0
68#define WARN_ON(x) ({ \
69 bool __i915_warn_cond = (x); \
70 if (__builtin_constant_p(__i915_warn_cond)) \
71 BUILD_BUG_ON(__i915_warn_cond); \
72 WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
73#else
Joonas Lahtinen152b2262015-12-18 14:27:27 +020074#define WARN_ON(x) WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
Daniel Vetter5f77eeb2014-12-08 16:40:10 +010075#endif
76
Jani Nikulacd9bfac2015-03-12 13:01:12 +020077#undef WARN_ON_ONCE
Joonas Lahtinen152b2262015-12-18 14:27:27 +020078#define WARN_ON_ONCE(x) WARN_ONCE((x), "%s", "WARN_ON_ONCE(" __stringify(x) ")")
Jani Nikulacd9bfac2015-03-12 13:01:12 +020079
Daniel Vetter5f77eeb2014-12-08 16:40:10 +010080#define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
81 (long) (x), __func__);
Mika Kuoppalac883ef12014-10-28 17:32:30 +020082
Rob Clarke2c719b2014-12-15 13:56:32 -050083/* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
84 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
85 * which may not necessarily be a user visible problem. This will either
86 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
87 * enable distros and users to tailor their preferred amount of i915 abrt
88 * spam.
89 */
90#define I915_STATE_WARN(condition, format...) ({ \
91 int __ret_warn_on = !!(condition); \
Joonas Lahtinen32753cb2015-12-18 14:27:26 +020092 if (unlikely(__ret_warn_on)) \
93 if (!WARN(i915.verbose_state_checks, format)) \
Rob Clarke2c719b2014-12-15 13:56:32 -050094 DRM_ERROR(format); \
Rob Clarke2c719b2014-12-15 13:56:32 -050095 unlikely(__ret_warn_on); \
96})
97
Joonas Lahtinen152b2262015-12-18 14:27:27 +020098#define I915_STATE_WARN_ON(x) \
99 I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
Jesse Barnes317c35d2008-08-25 15:11:06 -0700100
Imre Deak4fec15d2016-03-16 13:39:08 +0200101bool __i915_inject_load_failure(const char *func, int line);
102#define i915_inject_load_failure() \
103 __i915_inject_load_failure(__func__, __LINE__)
104
Jani Nikula42a8ca42015-08-27 16:23:30 +0300105static inline const char *yesno(bool v)
106{
107 return v ? "yes" : "no";
108}
109
Jani Nikula87ad3212016-01-14 12:53:34 +0200110static inline const char *onoff(bool v)
111{
112 return v ? "on" : "off";
113}
114
Linus Torvalds1da177e2005-04-16 15:20:36 -0700115enum pipe {
Jesse Barnes317c35d2008-08-25 15:11:06 -0700116 INVALID_PIPE = -1,
117 PIPE_A = 0,
118 PIPE_B,
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800119 PIPE_C,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200120 _PIPE_EDP,
121 I915_MAX_PIPES = _PIPE_EDP
Jesse Barnes317c35d2008-08-25 15:11:06 -0700122};
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800123#define pipe_name(p) ((p) + 'A')
Jesse Barnes317c35d2008-08-25 15:11:06 -0700124
Paulo Zanonia5c961d2012-10-24 15:59:34 -0200125enum transcoder {
126 TRANSCODER_A = 0,
127 TRANSCODER_B,
128 TRANSCODER_C,
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200129 TRANSCODER_EDP,
130 I915_MAX_TRANSCODERS
Paulo Zanonia5c961d2012-10-24 15:59:34 -0200131};
Jani Nikulada205632016-03-15 21:51:10 +0200132
133static inline const char *transcoder_name(enum transcoder transcoder)
134{
135 switch (transcoder) {
136 case TRANSCODER_A:
137 return "A";
138 case TRANSCODER_B:
139 return "B";
140 case TRANSCODER_C:
141 return "C";
142 case TRANSCODER_EDP:
143 return "EDP";
144 default:
145 return "<invalid>";
146 }
147}
Paulo Zanonia5c961d2012-10-24 15:59:34 -0200148
Damien Lespiau84139d12014-03-28 00:18:32 +0530149/*
Matt Roper31409e92015-09-24 15:53:09 -0700150 * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
151 * number of planes per CRTC. Not all platforms really have this many planes,
152 * which means some arrays of size I915_MAX_PLANES may have unused entries
153 * between the topmost sprite plane and the cursor plane.
Damien Lespiau84139d12014-03-28 00:18:32 +0530154 */
Jesse Barnes80824002009-09-10 15:28:06 -0700155enum plane {
156 PLANE_A = 0,
157 PLANE_B,
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800158 PLANE_C,
Matt Roper31409e92015-09-24 15:53:09 -0700159 PLANE_CURSOR,
160 I915_MAX_PLANES,
Jesse Barnes80824002009-09-10 15:28:06 -0700161};
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800162#define plane_name(p) ((p) + 'A')
Keith Packard52440212008-11-18 09:30:25 -0800163
Damien Lespiaud615a162014-03-03 17:31:48 +0000164#define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
Ville Syrjälä06da8da2013-04-17 17:48:51 +0300165
Eugeni Dodonov2b139522012-03-29 12:32:22 -0300166enum port {
167 PORT_A = 0,
168 PORT_B,
169 PORT_C,
170 PORT_D,
171 PORT_E,
172 I915_MAX_PORTS
173};
174#define port_name(p) ((p) + 'A')
175
Chon Ming Leea09cadd2014-04-09 13:28:14 +0300176#define I915_NUM_PHYS_VLV 2
Chon Ming Leee4607fc2013-11-06 14:36:35 +0800177
178enum dpio_channel {
179 DPIO_CH0,
180 DPIO_CH1
181};
182
183enum dpio_phy {
184 DPIO_PHY0,
185 DPIO_PHY1
186};
187
Paulo Zanonib97186f2013-05-03 12:15:36 -0300188enum intel_display_power_domain {
189 POWER_DOMAIN_PIPE_A,
190 POWER_DOMAIN_PIPE_B,
191 POWER_DOMAIN_PIPE_C,
192 POWER_DOMAIN_PIPE_A_PANEL_FITTER,
193 POWER_DOMAIN_PIPE_B_PANEL_FITTER,
194 POWER_DOMAIN_PIPE_C_PANEL_FITTER,
195 POWER_DOMAIN_TRANSCODER_A,
196 POWER_DOMAIN_TRANSCODER_B,
197 POWER_DOMAIN_TRANSCODER_C,
Imre Deakf52e3532013-10-16 17:25:48 +0300198 POWER_DOMAIN_TRANSCODER_EDP,
Patrik Jakobsson6331a702015-11-09 16:48:21 +0100199 POWER_DOMAIN_PORT_DDI_A_LANES,
200 POWER_DOMAIN_PORT_DDI_B_LANES,
201 POWER_DOMAIN_PORT_DDI_C_LANES,
202 POWER_DOMAIN_PORT_DDI_D_LANES,
203 POWER_DOMAIN_PORT_DDI_E_LANES,
Imre Deak319be8a2014-03-04 19:22:57 +0200204 POWER_DOMAIN_PORT_DSI,
205 POWER_DOMAIN_PORT_CRT,
206 POWER_DOMAIN_PORT_OTHER,
Ville Syrjäläcdf8dd72013-09-16 17:38:30 +0300207 POWER_DOMAIN_VGA,
Imre Deakfbeeaa22013-11-25 17:15:28 +0200208 POWER_DOMAIN_AUDIO,
Paulo Zanonibd2bb1b2014-07-04 11:27:38 -0300209 POWER_DOMAIN_PLLS,
Satheeshakrishna M14071212015-01-16 15:57:51 +0000210 POWER_DOMAIN_AUX_A,
211 POWER_DOMAIN_AUX_B,
212 POWER_DOMAIN_AUX_C,
213 POWER_DOMAIN_AUX_D,
Ville Syrjäläf0ab43e2015-11-09 16:48:19 +0100214 POWER_DOMAIN_GMBUS,
Patrik Jakobssondfa57622015-11-09 16:48:22 +0100215 POWER_DOMAIN_MODESET,
Imre Deakbaa70702013-10-25 17:36:48 +0300216 POWER_DOMAIN_INIT,
Imre Deakbddc7642013-10-16 17:25:49 +0300217
218 POWER_DOMAIN_NUM,
Paulo Zanonib97186f2013-05-03 12:15:36 -0300219};
220
221#define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
222#define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
223 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
Imre Deakf52e3532013-10-16 17:25:48 +0300224#define POWER_DOMAIN_TRANSCODER(tran) \
225 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
226 (tran) + POWER_DOMAIN_TRANSCODER_A)
Paulo Zanonib97186f2013-05-03 12:15:36 -0300227
Egbert Eich1d843f92013-02-25 12:06:49 -0500228enum hpd_pin {
229 HPD_NONE = 0,
Egbert Eich1d843f92013-02-25 12:06:49 -0500230 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
231 HPD_CRT,
232 HPD_SDVO_B,
233 HPD_SDVO_C,
Imre Deakcc24fcd2015-07-21 15:32:45 -0700234 HPD_PORT_A,
Egbert Eich1d843f92013-02-25 12:06:49 -0500235 HPD_PORT_B,
236 HPD_PORT_C,
237 HPD_PORT_D,
Xiong Zhang26951ca2015-08-17 15:55:50 +0800238 HPD_PORT_E,
Egbert Eich1d843f92013-02-25 12:06:49 -0500239 HPD_NUM_PINS
240};
241
Jani Nikulac91711f2015-05-28 15:43:48 +0300242#define for_each_hpd_pin(__pin) \
243 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
244
Jani Nikula5fcece82015-05-27 15:03:42 +0300245struct i915_hotplug {
246 struct work_struct hotplug_work;
247
248 struct {
249 unsigned long last_jiffies;
250 int count;
251 enum {
252 HPD_ENABLED = 0,
253 HPD_DISABLED = 1,
254 HPD_MARK_DISABLED = 2
255 } state;
256 } stats[HPD_NUM_PINS];
257 u32 event_bits;
258 struct delayed_work reenable_work;
259
260 struct intel_digital_port *irq_port[I915_MAX_PORTS];
261 u32 long_port_mask;
262 u32 short_port_mask;
263 struct work_struct dig_port_work;
264
265 /*
266 * if we get a HPD irq from DP and a HPD irq from non-DP
267 * the non-DP HPD could block the workqueue on a mode config
268 * mutex getting, that userspace may have taken. However
269 * userspace is waiting on the DP workqueue to run which is
270 * blocked behind the non-DP one.
271 */
272 struct workqueue_struct *dp_wq;
273};
274
Chris Wilson2a2d5482012-12-03 11:49:06 +0000275#define I915_GEM_GPU_DOMAINS \
276 (I915_GEM_DOMAIN_RENDER | \
277 I915_GEM_DOMAIN_SAMPLER | \
278 I915_GEM_DOMAIN_COMMAND | \
279 I915_GEM_DOMAIN_INSTRUCTION | \
280 I915_GEM_DOMAIN_VERTEX)
Eric Anholt62fdfea2010-05-21 13:26:39 -0700281
Damien Lespiau055e3932014-08-18 13:49:10 +0100282#define for_each_pipe(__dev_priv, __p) \
283 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
Ville Syrjälä6831f3e2016-02-19 20:47:31 +0200284#define for_each_pipe_masked(__dev_priv, __p, __mask) \
285 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \
286 for_each_if ((__mask) & (1 << (__p)))
Damien Lespiaudd740782015-02-28 14:54:08 +0000287#define for_each_plane(__dev_priv, __pipe, __p) \
288 for ((__p) = 0; \
289 (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
290 (__p)++)
Damien Lespiau3bdcfc02015-02-28 14:54:09 +0000291#define for_each_sprite(__dev_priv, __p, __s) \
292 for ((__s) = 0; \
293 (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \
294 (__s)++)
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800295
Jani Nikulac3aeadc82016-03-15 21:51:09 +0200296#define for_each_port_masked(__port, __ports_mask) \
297 for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) \
298 for_each_if ((__ports_mask) & (1 << (__port)))
299
Damien Lespiaud79b8142014-05-13 23:32:23 +0100300#define for_each_crtc(dev, crtc) \
301 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
302
Maarten Lankhorst27321ae2015-04-21 17:12:52 +0300303#define for_each_intel_plane(dev, intel_plane) \
304 list_for_each_entry(intel_plane, \
305 &dev->mode_config.plane_list, \
306 base.head)
307
Ville Syrjälä262cd2e2015-06-24 22:00:04 +0300308#define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \
309 list_for_each_entry(intel_plane, \
310 &(dev)->mode_config.plane_list, \
311 base.head) \
Jani Nikula95150bd2015-11-24 21:21:56 +0200312 for_each_if ((intel_plane)->pipe == (intel_crtc)->pipe)
Ville Syrjälä262cd2e2015-06-24 22:00:04 +0300313
Damien Lespiaud063ae42014-05-13 23:32:21 +0100314#define for_each_intel_crtc(dev, intel_crtc) \
315 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head)
316
Damien Lespiaub2784e12014-08-05 11:29:37 +0100317#define for_each_intel_encoder(dev, intel_encoder) \
318 list_for_each_entry(intel_encoder, \
319 &(dev)->mode_config.encoder_list, \
320 base.head)
321
Ander Conselvan de Oliveira3a3371f2015-03-03 15:21:56 +0200322#define for_each_intel_connector(dev, intel_connector) \
323 list_for_each_entry(intel_connector, \
324 &dev->mode_config.connector_list, \
325 base.head)
326
Daniel Vetter6c2b7c122012-07-05 09:50:24 +0200327#define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
328 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
Jani Nikula95150bd2015-11-24 21:21:56 +0200329 for_each_if ((intel_encoder)->base.crtc == (__crtc))
Daniel Vetter6c2b7c122012-07-05 09:50:24 +0200330
Jesse Barnes53f5e3c2014-02-07 12:48:15 -0800331#define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
332 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
Jani Nikula95150bd2015-11-24 21:21:56 +0200333 for_each_if ((intel_connector)->base.encoder == (__encoder))
Jesse Barnes53f5e3c2014-02-07 12:48:15 -0800334
Borun Fub04c5bd2014-07-12 10:02:27 +0530335#define for_each_power_domain(domain, mask) \
336 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
Jani Nikula95150bd2015-11-24 21:21:56 +0200337 for_each_if ((1 << (domain)) & (mask))
Borun Fub04c5bd2014-07-12 10:02:27 +0530338
Daniel Vettere7b903d2013-06-05 13:34:14 +0200339struct drm_i915_private;
Chris Wilsonad46cb52014-08-07 14:20:40 +0100340struct i915_mm_struct;
Chris Wilson5cc9ed42014-05-16 14:22:37 +0100341struct i915_mmu_object;
Daniel Vettere7b903d2013-06-05 13:34:14 +0200342
Chris Wilsona6f766f2015-04-27 13:41:20 +0100343struct drm_i915_file_private {
344 struct drm_i915_private *dev_priv;
345 struct drm_file *file;
346
347 struct {
348 spinlock_t lock;
349 struct list_head request_list;
Chris Wilsond0bc54f2015-05-21 21:01:48 +0100350/* 20ms is a fairly arbitrary limit (greater than the average frame time)
351 * chosen to prevent the CPU getting more than a frame ahead of the GPU
352 * (when using lax throttling for the frontbuffer). We also use it to
353 * offer free GPU waitboosts for severely congested workloads.
354 */
355#define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
Chris Wilsona6f766f2015-04-27 13:41:20 +0100356 } mm;
357 struct idr context_idr;
358
Chris Wilson2e1b8732015-04-27 13:41:22 +0100359 struct intel_rps_client {
360 struct list_head link;
361 unsigned boosts;
362 } rps;
Chris Wilsona6f766f2015-04-27 13:41:20 +0100363
Tvrtko Ursulinde1add32016-01-15 15:12:50 +0000364 unsigned int bsd_ring;
Chris Wilsona6f766f2015-04-27 13:41:20 +0100365};
366
Daniel Vettere69d0bc2012-11-29 15:59:36 +0100367/* Used by dp and fdi links */
368struct intel_link_m_n {
369 uint32_t tu;
370 uint32_t gmch_m;
371 uint32_t gmch_n;
372 uint32_t link_m;
373 uint32_t link_n;
374};
375
376void intel_link_compute_m_n(int bpp, int nlanes,
377 int pixel_clock, int link_clock,
378 struct intel_link_m_n *m_n);
379
Linus Torvalds1da177e2005-04-16 15:20:36 -0700380/* Interface history:
381 *
382 * 1.1: Original.
Dave Airlie0d6aa602006-01-02 20:14:23 +1100383 * 1.2: Add Power Management
384 * 1.3: Add vblank support
Dave Airliede227f52006-01-25 15:31:43 +1100385 * 1.4: Fix cmdbuffer path, add heap destroy
Dave Airlie702880f2006-06-24 17:07:34 +1000386 * 1.5: Add vblank pipe configuration
=?utf-8?q?Michel_D=C3=A4nzer?=2228ed62006-10-25 01:05:09 +1000387 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
388 * - Support vertical blank on secondary display pipe
Linus Torvalds1da177e2005-04-16 15:20:36 -0700389 */
390#define DRIVER_MAJOR 1
=?utf-8?q?Michel_D=C3=A4nzer?=2228ed62006-10-25 01:05:09 +1000391#define DRIVER_MINOR 6
Linus Torvalds1da177e2005-04-16 15:20:36 -0700392#define DRIVER_PATCHLEVEL 0
393
Chris Wilson23bc5982010-09-29 16:10:57 +0100394#define WATCH_LISTS 0
Eric Anholt673a3942008-07-30 12:06:12 -0700395
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700396struct opregion_header;
397struct opregion_acpi;
398struct opregion_swsci;
399struct opregion_asle;
400
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +0100401struct intel_opregion {
Williams, Dan J115719f2015-10-12 21:12:57 +0000402 struct opregion_header *header;
403 struct opregion_acpi *acpi;
404 struct opregion_swsci *swsci;
Jani Nikulaebde53c2013-09-02 10:38:59 +0300405 u32 swsci_gbda_sub_functions;
406 u32 swsci_sbcb_sub_functions;
Williams, Dan J115719f2015-10-12 21:12:57 +0000407 struct opregion_asle *asle;
Jani Nikula04ebaad2015-12-15 13:18:00 +0200408 void *rvda;
Jani Nikula82730382015-12-14 12:50:52 +0200409 const void *vbt;
Jani Nikulaada8f952015-12-15 13:17:12 +0200410 u32 vbt_size;
Williams, Dan J115719f2015-10-12 21:12:57 +0000411 u32 *lid_state;
Jani Nikula91a60f22013-10-31 18:55:48 +0200412 struct work_struct asle_work;
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +0100413};
Chris Wilson44834a62010-08-19 16:09:23 +0100414#define OPREGION_SIZE (8*1024)
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +0100415
Chris Wilson6ef3d422010-08-04 20:26:07 +0100416struct intel_overlay;
417struct intel_overlay_error_state;
418
Jesse Barnesde151cf2008-11-12 10:03:55 -0800419#define I915_FENCE_REG_NONE -1
Ville Syrjälä42b5aea2013-04-09 13:02:47 +0300420#define I915_MAX_NUM_FENCES 32
421/* 32 fences + sign bit for FENCE_REG_NONE */
422#define I915_MAX_NUM_FENCE_BITS 6
Jesse Barnesde151cf2008-11-12 10:03:55 -0800423
424struct drm_i915_fence_reg {
Daniel Vetter007cc8a2010-04-28 11:02:31 +0200425 struct list_head lru_list;
Chris Wilsoncaea7472010-11-12 13:53:37 +0000426 struct drm_i915_gem_object *obj;
Chris Wilson1690e1e2011-12-14 13:57:08 +0100427 int pin_count;
Jesse Barnesde151cf2008-11-12 10:03:55 -0800428};
Dave Airlie7c1c2872008-11-28 14:22:24 +1000429
yakui_zhao9b9d1722009-05-31 17:17:17 +0800430struct sdvo_device_mapping {
Chris Wilsone957d772010-09-24 12:52:03 +0100431 u8 initialized;
yakui_zhao9b9d1722009-05-31 17:17:17 +0800432 u8 dvo_port;
433 u8 slave_addr;
434 u8 dvo_wiring;
Chris Wilsone957d772010-09-24 12:52:03 +0100435 u8 i2c_pin;
Adam Jacksonb1083332010-04-23 16:07:40 -0400436 u8 ddc_pin;
yakui_zhao9b9d1722009-05-31 17:17:17 +0800437};
438
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +0000439struct intel_display_error_state;
440
Jesse Barnes63eeaf32009-06-18 16:56:52 -0700441struct drm_i915_error_state {
Daniel Vetter742cbee2012-04-27 15:17:39 +0200442 struct kref ref;
Ben Widawsky585b0282014-01-30 00:19:37 -0800443 struct timeval time;
444
Mika Kuoppalacb383002014-02-25 17:11:25 +0200445 char error_msg[128];
Chris Wilsoneb5be9d2015-08-07 20:24:15 +0100446 int iommu;
Mika Kuoppala48b031e2014-02-25 17:11:27 +0200447 u32 reset_count;
Mika Kuoppala62d5d692014-02-25 17:11:28 +0200448 u32 suspend_count;
Mika Kuoppalacb383002014-02-25 17:11:25 +0200449
Ben Widawsky585b0282014-01-30 00:19:37 -0800450 /* Generic register state */
Jesse Barnes63eeaf32009-06-18 16:56:52 -0700451 u32 eir;
452 u32 pgtbl_er;
Ben Widawskybe998e22012-04-26 16:03:00 -0700453 u32 ier;
Rodrigo Vivi885ea5a2014-08-05 10:07:13 -0700454 u32 gtier[4];
Ben Widawskyb9a39062012-06-04 14:42:52 -0700455 u32 ccid;
Chris Wilson0f3b6842013-01-15 12:05:55 +0000456 u32 derrmr;
457 u32 forcewake;
Ben Widawsky585b0282014-01-30 00:19:37 -0800458 u32 error; /* gen6+ */
459 u32 err_int; /* gen7 */
Mika Kuoppala6c826f32015-03-24 14:54:19 +0200460 u32 fault_data0; /* gen8, gen9 */
461 u32 fault_data1; /* gen8, gen9 */
Ben Widawsky585b0282014-01-30 00:19:37 -0800462 u32 done_reg;
Ben Widawsky91ec5d12014-01-30 00:19:39 -0800463 u32 gac_eco;
464 u32 gam_ecochk;
465 u32 gab_ctl;
466 u32 gfx_mode;
Ben Widawsky585b0282014-01-30 00:19:37 -0800467 u32 extra_instdone[I915_NUM_INSTDONE_REG];
Ben Widawsky585b0282014-01-30 00:19:37 -0800468 u64 fence[I915_MAX_NUM_FENCES];
469 struct intel_overlay_error_state *overlay;
470 struct intel_display_error_state *display;
Ben Widawsky0ca36d72014-06-30 09:53:41 -0700471 struct drm_i915_error_object *semaphore_obj;
Ben Widawsky585b0282014-01-30 00:19:37 -0800472
Chris Wilson52d39a22012-02-15 11:25:37 +0000473 struct drm_i915_error_ring {
Chris Wilson372fbb82014-01-27 13:52:34 +0000474 bool valid;
Ben Widawsky362b8af2014-01-30 00:19:38 -0800475 /* Software tracked state */
476 bool waiting;
477 int hangcheck_score;
478 enum intel_ring_hangcheck_action hangcheck_action;
479 int num_requests;
480
481 /* our own tracking of ring head and tail */
482 u32 cpu_ring_head;
483 u32 cpu_ring_tail;
484
Tvrtko Ursulin666796d2016-03-16 11:00:39 +0000485 u32 semaphore_seqno[I915_NUM_ENGINES - 1];
Ben Widawsky362b8af2014-01-30 00:19:38 -0800486
487 /* Register state */
Chris Wilson94f8cf12015-04-07 16:20:47 +0100488 u32 start;
Ben Widawsky362b8af2014-01-30 00:19:38 -0800489 u32 tail;
490 u32 head;
491 u32 ctl;
492 u32 hws;
493 u32 ipeir;
494 u32 ipehr;
495 u32 instdone;
Ben Widawsky362b8af2014-01-30 00:19:38 -0800496 u32 bbstate;
497 u32 instpm;
498 u32 instps;
499 u32 seqno;
500 u64 bbaddr;
Chris Wilson50877442014-03-21 12:41:53 +0000501 u64 acthd;
Ben Widawsky362b8af2014-01-30 00:19:38 -0800502 u32 fault_reg;
Ben Widawsky13ffadd2014-04-01 16:31:07 -0700503 u64 faddr;
Ben Widawsky362b8af2014-01-30 00:19:38 -0800504 u32 rc_psmi; /* sleep state */
Tvrtko Ursulin666796d2016-03-16 11:00:39 +0000505 u32 semaphore_mboxes[I915_NUM_ENGINES - 1];
Ben Widawsky362b8af2014-01-30 00:19:38 -0800506
Chris Wilson52d39a22012-02-15 11:25:37 +0000507 struct drm_i915_error_object {
508 int page_count;
Michel Thierrye1f12322015-07-29 17:23:56 +0100509 u64 gtt_offset;
Chris Wilson52d39a22012-02-15 11:25:37 +0000510 u32 *pages[0];
Chris Wilsonab0e7ff2014-02-25 17:11:24 +0200511 } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
Ben Widawsky362b8af2014-01-30 00:19:38 -0800512
arun.siluvery@linux.intel.comf85db052016-03-01 11:24:36 +0000513 struct drm_i915_error_object *wa_ctx;
514
Chris Wilson52d39a22012-02-15 11:25:37 +0000515 struct drm_i915_error_request {
516 long jiffies;
517 u32 seqno;
Chris Wilsonee4f42b2012-02-15 11:25:38 +0000518 u32 tail;
Chris Wilson52d39a22012-02-15 11:25:37 +0000519 } *requests;
Ben Widawsky6c7a01e2014-01-30 00:19:40 -0800520
521 struct {
522 u32 gfx_mode;
523 union {
524 u64 pdp[4];
525 u32 pp_dir_base;
526 };
527 } vm_info;
Chris Wilsonab0e7ff2014-02-25 17:11:24 +0200528
529 pid_t pid;
530 char comm[TASK_COMM_LEN];
Tvrtko Ursulin666796d2016-03-16 11:00:39 +0000531 } ring[I915_NUM_ENGINES];
Chris Wilson3a448732014-08-12 20:05:47 +0100532
Chris Wilson9df30792010-02-18 10:24:56 +0000533 struct drm_i915_error_buffer {
Chris Wilsona779e5a2011-01-09 21:07:49 +0000534 u32 size;
Chris Wilson9df30792010-02-18 10:24:56 +0000535 u32 name;
Tvrtko Ursulin666796d2016-03-16 11:00:39 +0000536 u32 rseqno[I915_NUM_ENGINES], wseqno;
Michel Thierrye1f12322015-07-29 17:23:56 +0100537 u64 gtt_offset;
Chris Wilson9df30792010-02-18 10:24:56 +0000538 u32 read_domains;
539 u32 write_domain;
Daniel Vetter4b9de732011-10-09 21:52:02 +0200540 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
Chris Wilson9df30792010-02-18 10:24:56 +0000541 s32 pinned:2;
542 u32 tiling:2;
543 u32 dirty:1;
544 u32 purgeable:1;
Chris Wilson5cc9ed42014-05-16 14:22:37 +0100545 u32 userptr:1;
Daniel Vetter5d1333f2012-02-16 11:03:29 +0100546 s32 ring:4;
Chris Wilsonf56383c2013-09-25 10:23:19 +0100547 u32 cache_level:3;
Ben Widawsky95f53012013-07-31 17:00:15 -0700548 } **active_bo, **pinned_bo;
Ben Widawsky6c7a01e2014-01-30 00:19:40 -0800549
Ben Widawsky95f53012013-07-31 17:00:15 -0700550 u32 *active_bo_count, *pinned_bo_count;
Chris Wilson3a448732014-08-12 20:05:47 +0100551 u32 vm_count;
Jesse Barnes63eeaf32009-06-18 16:56:52 -0700552};
553
Jani Nikula7bd688c2013-11-08 16:48:56 +0200554struct intel_connector;
Jani Nikula820d2d72014-10-27 16:26:47 +0200555struct intel_encoder;
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +0200556struct intel_crtc_state;
Damien Lespiau5724dbd2015-01-20 12:51:52 +0000557struct intel_initial_plane_config;
Daniel Vetter0e8ffe12013-03-28 10:42:00 +0100558struct intel_crtc;
Daniel Vetteree9300b2013-06-03 22:40:22 +0200559struct intel_limit;
560struct dpll;
Daniel Vetterb8cecdf2013-03-27 00:44:50 +0100561
Jesse Barnese70236a2009-09-21 10:42:27 -0700562struct drm_i915_display_funcs {
Jesse Barnese70236a2009-09-21 10:42:27 -0700563 int (*get_display_clock_speed)(struct drm_device *dev);
564 int (*get_fifo_size)(struct drm_device *dev, int plane);
Daniel Vetteree9300b2013-06-03 22:40:22 +0200565 /**
566 * find_dpll() - Find the best values for the PLL
567 * @limit: limits for the PLL
568 * @crtc: current CRTC
569 * @target: target frequency in kHz
570 * @refclk: reference clock frequency in kHz
571 * @match_clock: if provided, @best_clock P divider must
572 * match the P divider from @match_clock
573 * used for LVDS downclocking
574 * @best_clock: best PLL values found
575 *
576 * Returns true on success, false on failure.
577 */
578 bool (*find_dpll)(const struct intel_limit *limit,
Ander Conselvan de Oliveiraa93e2552015-03-20 16:18:17 +0200579 struct intel_crtc_state *crtc_state,
Daniel Vetteree9300b2013-06-03 22:40:22 +0200580 int target, int refclk,
581 struct dpll *match_clock,
582 struct dpll *best_clock);
Maarten Lankhorste3bddde2016-03-01 11:07:22 +0100583 int (*compute_pipe_wm)(struct intel_crtc_state *cstate);
Matt Ropered4a6a72016-02-23 17:20:13 -0800584 int (*compute_intermediate_wm)(struct drm_device *dev,
585 struct intel_crtc *intel_crtc,
586 struct intel_crtc_state *newstate);
587 void (*initial_watermarks)(struct intel_crtc_state *cstate);
588 void (*optimize_watermarks)(struct intel_crtc_state *cstate);
Ville Syrjälä46ba6142013-09-10 11:40:40 +0300589 void (*update_wm)(struct drm_crtc *crtc);
Maarten Lankhorst27c329e2015-06-15 12:33:56 +0200590 int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
591 void (*modeset_commit_cdclk)(struct drm_atomic_state *state);
Daniel Vetter0e8ffe12013-03-28 10:42:00 +0100592 /* Returns the active state of the crtc, and if the crtc is active,
593 * fills out the pipe-config with the hw state. */
594 bool (*get_pipe_config)(struct intel_crtc *,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +0200595 struct intel_crtc_state *);
Damien Lespiau5724dbd2015-01-20 12:51:52 +0000596 void (*get_initial_plane_config)(struct intel_crtc *,
597 struct intel_initial_plane_config *);
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +0200598 int (*crtc_compute_clock)(struct intel_crtc *crtc,
599 struct intel_crtc_state *crtc_state);
Daniel Vetter76e5a892012-06-29 22:39:33 +0200600 void (*crtc_enable)(struct drm_crtc *crtc);
601 void (*crtc_disable)(struct drm_crtc *crtc);
Jani Nikula69bfe1a2014-10-27 16:26:50 +0200602 void (*audio_codec_enable)(struct drm_connector *connector,
603 struct intel_encoder *encoder,
Ville Syrjälä5e7234c2015-09-25 16:37:43 +0300604 const struct drm_display_mode *adjusted_mode);
Jani Nikula69bfe1a2014-10-27 16:26:50 +0200605 void (*audio_codec_disable)(struct intel_encoder *encoder);
Jesse Barnes674cf962011-04-28 14:27:04 -0700606 void (*fdi_link_train)(struct drm_crtc *crtc);
Jesse Barnes6067aae2011-04-28 15:04:31 -0700607 void (*init_clock_gating)(struct drm_device *dev);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -0700608 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
609 struct drm_framebuffer *fb,
Keith Packarded8d1972013-07-22 18:49:58 -0700610 struct drm_i915_gem_object *obj,
John Harrison6258fbe2015-05-29 17:43:48 +0100611 struct drm_i915_gem_request *req,
Keith Packarded8d1972013-07-22 18:49:58 -0700612 uint32_t flags);
Daniel Vetter20afbda2012-12-11 14:05:07 +0100613 void (*hpd_irq_setup)(struct drm_device *dev);
Jesse Barnese70236a2009-09-21 10:42:27 -0700614 /* clock updates for mode set */
615 /* cursor updates */
616 /* render clock increase/decrease */
617 /* display clock increase/decrease */
618 /* pll clock increase/decrease */
Jesse Barnese70236a2009-09-21 10:42:27 -0700619};
620
Mika Kuoppala48c10262015-01-16 11:34:41 +0200621enum forcewake_domain_id {
622 FW_DOMAIN_ID_RENDER = 0,
623 FW_DOMAIN_ID_BLITTER,
624 FW_DOMAIN_ID_MEDIA,
625
626 FW_DOMAIN_ID_COUNT
627};
628
629enum forcewake_domains {
630 FORCEWAKE_RENDER = (1 << FW_DOMAIN_ID_RENDER),
631 FORCEWAKE_BLITTER = (1 << FW_DOMAIN_ID_BLITTER),
632 FORCEWAKE_MEDIA = (1 << FW_DOMAIN_ID_MEDIA),
633 FORCEWAKE_ALL = (FORCEWAKE_RENDER |
634 FORCEWAKE_BLITTER |
635 FORCEWAKE_MEDIA)
636};
637
Chris Wilson907b28c2013-07-19 20:36:52 +0100638struct intel_uncore_funcs {
Deepak Sc8d9a592013-11-23 14:55:42 +0530639 void (*force_wake_get)(struct drm_i915_private *dev_priv,
Mika Kuoppala48c10262015-01-16 11:34:41 +0200640 enum forcewake_domains domains);
Deepak Sc8d9a592013-11-23 14:55:42 +0530641 void (*force_wake_put)(struct drm_i915_private *dev_priv,
Mika Kuoppala48c10262015-01-16 11:34:41 +0200642 enum forcewake_domains domains);
Ben Widawsky0b274482013-10-04 21:22:51 -0700643
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200644 uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
645 uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
646 uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
647 uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
Ben Widawsky0b274482013-10-04 21:22:51 -0700648
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200649 void (*mmio_writeb)(struct drm_i915_private *dev_priv, i915_reg_t r,
Ben Widawsky0b274482013-10-04 21:22:51 -0700650 uint8_t val, bool trace);
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200651 void (*mmio_writew)(struct drm_i915_private *dev_priv, i915_reg_t r,
Ben Widawsky0b274482013-10-04 21:22:51 -0700652 uint16_t val, bool trace);
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200653 void (*mmio_writel)(struct drm_i915_private *dev_priv, i915_reg_t r,
Ben Widawsky0b274482013-10-04 21:22:51 -0700654 uint32_t val, bool trace);
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200655 void (*mmio_writeq)(struct drm_i915_private *dev_priv, i915_reg_t r,
Ben Widawsky0b274482013-10-04 21:22:51 -0700656 uint64_t val, bool trace);
Chris Wilson990bbda2012-07-02 11:51:02 -0300657};
658
Chris Wilson907b28c2013-07-19 20:36:52 +0100659struct intel_uncore {
660 spinlock_t lock; /** lock is also taken in irq contexts. */
661
662 struct intel_uncore_funcs funcs;
663
664 unsigned fifo_count;
Mika Kuoppala48c10262015-01-16 11:34:41 +0200665 enum forcewake_domains fw_domains;
Chris Wilsonaec347a2013-08-26 13:46:09 +0100666
Chris Wilsonb2cff0d2015-01-16 11:34:37 +0200667 struct intel_uncore_forcewake_domain {
668 struct drm_i915_private *i915;
Mika Kuoppala48c10262015-01-16 11:34:41 +0200669 enum forcewake_domain_id id;
Chris Wilsonb2cff0d2015-01-16 11:34:37 +0200670 unsigned wake_count;
671 struct timer_list timer;
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200672 i915_reg_t reg_set;
Mika Kuoppala05a2fb12015-01-19 16:20:43 +0200673 u32 val_set;
674 u32 val_clear;
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200675 i915_reg_t reg_ack;
676 i915_reg_t reg_post;
Mika Kuoppala05a2fb12015-01-19 16:20:43 +0200677 u32 val_reset;
Chris Wilsonb2cff0d2015-01-16 11:34:37 +0200678 } fw_domain[FW_DOMAIN_ID_COUNT];
Mika Kuoppala75714942015-12-16 09:26:48 +0200679
680 int unclaimed_mmio_check;
Chris Wilson907b28c2013-07-19 20:36:52 +0100681};
682
Chris Wilsonb2cff0d2015-01-16 11:34:37 +0200683/* Iterate over initialised fw domains */
684#define for_each_fw_domain_mask(domain__, mask__, dev_priv__, i__) \
685 for ((i__) = 0, (domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
686 (i__) < FW_DOMAIN_ID_COUNT; \
687 (i__)++, (domain__) = &(dev_priv__)->uncore.fw_domain[i__]) \
Jani Nikula95150bd2015-11-24 21:21:56 +0200688 for_each_if (((mask__) & (dev_priv__)->uncore.fw_domains) & (1 << (i__)))
Chris Wilsonb2cff0d2015-01-16 11:34:37 +0200689
690#define for_each_fw_domain(domain__, dev_priv__, i__) \
691 for_each_fw_domain_mask(domain__, FORCEWAKE_ALL, dev_priv__, i__)
692
Damien Lespiaub6e7d892015-10-27 14:46:59 +0200693#define CSR_VERSION(major, minor) ((major) << 16 | (minor))
694#define CSR_VERSION_MAJOR(version) ((version) >> 16)
695#define CSR_VERSION_MINOR(version) ((version) & 0xffff)
696
Daniel Vettereb805622015-05-04 14:58:44 +0200697struct intel_csr {
Daniel Vetter8144ac52015-10-28 23:59:04 +0200698 struct work_struct work;
Daniel Vettereb805622015-05-04 14:58:44 +0200699 const char *fw_path;
Animesh Mannaa7f749f2015-08-03 21:55:32 +0530700 uint32_t *dmc_payload;
Daniel Vettereb805622015-05-04 14:58:44 +0200701 uint32_t dmc_fw_size;
Damien Lespiaub6e7d892015-10-27 14:46:59 +0200702 uint32_t version;
Daniel Vettereb805622015-05-04 14:58:44 +0200703 uint32_t mmio_count;
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200704 i915_reg_t mmioaddr[8];
Daniel Vettereb805622015-05-04 14:58:44 +0200705 uint32_t mmiodata[8];
Patrik Jakobsson832dba82016-02-18 17:21:11 +0200706 uint32_t dc_state;
Imre Deaka37baf32016-02-29 22:49:03 +0200707 uint32_t allowed_dc_mask;
Daniel Vettereb805622015-05-04 14:58:44 +0200708};
709
Damien Lespiau79fc46d2013-04-23 16:37:17 +0100710#define DEV_INFO_FOR_EACH_FLAG(func, sep) \
711 func(is_mobile) sep \
712 func(is_i85x) sep \
713 func(is_i915g) sep \
714 func(is_i945gm) sep \
715 func(is_g33) sep \
716 func(need_gfx_hws) sep \
717 func(is_g4x) sep \
718 func(is_pineview) sep \
719 func(is_broadwater) sep \
720 func(is_crestline) sep \
721 func(is_ivybridge) sep \
722 func(is_valleyview) sep \
Wayne Boyer666a4532015-12-09 12:29:35 -0800723 func(is_cherryview) sep \
Damien Lespiau79fc46d2013-04-23 16:37:17 +0100724 func(is_haswell) sep \
Satheeshakrishna M7201c0b2014-04-02 11:24:50 +0530725 func(is_skylake) sep \
Rodrigo Vivi7526ac12015-10-27 10:14:54 -0700726 func(is_broxton) sep \
Rodrigo Vivief11bdb2015-10-28 04:16:45 -0700727 func(is_kabylake) sep \
Ben Widawskyb833d682013-08-23 16:00:07 -0700728 func(is_preliminary) sep \
Damien Lespiau79fc46d2013-04-23 16:37:17 +0100729 func(has_fbc) sep \
730 func(has_pipe_cxsr) sep \
731 func(has_hotplug) sep \
732 func(cursor_needs_physical) sep \
733 func(has_overlay) sep \
734 func(overlay_needs_physical) sep \
735 func(supports_tv) sep \
Damien Lespiaudd93be52013-04-22 18:40:39 +0100736 func(has_llc) sep \
Tvrtko Ursulinca377802016-03-02 12:10:31 +0000737 func(has_snoop) sep \
Damien Lespiau30568c42013-04-22 18:40:41 +0100738 func(has_ddi) sep \
739 func(has_fpga_dbg)
Daniel Vetterc96ea642012-08-08 22:01:51 +0200740
Damien Lespiaua587f772013-04-22 18:40:38 +0100741#define DEFINE_FLAG(name) u8 name:1
742#define SEP_SEMICOLON ;
Eugeni Dodonov3d29b842012-01-17 14:43:53 -0200743
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500744struct intel_device_info {
Ville Syrjälä10fce672013-01-24 15:29:28 +0200745 u32 display_mmio_offset;
Chris Wilson87f1f462014-08-09 19:18:42 +0100746 u16 device_id;
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700747 u8 num_pipes:3;
Damien Lespiaud615a162014-03-03 17:31:48 +0000748 u8 num_sprites[I915_MAX_PIPES];
=?utf-8?q?Michel_D=C3=A4nzer?=a6b54f32006-10-24 23:37:43 +1000749 u8 gen;
Ben Widawsky73ae4782013-10-15 10:02:57 -0700750 u8 ring_mask; /* Rings supported by the HW */
Damien Lespiaua587f772013-04-22 18:40:38 +0100751 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200752 /* Register offsets for the various display pipes and transcoders */
753 int pipe_offsets[I915_MAX_TRANSCODERS];
754 int trans_offsets[I915_MAX_TRANSCODERS];
Antti Koskipaaa57c7742014-02-04 14:22:24 +0200755 int palette_offsets[I915_MAX_PIPES];
Ville Syrjälä5efb3e22014-04-09 13:28:53 +0300756 int cursor_offsets[I915_MAX_PIPES];
Jeff McGee38732182015-02-13 10:27:54 -0600757
758 /* Slice/subslice/EU info */
759 u8 slice_total;
760 u8 subslice_total;
761 u8 subslice_per_slice;
762 u8 eu_total;
763 u8 eu_per_subslice;
Damien Lespiaub7668792015-02-14 18:30:29 +0000764 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
765 u8 subslice_7eu[3];
Jeff McGee38732182015-02-13 10:27:54 -0600766 u8 has_slice_pg:1;
767 u8 has_subslice_pg:1;
768 u8 has_eu_pg:1;
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500769};
770
Damien Lespiaua587f772013-04-22 18:40:38 +0100771#undef DEFINE_FLAG
772#undef SEP_SEMICOLON
773
Daniel Vetter7faf1ab2013-01-24 14:44:55 -0800774enum i915_cache_level {
775 I915_CACHE_NONE = 0,
Chris Wilson350ec882013-08-06 13:17:02 +0100776 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
777 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
778 caches, eg sampler/render caches, and the
779 large Last-Level-Cache. LLC is coherent with
780 the CPU, but L3 is only visible to the GPU. */
Chris Wilson651d7942013-08-08 14:41:10 +0100781 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
Daniel Vetter7faf1ab2013-01-24 14:44:55 -0800782};
783
Mika Kuoppalae59ec132013-06-12 12:35:28 +0300784struct i915_ctx_hang_stats {
785 /* This context had batch pending when hang was declared */
786 unsigned batch_pending;
787
788 /* This context had batch active when hang was declared */
789 unsigned batch_active;
Mika Kuoppalabe62acb2013-08-30 16:19:28 +0300790
791 /* Time when this context was last blamed for a GPU reset */
792 unsigned long guilty_ts;
793
Chris Wilson676fa572014-12-24 08:13:39 -0800794 /* If the contexts causes a second GPU hang within this time,
795 * it is permanently banned from submitting any more work.
796 */
797 unsigned long ban_period_seconds;
798
Mika Kuoppalabe62acb2013-08-30 16:19:28 +0300799 /* This context is banned to submit more work */
800 bool banned;
Mika Kuoppalae59ec132013-06-12 12:35:28 +0300801};
Ben Widawsky40521052012-06-04 14:42:43 -0700802
803/* This must match up with the value previously used for execbuf2.rsvd1. */
Oscar Mateo821d66d2014-07-03 16:28:00 +0100804#define DEFAULT_CONTEXT_HANDLE 0
David Weinehallb1b38272015-05-20 17:00:13 +0300805
806#define CONTEXT_NO_ZEROMAP (1<<0)
Oscar Mateo31b7a882014-07-03 16:28:01 +0100807/**
808 * struct intel_context - as the name implies, represents a context.
809 * @ref: reference count.
810 * @user_handle: userspace tracking identity for this context.
811 * @remap_slice: l3 row remapping information.
David Weinehallb1b38272015-05-20 17:00:13 +0300812 * @flags: context specific flags:
813 * CONTEXT_NO_ZEROMAP: do not allow mapping things to page 0.
Oscar Mateo31b7a882014-07-03 16:28:01 +0100814 * @file_priv: filp associated with this context (NULL for global default
815 * context).
816 * @hang_stats: information about the role of this context in possible GPU
817 * hangs.
Tvrtko Ursulin7df113e2015-04-17 12:49:07 +0100818 * @ppgtt: virtual memory space used by this context.
Oscar Mateo31b7a882014-07-03 16:28:01 +0100819 * @legacy_hw_ctx: render context backing object and whether it is correctly
820 * initialized (legacy ring submission mechanism only).
821 * @link: link in the global list of contexts.
822 *
823 * Contexts are memory images used by the hardware to store copies of their
824 * internal state.
825 */
Oscar Mateo273497e2014-05-22 14:13:37 +0100826struct intel_context {
Mika Kuoppaladce32712013-04-30 13:30:33 +0300827 struct kref ref;
Oscar Mateo821d66d2014-07-03 16:28:00 +0100828 int user_handle;
Ben Widawsky3ccfd192013-09-18 19:03:18 -0700829 uint8_t remap_slice;
Chris Wilson9ea4fee2015-05-05 09:17:29 +0100830 struct drm_i915_private *i915;
David Weinehallb1b38272015-05-20 17:00:13 +0300831 int flags;
Ben Widawsky40521052012-06-04 14:42:43 -0700832 struct drm_i915_file_private *file_priv;
Mika Kuoppalae59ec132013-06-12 12:35:28 +0300833 struct i915_ctx_hang_stats hang_stats;
Daniel Vetterae6c4802014-08-06 15:04:53 +0200834 struct i915_hw_ppgtt *ppgtt;
Ben Widawskya33afea2013-09-17 21:12:45 -0700835
Oscar Mateoc9e003a2014-07-24 17:04:13 +0100836 /* Legacy ring buffer submission */
Oscar Mateoea0c76f2014-07-03 16:27:59 +0100837 struct {
838 struct drm_i915_gem_object *rcs_state;
839 bool initialized;
840 } legacy_hw_ctx;
841
Oscar Mateoc9e003a2014-07-24 17:04:13 +0100842 /* Execlists */
843 struct {
844 struct drm_i915_gem_object *state;
Oscar Mateo84c23772014-07-24 17:04:15 +0100845 struct intel_ringbuffer *ringbuf;
Mika Kuoppalaa7cbede2015-01-13 11:32:25 +0200846 int pin_count;
Tvrtko Ursulinca82580c2016-01-15 15:10:27 +0000847 struct i915_vma *lrc_vma;
848 u64 lrc_desc;
Tvrtko Ursulin82352e92016-01-15 17:12:45 +0000849 uint32_t *lrc_reg_state;
Tvrtko Ursulin666796d2016-03-16 11:00:39 +0000850 } engine[I915_NUM_ENGINES];
Oscar Mateoc9e003a2014-07-24 17:04:13 +0100851
Ben Widawskya33afea2013-09-17 21:12:45 -0700852 struct list_head link;
Ben Widawsky40521052012-06-04 14:42:43 -0700853};
854
Paulo Zanonia4001f12015-02-13 17:23:44 -0200855enum fb_op_origin {
856 ORIGIN_GTT,
857 ORIGIN_CPU,
858 ORIGIN_CS,
859 ORIGIN_FLIP,
Paulo Zanoni74b4ea12015-07-14 16:29:14 -0300860 ORIGIN_DIRTYFB,
Paulo Zanonia4001f12015-02-13 17:23:44 -0200861};
862
Paulo Zanoniab34a7e2016-01-11 17:44:36 -0200863struct intel_fbc {
Paulo Zanoni25ad93f2015-07-02 19:25:10 -0300864 /* This is always the inner lock when overlapping with struct_mutex and
865 * it's the outer lock when overlapping with stolen_lock. */
866 struct mutex lock;
Ben Widawsky5e59f712014-06-30 10:41:24 -0700867 unsigned threshold;
Paulo Zanonidbef0f12015-02-13 17:23:46 -0200868 unsigned int possible_framebuffer_bits;
869 unsigned int busy_bits;
Paulo Zanoni010cf732016-01-19 11:35:48 -0200870 unsigned int visible_pipes_mask;
Paulo Zanonie35fef22015-02-09 14:46:29 -0200871 struct intel_crtc *crtc;
Ben Widawsky5c3fe8b2013-06-27 16:30:21 -0700872
Ben Widawskyc4213882014-06-19 12:06:10 -0700873 struct drm_mm_node compressed_fb;
Ben Widawsky5c3fe8b2013-06-27 16:30:21 -0700874 struct drm_mm_node *compressed_llb;
875
Rodrigo Vivida46f932014-08-01 02:04:45 -0700876 bool false_color;
877
Paulo Zanonid029bca2015-10-15 10:44:46 -0300878 bool enabled;
Paulo Zanoni0e631ad2015-10-14 17:45:36 -0300879 bool active;
Paulo Zanoni9adccc62014-09-19 16:04:55 -0300880
Paulo Zanoniaaf78d22016-01-19 11:35:42 -0200881 struct intel_fbc_state_cache {
882 struct {
883 unsigned int mode_flags;
884 uint32_t hsw_bdw_pixel_rate;
885 } crtc;
886
887 struct {
888 unsigned int rotation;
889 int src_w;
890 int src_h;
891 bool visible;
892 } plane;
893
894 struct {
895 u64 ilk_ggtt_offset;
Paulo Zanoniaaf78d22016-01-19 11:35:42 -0200896 uint32_t pixel_format;
897 unsigned int stride;
898 int fence_reg;
899 unsigned int tiling_mode;
900 } fb;
901 } state_cache;
902
Paulo Zanonib183b3f2015-12-23 18:28:11 -0200903 struct intel_fbc_reg_params {
904 struct {
905 enum pipe pipe;
906 enum plane plane;
907 unsigned int fence_y_offset;
908 } crtc;
909
910 struct {
911 u64 ggtt_offset;
Paulo Zanonib183b3f2015-12-23 18:28:11 -0200912 uint32_t pixel_format;
913 unsigned int stride;
914 int fence_reg;
915 } fb;
916
917 int cfb_size;
918 } params;
919
Ben Widawsky5c3fe8b2013-06-27 16:30:21 -0700920 struct intel_fbc_work {
Paulo Zanoni128d7352015-10-26 16:27:49 -0200921 bool scheduled;
Paulo Zanonica18d512016-01-21 18:03:05 -0200922 u32 scheduled_vblank;
Paulo Zanoni128d7352015-10-26 16:27:49 -0200923 struct work_struct work;
Paulo Zanoni128d7352015-10-26 16:27:49 -0200924 } work;
Ben Widawsky5c3fe8b2013-06-27 16:30:21 -0700925
Paulo Zanonibf6189c2015-10-27 14:50:03 -0200926 const char *no_fbc_reason;
Jesse Barnesb5e50c32010-02-05 12:42:41 -0800927};
928
Vandana Kannan96178ee2015-01-10 02:25:56 +0530929/**
930 * HIGH_RR is the highest eDP panel refresh rate read from EDID
931 * LOW_RR is the lowest eDP panel refresh rate found from EDID
932 * parsing for same resolution.
933 */
934enum drrs_refresh_rate_type {
935 DRRS_HIGH_RR,
936 DRRS_LOW_RR,
937 DRRS_MAX_RR, /* RR count */
938};
939
940enum drrs_support_type {
941 DRRS_NOT_SUPPORTED = 0,
942 STATIC_DRRS_SUPPORT = 1,
943 SEAMLESS_DRRS_SUPPORT = 2
Pradeep Bhat439d7ac2014-04-05 12:13:28 +0530944};
945
Daniel Vetter2807cf62014-07-11 10:30:11 -0700946struct intel_dp;
Vandana Kannan96178ee2015-01-10 02:25:56 +0530947struct i915_drrs {
948 struct mutex mutex;
949 struct delayed_work work;
950 struct intel_dp *dp;
951 unsigned busy_frontbuffer_bits;
952 enum drrs_refresh_rate_type refresh_rate_type;
953 enum drrs_support_type type;
954};
955
Rodrigo Vivia031d702013-10-03 16:15:06 -0300956struct i915_psr {
Daniel Vetterf0355c42014-07-11 10:30:15 -0700957 struct mutex lock;
Rodrigo Vivia031d702013-10-03 16:15:06 -0300958 bool sink_support;
959 bool source_ok;
Daniel Vetter2807cf62014-07-11 10:30:11 -0700960 struct intel_dp *enabled;
Rodrigo Vivi7c8f8a72014-06-13 05:10:03 -0700961 bool active;
962 struct delayed_work work;
Daniel Vetter9ca15302014-07-11 10:30:16 -0700963 unsigned busy_frontbuffer_bits;
Sonika Jindal474d1ec2015-04-02 11:02:44 +0530964 bool psr2_support;
965 bool aux_frame_sync;
Rodrigo Vivi60e5ffe2016-02-01 12:02:07 -0800966 bool link_standby;
Rodrigo Vivi3f51e472013-07-11 18:45:00 -0300967};
Ben Widawsky5c3fe8b2013-06-27 16:30:21 -0700968
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800969enum intel_pch {
Paulo Zanonif0350832012-07-03 18:48:16 -0300970 PCH_NONE = 0, /* No PCH present */
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800971 PCH_IBX, /* Ibexpeak PCH */
972 PCH_CPT, /* Cougarpoint PCH */
Eugeni Dodonoveb877eb2012-03-29 12:32:20 -0300973 PCH_LPT, /* Lynxpoint PCH */
Satheeshakrishna Me7e7ea22014-04-09 11:08:57 +0530974 PCH_SPT, /* Sunrisepoint PCH */
Ben Widawsky40c7ead2013-04-05 13:12:40 -0700975 PCH_NOP,
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800976};
977
Paulo Zanoni988d6ee2012-12-01 12:04:24 -0200978enum intel_sbi_destination {
979 SBI_ICLK,
980 SBI_MPHY,
981};
982
Jesse Barnesb690e962010-07-19 13:53:12 -0700983#define QUIRK_PIPEA_FORCE (1<<0)
Keith Packard435793d2011-07-12 14:56:22 -0700984#define QUIRK_LVDS_SSC_DISABLE (1<<1)
Carsten Emde4dca20e2012-03-15 15:56:26 +0100985#define QUIRK_INVERT_BRIGHTNESS (1<<2)
Scot Doyle9c72cc62014-07-03 23:27:50 +0000986#define QUIRK_BACKLIGHT_PRESENT (1<<3)
Ville Syrjäläb6b5d042014-08-15 01:22:07 +0300987#define QUIRK_PIPEB_FORCE (1<<4)
Daniel Vetter656bfa32014-11-20 09:26:30 +0100988#define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
Jesse Barnesb690e962010-07-19 13:53:12 -0700989
Dave Airlie8be48d92010-03-30 05:34:14 +0000990struct intel_fbdev;
Chris Wilson1630fe72011-07-08 12:22:42 +0100991struct intel_fbc_work;
Dave Airlie38651672010-03-30 05:34:13 +0000992
Daniel Vetterc2b91522012-02-14 22:37:19 +0100993struct intel_gmbus {
994 struct i2c_adapter adapter;
Chris Wilsonf2ce9fa2012-11-10 15:58:21 +0000995 u32 force_bit;
Daniel Vetterc2b91522012-02-14 22:37:19 +0100996 u32 reg0;
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200997 i915_reg_t gpio_reg;
Daniel Vetterc167a6f2012-02-28 00:43:09 +0100998 struct i2c_algo_bit_data bit_algo;
Daniel Vetterc2b91522012-02-14 22:37:19 +0100999 struct drm_i915_private *dev_priv;
1000};
1001
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001002struct i915_suspend_saved_registers {
Keith Packarde948e992008-05-07 12:27:53 +10001003 u32 saveDSPARB;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +10001004 u32 saveLVDS;
Jesse Barnes585fb112008-07-29 11:54:06 -07001005 u32 savePP_ON_DELAYS;
1006 u32 savePP_OFF_DELAYS;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +10001007 u32 savePP_ON;
1008 u32 savePP_OFF;
1009 u32 savePP_CONTROL;
Jesse Barnes585fb112008-07-29 11:54:06 -07001010 u32 savePP_DIVISOR;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +10001011 u32 saveFBC_CONTROL;
Keith Packard1f84e552008-02-16 19:19:29 -08001012 u32 saveCACHE_MODE_0;
Keith Packard1f84e552008-02-16 19:19:29 -08001013 u32 saveMI_ARB_STATE;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +10001014 u32 saveSWF0[16];
1015 u32 saveSWF1[16];
Ville Syrjälä85fa7922015-09-18 20:03:43 +03001016 u32 saveSWF3[3];
Daniel Vetter4b9de732011-10-09 21:52:02 +02001017 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
Adam Jacksoncda2bb72011-07-26 16:53:06 -04001018 u32 savePCH_PORT_HOTPLUG;
Jesse Barnes9f49c372014-12-10 12:16:05 -08001019 u16 saveGCDGMBUS;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001020};
Daniel Vetterc85aa882012-11-02 19:55:03 +01001021
Imre Deakddeea5b2014-05-05 15:19:56 +03001022struct vlv_s0ix_state {
1023 /* GAM */
1024 u32 wr_watermark;
1025 u32 gfx_prio_ctrl;
1026 u32 arb_mode;
1027 u32 gfx_pend_tlb0;
1028 u32 gfx_pend_tlb1;
1029 u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
1030 u32 media_max_req_count;
1031 u32 gfx_max_req_count;
1032 u32 render_hwsp;
1033 u32 ecochk;
1034 u32 bsd_hwsp;
1035 u32 blt_hwsp;
1036 u32 tlb_rd_addr;
1037
1038 /* MBC */
1039 u32 g3dctl;
1040 u32 gsckgctl;
1041 u32 mbctl;
1042
1043 /* GCP */
1044 u32 ucgctl1;
1045 u32 ucgctl3;
1046 u32 rcgctl1;
1047 u32 rcgctl2;
1048 u32 rstctl;
1049 u32 misccpctl;
1050
1051 /* GPM */
1052 u32 gfxpause;
1053 u32 rpdeuhwtc;
1054 u32 rpdeuc;
1055 u32 ecobus;
1056 u32 pwrdwnupctl;
1057 u32 rp_down_timeout;
1058 u32 rp_deucsw;
1059 u32 rcubmabdtmr;
1060 u32 rcedata;
1061 u32 spare2gh;
1062
1063 /* Display 1 CZ domain */
1064 u32 gt_imr;
1065 u32 gt_ier;
1066 u32 pm_imr;
1067 u32 pm_ier;
1068 u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
1069
1070 /* GT SA CZ domain */
1071 u32 tilectl;
1072 u32 gt_fifoctl;
1073 u32 gtlc_wake_ctrl;
1074 u32 gtlc_survive;
1075 u32 pmwgicz;
1076
1077 /* Display 2 CZ domain */
1078 u32 gu_ctl0;
1079 u32 gu_ctl1;
Jesse Barnes9c252102015-04-01 14:22:57 -07001080 u32 pcbr;
Imre Deakddeea5b2014-05-05 15:19:56 +03001081 u32 clock_gate_dis2;
1082};
1083
Chris Wilsonbf225f22014-07-10 20:31:18 +01001084struct intel_rps_ei {
1085 u32 cz_clock;
1086 u32 render_c0;
1087 u32 media_c0;
Deepak S31685c22014-07-03 17:33:01 -04001088};
1089
Daniel Vetterc85aa882012-11-02 19:55:03 +01001090struct intel_gen6_power_mgmt {
Imre Deakd4d70aa2014-11-19 15:30:04 +02001091 /*
1092 * work, interrupts_enabled and pm_iir are protected by
1093 * dev_priv->irq_lock
1094 */
Daniel Vetterc85aa882012-11-02 19:55:03 +01001095 struct work_struct work;
Imre Deakd4d70aa2014-11-19 15:30:04 +02001096 bool interrupts_enabled;
Daniel Vetterc85aa882012-11-02 19:55:03 +01001097 u32 pm_iir;
Daniel Vetter59cdb632013-07-04 23:35:28 +02001098
Ben Widawskyb39fb292014-03-19 18:31:11 -07001099 /* Frequencies are stored in potentially platform dependent multiples.
1100 * In other words, *_freq needs to be multiplied by X to be interesting.
1101 * Soft limits are those which are used for the dynamic reclocking done
1102 * by the driver (raise frequencies under heavy loads, and lower for
1103 * lighter loads). Hard limits are those imposed by the hardware.
1104 *
1105 * A distinction is made for overclocking, which is never enabled by
1106 * default, and is considered to be above the hard limit if it's
1107 * possible at all.
1108 */
1109 u8 cur_freq; /* Current frequency (cached, may not == HW) */
1110 u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */
1111 u8 max_freq_softlimit; /* Max frequency permitted by the driver */
1112 u8 max_freq; /* Maximum frequency, RP0 if not overclocking */
1113 u8 min_freq; /* AKA RPn. Minimum frequency */
Chris Wilsonaed242f2015-03-18 09:48:21 +00001114 u8 idle_freq; /* Frequency to request when we are idle */
Ben Widawskyb39fb292014-03-19 18:31:11 -07001115 u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */
1116 u8 rp1_freq; /* "less than" RP0 power/freqency */
1117 u8 rp0_freq; /* Non-overclocked max frequency. */
Jesse Barnes1a01ab32012-11-02 11:14:00 -07001118
Chris Wilson8fb55192015-04-07 16:20:28 +01001119 u8 up_threshold; /* Current %busy required to uplock */
1120 u8 down_threshold; /* Current %busy required to downclock */
1121
Chris Wilsondd75fdc2013-09-25 17:34:57 +01001122 int last_adj;
1123 enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
1124
Chris Wilson8d3afd72015-05-21 21:01:47 +01001125 spinlock_t client_lock;
1126 struct list_head clients;
1127 bool client_boost;
1128
Chris Wilsonc0951f02013-10-10 21:58:50 +01001129 bool enabled;
Jesse Barnes1a01ab32012-11-02 11:14:00 -07001130 struct delayed_work delayed_resume_work;
Chris Wilson1854d5c2015-04-07 16:20:32 +01001131 unsigned boosts;
Jesse Barnes4fc688c2012-11-02 11:14:01 -07001132
Chris Wilson2e1b8732015-04-27 13:41:22 +01001133 struct intel_rps_client semaphores, mmioflips;
Chris Wilsona6f766f2015-04-27 13:41:20 +01001134
Chris Wilsonbf225f22014-07-10 20:31:18 +01001135 /* manual wa residency calculations */
1136 struct intel_rps_ei up_ei, down_ei;
1137
Jesse Barnes4fc688c2012-11-02 11:14:01 -07001138 /*
1139 * Protects RPS/RC6 register access and PCU communication.
Chris Wilson8d3afd72015-05-21 21:01:47 +01001140 * Must be taken after struct_mutex if nested. Note that
1141 * this lock may be held for long periods of time when
1142 * talking to hw - so only take it when talking to hw!
Jesse Barnes4fc688c2012-11-02 11:14:01 -07001143 */
1144 struct mutex hw_lock;
Daniel Vetterc85aa882012-11-02 19:55:03 +01001145};
1146
Daniel Vetter1a240d42012-11-29 22:18:51 +01001147/* defined intel_pm.c */
1148extern spinlock_t mchdev_lock;
1149
Daniel Vetterc85aa882012-11-02 19:55:03 +01001150struct intel_ilk_power_mgmt {
1151 u8 cur_delay;
1152 u8 min_delay;
1153 u8 max_delay;
1154 u8 fmax;
1155 u8 fstart;
1156
1157 u64 last_count1;
1158 unsigned long last_time1;
1159 unsigned long chipset_power;
1160 u64 last_count2;
Thomas Gleixner5ed0bdf2014-07-16 21:05:06 +00001161 u64 last_time2;
Daniel Vetterc85aa882012-11-02 19:55:03 +01001162 unsigned long gfx_power;
1163 u8 corr;
1164
1165 int c_m;
1166 int r_t;
1167};
1168
Imre Deakc6cb5822014-03-04 19:22:55 +02001169struct drm_i915_private;
1170struct i915_power_well;
1171
1172struct i915_power_well_ops {
1173 /*
1174 * Synchronize the well's hw state to match the current sw state, for
1175 * example enable/disable it based on the current refcount. Called
1176 * during driver init and resume time, possibly after first calling
1177 * the enable/disable handlers.
1178 */
1179 void (*sync_hw)(struct drm_i915_private *dev_priv,
1180 struct i915_power_well *power_well);
1181 /*
1182 * Enable the well and resources that depend on it (for example
1183 * interrupts located on the well). Called after the 0->1 refcount
1184 * transition.
1185 */
1186 void (*enable)(struct drm_i915_private *dev_priv,
1187 struct i915_power_well *power_well);
1188 /*
1189 * Disable the well and resources that depend on it. Called after
1190 * the 1->0 refcount transition.
1191 */
1192 void (*disable)(struct drm_i915_private *dev_priv,
1193 struct i915_power_well *power_well);
1194 /* Returns the hw enabled state. */
1195 bool (*is_enabled)(struct drm_i915_private *dev_priv,
1196 struct i915_power_well *power_well);
1197};
1198
Wang Xingchaoa38911a2013-05-30 22:07:11 +08001199/* Power well structure for haswell */
1200struct i915_power_well {
Imre Deakc1ca7272013-11-25 17:15:29 +02001201 const char *name;
Imre Deak6f3ef5d2013-11-25 17:15:30 +02001202 bool always_on;
Wang Xingchaoa38911a2013-05-30 22:07:11 +08001203 /* power well enable/disable usage count */
1204 int count;
Imre Deakbfafe932014-06-05 20:31:47 +03001205 /* cached hw enabled state */
1206 bool hw_enabled;
Imre Deakc1ca7272013-11-25 17:15:29 +02001207 unsigned long domains;
Imre Deak77961eb2014-03-05 16:20:56 +02001208 unsigned long data;
Imre Deakc6cb5822014-03-04 19:22:55 +02001209 const struct i915_power_well_ops *ops;
Wang Xingchaoa38911a2013-05-30 22:07:11 +08001210};
1211
Imre Deak83c00f552013-10-25 17:36:47 +03001212struct i915_power_domains {
Imre Deakbaa70702013-10-25 17:36:48 +03001213 /*
1214 * Power wells needed for initialization at driver init and suspend
1215 * time are on. They are kept on until after the first modeset.
1216 */
1217 bool init_power_on;
Imre Deak0d116a22014-04-25 13:19:05 +03001218 bool initializing;
Imre Deakc1ca7272013-11-25 17:15:29 +02001219 int power_well_count;
Imre Deakbaa70702013-10-25 17:36:48 +03001220
Imre Deak83c00f552013-10-25 17:36:47 +03001221 struct mutex lock;
Imre Deak1da51582013-11-25 17:15:35 +02001222 int domain_use_count[POWER_DOMAIN_NUM];
Imre Deakc1ca7272013-11-25 17:15:29 +02001223 struct i915_power_well *power_wells;
Imre Deak83c00f552013-10-25 17:36:47 +03001224};
1225
Ben Widawsky35a85ac2013-09-19 11:13:41 -07001226#define MAX_L3_SLICES 2
Daniel Vettera4da4fa2012-11-02 19:55:07 +01001227struct intel_l3_parity {
Ben Widawsky35a85ac2013-09-19 11:13:41 -07001228 u32 *remap_info[MAX_L3_SLICES];
Daniel Vettera4da4fa2012-11-02 19:55:07 +01001229 struct work_struct error_work;
Ben Widawsky35a85ac2013-09-19 11:13:41 -07001230 int which_slice;
Daniel Vettera4da4fa2012-11-02 19:55:07 +01001231};
1232
Daniel Vetter4b5aed62012-11-14 17:14:03 +01001233struct i915_gem_mm {
Daniel Vetter4b5aed62012-11-14 17:14:03 +01001234 /** Memory allocator for GTT stolen memory */
1235 struct drm_mm stolen;
Paulo Zanoni92e97d22015-07-02 19:25:09 -03001236 /** Protects the usage of the GTT stolen memory allocator. This is
1237 * always the inner lock when overlapping with struct_mutex. */
1238 struct mutex stolen_lock;
1239
Daniel Vetter4b5aed62012-11-14 17:14:03 +01001240 /** List of all objects in gtt_space. Used to restore gtt
1241 * mappings on resume */
1242 struct list_head bound_list;
1243 /**
1244 * List of objects which are not bound to the GTT (thus
1245 * are idle and not used by the GPU) but still have
1246 * (presumably uncached) pages still attached.
1247 */
1248 struct list_head unbound_list;
1249
1250 /** Usable portion of the GTT for GEM */
1251 unsigned long stolen_base; /* limited to low memory (32-bit) */
1252
Daniel Vetter4b5aed62012-11-14 17:14:03 +01001253 /** PPGTT used for aliasing the PPGTT with the GTT */
1254 struct i915_hw_ppgtt *aliasing_ppgtt;
1255
Chris Wilson2cfcd322014-05-20 08:28:43 +01001256 struct notifier_block oom_notifier;
Chris Wilsonceabbba52014-03-25 13:23:04 +00001257 struct shrinker shrinker;
Daniel Vetter4b5aed62012-11-14 17:14:03 +01001258 bool shrinker_no_lock_stealing;
1259
Daniel Vetter4b5aed62012-11-14 17:14:03 +01001260 /** LRU list of objects with fence regs on them. */
1261 struct list_head fence_list;
1262
1263 /**
1264 * We leave the user IRQ off as much as possible,
1265 * but this means that requests will finish and never
1266 * be retired once the system goes idle. Set a timer to
1267 * fire periodically while the ring is running. When it
1268 * fires, go retire requests.
1269 */
1270 struct delayed_work retire_work;
1271
1272 /**
Chris Wilsonb29c19b2013-09-25 17:34:56 +01001273 * When we detect an idle GPU, we want to turn on
1274 * powersaving features. So once we see that there
1275 * are no more requests outstanding and no more
1276 * arrive within a small period of time, we fire
1277 * off the idle_work.
1278 */
1279 struct delayed_work idle_work;
1280
1281 /**
Daniel Vetter4b5aed62012-11-14 17:14:03 +01001282 * Are we in a non-interruptible section of code like
1283 * modesetting?
1284 */
1285 bool interruptible;
1286
Chris Wilsonf62a0072014-02-21 17:55:39 +00001287 /**
1288 * Is the GPU currently considered idle, or busy executing userspace
1289 * requests? Whilst idle, we attempt to power down the hardware and
1290 * display clocks. In order to reduce the effect on performance, there
1291 * is a slight delay before we do so.
1292 */
1293 bool busy;
1294
Daniel Vetterbdf1e7e2014-05-21 17:37:52 +02001295 /* the indicator for dispatch video commands on two BSD rings */
Tvrtko Ursulinde1add32016-01-15 15:12:50 +00001296 unsigned int bsd_ring_dispatch_index;
Daniel Vetterbdf1e7e2014-05-21 17:37:52 +02001297
Daniel Vetter4b5aed62012-11-14 17:14:03 +01001298 /** Bit 6 swizzling required for X tiling */
1299 uint32_t bit_6_swizzle_x;
1300 /** Bit 6 swizzling required for Y tiling */
1301 uint32_t bit_6_swizzle_y;
1302
Daniel Vetter4b5aed62012-11-14 17:14:03 +01001303 /* accounting, useful for userland debugging */
Daniel Vetterc20e8352013-07-24 22:40:23 +02001304 spinlock_t object_stat_lock;
Daniel Vetter4b5aed62012-11-14 17:14:03 +01001305 size_t object_memory;
1306 u32 object_count;
1307};
1308
Mika Kuoppalaedc3d882013-05-23 13:55:35 +03001309struct drm_i915_error_state_buf {
Chris Wilson0a4cd7c2014-08-22 14:41:39 +01001310 struct drm_i915_private *i915;
Mika Kuoppalaedc3d882013-05-23 13:55:35 +03001311 unsigned bytes;
1312 unsigned size;
1313 int err;
1314 u8 *buf;
1315 loff_t start;
1316 loff_t pos;
1317};
1318
Mika Kuoppalafc16b482013-06-06 15:18:39 +03001319struct i915_error_state_file_priv {
1320 struct drm_device *dev;
1321 struct drm_i915_error_state *error;
1322};
1323
Daniel Vetter99584db2012-11-14 17:14:04 +01001324struct i915_gpu_error {
1325 /* For hangcheck timer */
1326#define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1327#define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
Mika Kuoppalabe62acb2013-08-30 16:19:28 +03001328 /* Hang gpu twice in this window and your context gets banned */
1329#define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1330
Chris Wilson737b1502015-01-26 18:03:03 +02001331 struct workqueue_struct *hangcheck_wq;
1332 struct delayed_work hangcheck_work;
Daniel Vetter99584db2012-11-14 17:14:04 +01001333
1334 /* For reset and error_state handling. */
1335 spinlock_t lock;
1336 /* Protected by the above dev->gpu_error.lock. */
1337 struct drm_i915_error_state *first_error;
Chris Wilson094f9a52013-09-25 17:34:55 +01001338
1339 unsigned long missed_irq_rings;
1340
Daniel Vetter1f83fee2012-11-15 17:17:22 +01001341 /**
Mika Kuoppala2ac0f452013-11-12 14:44:19 +02001342 * State variable controlling the reset flow and count
Daniel Vetter1f83fee2012-11-15 17:17:22 +01001343 *
Mika Kuoppala2ac0f452013-11-12 14:44:19 +02001344 * This is a counter which gets incremented when reset is triggered,
1345 * and again when reset has been handled. So odd values (lowest bit set)
1346 * means that reset is in progress and even values that
1347 * (reset_counter >> 1):th reset was successfully completed.
1348 *
1349 * If reset is not completed succesfully, the I915_WEDGE bit is
1350 * set meaning that hardware is terminally sour and there is no
1351 * recovery. All waiters on the reset_queue will be woken when
1352 * that happens.
1353 *
1354 * This counter is used by the wait_seqno code to notice that reset
1355 * event happened and it needs to restart the entire ioctl (since most
1356 * likely the seqno it waited for won't ever signal anytime soon).
Daniel Vetterf69061b2012-12-06 09:01:42 +01001357 *
1358 * This is important for lock-free wait paths, where no contended lock
1359 * naturally enforces the correct ordering between the bail-out of the
1360 * waiter and the gpu reset work code.
Daniel Vetter1f83fee2012-11-15 17:17:22 +01001361 */
1362 atomic_t reset_counter;
1363
Daniel Vetter1f83fee2012-11-15 17:17:22 +01001364#define I915_RESET_IN_PROGRESS_FLAG 1
Mika Kuoppala2ac0f452013-11-12 14:44:19 +02001365#define I915_WEDGED (1 << 31)
Daniel Vetter1f83fee2012-11-15 17:17:22 +01001366
1367 /**
1368 * Waitqueue to signal when the reset has completed. Used by clients
1369 * that wait for dev_priv->mm.wedged to settle.
1370 */
1371 wait_queue_head_t reset_queue;
Daniel Vetter33196de2012-11-14 17:14:05 +01001372
Mika Kuoppala88b4aa82014-03-28 18:18:18 +02001373 /* Userspace knobs for gpu hang simulation;
1374 * combines both a ring mask, and extra flags
1375 */
1376 u32 stop_rings;
1377#define I915_STOP_RING_ALLOW_BAN (1 << 31)
1378#define I915_STOP_RING_ALLOW_WARN (1 << 30)
Chris Wilson094f9a52013-09-25 17:34:55 +01001379
1380 /* For missed irq/seqno simulation. */
1381 unsigned int test_irq_rings;
McAulay, Alistair6689c162014-08-15 18:51:35 +01001382
1383 /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
1384 bool reload_in_reset;
Daniel Vetter99584db2012-11-14 17:14:04 +01001385};
1386
Zhang Ruib8efb172013-02-05 15:41:53 +08001387enum modeset_restore {
1388 MODESET_ON_LID_OPEN,
1389 MODESET_DONE,
1390 MODESET_SUSPENDED,
1391};
1392
Rodrigo Vivi500ea702015-08-07 17:01:16 -07001393#define DP_AUX_A 0x40
1394#define DP_AUX_B 0x10
1395#define DP_AUX_C 0x20
1396#define DP_AUX_D 0x30
1397
Xiong Zhang11c1b652015-08-17 16:04:04 +08001398#define DDC_PIN_B 0x05
1399#define DDC_PIN_C 0x04
1400#define DDC_PIN_D 0x06
1401
Paulo Zanoni6acab152013-09-12 17:06:24 -03001402struct ddi_vbt_port_info {
Damien Lespiauce4dd492014-08-01 11:07:54 +01001403 /*
1404 * This is an index in the HDMI/DVI DDI buffer translation table.
1405 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1406 * populate this field.
1407 */
1408#define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
Paulo Zanoni6acab152013-09-12 17:06:24 -03001409 uint8_t hdmi_level_shift;
Paulo Zanoni311a2092013-09-12 17:12:18 -03001410
1411 uint8_t supports_dvi:1;
1412 uint8_t supports_hdmi:1;
1413 uint8_t supports_dp:1;
Rodrigo Vivi500ea702015-08-07 17:01:16 -07001414
1415 uint8_t alternate_aux_channel;
Xiong Zhang11c1b652015-08-17 16:04:04 +08001416 uint8_t alternate_ddc_pin;
Antti Koskipaa75067dd2015-07-10 14:10:55 +03001417
1418 uint8_t dp_boost_level;
1419 uint8_t hdmi_boost_level;
Paulo Zanoni6acab152013-09-12 17:06:24 -03001420};
1421
Rodrigo Vivibfd7ebd2014-11-14 08:52:30 -08001422enum psr_lines_to_wait {
1423 PSR_0_LINES_TO_WAIT = 0,
1424 PSR_1_LINE_TO_WAIT,
1425 PSR_4_LINES_TO_WAIT,
1426 PSR_8_LINES_TO_WAIT
Pradeep Bhat83a72802014-03-28 10:14:57 +05301427};
1428
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03001429struct intel_vbt_data {
1430 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1431 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1432
1433 /* Feature bits */
1434 unsigned int int_tv_support:1;
1435 unsigned int lvds_dither:1;
1436 unsigned int lvds_vbt:1;
1437 unsigned int int_crt_support:1;
1438 unsigned int lvds_use_ssc:1;
1439 unsigned int display_clock_mode:1;
1440 unsigned int fdi_rx_polarity_inverted:1;
1441 int lvds_ssc_freq;
1442 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1443
Pradeep Bhat83a72802014-03-28 10:14:57 +05301444 enum drrs_support_type drrs_type;
1445
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03001446 /* eDP */
1447 int edp_rate;
1448 int edp_lanes;
1449 int edp_preemphasis;
1450 int edp_vswing;
1451 bool edp_initialized;
1452 bool edp_support;
1453 int edp_bpp;
1454 struct edp_power_seq edp_pps;
1455
Jani Nikulaf00076d2013-12-14 20:38:29 -02001456 struct {
Rodrigo Vivibfd7ebd2014-11-14 08:52:30 -08001457 bool full_link;
1458 bool require_aux_wakeup;
1459 int idle_frames;
1460 enum psr_lines_to_wait lines_to_wait;
1461 int tp1_wakeup_time;
1462 int tp2_tp3_wakeup_time;
1463 } psr;
1464
1465 struct {
Jani Nikulaf00076d2013-12-14 20:38:29 -02001466 u16 pwm_freq_hz;
Jani Nikula39fbc9c2014-04-09 11:22:06 +03001467 bool present;
Jani Nikulaf00076d2013-12-14 20:38:29 -02001468 bool active_low_pwm;
Jani Nikula1de60682014-06-24 18:27:39 +03001469 u8 min_brightness; /* min_brightness/255 of max */
Jani Nikulaf00076d2013-12-14 20:38:29 -02001470 } backlight;
1471
Shobhit Kumard17c5442013-08-27 15:12:25 +03001472 /* MIPI DSI */
1473 struct {
1474 u16 panel_id;
Shobhit Kumard3b542f2014-04-14 11:00:34 +05301475 struct mipi_config *config;
1476 struct mipi_pps_data *pps;
1477 u8 seq_version;
1478 u32 size;
1479 u8 *data;
Jani Nikula8d3ed2f2015-12-21 15:10:57 +02001480 const u8 *sequence[MIPI_SEQ_MAX];
Shobhit Kumard17c5442013-08-27 15:12:25 +03001481 } dsi;
1482
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03001483 int crt_ddc_pin;
1484
1485 int child_dev_num;
Paulo Zanoni768f69c2013-09-11 18:02:47 -03001486 union child_device_config *child_dev;
Paulo Zanoni6acab152013-09-12 17:06:24 -03001487
1488 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03001489};
1490
Ville Syrjälä77c122b2013-08-06 22:24:04 +03001491enum intel_ddb_partitioning {
1492 INTEL_DDB_PART_1_2,
1493 INTEL_DDB_PART_5_6, /* IVB+ */
1494};
1495
Ville Syrjälä1fd527c2013-08-06 22:24:05 +03001496struct intel_wm_level {
1497 bool enable;
1498 uint32_t pri_val;
1499 uint32_t spr_val;
1500 uint32_t cur_val;
1501 uint32_t fbc_val;
1502};
1503
Imre Deak820c1982013-12-17 14:46:36 +02001504struct ilk_wm_values {
Ville Syrjälä609cede2013-10-09 19:18:03 +03001505 uint32_t wm_pipe[3];
1506 uint32_t wm_lp[3];
1507 uint32_t wm_lp_spr[3];
1508 uint32_t wm_linetime[3];
1509 bool enable_fbc_wm;
1510 enum intel_ddb_partitioning partitioning;
1511};
1512
Ville Syrjälä262cd2e2015-06-24 22:00:04 +03001513struct vlv_pipe_wm {
1514 uint16_t primary;
1515 uint16_t sprite[2];
1516 uint8_t cursor;
1517};
1518
1519struct vlv_sr_wm {
1520 uint16_t plane;
1521 uint8_t cursor;
1522};
1523
Ville Syrjälä0018fda2015-03-05 21:19:45 +02001524struct vlv_wm_values {
Ville Syrjälä262cd2e2015-06-24 22:00:04 +03001525 struct vlv_pipe_wm pipe[3];
1526 struct vlv_sr_wm sr;
Ville Syrjäläae801522015-03-05 21:19:49 +02001527 struct {
Ville Syrjälä0018fda2015-03-05 21:19:45 +02001528 uint8_t cursor;
1529 uint8_t sprite[2];
1530 uint8_t primary;
1531 } ddl[3];
Ville Syrjälä6eb1a682015-06-24 22:00:03 +03001532 uint8_t level;
1533 bool cxsr;
Ville Syrjälä0018fda2015-03-05 21:19:45 +02001534};
1535
Damien Lespiauc1939242014-11-04 17:06:41 +00001536struct skl_ddb_entry {
Damien Lespiau16160e32014-11-04 17:06:53 +00001537 uint16_t start, end; /* in number of blocks, 'end' is exclusive */
Damien Lespiauc1939242014-11-04 17:06:41 +00001538};
1539
1540static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
1541{
Damien Lespiau16160e32014-11-04 17:06:53 +00001542 return entry->end - entry->start;
Damien Lespiauc1939242014-11-04 17:06:41 +00001543}
1544
Damien Lespiau08db6652014-11-04 17:06:52 +00001545static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
1546 const struct skl_ddb_entry *e2)
1547{
1548 if (e1->start == e2->start && e1->end == e2->end)
1549 return true;
1550
1551 return false;
1552}
1553
Damien Lespiauc1939242014-11-04 17:06:41 +00001554struct skl_ddb_allocation {
Damien Lespiau34bb56a2014-11-04 17:07:01 +00001555 struct skl_ddb_entry pipe[I915_MAX_PIPES];
Chandra Konduru2cd601c2015-04-27 15:47:37 -07001556 struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */
Matt Roper4969d332015-09-24 15:53:10 -07001557 struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
Damien Lespiauc1939242014-11-04 17:06:41 +00001558};
1559
Pradeep Bhat2ac96d22014-11-04 17:06:40 +00001560struct skl_wm_values {
1561 bool dirty[I915_MAX_PIPES];
Damien Lespiauc1939242014-11-04 17:06:41 +00001562 struct skl_ddb_allocation ddb;
Pradeep Bhat2ac96d22014-11-04 17:06:40 +00001563 uint32_t wm_linetime[I915_MAX_PIPES];
1564 uint32_t plane[I915_MAX_PIPES][I915_MAX_PLANES][8];
Pradeep Bhat2ac96d22014-11-04 17:06:40 +00001565 uint32_t plane_trans[I915_MAX_PIPES][I915_MAX_PLANES];
Pradeep Bhat2ac96d22014-11-04 17:06:40 +00001566};
1567
1568struct skl_wm_level {
1569 bool plane_en[I915_MAX_PLANES];
1570 uint16_t plane_res_b[I915_MAX_PLANES];
1571 uint8_t plane_res_l[I915_MAX_PLANES];
Pradeep Bhat2ac96d22014-11-04 17:06:40 +00001572};
1573
Paulo Zanonic67a4702013-08-19 13:18:09 -03001574/*
Paulo Zanoni765dab62014-03-07 20:08:18 -03001575 * This struct helps tracking the state needed for runtime PM, which puts the
1576 * device in PCI D3 state. Notice that when this happens, nothing on the
1577 * graphics device works, even register access, so we don't get interrupts nor
1578 * anything else.
Paulo Zanonic67a4702013-08-19 13:18:09 -03001579 *
Paulo Zanoni765dab62014-03-07 20:08:18 -03001580 * Every piece of our code that needs to actually touch the hardware needs to
1581 * either call intel_runtime_pm_get or call intel_display_power_get with the
1582 * appropriate power domain.
Paulo Zanonia8a8bd52014-03-07 20:08:05 -03001583 *
Paulo Zanoni765dab62014-03-07 20:08:18 -03001584 * Our driver uses the autosuspend delay feature, which means we'll only really
1585 * suspend if we stay with zero refcount for a certain amount of time. The
Daniel Vetterf458ebb2014-09-30 10:56:39 +02001586 * default value is currently very conservative (see intel_runtime_pm_enable), but
Paulo Zanoni765dab62014-03-07 20:08:18 -03001587 * it can be changed with the standard runtime PM files from sysfs.
Paulo Zanonic67a4702013-08-19 13:18:09 -03001588 *
1589 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1590 * goes back to false exactly before we reenable the IRQs. We use this variable
1591 * to check if someone is trying to enable/disable IRQs while they're supposed
1592 * to be disabled. This shouldn't happen and we'll print some error messages in
Paulo Zanoni730488b2014-03-07 20:12:32 -03001593 * case it happens.
Paulo Zanonic67a4702013-08-19 13:18:09 -03001594 *
Paulo Zanoni765dab62014-03-07 20:08:18 -03001595 * For more, read the Documentation/power/runtime_pm.txt.
Paulo Zanonic67a4702013-08-19 13:18:09 -03001596 */
Paulo Zanoni5d584b22014-03-07 20:08:15 -03001597struct i915_runtime_pm {
Imre Deak1f814da2015-12-16 02:52:19 +02001598 atomic_t wakeref_count;
Imre Deak2b19efe2015-12-15 20:10:37 +02001599 atomic_t atomic_seq;
Paulo Zanoni5d584b22014-03-07 20:08:15 -03001600 bool suspended;
Daniel Vetter2aeb7d32014-09-30 10:56:43 +02001601 bool irqs_enabled;
Paulo Zanonic67a4702013-08-19 13:18:09 -03001602};
1603
Daniel Vetter926321d2013-10-16 13:30:34 +02001604enum intel_pipe_crc_source {
1605 INTEL_PIPE_CRC_SOURCE_NONE,
1606 INTEL_PIPE_CRC_SOURCE_PLANE1,
1607 INTEL_PIPE_CRC_SOURCE_PLANE2,
1608 INTEL_PIPE_CRC_SOURCE_PF,
Daniel Vetter5b3a8562013-10-16 22:55:48 +02001609 INTEL_PIPE_CRC_SOURCE_PIPE,
Daniel Vetter3d099a02013-10-16 22:55:58 +02001610 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1611 INTEL_PIPE_CRC_SOURCE_TV,
1612 INTEL_PIPE_CRC_SOURCE_DP_B,
1613 INTEL_PIPE_CRC_SOURCE_DP_C,
1614 INTEL_PIPE_CRC_SOURCE_DP_D,
Daniel Vetter46a19182013-11-01 10:50:20 +01001615 INTEL_PIPE_CRC_SOURCE_AUTO,
Daniel Vetter926321d2013-10-16 13:30:34 +02001616 INTEL_PIPE_CRC_SOURCE_MAX,
1617};
1618
Shuang He8bf1e9f2013-10-15 18:55:27 +01001619struct intel_pipe_crc_entry {
Damien Lespiauac2300d2013-10-15 18:55:30 +01001620 uint32_t frame;
Shuang He8bf1e9f2013-10-15 18:55:27 +01001621 uint32_t crc[5];
1622};
1623
Damien Lespiaub2c88f52013-10-15 18:55:29 +01001624#define INTEL_PIPE_CRC_ENTRIES_NR 128
Shuang He8bf1e9f2013-10-15 18:55:27 +01001625struct intel_pipe_crc {
Damien Lespiaud538bbd2013-10-21 14:29:30 +01001626 spinlock_t lock;
1627 bool opened; /* exclusive access to the result file */
Damien Lespiaue5f75ac2013-10-15 18:55:34 +01001628 struct intel_pipe_crc_entry *entries;
Daniel Vetter926321d2013-10-16 13:30:34 +02001629 enum intel_pipe_crc_source source;
Damien Lespiaud538bbd2013-10-21 14:29:30 +01001630 int head, tail;
Damien Lespiau07144422013-10-15 18:55:40 +01001631 wait_queue_head_t wq;
Shuang He8bf1e9f2013-10-15 18:55:27 +01001632};
1633
Daniel Vetterf99d7062014-06-19 16:01:59 +02001634struct i915_frontbuffer_tracking {
1635 struct mutex lock;
1636
1637 /*
1638 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1639 * scheduled flips.
1640 */
1641 unsigned busy_bits;
1642 unsigned flip_bits;
1643};
1644
Mika Kuoppala72253422014-10-07 17:21:26 +03001645struct i915_wa_reg {
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001646 i915_reg_t addr;
Mika Kuoppala72253422014-10-07 17:21:26 +03001647 u32 value;
1648 /* bitmask representing WA bits */
1649 u32 mask;
1650};
1651
Arun Siluvery33136b02016-01-21 21:43:47 +00001652/*
1653 * RING_MAX_NONPRIV_SLOTS is per-engine but at this point we are only
1654 * allowing it for RCS as we don't foresee any requirement of having
1655 * a whitelist for other engines. When it is really required for
1656 * other engines then the limit need to be increased.
1657 */
1658#define I915_MAX_WA_REGS (16 + RING_MAX_NONPRIV_SLOTS)
Mika Kuoppala72253422014-10-07 17:21:26 +03001659
1660struct i915_workarounds {
1661 struct i915_wa_reg reg[I915_MAX_WA_REGS];
1662 u32 count;
Tvrtko Ursulin666796d2016-03-16 11:00:39 +00001663 u32 hw_whitelist_count[I915_NUM_ENGINES];
Mika Kuoppala72253422014-10-07 17:21:26 +03001664};
1665
Yu Zhangcf9d2892015-02-10 19:05:47 +08001666struct i915_virtual_gpu {
1667 bool active;
1668};
1669
John Harrison5f19e2b2015-05-29 17:43:27 +01001670struct i915_execbuffer_params {
1671 struct drm_device *dev;
1672 struct drm_file *file;
1673 uint32_t dispatch_flags;
1674 uint32_t args_batch_start_offset;
Michel Thierryaf987142015-07-29 17:23:59 +01001675 uint64_t batch_obj_vm_offset;
Tvrtko Ursulin4a570db2016-03-16 11:00:38 +00001676 struct intel_engine_cs *engine;
John Harrison5f19e2b2015-05-29 17:43:27 +01001677 struct drm_i915_gem_object *batch_obj;
1678 struct intel_context *ctx;
John Harrison6a6ae792015-05-29 17:43:30 +01001679 struct drm_i915_gem_request *request;
John Harrison5f19e2b2015-05-29 17:43:27 +01001680};
1681
Matt Roperaa363132015-09-24 15:53:18 -07001682/* used in computing the new watermarks state */
1683struct intel_wm_config {
1684 unsigned int num_pipes_active;
1685 bool sprites_enabled;
1686 bool sprites_scaled;
1687};
1688
Jani Nikula77fec552014-03-31 14:27:22 +03001689struct drm_i915_private {
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001690 struct drm_device *dev;
Chris Wilsonefab6d82015-04-07 16:20:57 +01001691 struct kmem_cache *objects;
Chris Wilsone20d2ab2015-04-07 16:20:58 +01001692 struct kmem_cache *vmas;
Chris Wilsonefab6d82015-04-07 16:20:57 +01001693 struct kmem_cache *requests;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001694
Damien Lespiau5c969aa2014-02-07 19:12:48 +00001695 const struct intel_device_info info;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001696
1697 int relative_constants_mode;
1698
1699 void __iomem *regs;
1700
Chris Wilson907b28c2013-07-19 20:36:52 +01001701 struct intel_uncore uncore;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001702
Yu Zhangcf9d2892015-02-10 19:05:47 +08001703 struct i915_virtual_gpu vgpu;
1704
Alex Dai33a732f2015-08-12 15:43:36 +01001705 struct intel_guc guc;
1706
Daniel Vettereb805622015-05-04 14:58:44 +02001707 struct intel_csr csr;
1708
Jani Nikula5ea6e5e2015-04-01 10:55:04 +03001709 struct intel_gmbus gmbus[GMBUS_NUM_PINS];
Daniel Vetter28c70f12012-12-01 13:53:45 +01001710
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001711 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1712 * controller on different i2c buses. */
1713 struct mutex gmbus_mutex;
1714
1715 /**
1716 * Base address of the gmbus and gpio block.
1717 */
1718 uint32_t gpio_mmio_base;
1719
Shashank Sharmab6fdd0f2014-05-19 20:54:03 +05301720 /* MMIO base address for MIPI regs */
1721 uint32_t mipi_mmio_base;
1722
Ville Syrjälä443a3892015-11-11 20:34:15 +02001723 uint32_t psr_mmio_base;
1724
Daniel Vetter28c70f12012-12-01 13:53:45 +01001725 wait_queue_head_t gmbus_wait_queue;
1726
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001727 struct pci_dev *bridge_dev;
Tvrtko Ursulin666796d2016-03-16 11:00:39 +00001728 struct intel_engine_cs engine[I915_NUM_ENGINES];
Ben Widawsky3e789982014-06-30 09:53:37 -07001729 struct drm_i915_gem_object *semaphore_obj;
Mika Kuoppalaf72b3432012-12-10 15:41:48 +02001730 uint32_t last_seqno, next_seqno;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001731
Daniel Vetterba8286f2014-09-11 07:43:25 +02001732 struct drm_dma_handle *status_page_dmah;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001733 struct resource mch_res;
1734
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001735 /* protects the irq masks */
1736 spinlock_t irq_lock;
1737
Sourab Gupta84c33a62014-06-02 16:47:17 +05301738 /* protects the mmio flip data */
1739 spinlock_t mmio_flip_lock;
1740
Imre Deakf8b79e52014-03-04 19:23:07 +02001741 bool display_irqs_enabled;
1742
Daniel Vetter9ee32fea2012-12-01 13:53:48 +01001743 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1744 struct pm_qos_request pm_qos;
1745
Ville Syrjäläa5805162015-05-26 20:42:30 +03001746 /* Sideband mailbox protection */
1747 struct mutex sb_lock;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001748
1749 /** Cached value of IMR to avoid reads in updating the bitfield */
Ben Widawskyabd58f02013-11-02 21:07:09 -07001750 union {
1751 u32 irq_mask;
1752 u32 de_irq_mask[I915_MAX_PIPES];
1753 };
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001754 u32 gt_irq_mask;
Paulo Zanoni605cd252013-08-06 18:57:15 -03001755 u32 pm_irq_mask;
Deepak Sa6706b42014-03-15 20:23:22 +05301756 u32 pm_rps_events;
Imre Deak91d181d2014-02-10 18:42:49 +02001757 u32 pipestat_irq_mask[I915_MAX_PIPES];
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001758
Jani Nikula5fcece82015-05-27 15:03:42 +03001759 struct i915_hotplug hotplug;
Paulo Zanoniab34a7e2016-01-11 17:44:36 -02001760 struct intel_fbc fbc;
Pradeep Bhat439d7ac2014-04-05 12:13:28 +05301761 struct i915_drrs drrs;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001762 struct intel_opregion opregion;
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03001763 struct intel_vbt_data vbt;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001764
Jesse Barnesd9ceb812014-10-09 12:57:43 -07001765 bool preserve_bios_swizzle;
1766
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001767 /* overlay */
1768 struct intel_overlay *overlay;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001769
Jani Nikula58c68772013-11-08 16:48:54 +02001770 /* backlight registers and fields in struct intel_panel */
Daniel Vetter07f11d42014-09-15 14:35:09 +02001771 struct mutex backlight_lock;
Jani Nikula31ad8ec2013-04-02 15:48:09 +03001772
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001773 /* LVDS info */
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001774 bool no_aux_handshake;
1775
Ville Syrjäläe39b9992014-09-04 14:53:14 +03001776 /* protects panel power sequencer state */
1777 struct mutex pps_mutex;
1778
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001779 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001780 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
1781
1782 unsigned int fsb_freq, mem_freq, is_ddr3;
Damien Lespiau5d96d8a2015-05-21 16:37:48 +01001783 unsigned int skl_boot_cdclk;
Maarten Lankhorst1a617b72015-12-03 14:31:06 +01001784 unsigned int cdclk_freq, max_cdclk_freq, atomic_cdclk_freq;
Mika Kaholaadafdc62015-08-18 14:36:59 +03001785 unsigned int max_dotclk_freq;
Ville Syrjäläe7dc33f2016-03-02 17:22:13 +02001786 unsigned int rawclk_freq;
Ville Syrjälä6bcda4f2014-10-07 17:41:22 +03001787 unsigned int hpll_freq;
Ville Syrjäläbfa7df02015-09-24 23:29:18 +03001788 unsigned int czclk_freq;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001789
Daniel Vetter645416f2013-09-02 16:22:25 +02001790 /**
1791 * wq - Driver workqueue for GEM.
1792 *
1793 * NOTE: Work items scheduled here are not allowed to grab any modeset
1794 * locks, for otherwise the flushing done in the pageflip code will
1795 * result in deadlocks.
1796 */
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001797 struct workqueue_struct *wq;
1798
1799 /* Display functions */
1800 struct drm_i915_display_funcs display;
1801
1802 /* PCH chipset type */
1803 enum intel_pch pch_type;
Paulo Zanoni17a303e2012-11-20 15:12:07 -02001804 unsigned short pch_id;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001805
1806 unsigned long quirks;
1807
Zhang Ruib8efb172013-02-05 15:41:53 +08001808 enum modeset_restore modeset_restore;
1809 struct mutex modeset_restore_lock;
Maarten Lankhorste2c8b872016-02-16 10:06:14 +01001810 struct drm_atomic_state *modeset_restore_state;
Eric Anholt673a3942008-07-30 12:06:12 -07001811
Ben Widawskya7bbbd62013-07-16 16:50:07 -07001812 struct list_head vm_list; /* Global list of all address spaces */
Ben Widawsky0260c422014-03-22 22:47:21 -07001813 struct i915_gtt gtt; /* VM representing the global address space */
Ben Widawsky5d4545a2013-01-17 12:45:15 -08001814
Daniel Vetter4b5aed62012-11-14 17:14:03 +01001815 struct i915_gem_mm mm;
Chris Wilsonad46cb52014-08-07 14:20:40 +01001816 DECLARE_HASHTABLE(mm_structs, 7);
1817 struct mutex mm_lock;
Daniel Vetter87813422012-05-02 11:49:32 +02001818
Daniel Vetter87813422012-05-02 11:49:32 +02001819 /* Kernel Modesetting */
1820
yakui_zhao9b9d1722009-05-31 17:17:17 +08001821 struct sdvo_device_mapping sdvo_mappings[2];
Jesse Barnes652c3932009-08-17 13:31:43 -07001822
Damien Lespiau76c4ac02014-02-07 19:12:52 +00001823 struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
1824 struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001825 wait_queue_head_t pending_flip_queue;
1826
Daniel Vetterc4597872013-10-21 21:04:07 +02001827#ifdef CONFIG_DEBUG_FS
1828 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1829#endif
1830
Maarten Lankhorst565602d2015-12-10 12:33:57 +01001831 /* dpll and cdclk state is protected by connection_mutex */
Daniel Vettere72f9fb2013-06-05 13:34:06 +02001832 int num_shared_dpll;
1833 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
Ander Conselvan de Oliveiraf9476a62016-03-08 17:46:22 +02001834 const struct intel_dpll_mgr *dpll_mgr;
Maarten Lankhorst565602d2015-12-10 12:33:57 +01001835
1836 unsigned int active_crtcs;
1837 unsigned int min_pixclk[I915_MAX_PIPES];
1838
Chon Ming Leee4607fc2013-11-06 14:36:35 +08001839 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001840
Mika Kuoppala72253422014-10-07 17:21:26 +03001841 struct i915_workarounds workarounds;
Arun Siluvery888b5992014-08-26 14:44:51 +01001842
Jesse Barnes652c3932009-08-17 13:31:43 -07001843 /* Reclocking support */
1844 bool render_reclock_avail;
Daniel Vetterf99d7062014-06-19 16:01:59 +02001845
1846 struct i915_frontbuffer_tracking fb_tracking;
1847
Jesse Barnes652c3932009-08-17 13:31:43 -07001848 u16 orig_clock;
Jesse Barnesf97108d2010-01-29 11:27:07 -08001849
Zhenyu Wangc48044112009-12-17 14:48:43 +08001850 bool mchbar_need_disable;
Jesse Barnesf97108d2010-01-29 11:27:07 -08001851
Daniel Vettera4da4fa2012-11-02 19:55:07 +01001852 struct intel_l3_parity l3_parity;
Daniel Vetterc6a828d2012-08-08 23:35:35 +02001853
Ben Widawsky59124502013-07-04 11:02:05 -07001854 /* Cannot be determined by PCIID. You must always read a register. */
1855 size_t ellc_size;
1856
Daniel Vetterc6a828d2012-08-08 23:35:35 +02001857 /* gen6+ rps state */
Daniel Vetterc85aa882012-11-02 19:55:03 +01001858 struct intel_gen6_power_mgmt rps;
Daniel Vetterc6a828d2012-08-08 23:35:35 +02001859
Daniel Vetter20e4d402012-08-08 23:35:39 +02001860 /* ilk-only ips/rps state. Everything in here is protected by the global
1861 * mchdev_lock in intel_pm.c */
Daniel Vetterc85aa882012-11-02 19:55:03 +01001862 struct intel_ilk_power_mgmt ips;
Jesse Barnesb5e50c32010-02-05 12:42:41 -08001863
Imre Deak83c00f552013-10-25 17:36:47 +03001864 struct i915_power_domains power_domains;
Wang Xingchaoa38911a2013-05-30 22:07:11 +08001865
Rodrigo Vivia031d702013-10-03 16:15:06 -03001866 struct i915_psr psr;
Rodrigo Vivi3f51e472013-07-11 18:45:00 -03001867
Daniel Vetter99584db2012-11-14 17:14:04 +01001868 struct i915_gpu_error gpu_error;
Chris Wilsonae681d92010-10-01 14:57:56 +01001869
Jesse Barnesc9cddff2013-05-08 10:45:13 -07001870 struct drm_i915_gem_object *vlv_pctx;
1871
Daniel Vetter06957262015-08-10 13:34:08 +02001872#ifdef CONFIG_DRM_FBDEV_EMULATION
Dave Airlie8be48d92010-03-30 05:34:14 +00001873 /* list of fbdev register on this device */
1874 struct intel_fbdev *fbdev;
Chris Wilson82e3b8c2014-08-13 13:09:46 +01001875 struct work_struct fbdev_suspend_work;
Daniel Vetter4520f532013-10-09 09:18:51 +02001876#endif
Chris Wilsone953fd72011-02-21 22:23:52 +00001877
1878 struct drm_property *broadcast_rgb_property;
Chris Wilson3f43c482011-05-12 22:17:24 +01001879 struct drm_property *force_audio_property;
Ben Widawskye3689192012-05-25 16:56:22 -07001880
Imre Deak58fddc22015-01-08 17:54:14 +02001881 /* hda/i915 audio component */
David Henningsson51e1d832015-08-19 10:48:56 +02001882 struct i915_audio_component *audio_component;
Imre Deak58fddc22015-01-08 17:54:14 +02001883 bool audio_component_registered;
Libin Yang4a21ef72015-09-02 14:11:39 +08001884 /**
1885 * av_mutex - mutex for audio/video sync
1886 *
1887 */
1888 struct mutex av_mutex;
Imre Deak58fddc22015-01-08 17:54:14 +02001889
Ben Widawsky254f9652012-06-04 14:42:42 -07001890 uint32_t hw_context_size;
Ben Widawskya33afea2013-09-17 21:12:45 -07001891 struct list_head context_list;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001892
Damien Lespiau3e683202012-12-11 18:48:29 +00001893 u32 fdi_rx_config;
Paulo Zanoni68d18ad2012-12-01 12:04:26 -02001894
Ville Syrjälä70722462015-04-10 18:21:28 +03001895 u32 chv_phy_control;
1896
Daniel Vetter842f1c82014-03-10 10:01:44 +01001897 u32 suspend_count;
Imre Deakbc872292015-11-18 17:32:30 +02001898 bool suspended_to_idle;
Daniel Vetterf4c956a2012-11-02 19:55:02 +01001899 struct i915_suspend_saved_registers regfile;
Imre Deakddeea5b2014-05-05 15:19:56 +03001900 struct vlv_s0ix_state vlv_s0ix_state;
Daniel Vetter231f42a2012-11-02 19:55:05 +01001901
Ville Syrjälä53615a52013-08-01 16:18:50 +03001902 struct {
1903 /*
1904 * Raw watermark latency values:
1905 * in 0.1us units for WM0,
1906 * in 0.5us units for WM1+.
1907 */
1908 /* primary */
1909 uint16_t pri_latency[5];
1910 /* sprite */
1911 uint16_t spr_latency[5];
1912 /* cursor */
1913 uint16_t cur_latency[5];
Pradeep Bhat2af30a52014-11-04 17:06:38 +00001914 /*
1915 * Raw watermark memory latency values
1916 * for SKL for all 8 levels
1917 * in 1us units.
1918 */
1919 uint16_t skl_latency[8];
Ville Syrjälä609cede2013-10-09 19:18:03 +03001920
Matt Roperaa363132015-09-24 15:53:18 -07001921 /* Committed wm config */
1922 struct intel_wm_config config;
1923
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00001924 /*
1925 * The skl_wm_values structure is a bit too big for stack
1926 * allocation, so we keep the staging struct where we store
1927 * intermediate results here instead.
1928 */
1929 struct skl_wm_values skl_results;
1930
Ville Syrjälä609cede2013-10-09 19:18:03 +03001931 /* current hardware state */
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00001932 union {
1933 struct ilk_wm_values hw;
1934 struct skl_wm_values skl_hw;
Ville Syrjälä0018fda2015-03-05 21:19:45 +02001935 struct vlv_wm_values vlv;
Pradeep Bhat2d41c0b2014-11-04 17:06:42 +00001936 };
Ville Syrjälä58590c12015-09-08 21:05:12 +03001937
1938 uint8_t max_level;
Matt Ropered4a6a72016-02-23 17:20:13 -08001939
1940 /*
1941 * Should be held around atomic WM register writing; also
1942 * protects * intel_crtc->wm.active and
1943 * cstate->wm.need_postvbl_update.
1944 */
1945 struct mutex wm_mutex;
Ville Syrjälä53615a52013-08-01 16:18:50 +03001946 } wm;
1947
Paulo Zanoni8a187452013-12-06 20:32:13 -02001948 struct i915_runtime_pm pm;
1949
Oscar Mateoa83014d2014-07-24 17:04:21 +01001950 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
1951 struct {
John Harrison5f19e2b2015-05-29 17:43:27 +01001952 int (*execbuf_submit)(struct i915_execbuffer_params *params,
John Harrisonf3dc74c2015-03-19 12:30:06 +00001953 struct drm_i915_gem_execbuffer2 *args,
John Harrison5f19e2b2015-05-29 17:43:27 +01001954 struct list_head *vmas);
Tvrtko Ursulin117897f2016-03-16 11:00:40 +00001955 int (*init_engines)(struct drm_device *dev);
1956 void (*cleanup_engine)(struct intel_engine_cs *engine);
1957 void (*stop_engine)(struct intel_engine_cs *engine);
Oscar Mateoa83014d2014-07-24 17:04:21 +01001958 } gt;
1959
Dave Gordoned54c1a2016-01-19 19:02:54 +00001960 struct intel_context *kernel_context;
1961
Sonika Jindal9e458032015-05-06 17:35:48 +05301962 bool edp_low_vswing;
1963
Ville Syrjälä3be60de2015-09-08 18:05:45 +03001964 /* perform PHY state sanity checks? */
1965 bool chv_phy_assert[2];
1966
Takashi Iwai0bdf5a02015-11-30 18:19:39 +01001967 struct intel_encoder *dig_port_map[I915_MAX_PORTS];
1968
Daniel Vetterbdf1e7e2014-05-21 17:37:52 +02001969 /*
1970 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
1971 * will be rejected. Instead look for a better place.
1972 */
Jani Nikula77fec552014-03-31 14:27:22 +03001973};
Linus Torvalds1da177e2005-04-16 15:20:36 -07001974
Chris Wilson2c1792a2013-08-01 18:39:55 +01001975static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
1976{
1977 return dev->dev_private;
1978}
1979
Imre Deak888d0d42015-01-08 17:54:13 +02001980static inline struct drm_i915_private *dev_to_i915(struct device *dev)
1981{
1982 return to_i915(dev_get_drvdata(dev));
1983}
1984
Alex Dai33a732f2015-08-12 15:43:36 +01001985static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
1986{
1987 return container_of(guc, struct drm_i915_private, guc);
1988}
1989
Chris Wilsonb4519512012-05-11 14:29:30 +01001990/* Iterate over initialised rings */
Tvrtko Ursulin666796d2016-03-16 11:00:39 +00001991#define for_each_engine(ring__, dev_priv__, i__) \
1992 for ((i__) = 0; (i__) < I915_NUM_ENGINES; (i__)++) \
Tvrtko Ursulin117897f2016-03-16 11:00:40 +00001993 for_each_if ((((ring__) = &(dev_priv__)->engine[(i__)]), intel_engine_initialized((ring__))))
Chris Wilsonb4519512012-05-11 14:29:30 +01001994
Mika Kuoppalaee4b6fa2016-03-16 17:54:00 +02001995#define for_each_engine_masked(engine__, dev_priv__, mask__) \
1996 for ((engine__) = &dev_priv->engine[0]; (engine__) < &dev_priv->engine[I915_NUM_ENGINES]; (engine__)++) \
1997 for_each_if (intel_engine_flag((engine__)) & (mask__) && intel_engine_initialized((engine__)))
1998
Wu Fengguangb1d7e4b2012-02-14 11:45:36 +08001999enum hdmi_force_audio {
2000 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
2001 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
2002 HDMI_AUDIO_AUTO, /* trust EDID */
2003 HDMI_AUDIO_ON, /* force turn on HDMI audio */
2004};
2005
Daniel Vetter190d6cd2013-07-04 13:06:28 +02002006#define I915_GTT_OFFSET_NONE ((u32)-1)
Chris Wilsoned2f3452012-11-15 11:32:19 +00002007
Chris Wilson37e680a2012-06-07 15:38:42 +01002008struct drm_i915_gem_object_ops {
Chris Wilsonde472662016-01-22 18:32:31 +00002009 unsigned int flags;
2010#define I915_GEM_OBJECT_HAS_STRUCT_PAGE 0x1
2011
Chris Wilson37e680a2012-06-07 15:38:42 +01002012 /* Interface between the GEM object and its backing storage.
2013 * get_pages() is called once prior to the use of the associated set
2014 * of pages before to binding them into the GTT, and put_pages() is
2015 * called after we no longer need them. As we expect there to be
2016 * associated cost with migrating pages between the backing storage
2017 * and making them available for the GPU (e.g. clflush), we may hold
2018 * onto the pages after they are no longer referenced by the GPU
2019 * in case they may be used again shortly (for example migrating the
2020 * pages to a different memory domain within the GTT). put_pages()
2021 * will therefore most likely be called when the object itself is
2022 * being released or under memory pressure (where we attempt to
2023 * reap pages for the shrinker).
2024 */
2025 int (*get_pages)(struct drm_i915_gem_object *);
2026 void (*put_pages)(struct drm_i915_gem_object *);
Chris Wilsonde472662016-01-22 18:32:31 +00002027
Chris Wilson5cc9ed42014-05-16 14:22:37 +01002028 int (*dmabuf_export)(struct drm_i915_gem_object *);
2029 void (*release)(struct drm_i915_gem_object *);
Chris Wilson37e680a2012-06-07 15:38:42 +01002030};
2031
Daniel Vettera071fa02014-06-18 23:28:09 +02002032/*
2033 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
Sagar Arun Kambled1b9d032015-09-14 21:35:42 +05302034 * considered to be the frontbuffer for the given plane interface-wise. This
Daniel Vettera071fa02014-06-18 23:28:09 +02002035 * doesn't mean that the hw necessarily already scans it out, but that any
2036 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
2037 *
2038 * We have one bit per pipe and per scanout plane type.
2039 */
Sagar Arun Kambled1b9d032015-09-14 21:35:42 +05302040#define INTEL_MAX_SPRITE_BITS_PER_PIPE 5
2041#define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
Daniel Vettera071fa02014-06-18 23:28:09 +02002042#define INTEL_FRONTBUFFER_BITS \
2043 (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES)
2044#define INTEL_FRONTBUFFER_PRIMARY(pipe) \
2045 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2046#define INTEL_FRONTBUFFER_CURSOR(pipe) \
Sagar Arun Kambled1b9d032015-09-14 21:35:42 +05302047 (1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2048#define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \
2049 (1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
Daniel Vettera071fa02014-06-18 23:28:09 +02002050#define INTEL_FRONTBUFFER_OVERLAY(pipe) \
Sagar Arun Kambled1b9d032015-09-14 21:35:42 +05302051 (1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
Daniel Vettercc365132014-06-18 13:59:13 +02002052#define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
Sagar Arun Kambled1b9d032015-09-14 21:35:42 +05302053 (0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
Daniel Vettera071fa02014-06-18 23:28:09 +02002054
Eric Anholt673a3942008-07-30 12:06:12 -07002055struct drm_i915_gem_object {
Daniel Vetterc397b902010-04-09 19:05:07 +00002056 struct drm_gem_object base;
Eric Anholt673a3942008-07-30 12:06:12 -07002057
Chris Wilson37e680a2012-06-07 15:38:42 +01002058 const struct drm_i915_gem_object_ops *ops;
2059
Ben Widawsky2f633152013-07-17 12:19:03 -07002060 /** List of VMAs backed by this object */
2061 struct list_head vma_list;
2062
Chris Wilsonc1ad11f2012-11-15 11:32:21 +00002063 /** Stolen memory for this object, instead of being backed by shmem. */
2064 struct drm_mm_node *stolen;
Ben Widawsky35c20a62013-05-31 11:28:48 -07002065 struct list_head global_list;
Eric Anholt673a3942008-07-30 12:06:12 -07002066
Tvrtko Ursulin117897f2016-03-16 11:00:40 +00002067 struct list_head engine_list[I915_NUM_ENGINES];
Ben Widawskyb25cb2f2013-08-14 11:38:33 +02002068 /** Used in execbuf to temporarily hold a ref */
2069 struct list_head obj_exec_link;
Eric Anholt673a3942008-07-30 12:06:12 -07002070
Chris Wilson8d9d5742015-04-07 16:20:38 +01002071 struct list_head batch_pool_link;
Brad Volkin493018d2014-12-11 12:13:08 -08002072
Eric Anholt673a3942008-07-30 12:06:12 -07002073 /**
Chris Wilson65ce3022012-07-20 12:41:02 +01002074 * This is set if the object is on the active lists (has pending
2075 * rendering and so a non-zero seqno), and is not set if it i s on
2076 * inactive (ready to be unbound) list.
Eric Anholt673a3942008-07-30 12:06:12 -07002077 */
Tvrtko Ursulin666796d2016-03-16 11:00:39 +00002078 unsigned int active:I915_NUM_ENGINES;
Eric Anholt673a3942008-07-30 12:06:12 -07002079
2080 /**
2081 * This is set if the object has been written to since last bound
2082 * to the GTT
2083 */
Akshay Joshi0206e352011-08-16 15:34:10 -04002084 unsigned int dirty:1;
Daniel Vetter778c3542010-05-13 11:49:44 +02002085
2086 /**
2087 * Fence register bits (if any) for this object. Will be set
2088 * as needed when mapped into the GTT.
2089 * Protected by dev->struct_mutex.
Daniel Vetter778c3542010-05-13 11:49:44 +02002090 */
Daniel Vetter4b9de732011-10-09 21:52:02 +02002091 signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
Daniel Vetter778c3542010-05-13 11:49:44 +02002092
2093 /**
Daniel Vetter778c3542010-05-13 11:49:44 +02002094 * Advice: are the backing pages purgeable?
2095 */
Akshay Joshi0206e352011-08-16 15:34:10 -04002096 unsigned int madv:2;
Daniel Vetter778c3542010-05-13 11:49:44 +02002097
2098 /**
Daniel Vetter778c3542010-05-13 11:49:44 +02002099 * Current tiling mode for the object.
2100 */
Akshay Joshi0206e352011-08-16 15:34:10 -04002101 unsigned int tiling_mode:2;
Chris Wilson5d82e3e2012-04-21 16:23:23 +01002102 /**
2103 * Whether the tiling parameters for the currently associated fence
2104 * register have changed. Note that for the purposes of tracking
2105 * tiling changes we also treat the unfenced register, the register
2106 * slot that the object occupies whilst it executes a fenced
2107 * command (such as BLT on gen2/3), as a "fence".
2108 */
2109 unsigned int fence_dirty:1;
Daniel Vetter778c3542010-05-13 11:49:44 +02002110
Daniel Vetterfb7d5162010-10-01 22:05:20 +02002111 /**
Daniel Vetter75e9e912010-11-04 17:11:09 +01002112 * Is the object at the current location in the gtt mappable and
2113 * fenceable? Used to avoid costly recalculations.
2114 */
Akshay Joshi0206e352011-08-16 15:34:10 -04002115 unsigned int map_and_fenceable:1;
Daniel Vetter75e9e912010-11-04 17:11:09 +01002116
2117 /**
Daniel Vetterfb7d5162010-10-01 22:05:20 +02002118 * Whether the current gtt mapping needs to be mappable (and isn't just
2119 * mappable by accident). Track pin and fault separate for a more
2120 * accurate mappable working set.
2121 */
Akshay Joshi0206e352011-08-16 15:34:10 -04002122 unsigned int fault_mappable:1;
Daniel Vetterfb7d5162010-10-01 22:05:20 +02002123
Chris Wilsoncaea7472010-11-12 13:53:37 +00002124 /*
Akash Goel24f3a8c2014-06-17 10:59:42 +05302125 * Is the object to be mapped as read-only to the GPU
2126 * Only honoured if hardware has relevant pte bit
2127 */
2128 unsigned long gt_ro:1;
Chris Wilson651d7942013-08-08 14:41:10 +01002129 unsigned int cache_level:3;
Chris Wilson0f719792015-01-13 13:32:52 +00002130 unsigned int cache_dirty:1;
Chris Wilson93dfb402011-03-29 16:59:50 -07002131
Daniel Vettera071fa02014-06-18 23:28:09 +02002132 unsigned int frontbuffer_bits:INTEL_FRONTBUFFER_BITS;
2133
Tvrtko Ursulin8a0c39b2015-04-13 11:50:09 +01002134 unsigned int pin_display;
2135
Chris Wilson9da3da62012-06-01 15:20:22 +01002136 struct sg_table *pages;
Chris Wilsona5570172012-09-04 21:02:54 +01002137 int pages_pin_count;
Chris Wilsonee286372015-04-07 16:20:25 +01002138 struct get_page {
2139 struct scatterlist *sg;
2140 int last;
2141 } get_page;
Eric Anholt673a3942008-07-30 12:06:12 -07002142
Daniel Vetter1286ff72012-05-10 15:25:09 +02002143 /* prime dma-buf support */
Dave Airlie9a70cc22012-05-22 13:09:21 +01002144 void *dma_buf_vmapping;
2145 int vmapping_count;
2146
Chris Wilsonb4716182015-04-27 13:41:17 +01002147 /** Breadcrumb of last rendering to the buffer.
2148 * There can only be one writer, but we allow for multiple readers.
2149 * If there is a writer that necessarily implies that all other
2150 * read requests are complete - but we may only be lazily clearing
2151 * the read requests. A read request is naturally the most recent
2152 * request on a ring, so we may have two different write and read
2153 * requests on one ring where the write request is older than the
2154 * read request. This allows for the CPU to read from an active
2155 * buffer by only waiting for the write to complete.
2156 * */
Tvrtko Ursulin666796d2016-03-16 11:00:39 +00002157 struct drm_i915_gem_request *last_read_req[I915_NUM_ENGINES];
John Harrison97b2a6a2014-11-24 18:49:26 +00002158 struct drm_i915_gem_request *last_write_req;
Chris Wilsoncaea7472010-11-12 13:53:37 +00002159 /** Breadcrumb of last fenced GPU access to the buffer. */
John Harrison97b2a6a2014-11-24 18:49:26 +00002160 struct drm_i915_gem_request *last_fenced_req;
Eric Anholt673a3942008-07-30 12:06:12 -07002161
Daniel Vetter778c3542010-05-13 11:49:44 +02002162 /** Current tiling stride for the object, if it's tiled. */
Jesse Barnesde151cf2008-11-12 10:03:55 -08002163 uint32_t stride;
Eric Anholt673a3942008-07-30 12:06:12 -07002164
Daniel Vetter80075d42013-10-09 21:23:52 +02002165 /** References from framebuffers, locks out tiling changes. */
2166 unsigned long framebuffer_references;
2167
Eric Anholt280b7132009-03-12 16:56:27 -07002168 /** Record of address bit 17 of each page at last unbind. */
Chris Wilsond312ec22010-06-06 15:40:22 +01002169 unsigned long *bit_17;
Eric Anholt280b7132009-03-12 16:56:27 -07002170
Chris Wilson5cc9ed42014-05-16 14:22:37 +01002171 union {
Chris Wilson6a2c4232014-11-04 04:51:40 -08002172 /** for phy allocated objects */
2173 struct drm_dma_handle *phys_handle;
2174
Chris Wilson5cc9ed42014-05-16 14:22:37 +01002175 struct i915_gem_userptr {
2176 uintptr_t ptr;
2177 unsigned read_only :1;
2178 unsigned workers :4;
2179#define I915_GEM_USERPTR_MAX_WORKERS 15
2180
Chris Wilsonad46cb52014-08-07 14:20:40 +01002181 struct i915_mm_struct *mm;
2182 struct i915_mmu_object *mmu_object;
Chris Wilson5cc9ed42014-05-16 14:22:37 +01002183 struct work_struct *work;
2184 } userptr;
2185 };
2186};
Daniel Vetter62b8b212010-04-09 19:05:08 +00002187#define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
Daniel Vetter23010e42010-03-08 13:35:02 +01002188
Daniel Vettera071fa02014-06-18 23:28:09 +02002189void i915_gem_track_fb(struct drm_i915_gem_object *old,
2190 struct drm_i915_gem_object *new,
2191 unsigned frontbuffer_bits);
2192
Eric Anholt673a3942008-07-30 12:06:12 -07002193/**
2194 * Request queue structure.
2195 *
2196 * The request queue allows us to note sequence numbers that have been emitted
2197 * and may be associated with active buffers to be retired.
2198 *
John Harrison97b2a6a2014-11-24 18:49:26 +00002199 * By keeping this list, we can avoid having to do questionable sequence
2200 * number comparisons on buffer last_read|write_seqno. It also allows an
2201 * emission time to be associated with the request for tracking how far ahead
2202 * of the GPU the submission is.
Nick Hoathb3a38992015-02-19 16:30:47 +00002203 *
2204 * The requests are reference counted, so upon creation they should have an
2205 * initial reference taken using kref_init
Eric Anholt673a3942008-07-30 12:06:12 -07002206 */
2207struct drm_i915_gem_request {
John Harrisonabfe2622014-11-24 18:49:24 +00002208 struct kref ref;
2209
Zou Nan hai852835f2010-05-21 09:08:56 +08002210 /** On Which ring this request was generated */
Chris Wilsonefab6d82015-04-07 16:20:57 +01002211 struct drm_i915_private *i915;
Tvrtko Ursulin4a570db2016-03-16 11:00:38 +00002212 struct intel_engine_cs *engine;
Zou Nan hai852835f2010-05-21 09:08:56 +08002213
Chris Wilson821485d2015-12-11 11:32:59 +00002214 /** GEM sequence number associated with the previous request,
2215 * when the HWS breadcrumb is equal to this the GPU is processing
2216 * this request.
2217 */
2218 u32 previous_seqno;
2219
2220 /** GEM sequence number associated with this request,
2221 * when the HWS breadcrumb is equal or greater than this the GPU
2222 * has finished processing this request.
2223 */
2224 u32 seqno;
Eric Anholt673a3942008-07-30 12:06:12 -07002225
Mika Kuoppala7d736f42013-06-12 15:01:39 +03002226 /** Position in the ringbuffer of the start of the request */
2227 u32 head;
2228
Nick Hoath72f95af2015-01-15 13:10:37 +00002229 /**
2230 * Position in the ringbuffer of the start of the postfix.
2231 * This is required to calculate the maximum available ringbuffer
2232 * space without overwriting the postfix.
2233 */
2234 u32 postfix;
2235
2236 /** Position in the ringbuffer of the end of the whole request */
Chris Wilsona71d8d92012-02-15 11:25:36 +00002237 u32 tail;
2238
Nick Hoathb3a38992015-02-19 16:30:47 +00002239 /**
Dave Airliea8c6ecb2015-03-09 19:58:30 +10002240 * Context and ring buffer related to this request
Nick Hoathb3a38992015-02-19 16:30:47 +00002241 * Contexts are refcounted, so when this request is associated with a
2242 * context, we must increment the context's refcount, to guarantee that
2243 * it persists while any request is linked to it. Requests themselves
2244 * are also refcounted, so the request will only be freed when the last
2245 * reference to it is dismissed, and the code in
2246 * i915_gem_request_free() will then decrement the refcount on the
2247 * context.
2248 */
Oscar Mateo273497e2014-05-22 14:13:37 +01002249 struct intel_context *ctx;
John Harrison98e1bd42015-02-13 11:48:12 +00002250 struct intel_ringbuffer *ringbuf;
Mika Kuoppala0e50e962013-05-02 16:48:08 +03002251
John Harrisondc4be60712015-05-29 17:43:39 +01002252 /** Batch buffer related to this request if any (used for
2253 error state dump only) */
Mika Kuoppala7d736f42013-06-12 15:01:39 +03002254 struct drm_i915_gem_object *batch_obj;
2255
Eric Anholt673a3942008-07-30 12:06:12 -07002256 /** Time at which this request was emitted, in jiffies. */
2257 unsigned long emitted_jiffies;
2258
Eric Anholtb9624422009-06-03 07:27:35 +00002259 /** global list entry for this request */
Eric Anholt673a3942008-07-30 12:06:12 -07002260 struct list_head list;
Eric Anholtb9624422009-06-03 07:27:35 +00002261
Chris Wilsonf787a5f2010-09-24 16:02:42 +01002262 struct drm_i915_file_private *file_priv;
Eric Anholtb9624422009-06-03 07:27:35 +00002263 /** file_priv list entry for this request */
2264 struct list_head client_list;
John Harrison67e29372014-12-05 13:49:35 +00002265
Mika Kuoppala071c92d2015-02-12 10:26:02 +02002266 /** process identifier submitting this request */
2267 struct pid *pid;
2268
Nick Hoath6d3d8272015-01-15 13:10:39 +00002269 /**
2270 * The ELSP only accepts two elements at a time, so we queue
2271 * context/tail pairs on a given queue (ring->execlist_queue) until the
2272 * hardware is available. The queue serves a double purpose: we also use
2273 * it to keep track of the up to 2 contexts currently in the hardware
2274 * (usually one in execution and the other queued up by the GPU): We
2275 * only remove elements from the head of the queue when the hardware
2276 * informs us that an element has been completed.
2277 *
2278 * All accesses to the queue are mediated by a spinlock
2279 * (ring->execlist_lock).
2280 */
2281
2282 /** Execlist link in the submission queue.*/
2283 struct list_head execlist_link;
2284
2285 /** Execlists no. of times this request has been sent to the ELSP */
2286 int elsp_submitted;
2287
Eric Anholt673a3942008-07-30 12:06:12 -07002288};
2289
Dave Gordon26827082016-01-19 19:02:53 +00002290struct drm_i915_gem_request * __must_check
2291i915_gem_request_alloc(struct intel_engine_cs *engine,
2292 struct intel_context *ctx);
John Harrison29b1b412015-06-18 13:10:09 +01002293void i915_gem_request_cancel(struct drm_i915_gem_request *req);
John Harrisonabfe2622014-11-24 18:49:24 +00002294void i915_gem_request_free(struct kref *req_ref);
John Harrisonfcfa423c2015-05-29 17:44:12 +01002295int i915_gem_request_add_to_client(struct drm_i915_gem_request *req,
2296 struct drm_file *file);
John Harrisonabfe2622014-11-24 18:49:24 +00002297
John Harrisonb793a002014-11-24 18:49:25 +00002298static inline uint32_t
2299i915_gem_request_get_seqno(struct drm_i915_gem_request *req)
2300{
2301 return req ? req->seqno : 0;
2302}
2303
2304static inline struct intel_engine_cs *
Tvrtko Ursulin666796d2016-03-16 11:00:39 +00002305i915_gem_request_get_engine(struct drm_i915_gem_request *req)
John Harrisonb793a002014-11-24 18:49:25 +00002306{
Tvrtko Ursulin4a570db2016-03-16 11:00:38 +00002307 return req ? req->engine : NULL;
John Harrisonb793a002014-11-24 18:49:25 +00002308}
2309
Chris Wilsonb2cfe0a2015-04-27 13:41:16 +01002310static inline struct drm_i915_gem_request *
John Harrisonabfe2622014-11-24 18:49:24 +00002311i915_gem_request_reference(struct drm_i915_gem_request *req)
2312{
Chris Wilsonb2cfe0a2015-04-27 13:41:16 +01002313 if (req)
2314 kref_get(&req->ref);
2315 return req;
John Harrisonabfe2622014-11-24 18:49:24 +00002316}
2317
2318static inline void
2319i915_gem_request_unreference(struct drm_i915_gem_request *req)
2320{
Tvrtko Ursulin4a570db2016-03-16 11:00:38 +00002321 WARN_ON(!mutex_is_locked(&req->engine->dev->struct_mutex));
John Harrisonabfe2622014-11-24 18:49:24 +00002322 kref_put(&req->ref, i915_gem_request_free);
2323}
2324
Chris Wilson41037f92015-03-27 11:01:36 +00002325static inline void
2326i915_gem_request_unreference__unlocked(struct drm_i915_gem_request *req)
2327{
Maarten Lankhorstb833bb62015-04-07 11:32:02 +02002328 struct drm_device *dev;
Chris Wilson41037f92015-03-27 11:01:36 +00002329
Maarten Lankhorstb833bb62015-04-07 11:32:02 +02002330 if (!req)
2331 return;
2332
Tvrtko Ursulin4a570db2016-03-16 11:00:38 +00002333 dev = req->engine->dev;
Maarten Lankhorstb833bb62015-04-07 11:32:02 +02002334 if (kref_put_mutex(&req->ref, i915_gem_request_free, &dev->struct_mutex))
Chris Wilson41037f92015-03-27 11:01:36 +00002335 mutex_unlock(&dev->struct_mutex);
Chris Wilson41037f92015-03-27 11:01:36 +00002336}
2337
John Harrisonabfe2622014-11-24 18:49:24 +00002338static inline void i915_gem_request_assign(struct drm_i915_gem_request **pdst,
2339 struct drm_i915_gem_request *src)
2340{
2341 if (src)
2342 i915_gem_request_reference(src);
2343
2344 if (*pdst)
2345 i915_gem_request_unreference(*pdst);
2346
2347 *pdst = src;
2348}
2349
John Harrison1b5a4332014-11-24 18:49:42 +00002350/*
2351 * XXX: i915_gem_request_completed should be here but currently needs the
2352 * definition of i915_seqno_passed() which is below. It will be moved in
2353 * a later patch when the call to i915_seqno_passed() is obsoleted...
2354 */
2355
Brad Volkin351e3db2014-02-18 10:15:46 -08002356/*
2357 * A command that requires special handling by the command parser.
2358 */
2359struct drm_i915_cmd_descriptor {
2360 /*
2361 * Flags describing how the command parser processes the command.
2362 *
2363 * CMD_DESC_FIXED: The command has a fixed length if this is set,
2364 * a length mask if not set
2365 * CMD_DESC_SKIP: The command is allowed but does not follow the
2366 * standard length encoding for the opcode range in
2367 * which it falls
2368 * CMD_DESC_REJECT: The command is never allowed
2369 * CMD_DESC_REGISTER: The command should be checked against the
2370 * register whitelist for the appropriate ring
2371 * CMD_DESC_MASTER: The command is allowed if the submitting process
2372 * is the DRM master
2373 */
2374 u32 flags;
2375#define CMD_DESC_FIXED (1<<0)
2376#define CMD_DESC_SKIP (1<<1)
2377#define CMD_DESC_REJECT (1<<2)
2378#define CMD_DESC_REGISTER (1<<3)
2379#define CMD_DESC_BITMASK (1<<4)
2380#define CMD_DESC_MASTER (1<<5)
2381
2382 /*
2383 * The command's unique identification bits and the bitmask to get them.
2384 * This isn't strictly the opcode field as defined in the spec and may
2385 * also include type, subtype, and/or subop fields.
2386 */
2387 struct {
2388 u32 value;
2389 u32 mask;
2390 } cmd;
2391
2392 /*
2393 * The command's length. The command is either fixed length (i.e. does
2394 * not include a length field) or has a length field mask. The flag
2395 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
2396 * a length mask. All command entries in a command table must include
2397 * length information.
2398 */
2399 union {
2400 u32 fixed;
2401 u32 mask;
2402 } length;
2403
2404 /*
2405 * Describes where to find a register address in the command to check
2406 * against the ring's register whitelist. Only valid if flags has the
2407 * CMD_DESC_REGISTER bit set.
Francisco Jerez6a65c5b2015-05-29 16:44:13 +03002408 *
2409 * A non-zero step value implies that the command may access multiple
2410 * registers in sequence (e.g. LRI), in that case step gives the
2411 * distance in dwords between individual offset fields.
Brad Volkin351e3db2014-02-18 10:15:46 -08002412 */
2413 struct {
2414 u32 offset;
2415 u32 mask;
Francisco Jerez6a65c5b2015-05-29 16:44:13 +03002416 u32 step;
Brad Volkin351e3db2014-02-18 10:15:46 -08002417 } reg;
2418
2419#define MAX_CMD_DESC_BITMASKS 3
2420 /*
2421 * Describes command checks where a particular dword is masked and
2422 * compared against an expected value. If the command does not match
2423 * the expected value, the parser rejects it. Only valid if flags has
2424 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
2425 * are valid.
Brad Volkind4d48032014-02-18 10:15:54 -08002426 *
2427 * If the check specifies a non-zero condition_mask then the parser
2428 * only performs the check when the bits specified by condition_mask
2429 * are non-zero.
Brad Volkin351e3db2014-02-18 10:15:46 -08002430 */
2431 struct {
2432 u32 offset;
2433 u32 mask;
2434 u32 expected;
Brad Volkind4d48032014-02-18 10:15:54 -08002435 u32 condition_offset;
2436 u32 condition_mask;
Brad Volkin351e3db2014-02-18 10:15:46 -08002437 } bits[MAX_CMD_DESC_BITMASKS];
2438};
2439
2440/*
2441 * A table of commands requiring special handling by the command parser.
2442 *
2443 * Each ring has an array of tables. Each table consists of an array of command
2444 * descriptors, which must be sorted with command opcodes in ascending order.
2445 */
2446struct drm_i915_cmd_table {
2447 const struct drm_i915_cmd_descriptor *table;
2448 int count;
2449};
2450
Chris Wilsondbbe9122014-08-09 19:18:43 +01002451/* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */
Chris Wilson7312e2d2014-08-13 12:14:12 +01002452#define __I915__(p) ({ \
2453 struct drm_i915_private *__p; \
2454 if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
2455 __p = (struct drm_i915_private *)p; \
2456 else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
2457 __p = to_i915((struct drm_device *)p); \
2458 else \
2459 BUILD_BUG(); \
2460 __p; \
2461})
Chris Wilsondbbe9122014-08-09 19:18:43 +01002462#define INTEL_INFO(p) (&__I915__(p)->info)
Chris Wilson87f1f462014-08-09 19:18:42 +01002463#define INTEL_DEVID(p) (INTEL_INFO(p)->device_id)
Hoath, Nicholase90a21d2015-02-05 10:47:17 +00002464#define INTEL_REVID(p) (__I915__(p)->dev->pdev->revision)
Zou Nan haicae58522010-11-09 17:17:32 +08002465
Jani Nikulae87a0052015-10-20 15:22:02 +03002466#define REVID_FOREVER 0xff
2467/*
2468 * Return true if revision is in range [since,until] inclusive.
2469 *
2470 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
2471 */
2472#define IS_REVID(p, since, until) \
2473 (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
2474
Chris Wilson87f1f462014-08-09 19:18:42 +01002475#define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577)
2476#define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562)
Zou Nan haicae58522010-11-09 17:17:32 +08002477#define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
Chris Wilson87f1f462014-08-09 19:18:42 +01002478#define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572)
Zou Nan haicae58522010-11-09 17:17:32 +08002479#define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
Chris Wilson87f1f462014-08-09 19:18:42 +01002480#define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592)
2481#define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772)
Zou Nan haicae58522010-11-09 17:17:32 +08002482#define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
2483#define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
2484#define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
Chris Wilson87f1f462014-08-09 19:18:42 +01002485#define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42)
Zou Nan haicae58522010-11-09 17:17:32 +08002486#define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
Chris Wilson87f1f462014-08-09 19:18:42 +01002487#define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001)
2488#define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011)
Zou Nan haicae58522010-11-09 17:17:32 +08002489#define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
2490#define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
Chris Wilson87f1f462014-08-09 19:18:42 +01002491#define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046)
Jesse Barnes4b651772011-04-28 14:33:09 -07002492#define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
Chris Wilson87f1f462014-08-09 19:18:42 +01002493#define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \
2494 INTEL_DEVID(dev) == 0x0152 || \
2495 INTEL_DEVID(dev) == 0x015a)
Jesse Barnes70a3eb72012-03-28 13:39:21 -07002496#define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
Wayne Boyer666a4532015-12-09 12:29:35 -08002497#define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_cherryview)
Eugeni Dodonov4cae9ae2012-03-29 12:32:18 -03002498#define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
Wayne Boyer666a4532015-12-09 12:29:35 -08002499#define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_cherryview && IS_GEN8(dev))
Satheeshakrishna M7201c0b2014-04-02 11:24:50 +05302500#define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake)
Rodrigo Vivi7526ac12015-10-27 10:14:54 -07002501#define IS_BROXTON(dev) (INTEL_INFO(dev)->is_broxton)
Rodrigo Vivief11bdb2015-10-28 04:16:45 -07002502#define IS_KABYLAKE(dev) (INTEL_INFO(dev)->is_kabylake)
Zou Nan haicae58522010-11-09 17:17:32 +08002503#define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
Paulo Zanonied1c9e22013-08-12 14:34:08 -03002504#define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
Chris Wilson87f1f462014-08-09 19:18:42 +01002505 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
Ben Widawsky5dd8c4c2013-11-08 10:20:06 -08002506#define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
Rodrigo Vivi6b96d702015-01-19 16:16:15 -08002507 ((INTEL_DEVID(dev) & 0xf) == 0x6 || \
Rodrigo Vivi0dc6f202015-01-21 11:46:32 -08002508 (INTEL_DEVID(dev) & 0xf) == 0xb || \
Chris Wilson87f1f462014-08-09 19:18:42 +01002509 (INTEL_DEVID(dev) & 0xf) == 0xe))
Ville Syrjäläebb72aa2015-06-03 15:45:12 +03002510/* ULX machines are also considered ULT. */
2511#define IS_BDW_ULX(dev) (IS_BROADWELL(dev) && \
2512 (INTEL_DEVID(dev) & 0xf) == 0xe)
Rodrigo Vivia0fcbd92014-09-19 20:16:26 -04002513#define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \
2514 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
Ben Widawsky5dd8c4c2013-11-08 10:20:06 -08002515#define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
Chris Wilson87f1f462014-08-09 19:18:42 +01002516 (INTEL_DEVID(dev) & 0xFF00) == 0x0A00)
Rodrigo Vivi94353732013-08-28 16:45:46 -03002517#define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
Chris Wilson87f1f462014-08-09 19:18:42 +01002518 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
Paulo Zanoni9bbfd202014-04-29 11:00:22 -03002519/* ULX machines are also considered ULT. */
Chris Wilson87f1f462014-08-09 19:18:42 +01002520#define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \
2521 INTEL_DEVID(dev) == 0x0A1E)
David Weinehallf8896f52015-06-25 11:11:03 +03002522#define IS_SKL_ULT(dev) (INTEL_DEVID(dev) == 0x1906 || \
2523 INTEL_DEVID(dev) == 0x1913 || \
2524 INTEL_DEVID(dev) == 0x1916 || \
2525 INTEL_DEVID(dev) == 0x1921 || \
2526 INTEL_DEVID(dev) == 0x1926)
2527#define IS_SKL_ULX(dev) (INTEL_DEVID(dev) == 0x190E || \
2528 INTEL_DEVID(dev) == 0x1915 || \
2529 INTEL_DEVID(dev) == 0x191E)
Rodrigo Vivia5b79912015-12-08 16:58:37 -08002530#define IS_KBL_ULT(dev) (INTEL_DEVID(dev) == 0x5906 || \
2531 INTEL_DEVID(dev) == 0x5913 || \
2532 INTEL_DEVID(dev) == 0x5916 || \
2533 INTEL_DEVID(dev) == 0x5921 || \
2534 INTEL_DEVID(dev) == 0x5926)
2535#define IS_KBL_ULX(dev) (INTEL_DEVID(dev) == 0x590E || \
2536 INTEL_DEVID(dev) == 0x5915 || \
2537 INTEL_DEVID(dev) == 0x591E)
Sagar Arun Kamble7a58bad2015-09-12 10:17:50 +05302538#define IS_SKL_GT3(dev) (IS_SKYLAKE(dev) && \
2539 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2540#define IS_SKL_GT4(dev) (IS_SKYLAKE(dev) && \
2541 (INTEL_DEVID(dev) & 0x00F0) == 0x0030)
2542
Ben Widawskyb833d682013-08-23 16:00:07 -07002543#define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
Zou Nan haicae58522010-11-09 17:17:32 +08002544
Jani Nikulaef712bb2015-10-20 15:22:00 +03002545#define SKL_REVID_A0 0x0
2546#define SKL_REVID_B0 0x1
2547#define SKL_REVID_C0 0x2
2548#define SKL_REVID_D0 0x3
2549#define SKL_REVID_E0 0x4
2550#define SKL_REVID_F0 0x5
Hoath, Nicholase90a21d2015-02-05 10:47:17 +00002551
Jani Nikulae87a0052015-10-20 15:22:02 +03002552#define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
2553
Jani Nikulaef712bb2015-10-20 15:22:00 +03002554#define BXT_REVID_A0 0x0
Jani Nikulafffda3f2015-10-20 15:22:01 +03002555#define BXT_REVID_A1 0x1
Jani Nikulaef712bb2015-10-20 15:22:00 +03002556#define BXT_REVID_B0 0x3
2557#define BXT_REVID_C0 0x9
Nick Hoath6c74c872015-03-20 09:03:52 +00002558
Jani Nikulae87a0052015-10-20 15:22:02 +03002559#define IS_BXT_REVID(p, since, until) (IS_BROXTON(p) && IS_REVID(p, since, until))
2560
Jesse Barnes85436692011-04-06 12:11:14 -07002561/*
2562 * The genX designation typically refers to the render engine, so render
2563 * capability related checks should use IS_GEN, while display and other checks
2564 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2565 * chips, etc.).
2566 */
Zou Nan haicae58522010-11-09 17:17:32 +08002567#define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
2568#define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
2569#define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
2570#define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
2571#define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
Jesse Barnes85436692011-04-06 12:11:14 -07002572#define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
Ben Widawskyd2980842013-11-02 21:06:59 -07002573#define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8)
Damien Lespiaub71252d2013-02-13 15:27:24 +00002574#define IS_GEN9(dev) (INTEL_INFO(dev)->gen == 9)
Zou Nan haicae58522010-11-09 17:17:32 +08002575
Ben Widawsky73ae4782013-10-15 10:02:57 -07002576#define RENDER_RING (1<<RCS)
2577#define BSD_RING (1<<VCS)
2578#define BLT_RING (1<<BCS)
2579#define VEBOX_RING (1<<VECS)
Zhao Yakui845f74a2014-04-17 10:37:37 +08002580#define BSD2_RING (1<<VCS2)
Mika Kuoppalaee4b6fa2016-03-16 17:54:00 +02002581#define ALL_ENGINES (~0)
2582
Ben Widawsky63c42e52014-04-18 18:04:27 -03002583#define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING)
Zhao Yakui845f74a2014-04-17 10:37:37 +08002584#define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING)
Ben Widawsky63c42e52014-04-18 18:04:27 -03002585#define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING)
2586#define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
2587#define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
Tvrtko Ursulinca377802016-03-02 12:10:31 +00002588#define HAS_SNOOP(dev) (INTEL_INFO(dev)->has_snoop)
Ben Widawsky63c42e52014-04-18 18:04:27 -03002589#define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
Chris Wilsonf2fbc692014-08-24 19:35:31 +01002590 __I915__(dev)->ellc_size)
Zou Nan haicae58522010-11-09 17:17:32 +08002591#define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
2592
Ben Widawsky254f9652012-06-04 14:42:42 -07002593#define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
Oscar Mateod7f621e2014-07-24 17:04:49 +01002594#define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8)
Jesse Barnes692ef702014-08-05 07:51:18 -07002595#define USES_PPGTT(dev) (i915.enable_ppgtt)
Michel Thierry81ba8aef2015-08-03 09:52:01 +01002596#define USES_FULL_PPGTT(dev) (i915.enable_ppgtt >= 2)
2597#define USES_FULL_48BIT_PPGTT(dev) (i915.enable_ppgtt == 3)
Daniel Vetter1d2a3142012-02-09 17:15:46 +01002598
Chris Wilson05394f32010-11-08 19:18:58 +00002599#define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
Zou Nan haicae58522010-11-09 17:17:32 +08002600#define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
2601
Daniel Vetterb45305f2012-12-17 16:21:27 +01002602/* Early gen2 have a totally busted CS tlb and require pinned batches. */
2603#define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
Mika Kuoppala06e668a2015-12-16 19:18:37 +02002604
2605/* WaRsDisableCoarsePowerGating:skl,bxt */
2606#define NEEDS_WaRsDisableCoarsePowerGating(dev) (IS_BXT_REVID(dev, 0, BXT_REVID_A1) || \
2607 ((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) && \
2608 IS_SKL_REVID(dev, 0, SKL_REVID_F0)))
Daniel Vetter4e6b7882014-02-07 16:33:20 +01002609/*
2610 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2611 * even when in MSI mode. This results in spurious interrupt warnings if the
2612 * legacy irq no. is shared with another device. The kernel then disables that
2613 * interrupt source and so prevents the other device from working properly.
2614 */
2615#define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2616#define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
Daniel Vetterb45305f2012-12-17 16:21:27 +01002617
Zou Nan haicae58522010-11-09 17:17:32 +08002618/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2619 * rows, which changed the alignment requirements and fence programming.
2620 */
2621#define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
2622 IS_I915GM(dev)))
Zou Nan haicae58522010-11-09 17:17:32 +08002623#define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
2624#define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
Zou Nan haicae58522010-11-09 17:17:32 +08002625
2626#define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
2627#define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
Daniel Vetter3a77c4c2014-01-10 08:50:12 +01002628#define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
Zou Nan haicae58522010-11-09 17:17:32 +08002629
Damien Lespiaudbf77862014-10-01 20:04:14 +01002630#define HAS_IPS(dev) (IS_HSW_ULT(dev) || IS_BROADWELL(dev))
Damien Lespiauf5adf942013-06-24 18:29:34 +01002631
Jani Nikula0c9b3712015-05-18 17:10:01 +03002632#define HAS_DP_MST(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2633 INTEL_INFO(dev)->gen >= 9)
2634
Damien Lespiaudd93be52013-04-22 18:40:39 +01002635#define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
Damien Lespiau30568c42013-04-22 18:40:41 +01002636#define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
Rodrigo Vivib32c6f42014-11-20 03:44:37 -08002637#define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
Sonika Jindale3d99842015-01-22 14:30:54 +05302638 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \
Rodrigo Vivief11bdb2015-10-28 04:16:45 -07002639 IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
Paulo Zanoni6157d3c2014-03-07 20:12:37 -03002640#define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \
Suketu Shah00776512015-04-16 14:22:14 +05302641 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \
Wayne Boyer666a4532015-12-09 12:29:35 -08002642 IS_CHERRYVIEW(dev) || IS_SKYLAKE(dev) || \
2643 IS_KABYLAKE(dev))
Rodrigo Vivi58abf1d2014-10-07 07:06:50 -07002644#define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6)
2645#define HAS_RC6p(dev) (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
Paulo Zanoniaffa9352012-11-23 15:30:39 -02002646
Animesh Manna7b403ff2015-08-04 22:02:42 +05302647#define HAS_CSR(dev) (IS_GEN9(dev))
Daniel Vettereb805622015-05-04 14:58:44 +02002648
Rodrigo Vivi2b81b842015-12-08 16:58:38 -08002649#define HAS_GUC_UCODE(dev) (IS_GEN9(dev) && !IS_KABYLAKE(dev))
2650#define HAS_GUC_SCHED(dev) (IS_GEN9(dev) && !IS_KABYLAKE(dev))
Alex Dai33a732f2015-08-12 15:43:36 +01002651
Abdiel Janulguea9ed33c2015-07-01 10:12:23 +03002652#define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \
2653 INTEL_INFO(dev)->gen >= 8)
2654
Akash Goel97d33082015-06-29 14:50:23 +05302655#define HAS_CORE_RING_FREQ(dev) (INTEL_INFO(dev)->gen >= 6 && \
Wayne Boyer666a4532015-12-09 12:29:35 -08002656 !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && \
2657 !IS_BROXTON(dev))
Akash Goel97d33082015-06-29 14:50:23 +05302658
Paulo Zanoni17a303e2012-11-20 15:12:07 -02002659#define INTEL_PCH_DEVICE_ID_MASK 0xff00
2660#define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2661#define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2662#define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2663#define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2664#define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
Satheeshakrishna Me7e7ea22014-04-09 11:08:57 +05302665#define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2666#define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
Robert Beckett30c964a2015-08-28 13:10:22 +01002667#define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
Gerd Hoffmann39bfcd522015-11-26 12:03:51 +01002668#define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
Paulo Zanoni17a303e2012-11-20 15:12:07 -02002669
Chris Wilsonf2fbc692014-08-24 19:35:31 +01002670#define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
Satheeshakrishna Me7e7ea22014-04-09 11:08:57 +05302671#define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
Eugeni Dodonoveb877eb2012-03-29 12:32:20 -03002672#define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
Ville Syrjäläc2699522015-08-27 23:55:59 +03002673#define HAS_PCH_LPT_LP(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
Ville Syrjälä56f5f702015-11-30 16:23:44 +02002674#define HAS_PCH_LPT_H(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
Zou Nan haicae58522010-11-09 17:17:32 +08002675#define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
2676#define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
Ben Widawsky40c7ead2013-04-05 13:12:40 -07002677#define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
Paulo Zanoni45e6e3a2012-07-03 15:57:32 -03002678#define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
Zou Nan haicae58522010-11-09 17:17:32 +08002679
Wayne Boyer666a4532015-12-09 12:29:35 -08002680#define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || \
2681 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
Sonika Jindal5fafe292014-07-21 15:23:38 +05302682
Ben Widawsky040d2ba2013-09-19 11:01:40 -07002683/* DPF == dynamic parity feature */
2684#define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
2685#define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
Ben Widawskye1ef7cc2012-07-24 20:47:31 -07002686
Ben Widawskyc8735b02012-09-07 19:43:39 -07002687#define GT_FREQUENCY_MULTIPLIER 50
Akash Goelde43ae92015-03-06 11:07:14 +05302688#define GEN9_FREQ_SCALER 3
Ben Widawskyc8735b02012-09-07 19:43:39 -07002689
Chris Wilson05394f32010-11-08 19:18:58 +00002690#include "i915_trace.h"
2691
Rob Clarkbaa70942013-08-02 13:27:49 -04002692extern const struct drm_ioctl_desc i915_ioctls[];
Dave Airlieb3a83632005-09-30 18:37:36 +10002693extern int i915_max_ioctl;
2694
Maarten Lankhorst1751fcf2015-08-27 15:15:15 +02002695extern int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state);
2696extern int i915_resume_switcheroo(struct drm_device *dev);
Dave Airlie7c1c2872008-11-28 14:22:24 +10002697
Joonas Lahtinenc838d712015-12-18 13:08:15 +02002698/* i915_dma.c */
Dave Airlie22eae942005-11-10 22:16:34 +11002699extern int i915_driver_load(struct drm_device *, unsigned long flags);
Jesse Barnesba8bbcf2007-11-22 14:14:14 +10002700extern int i915_driver_unload(struct drm_device *);
John Harrison2885f6a2014-06-26 18:23:52 +01002701extern int i915_driver_open(struct drm_device *dev, struct drm_file *file);
Dave Airlie84b1fd12007-07-11 15:53:27 +10002702extern void i915_driver_lastclose(struct drm_device * dev);
Eric Anholt6c340ea2007-08-25 20:23:09 +10002703extern void i915_driver_preclose(struct drm_device *dev,
John Harrison2885f6a2014-06-26 18:23:52 +01002704 struct drm_file *file);
Eric Anholt673a3942008-07-30 12:06:12 -07002705extern void i915_driver_postclose(struct drm_device *dev,
John Harrison2885f6a2014-06-26 18:23:52 +01002706 struct drm_file *file);
Ben Widawskyc43b5632012-04-16 14:07:40 -07002707#ifdef CONFIG_COMPAT
Dave Airlie0d6aa602006-01-02 20:14:23 +11002708extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
2709 unsigned long arg);
Ben Widawskyc43b5632012-04-16 14:07:40 -07002710#endif
Mika Kuoppalaee4b6fa2016-03-16 17:54:00 +02002711extern int intel_gpu_reset(struct drm_device *dev, u32 engine_mask);
Chris Wilson49e4d842015-06-15 12:23:48 +01002712extern bool intel_has_gpu_reset(struct drm_device *dev);
Daniel Vetterd4b8bb22012-04-27 15:17:44 +02002713extern int i915_reset(struct drm_device *dev);
Jesse Barnes7648fa92010-05-20 14:28:11 -07002714extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
2715extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
2716extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
2717extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
Imre Deak650ad972014-04-18 16:35:02 +03002718int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
Jesse Barnes7648fa92010-05-20 14:28:11 -07002719
Jani Nikula77913b32015-06-18 13:06:16 +03002720/* intel_hotplug.c */
2721void intel_hpd_irq_handler(struct drm_device *dev, u32 pin_mask, u32 long_mask);
2722void intel_hpd_init(struct drm_i915_private *dev_priv);
2723void intel_hpd_init_work(struct drm_i915_private *dev_priv);
2724void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
Imre Deakcc24fcd2015-07-21 15:32:45 -07002725bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port);
Jani Nikula77913b32015-06-18 13:06:16 +03002726
Linus Torvalds1da177e2005-04-16 15:20:36 -07002727/* i915_irq.c */
Mika Kuoppala10cd45b2013-07-03 17:22:08 +03002728void i915_queue_hangcheck(struct drm_device *dev);
Mika Kuoppala58174462014-02-25 17:11:26 +02002729__printf(3, 4)
2730void i915_handle_error(struct drm_device *dev, bool wedged,
2731 const char *fmt, ...);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002732
Daniel Vetterb9632912014-09-30 10:56:44 +02002733extern void intel_irq_init(struct drm_i915_private *dev_priv);
Daniel Vetter2aeb7d32014-09-30 10:56:43 +02002734int intel_irq_install(struct drm_i915_private *dev_priv);
2735void intel_irq_uninstall(struct drm_i915_private *dev_priv);
Chris Wilson907b28c2013-07-19 20:36:52 +01002736
2737extern void intel_uncore_sanitize(struct drm_device *dev);
Imre Deak10018602014-06-06 12:59:39 +03002738extern void intel_uncore_early_sanitize(struct drm_device *dev,
2739 bool restore_forcewake);
Chris Wilson907b28c2013-07-19 20:36:52 +01002740extern void intel_uncore_init(struct drm_device *dev);
Mika Kuoppalafc976182015-12-15 16:25:07 +02002741extern bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv);
Mika Kuoppalabc3b9342016-01-08 15:51:20 +02002742extern bool intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv);
Chris Wilsonaec347a2013-08-26 13:46:09 +01002743extern void intel_uncore_fini(struct drm_device *dev);
Jesse Barnes156c7ca2014-06-12 08:35:45 -07002744extern void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore);
Mika Kuoppala48c10262015-01-16 11:34:41 +02002745const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);
Mika Kuoppala59bad942015-01-16 11:34:40 +02002746void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
Mika Kuoppala48c10262015-01-16 11:34:41 +02002747 enum forcewake_domains domains);
Mika Kuoppala59bad942015-01-16 11:34:40 +02002748void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
Mika Kuoppala48c10262015-01-16 11:34:41 +02002749 enum forcewake_domains domains);
Chris Wilsona6111f72015-04-07 16:21:02 +01002750/* Like above but the caller must manage the uncore.lock itself.
2751 * Must be used with I915_READ_FW and friends.
2752 */
2753void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
2754 enum forcewake_domains domains);
2755void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
2756 enum forcewake_domains domains);
Mika Kuoppala59bad942015-01-16 11:34:40 +02002757void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);
Yu Zhangcf9d2892015-02-10 19:05:47 +08002758static inline bool intel_vgpu_active(struct drm_device *dev)
2759{
2760 return to_i915(dev)->vgpu.active;
2761}
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07002762
Keith Packard7c463582008-11-04 02:03:27 -08002763void
Jani Nikula50227e12014-03-31 14:27:21 +03002764i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
Imre Deak755e9012014-02-10 18:42:47 +02002765 u32 status_mask);
Keith Packard7c463582008-11-04 02:03:27 -08002766
2767void
Jani Nikula50227e12014-03-31 14:27:21 +03002768i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
Imre Deak755e9012014-02-10 18:42:47 +02002769 u32 status_mask);
Keith Packard7c463582008-11-04 02:03:27 -08002770
Imre Deakf8b79e52014-03-04 19:23:07 +02002771void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
2772void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
Egbert Eich0706f172015-09-23 16:15:27 +02002773void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
2774 uint32_t mask,
2775 uint32_t bits);
Ville Syrjäläfbdedaea2015-11-23 18:06:16 +02002776void ilk_update_display_irq(struct drm_i915_private *dev_priv,
2777 uint32_t interrupt_mask,
2778 uint32_t enabled_irq_mask);
2779static inline void
2780ilk_enable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
2781{
2782 ilk_update_display_irq(dev_priv, bits, bits);
2783}
2784static inline void
2785ilk_disable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
2786{
2787 ilk_update_display_irq(dev_priv, bits, 0);
2788}
Ville Syrjälä013d3752015-11-23 18:06:17 +02002789void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
2790 enum pipe pipe,
2791 uint32_t interrupt_mask,
2792 uint32_t enabled_irq_mask);
2793static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv,
2794 enum pipe pipe, uint32_t bits)
2795{
2796 bdw_update_pipe_irq(dev_priv, pipe, bits, bits);
2797}
2798static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv,
2799 enum pipe pipe, uint32_t bits)
2800{
2801 bdw_update_pipe_irq(dev_priv, pipe, bits, 0);
2802}
Daniel Vetter47339cd2014-09-30 10:56:46 +02002803void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
2804 uint32_t interrupt_mask,
2805 uint32_t enabled_irq_mask);
Ville Syrjälä14443262015-11-23 18:06:15 +02002806static inline void
2807ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
2808{
2809 ibx_display_interrupt_update(dev_priv, bits, bits);
2810}
2811static inline void
2812ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
2813{
2814 ibx_display_interrupt_update(dev_priv, bits, 0);
2815}
2816
Imre Deakf8b79e52014-03-04 19:23:07 +02002817
Eric Anholt673a3942008-07-30 12:06:12 -07002818/* i915_gem.c */
Eric Anholt673a3942008-07-30 12:06:12 -07002819int i915_gem_create_ioctl(struct drm_device *dev, void *data,
2820 struct drm_file *file_priv);
2821int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
2822 struct drm_file *file_priv);
2823int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2824 struct drm_file *file_priv);
2825int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
2826 struct drm_file *file_priv);
Jesse Barnesde151cf2008-11-12 10:03:55 -08002827int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2828 struct drm_file *file_priv);
Eric Anholt673a3942008-07-30 12:06:12 -07002829int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2830 struct drm_file *file_priv);
2831int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
2832 struct drm_file *file_priv);
Oscar Mateoba8b7cc2014-07-24 17:04:33 +01002833void i915_gem_execbuffer_move_to_active(struct list_head *vmas,
John Harrison8a8edb52015-05-29 17:43:33 +01002834 struct drm_i915_gem_request *req);
John Harrisonadeca762015-05-29 17:43:28 +01002835void i915_gem_execbuffer_retire_commands(struct i915_execbuffer_params *params);
John Harrison5f19e2b2015-05-29 17:43:27 +01002836int i915_gem_ringbuffer_submission(struct i915_execbuffer_params *params,
Oscar Mateoa83014d2014-07-24 17:04:21 +01002837 struct drm_i915_gem_execbuffer2 *args,
John Harrison5f19e2b2015-05-29 17:43:27 +01002838 struct list_head *vmas);
Eric Anholt673a3942008-07-30 12:06:12 -07002839int i915_gem_execbuffer(struct drm_device *dev, void *data,
2840 struct drm_file *file_priv);
Jesse Barnes76446ca2009-12-17 22:05:42 -05002841int i915_gem_execbuffer2(struct drm_device *dev, void *data,
2842 struct drm_file *file_priv);
Eric Anholt673a3942008-07-30 12:06:12 -07002843int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
2844 struct drm_file *file_priv);
Ben Widawsky199adf42012-09-21 17:01:20 -07002845int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
2846 struct drm_file *file);
2847int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
2848 struct drm_file *file);
Eric Anholt673a3942008-07-30 12:06:12 -07002849int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
2850 struct drm_file *file_priv);
Chris Wilson3ef94da2009-09-14 16:50:29 +01002851int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
2852 struct drm_file *file_priv);
Eric Anholt673a3942008-07-30 12:06:12 -07002853int i915_gem_set_tiling(struct drm_device *dev, void *data,
2854 struct drm_file *file_priv);
2855int i915_gem_get_tiling(struct drm_device *dev, void *data,
2856 struct drm_file *file_priv);
Chris Wilson5cc9ed42014-05-16 14:22:37 +01002857int i915_gem_init_userptr(struct drm_device *dev);
2858int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
2859 struct drm_file *file);
Eric Anholt5a125c32008-10-22 21:40:13 -07002860int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
2861 struct drm_file *file_priv);
Ben Widawsky23ba4fd2012-05-24 15:03:10 -07002862int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
2863 struct drm_file *file_priv);
Imre Deakd64aa092016-01-19 15:26:29 +02002864void i915_gem_load_init(struct drm_device *dev);
2865void i915_gem_load_cleanup(struct drm_device *dev);
Imre Deak40ae4e12016-03-16 14:54:03 +02002866void i915_gem_load_init_fences(struct drm_i915_private *dev_priv);
Chris Wilson42dcedd2012-11-15 11:32:30 +00002867void *i915_gem_object_alloc(struct drm_device *dev);
2868void i915_gem_object_free(struct drm_i915_gem_object *obj);
Chris Wilson37e680a2012-06-07 15:38:42 +01002869void i915_gem_object_init(struct drm_i915_gem_object *obj,
2870 const struct drm_i915_gem_object_ops *ops);
Chris Wilson05394f32010-11-08 19:18:58 +00002871struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
2872 size_t size);
Dave Gordonea702992015-07-09 19:29:02 +01002873struct drm_i915_gem_object *i915_gem_object_create_from_data(
2874 struct drm_device *dev, const void *data, size_t size);
Eric Anholt673a3942008-07-30 12:06:12 -07002875void i915_gem_free_object(struct drm_gem_object *obj);
Ben Widawsky2f633152013-07-17 12:19:03 -07002876void i915_gem_vma_destroy(struct i915_vma *vma);
Chris Wilson42dcedd2012-11-15 11:32:30 +00002877
Daniel Vetter08755462015-04-20 09:04:05 -07002878/* Flags used by pin/bind&friends. */
2879#define PIN_MAPPABLE (1<<0)
2880#define PIN_NONBLOCK (1<<1)
2881#define PIN_GLOBAL (1<<2)
2882#define PIN_OFFSET_BIAS (1<<3)
2883#define PIN_USER (1<<4)
2884#define PIN_UPDATE (1<<5)
Michel Thierry101b5062015-10-01 13:33:57 +01002885#define PIN_ZONE_4G (1<<6)
2886#define PIN_HIGH (1<<7)
Chris Wilson506a8e82015-12-08 11:55:07 +00002887#define PIN_OFFSET_FIXED (1<<8)
Chris Wilsond23db882014-05-23 08:48:08 +02002888#define PIN_OFFSET_MASK (~4095)
Joonas Lahtinenec7adb62015-03-16 14:11:13 +02002889int __must_check
2890i915_gem_object_pin(struct drm_i915_gem_object *obj,
2891 struct i915_address_space *vm,
2892 uint32_t alignment,
2893 uint64_t flags);
2894int __must_check
2895i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
2896 const struct i915_ggtt_view *view,
2897 uint32_t alignment,
2898 uint64_t flags);
Tvrtko Ursulinfe14d5f2014-12-10 17:27:58 +00002899
2900int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
2901 u32 flags);
Chris Wilsond0710ab2015-11-20 14:16:39 +00002902void __i915_vma_set_map_and_fenceable(struct i915_vma *vma);
Ben Widawsky07fe0b12013-07-31 17:00:10 -07002903int __must_check i915_vma_unbind(struct i915_vma *vma);
Tvrtko Ursuline9f24d52015-10-05 13:26:36 +01002904/*
2905 * BEWARE: Do not use the function below unless you can _absolutely_
2906 * _guarantee_ VMA in question is _not in use_ anywhere.
2907 */
2908int __must_check __i915_vma_unbind_no_wait(struct i915_vma *vma);
Chris Wilsondd624af2013-01-15 12:39:35 +00002909int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
Paulo Zanoni48018a52013-12-13 15:22:31 -02002910void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv);
Chris Wilson05394f32010-11-08 19:18:58 +00002911void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
Chris Wilsonf787a5f2010-09-24 16:02:42 +01002912
Brad Volkin4c914c02014-02-18 10:15:45 -08002913int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
2914 int *needs_clflush);
2915
Chris Wilson37e680a2012-06-07 15:38:42 +01002916int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
Chris Wilsonee286372015-04-07 16:20:25 +01002917
2918static inline int __sg_page_count(struct scatterlist *sg)
Chris Wilson9da3da62012-06-01 15:20:22 +01002919{
Chris Wilsonee286372015-04-07 16:20:25 +01002920 return sg->length >> PAGE_SHIFT;
Chris Wilson9da3da62012-06-01 15:20:22 +01002921}
Chris Wilsonee286372015-04-07 16:20:25 +01002922
Dave Gordon033908a2015-12-10 18:51:23 +00002923struct page *
2924i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj, int n);
2925
Chris Wilsonee286372015-04-07 16:20:25 +01002926static inline struct page *
2927i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
2928{
2929 if (WARN_ON(n >= obj->base.size >> PAGE_SHIFT))
2930 return NULL;
2931
2932 if (n < obj->get_page.last) {
2933 obj->get_page.sg = obj->pages->sgl;
2934 obj->get_page.last = 0;
2935 }
2936
2937 while (obj->get_page.last + __sg_page_count(obj->get_page.sg) <= n) {
2938 obj->get_page.last += __sg_page_count(obj->get_page.sg++);
2939 if (unlikely(sg_is_chain(obj->get_page.sg)))
2940 obj->get_page.sg = sg_chain_ptr(obj->get_page.sg);
2941 }
2942
2943 return nth_page(sg_page(obj->get_page.sg), n - obj->get_page.last);
2944}
2945
Chris Wilsona5570172012-09-04 21:02:54 +01002946static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
2947{
2948 BUG_ON(obj->pages == NULL);
2949 obj->pages_pin_count++;
2950}
2951static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
2952{
2953 BUG_ON(obj->pages_pin_count == 0);
2954 obj->pages_pin_count--;
2955}
2956
Chris Wilson54cf91d2010-11-25 18:00:26 +00002957int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
Ben Widawsky2911a352012-04-05 14:47:36 -07002958int i915_gem_object_sync(struct drm_i915_gem_object *obj,
John Harrison91af1272015-06-18 13:14:56 +01002959 struct intel_engine_cs *to,
2960 struct drm_i915_gem_request **to_req);
Ben Widawskye2d05a82013-09-24 09:57:58 -07002961void i915_vma_move_to_active(struct i915_vma *vma,
John Harrisonb2af0372015-05-29 17:43:50 +01002962 struct drm_i915_gem_request *req);
Dave Airlieff72145b2011-02-07 12:16:14 +10002963int i915_gem_dumb_create(struct drm_file *file_priv,
2964 struct drm_device *dev,
2965 struct drm_mode_create_dumb *args);
Dave Airlieda6b51d2014-12-24 13:11:17 +10002966int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
2967 uint32_t handle, uint64_t *offset);
Chris Wilsonf787a5f2010-09-24 16:02:42 +01002968/**
2969 * Returns true if seq1 is later than seq2.
2970 */
2971static inline bool
2972i915_seqno_passed(uint32_t seq1, uint32_t seq2)
2973{
2974 return (int32_t)(seq1 - seq2) >= 0;
2975}
2976
Chris Wilson821485d2015-12-11 11:32:59 +00002977static inline bool i915_gem_request_started(struct drm_i915_gem_request *req,
2978 bool lazy_coherency)
2979{
Tvrtko Ursulin4a570db2016-03-16 11:00:38 +00002980 u32 seqno = req->engine->get_seqno(req->engine, lazy_coherency);
Chris Wilson821485d2015-12-11 11:32:59 +00002981 return i915_seqno_passed(seqno, req->previous_seqno);
2982}
2983
John Harrison1b5a4332014-11-24 18:49:42 +00002984static inline bool i915_gem_request_completed(struct drm_i915_gem_request *req,
2985 bool lazy_coherency)
2986{
Tvrtko Ursulin4a570db2016-03-16 11:00:38 +00002987 u32 seqno = req->engine->get_seqno(req->engine, lazy_coherency);
John Harrison1b5a4332014-11-24 18:49:42 +00002988 return i915_seqno_passed(seqno, req->seqno);
2989}
2990
Mika Kuoppalafca26bb2012-12-19 11:13:08 +02002991int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
2992int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
Chris Wilson1690e1e2011-12-14 13:57:08 +01002993
Chris Wilson8d9fc7f2014-02-25 17:11:23 +02002994struct drm_i915_gem_request *
Tvrtko Ursulin0bc40be2016-03-16 11:00:37 +00002995i915_gem_find_active_request(struct intel_engine_cs *engine);
Chris Wilson8d9fc7f2014-02-25 17:11:23 +02002996
Chris Wilsonb29c19b2013-09-25 17:34:56 +01002997bool i915_gem_retire_requests(struct drm_device *dev);
Tvrtko Ursulin0bc40be2016-03-16 11:00:37 +00002998void i915_gem_retire_requests_ring(struct intel_engine_cs *engine);
Daniel Vetter33196de2012-11-14 17:14:05 +01002999int __must_check i915_gem_check_wedge(struct i915_gpu_error *error,
Daniel Vetterd6b2c792012-07-04 22:54:13 +02003000 bool interruptible);
Sourab Gupta84c33a62014-06-02 16:47:17 +05303001
Daniel Vetter1f83fee2012-11-15 17:17:22 +01003002static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
3003{
3004 return unlikely(atomic_read(&error->reset_counter)
Mika Kuoppala2ac0f452013-11-12 14:44:19 +02003005 & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED));
Daniel Vetter1f83fee2012-11-15 17:17:22 +01003006}
3007
3008static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
3009{
Mika Kuoppala2ac0f452013-11-12 14:44:19 +02003010 return atomic_read(&error->reset_counter) & I915_WEDGED;
3011}
3012
3013static inline u32 i915_reset_count(struct i915_gpu_error *error)
3014{
3015 return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2;
Daniel Vetter1f83fee2012-11-15 17:17:22 +01003016}
Chris Wilsona71d8d92012-02-15 11:25:36 +00003017
Mika Kuoppala88b4aa82014-03-28 18:18:18 +02003018static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv)
3019{
3020 return dev_priv->gpu_error.stop_rings == 0 ||
3021 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_BAN;
3022}
3023
3024static inline bool i915_stop_ring_allow_warn(struct drm_i915_private *dev_priv)
3025{
3026 return dev_priv->gpu_error.stop_rings == 0 ||
3027 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_WARN;
3028}
3029
Chris Wilson069efc12010-09-30 16:53:18 +01003030void i915_gem_reset(struct drm_device *dev);
Chris Wilson000433b2013-08-08 14:41:09 +01003031bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
Chris Wilson1070a422012-04-24 15:47:41 +01003032int __must_check i915_gem_init(struct drm_device *dev);
Tvrtko Ursulin117897f2016-03-16 11:00:40 +00003033int i915_gem_init_engines(struct drm_device *dev);
Daniel Vetterf691e2f2012-02-02 09:58:12 +01003034int __must_check i915_gem_init_hw(struct drm_device *dev);
John Harrison6909a662015-05-29 17:43:51 +01003035int i915_gem_l3_remap(struct drm_i915_gem_request *req, int slice);
Daniel Vetterf691e2f2012-02-02 09:58:12 +01003036void i915_gem_init_swizzling(struct drm_device *dev);
Tvrtko Ursulin117897f2016-03-16 11:00:40 +00003037void i915_gem_cleanup_engines(struct drm_device *dev);
Ben Widawskyb2da9fe2012-04-26 16:02:58 -07003038int __must_check i915_gpu_idle(struct drm_device *dev);
Chris Wilson45c5f202013-10-16 11:50:01 +01003039int __must_check i915_gem_suspend(struct drm_device *dev);
John Harrison75289872015-05-29 17:43:49 +01003040void __i915_add_request(struct drm_i915_gem_request *req,
John Harrison5b4a60c2015-05-29 17:43:34 +01003041 struct drm_i915_gem_object *batch_obj,
3042 bool flush_caches);
John Harrison75289872015-05-29 17:43:49 +01003043#define i915_add_request(req) \
John Harrisonfcfa423c2015-05-29 17:44:12 +01003044 __i915_add_request(req, NULL, true)
John Harrison75289872015-05-29 17:43:49 +01003045#define i915_add_request_no_flush(req) \
John Harrisonfcfa423c2015-05-29 17:44:12 +01003046 __i915_add_request(req, NULL, false)
John Harrison9c654812014-11-24 18:49:35 +00003047int __i915_wait_request(struct drm_i915_gem_request *req,
Ander Conselvan de Oliveira16e9a212014-11-06 09:26:38 +02003048 unsigned reset_counter,
3049 bool interruptible,
3050 s64 *timeout,
Chris Wilson2e1b8732015-04-27 13:41:22 +01003051 struct intel_rps_client *rps);
Daniel Vettera4b3a572014-11-26 14:17:05 +01003052int __must_check i915_wait_request(struct drm_i915_gem_request *req);
Jesse Barnesde151cf2008-11-12 10:03:55 -08003053int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
Chris Wilson20217462010-11-23 15:26:33 +00003054int __must_check
Chris Wilson2e2f3512015-04-27 13:41:14 +01003055i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
3056 bool readonly);
3057int __must_check
Chris Wilson20217462010-11-23 15:26:33 +00003058i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
3059 bool write);
3060int __must_check
Chris Wilsondabdfe02012-03-26 10:10:27 +02003061i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
3062int __must_check
Chris Wilson2da3b9b2011-04-14 09:41:17 +01003063i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3064 u32 alignment,
Tvrtko Ursuline6617332015-03-23 11:10:33 +00003065 const struct i915_ggtt_view *view);
3066void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj,
3067 const struct i915_ggtt_view *view);
Chris Wilson00731152014-05-21 12:42:56 +01003068int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
Chris Wilson6eeefaf2010-08-07 11:01:39 +01003069 int align);
Chris Wilsonb29c19b2013-09-25 17:34:56 +01003070int i915_gem_open(struct drm_device *dev, struct drm_file *file);
Chris Wilson05394f32010-11-08 19:18:58 +00003071void i915_gem_release(struct drm_device *dev, struct drm_file *file);
Eric Anholt673a3942008-07-30 12:06:12 -07003072
Chris Wilson467cffb2011-03-07 10:42:03 +00003073uint32_t
Imre Deak0fa87792013-01-07 21:47:35 +02003074i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
3075uint32_t
Imre Deakd8651102013-01-07 21:47:33 +02003076i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
3077 int tiling_mode, bool fenced);
Chris Wilson467cffb2011-03-07 10:42:03 +00003078
Chris Wilsone4ffd172011-04-04 09:44:39 +01003079int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3080 enum i915_cache_level cache_level);
3081
Daniel Vetter1286ff72012-05-10 15:25:09 +02003082struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
3083 struct dma_buf *dma_buf);
3084
3085struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
3086 struct drm_gem_object *gem_obj, int flags);
3087
Michel Thierry088e0df2015-08-07 17:40:17 +01003088u64 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o,
3089 const struct i915_ggtt_view *view);
3090u64 i915_gem_obj_offset(struct drm_i915_gem_object *o,
3091 struct i915_address_space *vm);
3092static inline u64
Joonas Lahtinenec7adb62015-03-16 14:11:13 +02003093i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *o)
Tvrtko Ursulinfe14d5f2014-12-10 17:27:58 +00003094{
Joonas Lahtinen9abc4642015-03-27 13:09:22 +02003095 return i915_gem_obj_ggtt_offset_view(o, &i915_ggtt_view_normal);
Tvrtko Ursulinfe14d5f2014-12-10 17:27:58 +00003096}
Joonas Lahtinenec7adb62015-03-16 14:11:13 +02003097
Ben Widawskya70a3142013-07-31 16:59:56 -07003098bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o);
Joonas Lahtinenec7adb62015-03-16 14:11:13 +02003099bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o,
Joonas Lahtinen9abc4642015-03-27 13:09:22 +02003100 const struct i915_ggtt_view *view);
Ben Widawskya70a3142013-07-31 16:59:56 -07003101bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
Joonas Lahtinenec7adb62015-03-16 14:11:13 +02003102 struct i915_address_space *vm);
Tvrtko Ursulinfe14d5f2014-12-10 17:27:58 +00003103
Ben Widawskya70a3142013-07-31 16:59:56 -07003104unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
3105 struct i915_address_space *vm);
Tvrtko Ursulinfe14d5f2014-12-10 17:27:58 +00003106struct i915_vma *
Joonas Lahtinenec7adb62015-03-16 14:11:13 +02003107i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
3108 struct i915_address_space *vm);
3109struct i915_vma *
3110i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj,
3111 const struct i915_ggtt_view *view);
Tvrtko Ursulinfe14d5f2014-12-10 17:27:58 +00003112
Ben Widawskyaccfef22013-08-14 11:38:35 +02003113struct i915_vma *
3114i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
Joonas Lahtinenec7adb62015-03-16 14:11:13 +02003115 struct i915_address_space *vm);
3116struct i915_vma *
3117i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj,
3118 const struct i915_ggtt_view *view);
Ben Widawsky5c2abbe2013-09-24 09:57:57 -07003119
Joonas Lahtinenec7adb62015-03-16 14:11:13 +02003120static inline struct i915_vma *
3121i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj)
3122{
3123 return i915_gem_obj_to_ggtt_view(obj, &i915_ggtt_view_normal);
Ben Widawskyd7f46fc2013-12-06 14:10:55 -08003124}
Joonas Lahtinenec7adb62015-03-16 14:11:13 +02003125bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj);
Ben Widawsky5c2abbe2013-09-24 09:57:57 -07003126
Ben Widawskya70a3142013-07-31 16:59:56 -07003127/* Some GGTT VM helpers */
Daniel Vetter5dc383b2014-08-06 15:04:49 +02003128#define i915_obj_to_ggtt(obj) \
Ben Widawskya70a3142013-07-31 16:59:56 -07003129 (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
Ben Widawskya70a3142013-07-31 16:59:56 -07003130
Daniel Vetter841cd772014-08-06 15:04:48 +02003131static inline struct i915_hw_ppgtt *
3132i915_vm_to_ppgtt(struct i915_address_space *vm)
3133{
3134 WARN_ON(i915_is_ggtt(vm));
Daniel Vetter841cd772014-08-06 15:04:48 +02003135 return container_of(vm, struct i915_hw_ppgtt, base);
3136}
3137
3138
Ben Widawskya70a3142013-07-31 16:59:56 -07003139static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj)
3140{
Joonas Lahtinen9abc4642015-03-27 13:09:22 +02003141 return i915_gem_obj_ggtt_bound_view(obj, &i915_ggtt_view_normal);
Ben Widawskya70a3142013-07-31 16:59:56 -07003142}
3143
3144static inline unsigned long
3145i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj)
3146{
Daniel Vetter5dc383b2014-08-06 15:04:49 +02003147 return i915_gem_obj_size(obj, i915_obj_to_ggtt(obj));
Ben Widawskya70a3142013-07-31 16:59:56 -07003148}
Ben Widawskyc37e2202013-07-31 16:59:58 -07003149
3150static inline int __must_check
3151i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj,
3152 uint32_t alignment,
Daniel Vetter1ec9e262014-02-14 14:01:11 +01003153 unsigned flags)
Ben Widawskyc37e2202013-07-31 16:59:58 -07003154{
Daniel Vetter5dc383b2014-08-06 15:04:49 +02003155 return i915_gem_object_pin(obj, i915_obj_to_ggtt(obj),
3156 alignment, flags | PIN_GLOBAL);
Ben Widawskyc37e2202013-07-31 16:59:58 -07003157}
Ben Widawskya70a3142013-07-31 16:59:56 -07003158
Daniel Vetterb2871102014-02-14 14:01:19 +01003159static inline int
3160i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj)
3161{
3162 return i915_vma_unbind(i915_gem_obj_to_ggtt(obj));
3163}
3164
Tvrtko Ursuline6617332015-03-23 11:10:33 +00003165void i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj,
3166 const struct i915_ggtt_view *view);
3167static inline void
3168i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj)
3169{
3170 i915_gem_object_ggtt_unpin_view(obj, &i915_ggtt_view_normal);
3171}
Daniel Vetterb2871102014-02-14 14:01:19 +01003172
Daniel Vetter41a36b72015-07-24 13:55:11 +02003173/* i915_gem_fence.c */
3174int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
3175int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
3176
3177bool i915_gem_object_pin_fence(struct drm_i915_gem_object *obj);
3178void i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj);
3179
3180void i915_gem_restore_fences(struct drm_device *dev);
3181
Daniel Vetter7f96eca2015-07-24 17:40:14 +02003182void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
3183void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
3184void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
3185
Ben Widawsky254f9652012-06-04 14:42:42 -07003186/* i915_gem_context.c */
Ben Widawsky8245be32013-11-06 13:56:29 -02003187int __must_check i915_gem_context_init(struct drm_device *dev);
Ben Widawsky254f9652012-06-04 14:42:42 -07003188void i915_gem_context_fini(struct drm_device *dev);
Ben Widawskyacce9ff2013-12-06 14:11:03 -08003189void i915_gem_context_reset(struct drm_device *dev);
Ben Widawskye422b882013-12-06 14:10:58 -08003190int i915_gem_context_open(struct drm_device *dev, struct drm_file *file);
John Harrisonb3dd6b92015-05-29 17:43:40 +01003191int i915_gem_context_enable(struct drm_i915_gem_request *req);
Ben Widawsky254f9652012-06-04 14:42:42 -07003192void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
John Harrisonba01cc92015-05-29 17:43:41 +01003193int i915_switch_context(struct drm_i915_gem_request *req);
Oscar Mateo273497e2014-05-22 14:13:37 +01003194struct intel_context *
Ben Widawsky41bde552013-12-06 14:11:21 -08003195i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id);
Mika Kuoppaladce32712013-04-30 13:30:33 +03003196void i915_gem_context_free(struct kref *ctx_ref);
Oscar Mateo8c8579172014-07-24 17:04:14 +01003197struct drm_i915_gem_object *
3198i915_gem_alloc_context_obj(struct drm_device *dev, size_t size);
Oscar Mateo273497e2014-05-22 14:13:37 +01003199static inline void i915_gem_context_reference(struct intel_context *ctx)
Mika Kuoppaladce32712013-04-30 13:30:33 +03003200{
Chris Wilson691e6412014-04-09 09:07:36 +01003201 kref_get(&ctx->ref);
Mika Kuoppaladce32712013-04-30 13:30:33 +03003202}
3203
Oscar Mateo273497e2014-05-22 14:13:37 +01003204static inline void i915_gem_context_unreference(struct intel_context *ctx)
Mika Kuoppaladce32712013-04-30 13:30:33 +03003205{
Chris Wilson691e6412014-04-09 09:07:36 +01003206 kref_put(&ctx->ref, i915_gem_context_free);
Mika Kuoppaladce32712013-04-30 13:30:33 +03003207}
3208
Oscar Mateo273497e2014-05-22 14:13:37 +01003209static inline bool i915_gem_context_is_default(const struct intel_context *c)
Mika Kuoppala3fac8972014-01-30 16:05:48 +02003210{
Oscar Mateo821d66d2014-07-03 16:28:00 +01003211 return c->user_handle == DEFAULT_CONTEXT_HANDLE;
Mika Kuoppala3fac8972014-01-30 16:05:48 +02003212}
3213
Ben Widawsky84624812012-06-04 14:42:54 -07003214int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
3215 struct drm_file *file);
3216int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
3217 struct drm_file *file);
Chris Wilsonc9dc0f32014-12-24 08:13:40 -08003218int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
3219 struct drm_file *file_priv);
3220int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data,
3221 struct drm_file *file_priv);
Daniel Vetter1286ff72012-05-10 15:25:09 +02003222
Chris Wilsonb47eb4a2010-08-07 11:01:23 +01003223/* i915_gem_evict.c */
Ben Widawskyf6cd1f12013-07-31 17:00:11 -07003224int __must_check i915_gem_evict_something(struct drm_device *dev,
3225 struct i915_address_space *vm,
3226 int min_size,
Chris Wilson42d6ab42012-07-26 11:49:32 +01003227 unsigned alignment,
3228 unsigned cache_level,
Chris Wilsond23db882014-05-23 08:48:08 +02003229 unsigned long start,
3230 unsigned long end,
Daniel Vetter1ec9e262014-02-14 14:01:11 +01003231 unsigned flags);
Chris Wilson506a8e82015-12-08 11:55:07 +00003232int __must_check i915_gem_evict_for_vma(struct i915_vma *target);
Ben Widawsky68c8c172013-09-11 14:57:50 -07003233int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
Chris Wilsonb47eb4a2010-08-07 11:01:23 +01003234
Ben Widawsky0260c422014-03-22 22:47:21 -07003235/* belongs in i915_gem_gtt.h */
Eric Anholt673a3942008-07-30 12:06:12 -07003236static inline void i915_gem_chipset_flush(struct drm_device *dev)
3237{
Chris Wilson05394f32010-11-08 19:18:58 +00003238 if (INTEL_INFO(dev)->gen < 6)
3239 intel_gtt_chipset_flush();
Chris Wilson9797fbf2012-04-24 15:47:39 +01003240}
Ben Widawsky246cbfb2013-12-06 14:11:14 -08003241
Chris Wilson9797fbf2012-04-24 15:47:39 +01003242/* i915_gem_stolen.c */
Paulo Zanonid713fd42015-07-02 19:25:07 -03003243int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
3244 struct drm_mm_node *node, u64 size,
3245 unsigned alignment);
Paulo Zanonia9da5122015-09-14 15:19:57 -03003246int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
3247 struct drm_mm_node *node, u64 size,
3248 unsigned alignment, u64 start,
3249 u64 end);
Paulo Zanonid713fd42015-07-02 19:25:07 -03003250void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
3251 struct drm_mm_node *node);
Chris Wilson9797fbf2012-04-24 15:47:39 +01003252int i915_gem_init_stolen(struct drm_device *dev);
3253void i915_gem_cleanup_stolen(struct drm_device *dev);
Chris Wilson0104fdb2012-11-15 11:32:26 +00003254struct drm_i915_gem_object *
3255i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
Chris Wilson866d12b2013-02-19 13:31:37 -08003256struct drm_i915_gem_object *
3257i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
3258 u32 stolen_offset,
3259 u32 gtt_offset,
3260 u32 size);
Chris Wilson9797fbf2012-04-24 15:47:39 +01003261
Daniel Vetterbe6a0372015-03-18 10:46:04 +01003262/* i915_gem_shrinker.c */
3263unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv,
Chris Wilson14387542015-10-01 12:18:25 +01003264 unsigned long target,
Daniel Vetterbe6a0372015-03-18 10:46:04 +01003265 unsigned flags);
3266#define I915_SHRINK_PURGEABLE 0x1
3267#define I915_SHRINK_UNBOUND 0x2
3268#define I915_SHRINK_BOUND 0x4
Chris Wilson5763ff02015-10-01 12:18:29 +01003269#define I915_SHRINK_ACTIVE 0x8
Daniel Vetterbe6a0372015-03-18 10:46:04 +01003270unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
3271void i915_gem_shrinker_init(struct drm_i915_private *dev_priv);
Imre Deaka8a40582016-01-19 15:26:28 +02003272void i915_gem_shrinker_cleanup(struct drm_i915_private *dev_priv);
Daniel Vetterbe6a0372015-03-18 10:46:04 +01003273
3274
Eric Anholt673a3942008-07-30 12:06:12 -07003275/* i915_gem_tiling.c */
Chris Wilson2c1792a2013-08-01 18:39:55 +01003276static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
Chris Wilsone9b73c62012-12-03 21:03:14 +00003277{
Jani Nikula50227e12014-03-31 14:27:21 +03003278 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
Chris Wilsone9b73c62012-12-03 21:03:14 +00003279
3280 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
3281 obj->tiling_mode != I915_TILING_NONE;
3282}
3283
Eric Anholt673a3942008-07-30 12:06:12 -07003284/* i915_gem_debug.c */
Chris Wilson23bc5982010-09-29 16:10:57 +01003285#if WATCH_LISTS
3286int i915_verify_lists(struct drm_device *dev);
Eric Anholt673a3942008-07-30 12:06:12 -07003287#else
Chris Wilson23bc5982010-09-29 16:10:57 +01003288#define i915_verify_lists(dev) 0
Eric Anholt673a3942008-07-30 12:06:12 -07003289#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07003290
Ben Gamari20172632009-02-17 20:08:50 -05003291/* i915_debugfs.c */
Ben Gamari27c202a2009-07-01 22:26:52 -04003292int i915_debugfs_init(struct drm_minor *minor);
3293void i915_debugfs_cleanup(struct drm_minor *minor);
Daniel Vetterf8c168f2013-10-16 11:49:58 +02003294#ifdef CONFIG_DEBUG_FS
Jani Nikula249e87d2015-04-10 16:59:32 +03003295int i915_debugfs_connector_add(struct drm_connector *connector);
Damien Lespiau07144422013-10-15 18:55:40 +01003296void intel_display_crc_init(struct drm_device *dev);
3297#else
Daniel Vetter101057f2015-07-13 09:23:19 +02003298static inline int i915_debugfs_connector_add(struct drm_connector *connector)
3299{ return 0; }
Daniel Vetterf8c168f2013-10-16 11:49:58 +02003300static inline void intel_display_crc_init(struct drm_device *dev) {}
Damien Lespiau07144422013-10-15 18:55:40 +01003301#endif
Mika Kuoppala84734a02013-07-12 16:50:57 +03003302
3303/* i915_gpu_error.c */
Mika Kuoppalaedc3d882013-05-23 13:55:35 +03003304__printf(2, 3)
3305void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
Mika Kuoppalafc16b482013-06-06 15:18:39 +03003306int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
3307 const struct i915_error_state_file_priv *error);
Mika Kuoppala4dc955f2013-06-06 15:18:41 +03003308int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
Chris Wilson0a4cd7c2014-08-22 14:41:39 +01003309 struct drm_i915_private *i915,
Mika Kuoppala4dc955f2013-06-06 15:18:41 +03003310 size_t count, loff_t pos);
3311static inline void i915_error_state_buf_release(
3312 struct drm_i915_error_state_buf *eb)
3313{
3314 kfree(eb->buf);
3315}
Mika Kuoppala58174462014-02-25 17:11:26 +02003316void i915_capture_error_state(struct drm_device *dev, bool wedge,
3317 const char *error_msg);
Mika Kuoppala84734a02013-07-12 16:50:57 +03003318void i915_error_state_get(struct drm_device *dev,
3319 struct i915_error_state_file_priv *error_priv);
3320void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
3321void i915_destroy_error_state(struct drm_device *dev);
3322
3323void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone);
Chris Wilson0a4cd7c2014-08-22 14:41:39 +01003324const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
Ben Gamari20172632009-02-17 20:08:50 -05003325
Brad Volkin351e3db2014-02-18 10:15:46 -08003326/* i915_cmd_parser.c */
Brad Volkind728c8e2014-02-18 10:15:56 -08003327int i915_cmd_parser_get_version(void);
Tvrtko Ursulin0bc40be2016-03-16 11:00:37 +00003328int i915_cmd_parser_init_ring(struct intel_engine_cs *engine);
3329void i915_cmd_parser_fini_ring(struct intel_engine_cs *engine);
3330bool i915_needs_cmd_parser(struct intel_engine_cs *engine);
3331int i915_parse_cmds(struct intel_engine_cs *engine,
Brad Volkin351e3db2014-02-18 10:15:46 -08003332 struct drm_i915_gem_object *batch_obj,
Brad Volkin78a42372014-12-11 12:13:09 -08003333 struct drm_i915_gem_object *shadow_batch_obj,
Brad Volkin351e3db2014-02-18 10:15:46 -08003334 u32 batch_start_offset,
Brad Volkinb9ffd802014-12-11 12:13:10 -08003335 u32 batch_len,
Brad Volkin351e3db2014-02-18 10:15:46 -08003336 bool is_master);
3337
Jesse Barnes317c35d2008-08-25 15:11:06 -07003338/* i915_suspend.c */
3339extern int i915_save_state(struct drm_device *dev);
3340extern int i915_restore_state(struct drm_device *dev);
3341
Ben Widawsky0136db582012-04-10 21:17:01 -07003342/* i915_sysfs.c */
3343void i915_setup_sysfs(struct drm_device *dev_priv);
3344void i915_teardown_sysfs(struct drm_device *dev_priv);
3345
Chris Wilsonf899fc62010-07-20 15:44:45 -07003346/* intel_i2c.c */
3347extern int intel_setup_gmbus(struct drm_device *dev);
3348extern void intel_teardown_gmbus(struct drm_device *dev);
Jani Nikula88ac7932015-03-27 00:20:22 +02003349extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
3350 unsigned int pin);
Daniel Kurtz3bd7d902012-03-28 02:36:14 +08003351
Jani Nikula0184df42015-03-27 00:20:20 +02003352extern struct i2c_adapter *
3353intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
Chris Wilsone957d772010-09-24 12:52:03 +01003354extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
3355extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
Jan-Simon Möller8f375e12013-05-06 14:52:08 +02003356static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
Chris Wilsonb8232e92010-09-28 16:41:32 +01003357{
3358 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
3359}
Chris Wilsonf899fc62010-07-20 15:44:45 -07003360extern void intel_i2c_reset(struct drm_device *dev);
3361
Jani Nikula8b8e1a82015-12-14 12:50:49 +02003362/* intel_bios.c */
Jani Nikula98f3a1d2015-12-16 15:04:20 +02003363int intel_bios_init(struct drm_i915_private *dev_priv);
Jani Nikulaf0067a32015-12-15 13:16:15 +02003364bool intel_bios_is_valid_vbt(const void *buf, size_t size);
Jani Nikula3bdd14d2016-03-16 12:43:29 +02003365bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv);
Jani Nikula5a69d132016-03-16 12:43:30 +02003366bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin);
Jani Nikula951d9ef2016-03-16 12:43:31 +02003367bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
Jani Nikula7137aec2016-03-16 12:43:32 +02003368bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv, enum port *port);
Jani Nikula8b8e1a82015-12-14 12:50:49 +02003369
Chris Wilson3b617962010-08-24 09:02:58 +01003370/* intel_opregion.c */
Chris Wilson44834a62010-08-19 16:09:23 +01003371#ifdef CONFIG_ACPI
Lv Zheng27d50c82013-12-06 16:52:05 +08003372extern int intel_opregion_setup(struct drm_device *dev);
Chris Wilson44834a62010-08-19 16:09:23 +01003373extern void intel_opregion_init(struct drm_device *dev);
3374extern void intel_opregion_fini(struct drm_device *dev);
Chris Wilson3b617962010-08-24 09:02:58 +01003375extern void intel_opregion_asle_intr(struct drm_device *dev);
Jani Nikula9c4b0a62013-08-30 19:40:30 +03003376extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
3377 bool enable);
Jani Nikulaecbc5cf2013-08-30 19:40:31 +03003378extern int intel_opregion_notify_adapter(struct drm_device *dev,
3379 pci_power_t state);
Len Brown65e082c2008-10-24 17:18:10 -04003380#else
Lv Zheng27d50c82013-12-06 16:52:05 +08003381static inline int intel_opregion_setup(struct drm_device *dev) { return 0; }
Chris Wilson44834a62010-08-19 16:09:23 +01003382static inline void intel_opregion_init(struct drm_device *dev) { return; }
3383static inline void intel_opregion_fini(struct drm_device *dev) { return; }
Chris Wilson3b617962010-08-24 09:02:58 +01003384static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
Jani Nikula9c4b0a62013-08-30 19:40:30 +03003385static inline int
3386intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
3387{
3388 return 0;
3389}
Jani Nikulaecbc5cf2013-08-30 19:40:31 +03003390static inline int
3391intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state)
3392{
3393 return 0;
3394}
Len Brown65e082c2008-10-24 17:18:10 -04003395#endif
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +01003396
Jesse Barnes723bfd72010-10-07 16:01:13 -07003397/* intel_acpi.c */
3398#ifdef CONFIG_ACPI
3399extern void intel_register_dsm_handler(void);
3400extern void intel_unregister_dsm_handler(void);
3401#else
3402static inline void intel_register_dsm_handler(void) { return; }
3403static inline void intel_unregister_dsm_handler(void) { return; }
3404#endif /* CONFIG_ACPI */
3405
Jesse Barnes79e53942008-11-07 14:24:08 -08003406/* modesetting */
Daniel Vetterf8175862012-04-10 15:50:11 +02003407extern void intel_modeset_init_hw(struct drm_device *dev);
Jesse Barnes79e53942008-11-07 14:24:08 -08003408extern void intel_modeset_init(struct drm_device *dev);
Chris Wilson2c7111d2011-03-29 10:40:27 +01003409extern void intel_modeset_gem_init(struct drm_device *dev);
Jesse Barnes79e53942008-11-07 14:24:08 -08003410extern void intel_modeset_cleanup(struct drm_device *dev);
Imre Deak4932e2c2014-02-11 17:12:48 +02003411extern void intel_connector_unregister(struct intel_connector *);
Dave Airlie28d52042009-09-21 14:33:58 +10003412extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
Maarten Lankhorst043e9bd2015-07-13 16:30:25 +02003413extern void intel_display_resume(struct drm_device *dev);
Daniel Vetter44cec742013-01-25 17:53:21 +01003414extern void i915_redisable_vga(struct drm_device *dev);
Imre Deak04098752014-02-18 00:02:16 +02003415extern void i915_redisable_vga_power_on(struct drm_device *dev);
Jesse Barnes7648fa92010-05-20 14:28:11 -07003416extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
Paulo Zanonidde86e22012-12-01 12:04:25 -02003417extern void intel_init_pch_refclk(struct drm_device *dev);
Ville Syrjäläffe02b42015-02-02 19:09:50 +02003418extern void intel_set_rps(struct drm_device *dev, u8 val);
Imre Deak5209b1f2014-07-01 12:36:17 +03003419extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
3420 bool enable);
Akshay Joshi0206e352011-08-16 15:34:10 -04003421extern void intel_detect_pch(struct drm_device *dev);
Ben Widawsky0136db582012-04-10 21:17:01 -07003422extern int intel_enable_rc6(const struct drm_device *dev);
Zhenyu Wang3bad0782010-04-07 16:15:53 +08003423
Ben Widawsky2911a352012-04-05 14:47:36 -07003424extern bool i915_semaphore_is_enabled(struct drm_device *dev);
Ben Widawskyc0c7bab2012-07-12 11:01:05 -07003425int i915_reg_read_ioctl(struct drm_device *dev, void *data,
3426 struct drm_file *file);
Mika Kuoppalab6359912013-10-30 15:44:16 +02003427int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data,
3428 struct drm_file *file);
Jesse Barnes575155a2012-03-28 13:39:37 -07003429
Chris Wilson6ef3d422010-08-04 20:26:07 +01003430/* overlay */
3431extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
Mika Kuoppalaedc3d882013-05-23 13:55:35 +03003432extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
3433 struct intel_overlay_error_state *error);
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +00003434
3435extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
Mika Kuoppalaedc3d882013-05-23 13:55:35 +03003436extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +00003437 struct drm_device *dev,
3438 struct intel_display_error_state *error);
Chris Wilson6ef3d422010-08-04 20:26:07 +01003439
Tom O'Rourke151a49d2014-11-13 18:50:10 -08003440int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
3441int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val);
Jani Nikula59de0812013-05-22 15:36:16 +03003442
3443/* intel_sideband.c */
Deepak S707b6e32015-01-16 20:42:17 +05303444u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
3445void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
Jani Nikula64936252013-05-22 15:36:20 +03003446u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
Deepak Mdfb19ed2016-02-04 18:55:15 +02003447u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg);
3448void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, u8 port, u32 reg, u32 val);
Jani Nikulae9f882a2013-08-27 15:12:14 +03003449u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
3450void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3451u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
3452void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
Jesse Barnesf3419152013-11-04 11:52:44 -08003453u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
3454void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
Chon Ming Lee5e69f972013-09-05 20:41:49 +08003455u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
3456void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
Jani Nikula59de0812013-05-22 15:36:16 +03003457u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
3458 enum intel_sbi_destination destination);
3459void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
3460 enum intel_sbi_destination destination);
Shobhit Kumare9fe51c2013-12-10 12:14:55 +05303461u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
3462void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
Jesse Barnes0a073b82013-04-17 15:54:58 -07003463
Ville Syrjälä616bc822015-01-23 21:04:25 +02003464int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
3465int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
Deepak Sc8d9a592013-11-23 14:55:42 +05303466
Ben Widawsky0b274482013-10-04 21:22:51 -07003467#define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3468#define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
Keith Packard5f753772010-11-22 09:24:22 +00003469
Ben Widawsky0b274482013-10-04 21:22:51 -07003470#define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3471#define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3472#define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3473#define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
Keith Packard5f753772010-11-22 09:24:22 +00003474
Ben Widawsky0b274482013-10-04 21:22:51 -07003475#define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3476#define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3477#define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3478#define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
Keith Packard5f753772010-11-22 09:24:22 +00003479
Chris Wilson698b3132014-03-21 13:16:43 +00003480/* Be very careful with read/write 64-bit values. On 32-bit machines, they
3481 * will be implemented using 2 32-bit writes in an arbitrary order with
3482 * an arbitrary delay between them. This can cause the hardware to
3483 * act upon the intermediate value, possibly leading to corruption and
3484 * machine death. You have been warned.
3485 */
Ben Widawsky0b274482013-10-04 21:22:51 -07003486#define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
3487#define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
Zou Nan haicae58522010-11-09 17:17:32 +08003488
Chris Wilson50877442014-03-21 12:41:53 +00003489#define I915_READ64_2x32(lower_reg, upper_reg) ({ \
Chris Wilsonacd29f72015-09-08 14:17:13 +01003490 u32 upper, lower, old_upper, loop = 0; \
3491 upper = I915_READ(upper_reg); \
Chris Wilsonee0a2272015-07-15 09:50:42 +01003492 do { \
Chris Wilsonacd29f72015-09-08 14:17:13 +01003493 old_upper = upper; \
Chris Wilsonee0a2272015-07-15 09:50:42 +01003494 lower = I915_READ(lower_reg); \
Chris Wilsonacd29f72015-09-08 14:17:13 +01003495 upper = I915_READ(upper_reg); \
3496 } while (upper != old_upper && loop++ < 2); \
Chris Wilsonee0a2272015-07-15 09:50:42 +01003497 (u64)upper << 32 | lower; })
Chris Wilson50877442014-03-21 12:41:53 +00003498
Zou Nan haicae58522010-11-09 17:17:32 +08003499#define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
3500#define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
3501
Ville Syrjälä75aa3f62015-10-22 15:34:56 +03003502#define __raw_read(x, s) \
3503static inline uint##x##_t __raw_i915_read##x(struct drm_i915_private *dev_priv, \
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003504 i915_reg_t reg) \
Ville Syrjälä75aa3f62015-10-22 15:34:56 +03003505{ \
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003506 return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
Ville Syrjälä75aa3f62015-10-22 15:34:56 +03003507}
3508
3509#define __raw_write(x, s) \
3510static inline void __raw_i915_write##x(struct drm_i915_private *dev_priv, \
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003511 i915_reg_t reg, uint##x##_t val) \
Ville Syrjälä75aa3f62015-10-22 15:34:56 +03003512{ \
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003513 write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
Ville Syrjälä75aa3f62015-10-22 15:34:56 +03003514}
3515__raw_read(8, b)
3516__raw_read(16, w)
3517__raw_read(32, l)
3518__raw_read(64, q)
3519
3520__raw_write(8, b)
3521__raw_write(16, w)
3522__raw_write(32, l)
3523__raw_write(64, q)
3524
3525#undef __raw_read
3526#undef __raw_write
3527
Chris Wilsona6111f72015-04-07 16:21:02 +01003528/* These are untraced mmio-accessors that are only valid to be used inside
3529 * criticial sections inside IRQ handlers where forcewake is explicitly
3530 * controlled.
3531 * Think twice, and think again, before using these.
3532 * Note: Should only be used between intel_uncore_forcewake_irqlock() and
3533 * intel_uncore_forcewake_irqunlock().
3534 */
Ville Syrjälä75aa3f62015-10-22 15:34:56 +03003535#define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
3536#define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
Chris Wilsona6111f72015-04-07 16:21:02 +01003537#define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
3538
Ville Syrjälä55bc60d2013-01-17 16:31:29 +02003539/* "Broadcast RGB" property */
3540#define INTEL_BROADCAST_RGB_AUTO 0
3541#define INTEL_BROADCAST_RGB_FULL 1
3542#define INTEL_BROADCAST_RGB_LIMITED 2
Yuanhan Liuba4f01a2010-11-08 17:09:41 +08003543
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02003544static inline i915_reg_t i915_vgacntrl_reg(struct drm_device *dev)
Ville Syrjälä766aa1c2013-01-25 21:44:46 +02003545{
Wayne Boyer666a4532015-12-09 12:29:35 -08003546 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
Ville Syrjälä766aa1c2013-01-25 21:44:46 +02003547 return VLV_VGACNTRL;
Sonika Jindal92e23b92014-07-21 15:23:40 +05303548 else if (INTEL_INFO(dev)->gen >= 5)
3549 return CPU_VGACNTRL;
Ville Syrjälä766aa1c2013-01-25 21:44:46 +02003550 else
3551 return VGACNTRL;
3552}
3553
Ville Syrjälä2bb46292013-02-22 16:12:51 +02003554static inline void __user *to_user_ptr(u64 address)
3555{
3556 return (void __user *)(uintptr_t)address;
3557}
3558
Imre Deakdf977292013-05-21 20:03:17 +03003559static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
3560{
3561 unsigned long j = msecs_to_jiffies(m);
3562
3563 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3564}
3565
Daniel Vetter7bd0e222014-12-04 11:12:54 +01003566static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
3567{
3568 return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
3569}
3570
Imre Deakdf977292013-05-21 20:03:17 +03003571static inline unsigned long
3572timespec_to_jiffies_timeout(const struct timespec *value)
3573{
3574 unsigned long j = timespec_to_jiffies(value);
3575
3576 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3577}
3578
Paulo Zanonidce56b32013-12-19 14:29:40 -02003579/*
3580 * If you need to wait X milliseconds between events A and B, but event B
3581 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
3582 * when event A happened, then just before event B you call this function and
3583 * pass the timestamp as the first argument, and X as the second argument.
3584 */
3585static inline void
3586wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
3587{
Imre Deakec5e0cf2014-01-29 13:25:40 +02003588 unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
Paulo Zanonidce56b32013-12-19 14:29:40 -02003589
3590 /*
3591 * Don't re-read the value of "jiffies" every time since it may change
3592 * behind our back and break the math.
3593 */
3594 tmp_jiffies = jiffies;
3595 target_jiffies = timestamp_jiffies +
3596 msecs_to_jiffies_timeout(to_wait_ms);
3597
3598 if (time_after(target_jiffies, tmp_jiffies)) {
Imre Deakec5e0cf2014-01-29 13:25:40 +02003599 remaining_jiffies = target_jiffies - tmp_jiffies;
3600 while (remaining_jiffies)
3601 remaining_jiffies =
3602 schedule_timeout_uninterruptible(remaining_jiffies);
Paulo Zanonidce56b32013-12-19 14:29:40 -02003603 }
3604}
3605
Tvrtko Ursulin0bc40be2016-03-16 11:00:37 +00003606static inline void i915_trace_irq_get(struct intel_engine_cs *engine,
John Harrison581c26e82014-11-24 18:49:39 +00003607 struct drm_i915_gem_request *req)
3608{
Tvrtko Ursulin0bc40be2016-03-16 11:00:37 +00003609 if (engine->trace_irq_req == NULL && engine->irq_get(engine))
3610 i915_gem_request_assign(&engine->trace_irq_req, req);
John Harrison581c26e82014-11-24 18:49:39 +00003611}
3612
Linus Torvalds1da177e2005-04-16 15:20:36 -07003613#endif