blob: 4c51377934317190bc38738eb0b79d6739c464b4 [file] [log] [blame]
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +02001/*
Anatolij Gustschine39d5ef2010-08-09 07:58:48 +02002 * GPIOs on MPC512x/8349/8572/8610 and compatible
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +02003 *
4 * Copyright (C) 2008 Peter Korsgaard <jacmet@sunsite.dk>
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/spinlock.h>
14#include <linux/io.h>
15#include <linux/of.h>
16#include <linux/of_gpio.h>
Rob Herring5af50732013-09-17 14:28:33 -050017#include <linux/of_irq.h>
Ricardo Ribalda Delgado98686d9a52015-01-18 12:39:32 +010018#include <linux/of_platform.h>
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +020019#include <linux/gpio.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090020#include <linux/slab.h>
Peter Korsgaard345e5c82010-01-07 17:57:46 +010021#include <linux/irq.h>
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +020022
23#define MPC8XXX_GPIO_PINS 32
24
25#define GPIO_DIR 0x00
26#define GPIO_ODR 0x04
27#define GPIO_DAT 0x08
28#define GPIO_IER 0x0c
29#define GPIO_IMR 0x10
30#define GPIO_ICR 0x14
Anatolij Gustschine39d5ef2010-08-09 07:58:48 +020031#define GPIO_ICR2 0x18
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +020032
33struct mpc8xxx_gpio_chip {
34 struct of_mm_gpio_chip mm_gc;
35 spinlock_t lock;
36
37 /*
38 * shadowed data register to be able to clear/set output pins in
39 * open drain mode safely
40 */
41 u32 data;
Grant Likelybae1d8f2012-02-14 14:06:50 -070042 struct irq_domain *irq;
Ricardo Ribalda Delgado257e1072015-01-18 12:39:33 +010043 unsigned int irqn;
Uwe Kleine-König01a04dd2012-05-21 21:57:39 +020044 const void *of_dev_id_data;
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +020045};
46
47static inline u32 mpc8xxx_gpio2mask(unsigned int gpio)
48{
49 return 1u << (MPC8XXX_GPIO_PINS - 1 - gpio);
50}
51
52static inline struct mpc8xxx_gpio_chip *
53to_mpc8xxx_gpio_chip(struct of_mm_gpio_chip *mm)
54{
55 return container_of(mm, struct mpc8xxx_gpio_chip, mm_gc);
56}
57
58static void mpc8xxx_gpio_save_regs(struct of_mm_gpio_chip *mm)
59{
60 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
61
62 mpc8xxx_gc->data = in_be32(mm->regs + GPIO_DAT);
63}
64
Felix Radenskyc1a676d2009-08-12 08:57:39 +030065/* Workaround GPIO 1 errata on MPC8572/MPC8536. The status of GPIOs
66 * defined as output cannot be determined by reading GPDAT register,
67 * so we use shadow data register instead. The status of input pins
68 * is determined by reading GPDAT register.
69 */
70static int mpc8572_gpio_get(struct gpio_chip *gc, unsigned int gpio)
71{
72 u32 val;
73 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
74 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
Liu Gang1aeef302013-11-22 16:12:40 +080075 u32 out_mask, out_shadow;
Felix Radenskyc1a676d2009-08-12 08:57:39 +030076
Liu Gang1aeef302013-11-22 16:12:40 +080077 out_mask = in_be32(mm->regs + GPIO_DIR);
Felix Radenskyc1a676d2009-08-12 08:57:39 +030078
Liu Gang1aeef302013-11-22 16:12:40 +080079 val = in_be32(mm->regs + GPIO_DAT) & ~out_mask;
80 out_shadow = mpc8xxx_gc->data & out_mask;
81
82 return (val | out_shadow) & mpc8xxx_gpio2mask(gpio);
Felix Radenskyc1a676d2009-08-12 08:57:39 +030083}
84
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +020085static int mpc8xxx_gpio_get(struct gpio_chip *gc, unsigned int gpio)
86{
87 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
88
89 return in_be32(mm->regs + GPIO_DAT) & mpc8xxx_gpio2mask(gpio);
90}
91
92static void mpc8xxx_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
93{
94 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
95 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
96 unsigned long flags;
97
98 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
99
100 if (val)
101 mpc8xxx_gc->data |= mpc8xxx_gpio2mask(gpio);
102 else
103 mpc8xxx_gc->data &= ~mpc8xxx_gpio2mask(gpio);
104
105 out_be32(mm->regs + GPIO_DAT, mpc8xxx_gc->data);
106
107 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
108}
109
Rojhalat Ibrahime5db3b32014-11-04 17:12:09 +0100110static void mpc8xxx_gpio_set_multiple(struct gpio_chip *gc,
111 unsigned long *mask, unsigned long *bits)
112{
113 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
114 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
115 unsigned long flags;
116 int i;
117
118 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
119
120 for (i = 0; i < gc->ngpio; i++) {
121 if (*mask == 0)
122 break;
123 if (__test_and_clear_bit(i, mask)) {
124 if (test_bit(i, bits))
125 mpc8xxx_gc->data |= mpc8xxx_gpio2mask(i);
126 else
127 mpc8xxx_gc->data &= ~mpc8xxx_gpio2mask(i);
128 }
129 }
130
131 out_be32(mm->regs + GPIO_DAT, mpc8xxx_gc->data);
132
133 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
134}
135
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +0200136static int mpc8xxx_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
137{
138 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
139 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
140 unsigned long flags;
141
142 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
143
144 clrbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio));
145
146 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
147
148 return 0;
149}
150
151static int mpc8xxx_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
152{
153 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
154 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
155 unsigned long flags;
156
157 mpc8xxx_gpio_set(gc, gpio, val);
158
159 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
160
161 setbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio));
162
163 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
164
165 return 0;
166}
167
Wolfram Sang28538df2011-12-13 10:12:48 +0100168static int mpc5121_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
169{
170 /* GPIO 28..31 are input only on MPC5121 */
171 if (gpio >= 28)
172 return -EINVAL;
173
174 return mpc8xxx_gpio_dir_out(gc, gpio, val);
175}
176
Uwe Kleine-König0ba69e02015-07-16 21:08:23 +0200177static int mpc5125_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
178{
179 /* GPIO 0..3 are input only on MPC5125 */
180 if (gpio <= 3)
181 return -EINVAL;
182
183 return mpc8xxx_gpio_dir_out(gc, gpio, val);
184}
185
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100186static int mpc8xxx_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
187{
188 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
189 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
190
191 if (mpc8xxx_gc->irq && offset < MPC8XXX_GPIO_PINS)
192 return irq_create_mapping(mpc8xxx_gc->irq, offset);
193 else
194 return -ENXIO;
195}
196
197static void mpc8xxx_gpio_irq_cascade(unsigned int irq, struct irq_desc *desc)
198{
Thomas Gleixnerec775d02011-03-25 16:45:20 +0100199 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_desc_get_handler_data(desc);
Felix Radenskycfadd832011-10-11 10:24:21 +0200200 struct irq_chip *chip = irq_desc_get_chip(desc);
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100201 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
202 unsigned int mask;
203
204 mask = in_be32(mm->regs + GPIO_IER) & in_be32(mm->regs + GPIO_IMR);
205 if (mask)
206 generic_handle_irq(irq_linear_revmap(mpc8xxx_gc->irq,
207 32 - ffs(mask)));
Thomas Gleixnerd6de85e2012-05-03 12:22:06 +0200208 if (chip->irq_eoi)
209 chip->irq_eoi(&desc->irq_data);
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100210}
211
Lennert Buytenhek94347cb2011-03-08 22:26:58 +0000212static void mpc8xxx_irq_unmask(struct irq_data *d)
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100213{
Lennert Buytenhek94347cb2011-03-08 22:26:58 +0000214 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100215 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
216 unsigned long flags;
217
218 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
219
Grant Likely476eb492011-05-04 15:02:15 +1000220 setbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100221
222 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
223}
224
Lennert Buytenhek94347cb2011-03-08 22:26:58 +0000225static void mpc8xxx_irq_mask(struct irq_data *d)
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100226{
Lennert Buytenhek94347cb2011-03-08 22:26:58 +0000227 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100228 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
229 unsigned long flags;
230
231 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
232
Grant Likely476eb492011-05-04 15:02:15 +1000233 clrbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100234
235 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
236}
237
Lennert Buytenhek94347cb2011-03-08 22:26:58 +0000238static void mpc8xxx_irq_ack(struct irq_data *d)
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100239{
Lennert Buytenhek94347cb2011-03-08 22:26:58 +0000240 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100241 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
242
Grant Likely476eb492011-05-04 15:02:15 +1000243 out_be32(mm->regs + GPIO_IER, mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100244}
245
Lennert Buytenhek94347cb2011-03-08 22:26:58 +0000246static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type)
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100247{
Lennert Buytenhek94347cb2011-03-08 22:26:58 +0000248 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100249 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
250 unsigned long flags;
251
252 switch (flow_type) {
253 case IRQ_TYPE_EDGE_FALLING:
254 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
255 setbits32(mm->regs + GPIO_ICR,
Grant Likely476eb492011-05-04 15:02:15 +1000256 mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100257 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
258 break;
259
260 case IRQ_TYPE_EDGE_BOTH:
261 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
262 clrbits32(mm->regs + GPIO_ICR,
Grant Likely476eb492011-05-04 15:02:15 +1000263 mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100264 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
265 break;
266
267 default:
268 return -EINVAL;
269 }
270
271 return 0;
272}
273
Lennert Buytenhek94347cb2011-03-08 22:26:58 +0000274static int mpc512x_irq_set_type(struct irq_data *d, unsigned int flow_type)
Anatolij Gustschine39d5ef2010-08-09 07:58:48 +0200275{
Lennert Buytenhek94347cb2011-03-08 22:26:58 +0000276 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
Anatolij Gustschine39d5ef2010-08-09 07:58:48 +0200277 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
Grant Likely476eb492011-05-04 15:02:15 +1000278 unsigned long gpio = irqd_to_hwirq(d);
Anatolij Gustschine39d5ef2010-08-09 07:58:48 +0200279 void __iomem *reg;
280 unsigned int shift;
281 unsigned long flags;
282
283 if (gpio < 16) {
284 reg = mm->regs + GPIO_ICR;
285 shift = (15 - gpio) * 2;
286 } else {
287 reg = mm->regs + GPIO_ICR2;
288 shift = (15 - (gpio % 16)) * 2;
289 }
290
291 switch (flow_type) {
292 case IRQ_TYPE_EDGE_FALLING:
293 case IRQ_TYPE_LEVEL_LOW:
294 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
295 clrsetbits_be32(reg, 3 << shift, 2 << shift);
296 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
297 break;
298
299 case IRQ_TYPE_EDGE_RISING:
300 case IRQ_TYPE_LEVEL_HIGH:
301 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
302 clrsetbits_be32(reg, 3 << shift, 1 << shift);
303 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
304 break;
305
306 case IRQ_TYPE_EDGE_BOTH:
307 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
308 clrbits32(reg, 3 << shift);
309 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
310 break;
311
312 default:
313 return -EINVAL;
314 }
315
316 return 0;
317}
318
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100319static struct irq_chip mpc8xxx_irq_chip = {
320 .name = "mpc8xxx-gpio",
Lennert Buytenhek94347cb2011-03-08 22:26:58 +0000321 .irq_unmask = mpc8xxx_irq_unmask,
322 .irq_mask = mpc8xxx_irq_mask,
323 .irq_ack = mpc8xxx_irq_ack,
Uwe Kleine-König82e39b02015-07-16 21:08:22 +0200324 /* this might get overwritten in mpc8xxx_probe() */
Lennert Buytenhek94347cb2011-03-08 22:26:58 +0000325 .irq_set_type = mpc8xxx_irq_set_type,
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100326};
327
Linus Walleij5ba17ae2013-10-11 19:37:30 +0200328static int mpc8xxx_gpio_irq_map(struct irq_domain *h, unsigned int irq,
329 irq_hw_number_t hwirq)
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100330{
Linus Walleij5ba17ae2013-10-11 19:37:30 +0200331 irq_set_chip_data(irq, h->host_data);
332 irq_set_chip_and_handler(irq, &mpc8xxx_irq_chip, handle_level_irq);
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100333
334 return 0;
335}
336
Krzysztof Kozlowski0b354dc2015-04-27 21:54:07 +0900337static const struct irq_domain_ops mpc8xxx_gpio_irq_ops = {
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100338 .map = mpc8xxx_gpio_irq_map,
Grant Likelyff8c3ab2012-01-24 17:09:13 -0700339 .xlate = irq_domain_xlate_twocell,
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100340};
341
Uwe Kleine-König82e39b02015-07-16 21:08:22 +0200342struct mpc8xxx_gpio_devtype {
343 int (*gpio_dir_out)(struct gpio_chip *, unsigned int, int);
344 int (*gpio_get)(struct gpio_chip *, unsigned int);
345 int (*irq_set_type)(struct irq_data *, unsigned int);
346};
347
348static const struct mpc8xxx_gpio_devtype mpc512x_gpio_devtype = {
349 .gpio_dir_out = mpc5121_gpio_dir_out,
350 .irq_set_type = mpc512x_irq_set_type,
351};
352
Uwe Kleine-König0ba69e02015-07-16 21:08:23 +0200353static const struct mpc8xxx_gpio_devtype mpc5125_gpio_devtype = {
354 .gpio_dir_out = mpc5125_gpio_dir_out,
355 .irq_set_type = mpc512x_irq_set_type,
356};
357
Uwe Kleine-König82e39b02015-07-16 21:08:22 +0200358static const struct mpc8xxx_gpio_devtype mpc8572_gpio_devtype = {
359 .gpio_get = mpc8572_gpio_get,
360};
361
362static const struct mpc8xxx_gpio_devtype mpc8xxx_gpio_devtype_default = {
363 .gpio_dir_out = mpc8xxx_gpio_dir_out,
364 .gpio_get = mpc8xxx_gpio_get,
365 .irq_set_type = mpc8xxx_irq_set_type,
366};
367
Uwe Kleine-König4183afe2015-07-16 21:08:21 +0200368static const struct of_device_id mpc8xxx_gpio_ids[] = {
Anatolij Gustschine39d5ef2010-08-09 07:58:48 +0200369 { .compatible = "fsl,mpc8349-gpio", },
Uwe Kleine-König82e39b02015-07-16 21:08:22 +0200370 { .compatible = "fsl,mpc8572-gpio", .data = &mpc8572_gpio_devtype, },
Anatolij Gustschine39d5ef2010-08-09 07:58:48 +0200371 { .compatible = "fsl,mpc8610-gpio", },
Uwe Kleine-König82e39b02015-07-16 21:08:22 +0200372 { .compatible = "fsl,mpc5121-gpio", .data = &mpc512x_gpio_devtype, },
Uwe Kleine-König0ba69e02015-07-16 21:08:23 +0200373 { .compatible = "fsl,mpc5125-gpio", .data = &mpc5125_gpio_devtype, },
Kumar Gala15a51482011-10-22 16:20:42 -0500374 { .compatible = "fsl,pq3-gpio", },
Anatolij Gustschind1dcfbb2011-01-08 16:51:16 +0100375 { .compatible = "fsl,qoriq-gpio", },
Anatolij Gustschine39d5ef2010-08-09 07:58:48 +0200376 {}
377};
378
Ricardo Ribalda Delgado98686d9a52015-01-18 12:39:32 +0100379static int mpc8xxx_probe(struct platform_device *pdev)
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +0200380{
Ricardo Ribalda Delgado98686d9a52015-01-18 12:39:32 +0100381 struct device_node *np = pdev->dev.of_node;
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +0200382 struct mpc8xxx_gpio_chip *mpc8xxx_gc;
383 struct of_mm_gpio_chip *mm_gc;
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +0200384 struct gpio_chip *gc;
Anatolij Gustschine39d5ef2010-08-09 07:58:48 +0200385 const struct of_device_id *id;
Uwe Kleine-König82e39b02015-07-16 21:08:22 +0200386 const struct mpc8xxx_gpio_devtype *devtype =
387 of_device_get_match_data(&pdev->dev);
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +0200388 int ret;
389
Ricardo Ribalda Delgado98686d9a52015-01-18 12:39:32 +0100390 mpc8xxx_gc = devm_kzalloc(&pdev->dev, sizeof(*mpc8xxx_gc), GFP_KERNEL);
391 if (!mpc8xxx_gc)
392 return -ENOMEM;
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +0200393
Ricardo Ribalda Delgado257e1072015-01-18 12:39:33 +0100394 platform_set_drvdata(pdev, mpc8xxx_gc);
395
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +0200396 spin_lock_init(&mpc8xxx_gc->lock);
397
398 mm_gc = &mpc8xxx_gc->mm_gc;
Anton Vorontsova19e3da2010-06-08 07:48:16 -0600399 gc = &mm_gc->gc;
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +0200400
401 mm_gc->save_regs = mpc8xxx_gpio_save_regs;
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +0200402 gc->ngpio = MPC8XXX_GPIO_PINS;
403 gc->direction_input = mpc8xxx_gpio_dir_in;
Uwe Kleine-König82e39b02015-07-16 21:08:22 +0200404
405 if (!devtype)
406 devtype = &mpc8xxx_gpio_devtype_default;
407
408 /*
409 * It's assumed that only a single type of gpio controller is available
410 * on the current machine, so overwriting global data is fine.
411 */
412 mpc8xxx_irq_chip.irq_set_type = devtype->irq_set_type;
413
414 gc->direction_output = devtype->gpio_dir_out ?: mpc8xxx_gpio_dir_out;
415 gc->get = devtype->gpio_get ?: mpc8xxx_gpio_get;
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +0200416 gc->set = mpc8xxx_gpio_set;
Rojhalat Ibrahime5db3b32014-11-04 17:12:09 +0100417 gc->set_multiple = mpc8xxx_gpio_set_multiple;
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100418 gc->to_irq = mpc8xxx_gpio_to_irq;
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +0200419
420 ret = of_mm_gpiochip_add(np, mm_gc);
421 if (ret)
Ricardo Ribalda Delgado98686d9a52015-01-18 12:39:32 +0100422 return ret;
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +0200423
Ricardo Ribalda Delgado257e1072015-01-18 12:39:33 +0100424 mpc8xxx_gc->irqn = irq_of_parse_and_map(np, 0);
425 if (mpc8xxx_gc->irqn == NO_IRQ)
Ricardo Ribalda Delgado98686d9a52015-01-18 12:39:32 +0100426 return 0;
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100427
Grant Likelya8db8cf2012-02-14 14:06:54 -0700428 mpc8xxx_gc->irq = irq_domain_add_linear(np, MPC8XXX_GPIO_PINS,
429 &mpc8xxx_gpio_irq_ops, mpc8xxx_gc);
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100430 if (!mpc8xxx_gc->irq)
Ricardo Ribalda Delgado98686d9a52015-01-18 12:39:32 +0100431 return 0;
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100432
Anatolij Gustschine39d5ef2010-08-09 07:58:48 +0200433 id = of_match_node(mpc8xxx_gpio_ids, np);
434 if (id)
435 mpc8xxx_gc->of_dev_id_data = id->data;
436
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100437 /* ack and mask all irqs */
438 out_be32(mm_gc->regs + GPIO_IER, 0xffffffff);
439 out_be32(mm_gc->regs + GPIO_IMR, 0);
440
Thomas Gleixner05379812015-06-21 21:10:46 +0200441 irq_set_chained_handler_and_data(mpc8xxx_gc->irqn,
442 mpc8xxx_gpio_irq_cascade, mpc8xxx_gc);
Ricardo Ribalda Delgado257e1072015-01-18 12:39:33 +0100443
444 return 0;
445}
446
447static int mpc8xxx_remove(struct platform_device *pdev)
448{
449 struct mpc8xxx_gpio_chip *mpc8xxx_gc = platform_get_drvdata(pdev);
450
451 if (mpc8xxx_gc->irq) {
Thomas Gleixner05379812015-06-21 21:10:46 +0200452 irq_set_chained_handler_and_data(mpc8xxx_gc->irqn, NULL, NULL);
Ricardo Ribalda Delgado257e1072015-01-18 12:39:33 +0100453 irq_domain_remove(mpc8xxx_gc->irq);
454 }
455
456 of_mm_gpiochip_remove(&mpc8xxx_gc->mm_gc);
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100457
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +0200458 return 0;
459}
Ricardo Ribalda Delgado98686d9a52015-01-18 12:39:32 +0100460
461static struct platform_driver mpc8xxx_plat_driver = {
462 .probe = mpc8xxx_probe,
Ricardo Ribalda Delgado257e1072015-01-18 12:39:33 +0100463 .remove = mpc8xxx_remove,
Ricardo Ribalda Delgado98686d9a52015-01-18 12:39:32 +0100464 .driver = {
465 .name = "gpio-mpc8xxx",
466 .of_match_table = mpc8xxx_gpio_ids,
467 },
468};
469
470static int __init mpc8xxx_init(void)
471{
472 return platform_driver_register(&mpc8xxx_plat_driver);
473}
474
475arch_initcall(mpc8xxx_init);