Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* $Id: init.c,v 1.209 2002/02/09 19:49:31 davem Exp $ |
| 2 | * arch/sparc64/mm/init.c |
| 3 | * |
| 4 | * Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu) |
| 5 | * Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz) |
| 6 | */ |
| 7 | |
| 8 | #include <linux/config.h> |
| 9 | #include <linux/kernel.h> |
| 10 | #include <linux/sched.h> |
| 11 | #include <linux/string.h> |
| 12 | #include <linux/init.h> |
| 13 | #include <linux/bootmem.h> |
| 14 | #include <linux/mm.h> |
| 15 | #include <linux/hugetlb.h> |
| 16 | #include <linux/slab.h> |
| 17 | #include <linux/initrd.h> |
| 18 | #include <linux/swap.h> |
| 19 | #include <linux/pagemap.h> |
| 20 | #include <linux/fs.h> |
| 21 | #include <linux/seq_file.h> |
Prasanna S Panchamukhi | 05e14cb | 2005-09-06 15:19:30 -0700 | [diff] [blame] | 22 | #include <linux/kprobes.h> |
David S. Miller | 1ac4f5e | 2005-09-21 21:49:32 -0700 | [diff] [blame] | 23 | #include <linux/cache.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 24 | |
| 25 | #include <asm/head.h> |
| 26 | #include <asm/system.h> |
| 27 | #include <asm/page.h> |
| 28 | #include <asm/pgalloc.h> |
| 29 | #include <asm/pgtable.h> |
| 30 | #include <asm/oplib.h> |
| 31 | #include <asm/iommu.h> |
| 32 | #include <asm/io.h> |
| 33 | #include <asm/uaccess.h> |
| 34 | #include <asm/mmu_context.h> |
| 35 | #include <asm/tlbflush.h> |
| 36 | #include <asm/dma.h> |
| 37 | #include <asm/starfire.h> |
| 38 | #include <asm/tlb.h> |
| 39 | #include <asm/spitfire.h> |
| 40 | #include <asm/sections.h> |
| 41 | |
| 42 | extern void device_scan(void); |
| 43 | |
| 44 | struct sparc_phys_banks sp_banks[SPARC_PHYS_BANKS]; |
| 45 | |
| 46 | unsigned long *sparc64_valid_addr_bitmap; |
| 47 | |
| 48 | /* Ugly, but necessary... -DaveM */ |
David S. Miller | 1ac4f5e | 2005-09-21 21:49:32 -0700 | [diff] [blame] | 49 | unsigned long phys_base __read_mostly; |
| 50 | unsigned long kern_base __read_mostly; |
| 51 | unsigned long kern_size __read_mostly; |
| 52 | unsigned long pfn_base __read_mostly; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 53 | |
| 54 | /* This is even uglier. We have a problem where the kernel may not be |
| 55 | * located at phys_base. However, initial __alloc_bootmem() calls need to |
| 56 | * be adjusted to be within the 4-8Megs that the kernel is mapped to, else |
| 57 | * those page mappings wont work. Things are ok after inherit_prom_mappings |
| 58 | * is called though. Dave says he'll clean this up some other time. |
| 59 | * -- BenC |
| 60 | */ |
| 61 | static unsigned long bootmap_base; |
| 62 | |
| 63 | /* get_new_mmu_context() uses "cache + 1". */ |
| 64 | DEFINE_SPINLOCK(ctx_alloc_lock); |
| 65 | unsigned long tlb_context_cache = CTX_FIRST_VERSION - 1; |
| 66 | #define CTX_BMAP_SLOTS (1UL << (CTX_NR_BITS - 6)) |
| 67 | unsigned long mmu_context_bmap[CTX_BMAP_SLOTS]; |
| 68 | |
| 69 | /* References to special section boundaries */ |
| 70 | extern char _start[], _end[]; |
| 71 | |
| 72 | /* Initial ramdisk setup */ |
| 73 | extern unsigned long sparc_ramdisk_image64; |
| 74 | extern unsigned int sparc_ramdisk_image; |
| 75 | extern unsigned int sparc_ramdisk_size; |
| 76 | |
David S. Miller | 1ac4f5e | 2005-09-21 21:49:32 -0700 | [diff] [blame] | 77 | struct page *mem_map_zero __read_mostly; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 78 | |
| 79 | int bigkernel = 0; |
| 80 | |
| 81 | /* XXX Tune this... */ |
| 82 | #define PGT_CACHE_LOW 25 |
| 83 | #define PGT_CACHE_HIGH 50 |
| 84 | |
| 85 | void check_pgt_cache(void) |
| 86 | { |
| 87 | preempt_disable(); |
| 88 | if (pgtable_cache_size > PGT_CACHE_HIGH) { |
| 89 | do { |
| 90 | if (pgd_quicklist) |
| 91 | free_pgd_slow(get_pgd_fast()); |
| 92 | if (pte_quicklist[0]) |
| 93 | free_pte_slow(pte_alloc_one_fast(NULL, 0)); |
| 94 | if (pte_quicklist[1]) |
| 95 | free_pte_slow(pte_alloc_one_fast(NULL, 1 << (PAGE_SHIFT + 10))); |
| 96 | } while (pgtable_cache_size > PGT_CACHE_LOW); |
| 97 | } |
| 98 | preempt_enable(); |
| 99 | } |
| 100 | |
| 101 | #ifdef CONFIG_DEBUG_DCFLUSH |
| 102 | atomic_t dcpage_flushes = ATOMIC_INIT(0); |
| 103 | #ifdef CONFIG_SMP |
| 104 | atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0); |
| 105 | #endif |
| 106 | #endif |
| 107 | |
| 108 | __inline__ void flush_dcache_page_impl(struct page *page) |
| 109 | { |
| 110 | #ifdef CONFIG_DEBUG_DCFLUSH |
| 111 | atomic_inc(&dcpage_flushes); |
| 112 | #endif |
| 113 | |
| 114 | #ifdef DCACHE_ALIASING_POSSIBLE |
| 115 | __flush_dcache_page(page_address(page), |
| 116 | ((tlb_type == spitfire) && |
| 117 | page_mapping(page) != NULL)); |
| 118 | #else |
| 119 | if (page_mapping(page) != NULL && |
| 120 | tlb_type == spitfire) |
| 121 | __flush_icache_page(__pa(page_address(page))); |
| 122 | #endif |
| 123 | } |
| 124 | |
| 125 | #define PG_dcache_dirty PG_arch_1 |
David S. Miller | 48b0e54 | 2005-07-27 16:08:44 -0700 | [diff] [blame] | 126 | #define PG_dcache_cpu_shift 24 |
| 127 | #define PG_dcache_cpu_mask (256 - 1) |
| 128 | |
| 129 | #if NR_CPUS > 256 |
| 130 | #error D-cache dirty tracking and thread_info->cpu need fixing for > 256 cpus |
| 131 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 132 | |
| 133 | #define dcache_dirty_cpu(page) \ |
David S. Miller | 48b0e54 | 2005-07-27 16:08:44 -0700 | [diff] [blame] | 134 | (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 135 | |
| 136 | static __inline__ void set_dcache_dirty(struct page *page, int this_cpu) |
| 137 | { |
| 138 | unsigned long mask = this_cpu; |
David S. Miller | 48b0e54 | 2005-07-27 16:08:44 -0700 | [diff] [blame] | 139 | unsigned long non_cpu_bits; |
| 140 | |
| 141 | non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift); |
| 142 | mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty); |
| 143 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 144 | __asm__ __volatile__("1:\n\t" |
| 145 | "ldx [%2], %%g7\n\t" |
| 146 | "and %%g7, %1, %%g1\n\t" |
| 147 | "or %%g1, %0, %%g1\n\t" |
| 148 | "casx [%2], %%g7, %%g1\n\t" |
| 149 | "cmp %%g7, %%g1\n\t" |
David S. Miller | b445e26 | 2005-06-27 15:42:04 -0700 | [diff] [blame] | 150 | "membar #StoreLoad | #StoreStore\n\t" |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 151 | "bne,pn %%xcc, 1b\n\t" |
David S. Miller | b445e26 | 2005-06-27 15:42:04 -0700 | [diff] [blame] | 152 | " nop" |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 153 | : /* no outputs */ |
| 154 | : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags) |
| 155 | : "g1", "g7"); |
| 156 | } |
| 157 | |
| 158 | static __inline__ void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu) |
| 159 | { |
| 160 | unsigned long mask = (1UL << PG_dcache_dirty); |
| 161 | |
| 162 | __asm__ __volatile__("! test_and_clear_dcache_dirty\n" |
| 163 | "1:\n\t" |
| 164 | "ldx [%2], %%g7\n\t" |
David S. Miller | 48b0e54 | 2005-07-27 16:08:44 -0700 | [diff] [blame] | 165 | "srlx %%g7, %4, %%g1\n\t" |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 166 | "and %%g1, %3, %%g1\n\t" |
| 167 | "cmp %%g1, %0\n\t" |
| 168 | "bne,pn %%icc, 2f\n\t" |
| 169 | " andn %%g7, %1, %%g1\n\t" |
| 170 | "casx [%2], %%g7, %%g1\n\t" |
| 171 | "cmp %%g7, %%g1\n\t" |
David S. Miller | b445e26 | 2005-06-27 15:42:04 -0700 | [diff] [blame] | 172 | "membar #StoreLoad | #StoreStore\n\t" |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 173 | "bne,pn %%xcc, 1b\n\t" |
David S. Miller | b445e26 | 2005-06-27 15:42:04 -0700 | [diff] [blame] | 174 | " nop\n" |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 175 | "2:" |
| 176 | : /* no outputs */ |
| 177 | : "r" (cpu), "r" (mask), "r" (&page->flags), |
David S. Miller | 48b0e54 | 2005-07-27 16:08:44 -0700 | [diff] [blame] | 178 | "i" (PG_dcache_cpu_mask), |
| 179 | "i" (PG_dcache_cpu_shift) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 180 | : "g1", "g7"); |
| 181 | } |
| 182 | |
| 183 | extern void __update_mmu_cache(unsigned long mmu_context_hw, unsigned long address, pte_t pte, int code); |
| 184 | |
| 185 | void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte) |
| 186 | { |
| 187 | struct page *page; |
| 188 | unsigned long pfn; |
| 189 | unsigned long pg_flags; |
| 190 | |
| 191 | pfn = pte_pfn(pte); |
| 192 | if (pfn_valid(pfn) && |
| 193 | (page = pfn_to_page(pfn), page_mapping(page)) && |
| 194 | ((pg_flags = page->flags) & (1UL << PG_dcache_dirty))) { |
David S. Miller | 48b0e54 | 2005-07-27 16:08:44 -0700 | [diff] [blame] | 195 | int cpu = ((pg_flags >> PG_dcache_cpu_shift) & |
| 196 | PG_dcache_cpu_mask); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 197 | int this_cpu = get_cpu(); |
| 198 | |
| 199 | /* This is just to optimize away some function calls |
| 200 | * in the SMP case. |
| 201 | */ |
| 202 | if (cpu == this_cpu) |
| 203 | flush_dcache_page_impl(page); |
| 204 | else |
| 205 | smp_flush_dcache_page_impl(page, cpu); |
| 206 | |
| 207 | clear_dcache_dirty_cpu(page, cpu); |
| 208 | |
| 209 | put_cpu(); |
| 210 | } |
| 211 | |
| 212 | if (get_thread_fault_code()) |
| 213 | __update_mmu_cache(CTX_NRBITS(vma->vm_mm->context), |
| 214 | address, pte, get_thread_fault_code()); |
| 215 | } |
| 216 | |
| 217 | void flush_dcache_page(struct page *page) |
| 218 | { |
David S. Miller | a9546f5 | 2005-04-17 18:03:09 -0700 | [diff] [blame] | 219 | struct address_space *mapping; |
| 220 | int this_cpu; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 221 | |
David S. Miller | a9546f5 | 2005-04-17 18:03:09 -0700 | [diff] [blame] | 222 | /* Do not bother with the expensive D-cache flush if it |
| 223 | * is merely the zero page. The 'bigcore' testcase in GDB |
| 224 | * causes this case to run millions of times. |
| 225 | */ |
| 226 | if (page == ZERO_PAGE(0)) |
| 227 | return; |
| 228 | |
| 229 | this_cpu = get_cpu(); |
| 230 | |
| 231 | mapping = page_mapping(page); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 232 | if (mapping && !mapping_mapped(mapping)) { |
David S. Miller | a9546f5 | 2005-04-17 18:03:09 -0700 | [diff] [blame] | 233 | int dirty = test_bit(PG_dcache_dirty, &page->flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 234 | if (dirty) { |
David S. Miller | a9546f5 | 2005-04-17 18:03:09 -0700 | [diff] [blame] | 235 | int dirty_cpu = dcache_dirty_cpu(page); |
| 236 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 237 | if (dirty_cpu == this_cpu) |
| 238 | goto out; |
| 239 | smp_flush_dcache_page_impl(page, dirty_cpu); |
| 240 | } |
| 241 | set_dcache_dirty(page, this_cpu); |
| 242 | } else { |
| 243 | /* We could delay the flush for the !page_mapping |
| 244 | * case too. But that case is for exec env/arg |
| 245 | * pages and those are %99 certainly going to get |
| 246 | * faulted into the tlb (and thus flushed) anyways. |
| 247 | */ |
| 248 | flush_dcache_page_impl(page); |
| 249 | } |
| 250 | |
| 251 | out: |
| 252 | put_cpu(); |
| 253 | } |
| 254 | |
Prasanna S Panchamukhi | 05e14cb | 2005-09-06 15:19:30 -0700 | [diff] [blame] | 255 | void __kprobes flush_icache_range(unsigned long start, unsigned long end) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 256 | { |
| 257 | /* Cheetah has coherent I-cache. */ |
| 258 | if (tlb_type == spitfire) { |
| 259 | unsigned long kaddr; |
| 260 | |
| 261 | for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE) |
| 262 | __flush_icache_page(__get_phys(kaddr)); |
| 263 | } |
| 264 | } |
| 265 | |
| 266 | unsigned long page_to_pfn(struct page *page) |
| 267 | { |
| 268 | return (unsigned long) ((page - mem_map) + pfn_base); |
| 269 | } |
| 270 | |
| 271 | struct page *pfn_to_page(unsigned long pfn) |
| 272 | { |
| 273 | return (mem_map + (pfn - pfn_base)); |
| 274 | } |
| 275 | |
| 276 | void show_mem(void) |
| 277 | { |
| 278 | printk("Mem-info:\n"); |
| 279 | show_free_areas(); |
| 280 | printk("Free swap: %6ldkB\n", |
| 281 | nr_swap_pages << (PAGE_SHIFT-10)); |
| 282 | printk("%ld pages of RAM\n", num_physpages); |
| 283 | printk("%d free pages\n", nr_free_pages()); |
| 284 | printk("%d pages in page table cache\n",pgtable_cache_size); |
| 285 | } |
| 286 | |
| 287 | void mmu_info(struct seq_file *m) |
| 288 | { |
| 289 | if (tlb_type == cheetah) |
| 290 | seq_printf(m, "MMU Type\t: Cheetah\n"); |
| 291 | else if (tlb_type == cheetah_plus) |
| 292 | seq_printf(m, "MMU Type\t: Cheetah+\n"); |
| 293 | else if (tlb_type == spitfire) |
| 294 | seq_printf(m, "MMU Type\t: Spitfire\n"); |
| 295 | else |
| 296 | seq_printf(m, "MMU Type\t: ???\n"); |
| 297 | |
| 298 | #ifdef CONFIG_DEBUG_DCFLUSH |
| 299 | seq_printf(m, "DCPageFlushes\t: %d\n", |
| 300 | atomic_read(&dcpage_flushes)); |
| 301 | #ifdef CONFIG_SMP |
| 302 | seq_printf(m, "DCPageFlushesXC\t: %d\n", |
| 303 | atomic_read(&dcpage_flushes_xcall)); |
| 304 | #endif /* CONFIG_SMP */ |
| 305 | #endif /* CONFIG_DEBUG_DCFLUSH */ |
| 306 | } |
| 307 | |
| 308 | struct linux_prom_translation { |
| 309 | unsigned long virt; |
| 310 | unsigned long size; |
| 311 | unsigned long data; |
| 312 | }; |
David S. Miller | b206fc4 | 2005-09-21 22:31:13 -0700 | [diff] [blame] | 313 | static struct linux_prom_translation prom_trans[512] __initdata; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 314 | |
| 315 | extern unsigned long prom_boot_page; |
| 316 | extern void prom_remap(unsigned long physpage, unsigned long virtpage, int mmu_ihandle); |
| 317 | extern int prom_get_mmu_ihandle(void); |
| 318 | extern void register_prom_callbacks(void); |
| 319 | |
| 320 | /* Exported for SMP bootup purposes. */ |
| 321 | unsigned long kern_locked_tte_data; |
| 322 | |
David S. Miller | 1ac4f5e | 2005-09-21 21:49:32 -0700 | [diff] [blame] | 323 | /* Exported for kernel TLB miss handling in ktlb.S */ |
| 324 | unsigned long prom_pmd_phys __read_mostly; |
| 325 | unsigned int swapper_pgd_zero __read_mostly; |
| 326 | |
David S. Miller | 5085b4a | 2005-09-22 00:45:41 -0700 | [diff] [blame^] | 327 | /* Allocate power-of-2 aligned chunks from the end of the |
| 328 | * kernel image. Return physical address. |
| 329 | */ |
| 330 | static inline unsigned long early_alloc_phys(unsigned long size) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 331 | { |
David S. Miller | 5085b4a | 2005-09-22 00:45:41 -0700 | [diff] [blame^] | 332 | unsigned long base; |
| 333 | |
| 334 | BUILD_BUG_ON(size & (size - 1)); |
| 335 | |
| 336 | kern_size = (kern_size + (size - 1)) & ~(size - 1); |
| 337 | base = kern_base + kern_size; |
| 338 | kern_size += size; |
| 339 | |
| 340 | return base; |
| 341 | } |
| 342 | |
| 343 | static inline unsigned long load_phys32(unsigned long pa) |
| 344 | { |
| 345 | unsigned long val; |
| 346 | |
| 347 | __asm__ __volatile__("lduwa [%1] %2, %0" |
| 348 | : "=&r" (val) |
| 349 | : "r" (pa), "i" (ASI_PHYS_USE_EC)); |
| 350 | |
| 351 | return val; |
| 352 | } |
| 353 | |
| 354 | static inline unsigned long load_phys64(unsigned long pa) |
| 355 | { |
| 356 | unsigned long val; |
| 357 | |
| 358 | __asm__ __volatile__("ldxa [%1] %2, %0" |
| 359 | : "=&r" (val) |
| 360 | : "r" (pa), "i" (ASI_PHYS_USE_EC)); |
| 361 | |
| 362 | return val; |
| 363 | } |
| 364 | |
| 365 | static inline void store_phys32(unsigned long pa, unsigned long val) |
| 366 | { |
| 367 | __asm__ __volatile__("stwa %0, [%1] %2" |
| 368 | : /* no outputs */ |
| 369 | : "r" (val), "r" (pa), "i" (ASI_PHYS_USE_EC)); |
| 370 | } |
| 371 | |
| 372 | static inline void store_phys64(unsigned long pa, unsigned long val) |
| 373 | { |
| 374 | __asm__ __volatile__("stxa %0, [%1] %2" |
| 375 | : /* no outputs */ |
| 376 | : "r" (val), "r" (pa), "i" (ASI_PHYS_USE_EC)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 377 | } |
| 378 | |
| 379 | #define BASE_PAGE_SIZE 8192 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 380 | |
| 381 | /* |
| 382 | * Translate PROM's mapping we capture at boot time into physical address. |
| 383 | * The second parameter is only set from prom_callback() invocations. |
| 384 | */ |
| 385 | unsigned long prom_virt_to_phys(unsigned long promva, int *error) |
| 386 | { |
David S. Miller | 5085b4a | 2005-09-22 00:45:41 -0700 | [diff] [blame^] | 387 | unsigned long pmd_phys = (prom_pmd_phys + |
| 388 | ((promva >> 23) & 0x7ff) * sizeof(pmd_t)); |
| 389 | unsigned long pte_phys; |
| 390 | pmd_t pmd_ent; |
| 391 | pte_t pte_ent; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 392 | unsigned long base; |
| 393 | |
David S. Miller | 5085b4a | 2005-09-22 00:45:41 -0700 | [diff] [blame^] | 394 | pmd_val(pmd_ent) = load_phys32(pmd_phys); |
| 395 | if (pmd_none(pmd_ent)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 396 | if (error) |
| 397 | *error = 1; |
David S. Miller | 5085b4a | 2005-09-22 00:45:41 -0700 | [diff] [blame^] | 398 | return 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 399 | } |
David S. Miller | 5085b4a | 2005-09-22 00:45:41 -0700 | [diff] [blame^] | 400 | |
| 401 | pte_phys = (unsigned long)pmd_val(pmd_ent) << 11UL; |
| 402 | pte_phys += ((promva >> 13) & 0x3ff) * sizeof(pte_t); |
| 403 | pte_val(pte_ent) = load_phys64(pte_phys); |
| 404 | if (!pte_present(pte_ent)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 405 | if (error) |
| 406 | *error = 1; |
David S. Miller | 5085b4a | 2005-09-22 00:45:41 -0700 | [diff] [blame^] | 407 | return 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 408 | } |
| 409 | if (error) { |
| 410 | *error = 0; |
David S. Miller | 5085b4a | 2005-09-22 00:45:41 -0700 | [diff] [blame^] | 411 | return pte_val(pte_ent); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 412 | } |
David S. Miller | 5085b4a | 2005-09-22 00:45:41 -0700 | [diff] [blame^] | 413 | base = pte_val(pte_ent) & _PAGE_PADDR; |
| 414 | return (base + (promva & (BASE_PAGE_SIZE - 1))); |
David S. Miller | 405599b | 2005-09-22 00:12:35 -0700 | [diff] [blame] | 415 | } |
| 416 | |
| 417 | /* The obp translations are saved based on 8k pagesize, since obp can |
| 418 | * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS -> |
| 419 | * HI_OBP_ADDRESS range are handled in entry.S and do not use the vpte |
| 420 | * scheme (also, see rant in inherit_locked_prom_mappings()). |
| 421 | */ |
| 422 | static void build_obp_range(unsigned long start, unsigned long end, unsigned long data) |
| 423 | { |
| 424 | unsigned long vaddr; |
| 425 | |
| 426 | for (vaddr = start; vaddr < end; vaddr += BASE_PAGE_SIZE) { |
David S. Miller | 5085b4a | 2005-09-22 00:45:41 -0700 | [diff] [blame^] | 427 | unsigned long val, pte_phys, pmd_phys; |
| 428 | pmd_t pmd_ent; |
| 429 | int i; |
David S. Miller | 405599b | 2005-09-22 00:12:35 -0700 | [diff] [blame] | 430 | |
David S. Miller | 5085b4a | 2005-09-22 00:45:41 -0700 | [diff] [blame^] | 431 | pmd_phys = (prom_pmd_phys + |
| 432 | (((vaddr >> 23) & 0x7ff) * sizeof(pmd_t))); |
| 433 | pmd_val(pmd_ent) = load_phys32(pmd_phys); |
| 434 | if (pmd_none(pmd_ent)) { |
| 435 | pte_phys = early_alloc_phys(BASE_PAGE_SIZE); |
| 436 | |
| 437 | for (i = 0; i < BASE_PAGE_SIZE / sizeof(pte_t); i++) |
| 438 | store_phys64(pte_phys+i*sizeof(pte_t),0); |
| 439 | |
| 440 | pmd_val(pmd_ent) = pte_phys >> 11UL; |
| 441 | store_phys32(pmd_phys, pmd_val(pmd_ent)); |
David S. Miller | 405599b | 2005-09-22 00:12:35 -0700 | [diff] [blame] | 442 | } |
David S. Miller | 5085b4a | 2005-09-22 00:45:41 -0700 | [diff] [blame^] | 443 | |
| 444 | pte_phys = (unsigned long)pmd_val(pmd_ent) << 11UL; |
| 445 | pte_phys += (((vaddr >> 13) & 0x3ff) * sizeof(pte_t)); |
David S. Miller | 405599b | 2005-09-22 00:12:35 -0700 | [diff] [blame] | 446 | |
| 447 | val = data; |
| 448 | |
| 449 | /* Clear diag TTE bits. */ |
| 450 | if (tlb_type == spitfire) |
| 451 | val &= ~0x0003fe0000000000UL; |
| 452 | |
David S. Miller | 5085b4a | 2005-09-22 00:45:41 -0700 | [diff] [blame^] | 453 | store_phys64(pte_phys, val | _PAGE_MODIFIED); |
| 454 | |
David S. Miller | 405599b | 2005-09-22 00:12:35 -0700 | [diff] [blame] | 455 | data += BASE_PAGE_SIZE; |
| 456 | } |
| 457 | } |
| 458 | |
David S. Miller | 5085b4a | 2005-09-22 00:45:41 -0700 | [diff] [blame^] | 459 | static inline int in_obp_range(unsigned long vaddr) |
| 460 | { |
| 461 | return (vaddr >= LOW_OBP_ADDRESS && |
| 462 | vaddr < HI_OBP_ADDRESS); |
| 463 | } |
| 464 | |
David S. Miller | 405599b | 2005-09-22 00:12:35 -0700 | [diff] [blame] | 465 | #define OBP_PMD_SIZE 2048 |
| 466 | static void build_obp_pgtable(int prom_trans_ents) |
| 467 | { |
David S. Miller | 5085b4a | 2005-09-22 00:45:41 -0700 | [diff] [blame^] | 468 | unsigned long i; |
David S. Miller | 405599b | 2005-09-22 00:12:35 -0700 | [diff] [blame] | 469 | |
David S. Miller | 5085b4a | 2005-09-22 00:45:41 -0700 | [diff] [blame^] | 470 | prom_pmd_phys = early_alloc_phys(OBP_PMD_SIZE); |
| 471 | for (i = 0; i < OBP_PMD_SIZE; i += 4) |
| 472 | store_phys32(prom_pmd_phys + i, 0); |
| 473 | |
David S. Miller | 405599b | 2005-09-22 00:12:35 -0700 | [diff] [blame] | 474 | for (i = 0; i < prom_trans_ents; i++) { |
| 475 | unsigned long start, end; |
| 476 | |
| 477 | if (!in_obp_range(prom_trans[i].virt)) |
| 478 | continue; |
| 479 | |
| 480 | start = prom_trans[i].virt; |
| 481 | end = start + prom_trans[i].size; |
| 482 | if (end > HI_OBP_ADDRESS) |
| 483 | end = HI_OBP_ADDRESS; |
| 484 | |
| 485 | build_obp_range(start, end, prom_trans[i].data); |
| 486 | } |
David S. Miller | 405599b | 2005-09-22 00:12:35 -0700 | [diff] [blame] | 487 | } |
| 488 | |
| 489 | /* Read OBP translations property into 'prom_trans[]'. |
| 490 | * Return the number of entries. |
| 491 | */ |
| 492 | static int read_obp_translations(void) |
| 493 | { |
| 494 | int n, node; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 495 | |
| 496 | node = prom_finddevice("/virtual-memory"); |
| 497 | n = prom_getproplen(node, "translations"); |
David S. Miller | 405599b | 2005-09-22 00:12:35 -0700 | [diff] [blame] | 498 | if (unlikely(n == 0 || n == -1)) { |
David S. Miller | b206fc4 | 2005-09-21 22:31:13 -0700 | [diff] [blame] | 499 | prom_printf("prom_mappings: Couldn't get size.\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 500 | prom_halt(); |
| 501 | } |
David S. Miller | 405599b | 2005-09-22 00:12:35 -0700 | [diff] [blame] | 502 | if (unlikely(n > sizeof(prom_trans))) { |
| 503 | prom_printf("prom_mappings: Size %Zd is too big.\n", n); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 504 | prom_halt(); |
| 505 | } |
David S. Miller | 405599b | 2005-09-22 00:12:35 -0700 | [diff] [blame] | 506 | |
David S. Miller | b206fc4 | 2005-09-21 22:31:13 -0700 | [diff] [blame] | 507 | if ((n = prom_getproperty(node, "translations", |
David S. Miller | 405599b | 2005-09-22 00:12:35 -0700 | [diff] [blame] | 508 | (char *)&prom_trans[0], |
| 509 | sizeof(prom_trans))) == -1) { |
David S. Miller | b206fc4 | 2005-09-21 22:31:13 -0700 | [diff] [blame] | 510 | prom_printf("prom_mappings: Couldn't get property.\n"); |
| 511 | prom_halt(); |
| 512 | } |
| 513 | n = n / sizeof(struct linux_prom_translation); |
David S. Miller | 405599b | 2005-09-22 00:12:35 -0700 | [diff] [blame] | 514 | return n; |
| 515 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 516 | |
David S. Miller | 405599b | 2005-09-22 00:12:35 -0700 | [diff] [blame] | 517 | static inline void early_spitfire_errata32(void) |
| 518 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 519 | /* Spitfire Errata #32 workaround */ |
| 520 | /* NOTE: Using plain zero for the context value is |
| 521 | * correct here, we are not using the Linux trap |
| 522 | * tables yet so we should not use the special |
| 523 | * UltraSPARC-III+ page size encodings yet. |
| 524 | */ |
| 525 | __asm__ __volatile__("stxa %0, [%1] %2\n\t" |
| 526 | "flush %%g6" |
| 527 | : /* No outputs */ |
David S. Miller | 405599b | 2005-09-22 00:12:35 -0700 | [diff] [blame] | 528 | : "r" (0), "r" (PRIMARY_CONTEXT), |
| 529 | "i" (ASI_DMMU)); |
| 530 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 531 | |
David S. Miller | 405599b | 2005-09-22 00:12:35 -0700 | [diff] [blame] | 532 | static void lock_remap_func_page(unsigned long phys_page) |
| 533 | { |
| 534 | unsigned long tte_data = (phys_page | pgprot_val(PAGE_KERNEL)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 535 | |
| 536 | if (tlb_type == spitfire) { |
| 537 | /* Lock this into i/d tlb entry 59 */ |
| 538 | __asm__ __volatile__( |
| 539 | "stxa %%g0, [%2] %3\n\t" |
| 540 | "stxa %0, [%1] %4\n\t" |
| 541 | "membar #Sync\n\t" |
| 542 | "flush %%g6\n\t" |
| 543 | "stxa %%g0, [%2] %5\n\t" |
| 544 | "stxa %0, [%1] %6\n\t" |
| 545 | "membar #Sync\n\t" |
| 546 | "flush %%g6" |
David S. Miller | 405599b | 2005-09-22 00:12:35 -0700 | [diff] [blame] | 547 | : /* no outputs */ |
| 548 | : "r" (tte_data), "r" (59 << 3), "r" (TLB_TAG_ACCESS), |
| 549 | "i" (ASI_DMMU), "i" (ASI_DTLB_DATA_ACCESS), |
| 550 | "i" (ASI_IMMU), "i" (ASI_ITLB_DATA_ACCESS) |
| 551 | : "memory"); |
| 552 | } else { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 553 | /* Lock this into i/d tlb-0 entry 11 */ |
| 554 | __asm__ __volatile__( |
| 555 | "stxa %%g0, [%2] %3\n\t" |
| 556 | "stxa %0, [%1] %4\n\t" |
| 557 | "membar #Sync\n\t" |
| 558 | "flush %%g6\n\t" |
| 559 | "stxa %%g0, [%2] %5\n\t" |
| 560 | "stxa %0, [%1] %6\n\t" |
| 561 | "membar #Sync\n\t" |
| 562 | "flush %%g6" |
David S. Miller | 405599b | 2005-09-22 00:12:35 -0700 | [diff] [blame] | 563 | : /* no outputs */ |
| 564 | : "r" (tte_data), "r" ((0 << 16) | (11 << 3)), |
| 565 | "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU), |
| 566 | "i" (ASI_DTLB_DATA_ACCESS), "i" (ASI_IMMU), |
| 567 | "i" (ASI_ITLB_DATA_ACCESS) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 568 | : "memory"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 569 | } |
David S. Miller | 405599b | 2005-09-22 00:12:35 -0700 | [diff] [blame] | 570 | } |
| 571 | |
| 572 | static void remap_kernel(void) |
| 573 | { |
| 574 | unsigned long phys_page, tte_vaddr, tte_data; |
| 575 | void (*remap_func)(unsigned long, unsigned long, int); |
| 576 | int tlb_ent = sparc64_highest_locked_tlbent(); |
| 577 | |
| 578 | early_spitfire_errata32(); |
| 579 | |
| 580 | if (tlb_type == spitfire) |
| 581 | phys_page = spitfire_get_dtlb_data(tlb_ent); |
| 582 | else |
| 583 | phys_page = cheetah_get_ldtlb_data(tlb_ent); |
| 584 | |
| 585 | phys_page &= _PAGE_PADDR; |
| 586 | phys_page += ((unsigned long)&prom_boot_page - |
| 587 | (unsigned long)KERNBASE); |
| 588 | |
| 589 | lock_remap_func_page(phys_page); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 590 | |
| 591 | tte_vaddr = (unsigned long) KERNBASE; |
| 592 | |
David S. Miller | 405599b | 2005-09-22 00:12:35 -0700 | [diff] [blame] | 593 | early_spitfire_errata32(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 594 | |
| 595 | if (tlb_type == spitfire) |
David S. Miller | 405599b | 2005-09-22 00:12:35 -0700 | [diff] [blame] | 596 | tte_data = spitfire_get_dtlb_data(tlb_ent); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 597 | else |
David S. Miller | 405599b | 2005-09-22 00:12:35 -0700 | [diff] [blame] | 598 | tte_data = cheetah_get_ldtlb_data(tlb_ent); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 599 | |
| 600 | kern_locked_tte_data = tte_data; |
| 601 | |
| 602 | remap_func = (void *) ((unsigned long) &prom_remap - |
| 603 | (unsigned long) &prom_boot_page); |
| 604 | |
David S. Miller | 405599b | 2005-09-22 00:12:35 -0700 | [diff] [blame] | 605 | early_spitfire_errata32(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 606 | |
David S. Miller | 405599b | 2005-09-22 00:12:35 -0700 | [diff] [blame] | 607 | phys_page = tte_data & _PAGE_PADDR; |
| 608 | remap_func(phys_page, KERNBASE, prom_get_mmu_ihandle()); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 609 | if (bigkernel) |
David S. Miller | 405599b | 2005-09-22 00:12:35 -0700 | [diff] [blame] | 610 | remap_func(phys_page + 0x400000, |
| 611 | KERNBASE + 0x400000, |
| 612 | prom_get_mmu_ihandle()); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 613 | |
| 614 | /* Flush out that temporary mapping. */ |
| 615 | spitfire_flush_dtlb_nucleus_page(0x0); |
| 616 | spitfire_flush_itlb_nucleus_page(0x0); |
| 617 | |
| 618 | /* Now lock us back into the TLBs via OBP. */ |
David S. Miller | 405599b | 2005-09-22 00:12:35 -0700 | [diff] [blame] | 619 | prom_dtlb_load(tlb_ent, tte_data, tte_vaddr); |
| 620 | prom_itlb_load(tlb_ent, tte_data, tte_vaddr); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 621 | if (bigkernel) { |
David S. Miller | 405599b | 2005-09-22 00:12:35 -0700 | [diff] [blame] | 622 | prom_dtlb_load(tlb_ent - 1, |
| 623 | tte_data + 0x400000, |
| 624 | tte_vaddr + 0x400000); |
| 625 | prom_itlb_load(tlb_ent - 1, |
| 626 | tte_data + 0x400000, |
| 627 | tte_vaddr + 0x400000); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 628 | } |
David S. Miller | 405599b | 2005-09-22 00:12:35 -0700 | [diff] [blame] | 629 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 630 | |
David S. Miller | 405599b | 2005-09-22 00:12:35 -0700 | [diff] [blame] | 631 | static void readjust_prom_translations(void) |
| 632 | { |
| 633 | int nents, i; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 634 | |
David S. Miller | 405599b | 2005-09-22 00:12:35 -0700 | [diff] [blame] | 635 | nents = read_obp_translations(); |
| 636 | for (i = 0; i < nents; i++) { |
David S. Miller | b206fc4 | 2005-09-21 22:31:13 -0700 | [diff] [blame] | 637 | unsigned long vaddr = prom_trans[i].virt; |
| 638 | unsigned long size = prom_trans[i].size; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 639 | |
| 640 | if (vaddr < 0xf0000000UL) { |
| 641 | unsigned long avoid_start = (unsigned long) KERNBASE; |
| 642 | unsigned long avoid_end = avoid_start + (4 * 1024 * 1024); |
| 643 | |
| 644 | if (bigkernel) |
| 645 | avoid_end += (4 * 1024 * 1024); |
| 646 | if (vaddr < avoid_start) { |
| 647 | unsigned long top = vaddr + size; |
| 648 | |
| 649 | if (top > avoid_start) |
| 650 | top = avoid_start; |
| 651 | prom_unmap(top - vaddr, vaddr); |
| 652 | } |
| 653 | if ((vaddr + size) > avoid_end) { |
| 654 | unsigned long bottom = vaddr; |
| 655 | |
| 656 | if (bottom < avoid_end) |
| 657 | bottom = avoid_end; |
| 658 | prom_unmap((vaddr + size) - bottom, bottom); |
| 659 | } |
| 660 | } |
| 661 | } |
David S. Miller | 405599b | 2005-09-22 00:12:35 -0700 | [diff] [blame] | 662 | } |
| 663 | |
| 664 | static void inherit_prom_mappings(void) |
| 665 | { |
| 666 | int n; |
| 667 | |
| 668 | n = read_obp_translations(); |
| 669 | build_obp_pgtable(n); |
| 670 | |
| 671 | /* Now fixup OBP's idea about where we really are mapped. */ |
| 672 | prom_printf("Remapping the kernel... "); |
| 673 | remap_kernel(); |
| 674 | |
| 675 | readjust_prom_translations(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 676 | |
| 677 | prom_printf("done.\n"); |
| 678 | |
| 679 | register_prom_callbacks(); |
| 680 | } |
| 681 | |
| 682 | /* The OBP specifications for sun4u mark 0xfffffffc00000000 and |
| 683 | * upwards as reserved for use by the firmware (I wonder if this |
| 684 | * will be the same on Cheetah...). We use this virtual address |
| 685 | * range for the VPTE table mappings of the nucleus so we need |
| 686 | * to zap them when we enter the PROM. -DaveM |
| 687 | */ |
| 688 | static void __flush_nucleus_vptes(void) |
| 689 | { |
| 690 | unsigned long prom_reserved_base = 0xfffffffc00000000UL; |
| 691 | int i; |
| 692 | |
| 693 | /* Only DTLB must be checked for VPTE entries. */ |
| 694 | if (tlb_type == spitfire) { |
| 695 | for (i = 0; i < 63; i++) { |
| 696 | unsigned long tag; |
| 697 | |
| 698 | /* Spitfire Errata #32 workaround */ |
| 699 | /* NOTE: Always runs on spitfire, so no cheetah+ |
| 700 | * page size encodings. |
| 701 | */ |
| 702 | __asm__ __volatile__("stxa %0, [%1] %2\n\t" |
| 703 | "flush %%g6" |
| 704 | : /* No outputs */ |
| 705 | : "r" (0), |
| 706 | "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU)); |
| 707 | |
| 708 | tag = spitfire_get_dtlb_tag(i); |
| 709 | if (((tag & ~(PAGE_MASK)) == 0) && |
| 710 | ((tag & (PAGE_MASK)) >= prom_reserved_base)) { |
| 711 | __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" |
| 712 | "membar #Sync" |
| 713 | : /* no outputs */ |
| 714 | : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU)); |
| 715 | spitfire_put_dtlb_data(i, 0x0UL); |
| 716 | } |
| 717 | } |
| 718 | } else if (tlb_type == cheetah || tlb_type == cheetah_plus) { |
| 719 | for (i = 0; i < 512; i++) { |
| 720 | unsigned long tag = cheetah_get_dtlb_tag(i, 2); |
| 721 | |
| 722 | if ((tag & ~PAGE_MASK) == 0 && |
| 723 | (tag & PAGE_MASK) >= prom_reserved_base) { |
| 724 | __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" |
| 725 | "membar #Sync" |
| 726 | : /* no outputs */ |
| 727 | : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU)); |
| 728 | cheetah_put_dtlb_data(i, 0x0UL, 2); |
| 729 | } |
| 730 | |
| 731 | if (tlb_type != cheetah_plus) |
| 732 | continue; |
| 733 | |
| 734 | tag = cheetah_get_dtlb_tag(i, 3); |
| 735 | |
| 736 | if ((tag & ~PAGE_MASK) == 0 && |
| 737 | (tag & PAGE_MASK) >= prom_reserved_base) { |
| 738 | __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" |
| 739 | "membar #Sync" |
| 740 | : /* no outputs */ |
| 741 | : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU)); |
| 742 | cheetah_put_dtlb_data(i, 0x0UL, 3); |
| 743 | } |
| 744 | } |
| 745 | } else { |
| 746 | /* Implement me :-) */ |
| 747 | BUG(); |
| 748 | } |
| 749 | } |
| 750 | |
| 751 | static int prom_ditlb_set; |
| 752 | struct prom_tlb_entry { |
| 753 | int tlb_ent; |
| 754 | unsigned long tlb_tag; |
| 755 | unsigned long tlb_data; |
| 756 | }; |
| 757 | struct prom_tlb_entry prom_itlb[16], prom_dtlb[16]; |
| 758 | |
| 759 | void prom_world(int enter) |
| 760 | { |
| 761 | unsigned long pstate; |
| 762 | int i; |
| 763 | |
| 764 | if (!enter) |
| 765 | set_fs((mm_segment_t) { get_thread_current_ds() }); |
| 766 | |
| 767 | if (!prom_ditlb_set) |
| 768 | return; |
| 769 | |
| 770 | /* Make sure the following runs atomically. */ |
| 771 | __asm__ __volatile__("flushw\n\t" |
| 772 | "rdpr %%pstate, %0\n\t" |
| 773 | "wrpr %0, %1, %%pstate" |
| 774 | : "=r" (pstate) |
| 775 | : "i" (PSTATE_IE)); |
| 776 | |
| 777 | if (enter) { |
| 778 | /* Kick out nucleus VPTEs. */ |
| 779 | __flush_nucleus_vptes(); |
| 780 | |
| 781 | /* Install PROM world. */ |
| 782 | for (i = 0; i < 16; i++) { |
| 783 | if (prom_dtlb[i].tlb_ent != -1) { |
| 784 | __asm__ __volatile__("stxa %0, [%1] %2\n\t" |
| 785 | "membar #Sync" |
| 786 | : : "r" (prom_dtlb[i].tlb_tag), "r" (TLB_TAG_ACCESS), |
| 787 | "i" (ASI_DMMU)); |
| 788 | if (tlb_type == spitfire) |
| 789 | spitfire_put_dtlb_data(prom_dtlb[i].tlb_ent, |
| 790 | prom_dtlb[i].tlb_data); |
| 791 | else if (tlb_type == cheetah || tlb_type == cheetah_plus) |
| 792 | cheetah_put_ldtlb_data(prom_dtlb[i].tlb_ent, |
| 793 | prom_dtlb[i].tlb_data); |
| 794 | } |
| 795 | if (prom_itlb[i].tlb_ent != -1) { |
| 796 | __asm__ __volatile__("stxa %0, [%1] %2\n\t" |
| 797 | "membar #Sync" |
| 798 | : : "r" (prom_itlb[i].tlb_tag), |
| 799 | "r" (TLB_TAG_ACCESS), |
| 800 | "i" (ASI_IMMU)); |
| 801 | if (tlb_type == spitfire) |
| 802 | spitfire_put_itlb_data(prom_itlb[i].tlb_ent, |
| 803 | prom_itlb[i].tlb_data); |
| 804 | else if (tlb_type == cheetah || tlb_type == cheetah_plus) |
| 805 | cheetah_put_litlb_data(prom_itlb[i].tlb_ent, |
| 806 | prom_itlb[i].tlb_data); |
| 807 | } |
| 808 | } |
| 809 | } else { |
| 810 | for (i = 0; i < 16; i++) { |
| 811 | if (prom_dtlb[i].tlb_ent != -1) { |
| 812 | __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" |
| 813 | "membar #Sync" |
| 814 | : : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU)); |
| 815 | if (tlb_type == spitfire) |
| 816 | spitfire_put_dtlb_data(prom_dtlb[i].tlb_ent, 0x0UL); |
| 817 | else |
| 818 | cheetah_put_ldtlb_data(prom_dtlb[i].tlb_ent, 0x0UL); |
| 819 | } |
| 820 | if (prom_itlb[i].tlb_ent != -1) { |
| 821 | __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" |
| 822 | "membar #Sync" |
| 823 | : : "r" (TLB_TAG_ACCESS), |
| 824 | "i" (ASI_IMMU)); |
| 825 | if (tlb_type == spitfire) |
| 826 | spitfire_put_itlb_data(prom_itlb[i].tlb_ent, 0x0UL); |
| 827 | else |
| 828 | cheetah_put_litlb_data(prom_itlb[i].tlb_ent, 0x0UL); |
| 829 | } |
| 830 | } |
| 831 | } |
| 832 | __asm__ __volatile__("wrpr %0, 0, %%pstate" |
| 833 | : : "r" (pstate)); |
| 834 | } |
| 835 | |
| 836 | void inherit_locked_prom_mappings(int save_p) |
| 837 | { |
| 838 | int i; |
| 839 | int dtlb_seen = 0; |
| 840 | int itlb_seen = 0; |
| 841 | |
| 842 | /* Fucking losing PROM has more mappings in the TLB, but |
| 843 | * it (conveniently) fails to mention any of these in the |
| 844 | * translations property. The only ones that matter are |
| 845 | * the locked PROM tlb entries, so we impose the following |
| 846 | * irrecovable rule on the PROM, it is allowed 8 locked |
| 847 | * entries in the ITLB and 8 in the DTLB. |
| 848 | * |
| 849 | * Supposedly the upper 16GB of the address space is |
| 850 | * reserved for OBP, BUT I WISH THIS WAS DOCUMENTED |
| 851 | * SOMEWHERE!!!!!!!!!!!!!!!!! Furthermore the entire interface |
| 852 | * used between the client program and the firmware on sun5 |
| 853 | * systems to coordinate mmu mappings is also COMPLETELY |
| 854 | * UNDOCUMENTED!!!!!! Thanks S(t)un! |
| 855 | */ |
| 856 | if (save_p) { |
| 857 | for (i = 0; i < 16; i++) { |
| 858 | prom_itlb[i].tlb_ent = -1; |
| 859 | prom_dtlb[i].tlb_ent = -1; |
| 860 | } |
| 861 | } |
| 862 | if (tlb_type == spitfire) { |
| 863 | int high = SPITFIRE_HIGHEST_LOCKED_TLBENT - bigkernel; |
| 864 | for (i = 0; i < high; i++) { |
| 865 | unsigned long data; |
| 866 | |
| 867 | /* Spitfire Errata #32 workaround */ |
| 868 | /* NOTE: Always runs on spitfire, so no cheetah+ |
| 869 | * page size encodings. |
| 870 | */ |
| 871 | __asm__ __volatile__("stxa %0, [%1] %2\n\t" |
| 872 | "flush %%g6" |
| 873 | : /* No outputs */ |
| 874 | : "r" (0), |
| 875 | "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU)); |
| 876 | |
| 877 | data = spitfire_get_dtlb_data(i); |
| 878 | if ((data & (_PAGE_L|_PAGE_VALID)) == (_PAGE_L|_PAGE_VALID)) { |
| 879 | unsigned long tag; |
| 880 | |
| 881 | /* Spitfire Errata #32 workaround */ |
| 882 | /* NOTE: Always runs on spitfire, so no |
| 883 | * cheetah+ page size encodings. |
| 884 | */ |
| 885 | __asm__ __volatile__("stxa %0, [%1] %2\n\t" |
| 886 | "flush %%g6" |
| 887 | : /* No outputs */ |
| 888 | : "r" (0), |
| 889 | "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU)); |
| 890 | |
| 891 | tag = spitfire_get_dtlb_tag(i); |
| 892 | if (save_p) { |
| 893 | prom_dtlb[dtlb_seen].tlb_ent = i; |
| 894 | prom_dtlb[dtlb_seen].tlb_tag = tag; |
| 895 | prom_dtlb[dtlb_seen].tlb_data = data; |
| 896 | } |
| 897 | __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" |
| 898 | "membar #Sync" |
| 899 | : : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU)); |
| 900 | spitfire_put_dtlb_data(i, 0x0UL); |
| 901 | |
| 902 | dtlb_seen++; |
| 903 | if (dtlb_seen > 15) |
| 904 | break; |
| 905 | } |
| 906 | } |
| 907 | |
| 908 | for (i = 0; i < high; i++) { |
| 909 | unsigned long data; |
| 910 | |
| 911 | /* Spitfire Errata #32 workaround */ |
| 912 | /* NOTE: Always runs on spitfire, so no |
| 913 | * cheetah+ page size encodings. |
| 914 | */ |
| 915 | __asm__ __volatile__("stxa %0, [%1] %2\n\t" |
| 916 | "flush %%g6" |
| 917 | : /* No outputs */ |
| 918 | : "r" (0), |
| 919 | "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU)); |
| 920 | |
| 921 | data = spitfire_get_itlb_data(i); |
| 922 | if ((data & (_PAGE_L|_PAGE_VALID)) == (_PAGE_L|_PAGE_VALID)) { |
| 923 | unsigned long tag; |
| 924 | |
| 925 | /* Spitfire Errata #32 workaround */ |
| 926 | /* NOTE: Always runs on spitfire, so no |
| 927 | * cheetah+ page size encodings. |
| 928 | */ |
| 929 | __asm__ __volatile__("stxa %0, [%1] %2\n\t" |
| 930 | "flush %%g6" |
| 931 | : /* No outputs */ |
| 932 | : "r" (0), |
| 933 | "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU)); |
| 934 | |
| 935 | tag = spitfire_get_itlb_tag(i); |
| 936 | if (save_p) { |
| 937 | prom_itlb[itlb_seen].tlb_ent = i; |
| 938 | prom_itlb[itlb_seen].tlb_tag = tag; |
| 939 | prom_itlb[itlb_seen].tlb_data = data; |
| 940 | } |
| 941 | __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" |
| 942 | "membar #Sync" |
| 943 | : : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU)); |
| 944 | spitfire_put_itlb_data(i, 0x0UL); |
| 945 | |
| 946 | itlb_seen++; |
| 947 | if (itlb_seen > 15) |
| 948 | break; |
| 949 | } |
| 950 | } |
| 951 | } else if (tlb_type == cheetah || tlb_type == cheetah_plus) { |
| 952 | int high = CHEETAH_HIGHEST_LOCKED_TLBENT - bigkernel; |
| 953 | |
| 954 | for (i = 0; i < high; i++) { |
| 955 | unsigned long data; |
| 956 | |
| 957 | data = cheetah_get_ldtlb_data(i); |
| 958 | if ((data & (_PAGE_L|_PAGE_VALID)) == (_PAGE_L|_PAGE_VALID)) { |
| 959 | unsigned long tag; |
| 960 | |
| 961 | tag = cheetah_get_ldtlb_tag(i); |
| 962 | if (save_p) { |
| 963 | prom_dtlb[dtlb_seen].tlb_ent = i; |
| 964 | prom_dtlb[dtlb_seen].tlb_tag = tag; |
| 965 | prom_dtlb[dtlb_seen].tlb_data = data; |
| 966 | } |
| 967 | __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" |
| 968 | "membar #Sync" |
| 969 | : : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU)); |
| 970 | cheetah_put_ldtlb_data(i, 0x0UL); |
| 971 | |
| 972 | dtlb_seen++; |
| 973 | if (dtlb_seen > 15) |
| 974 | break; |
| 975 | } |
| 976 | } |
| 977 | |
| 978 | for (i = 0; i < high; i++) { |
| 979 | unsigned long data; |
| 980 | |
| 981 | data = cheetah_get_litlb_data(i); |
| 982 | if ((data & (_PAGE_L|_PAGE_VALID)) == (_PAGE_L|_PAGE_VALID)) { |
| 983 | unsigned long tag; |
| 984 | |
| 985 | tag = cheetah_get_litlb_tag(i); |
| 986 | if (save_p) { |
| 987 | prom_itlb[itlb_seen].tlb_ent = i; |
| 988 | prom_itlb[itlb_seen].tlb_tag = tag; |
| 989 | prom_itlb[itlb_seen].tlb_data = data; |
| 990 | } |
| 991 | __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" |
| 992 | "membar #Sync" |
| 993 | : : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU)); |
| 994 | cheetah_put_litlb_data(i, 0x0UL); |
| 995 | |
| 996 | itlb_seen++; |
| 997 | if (itlb_seen > 15) |
| 998 | break; |
| 999 | } |
| 1000 | } |
| 1001 | } else { |
| 1002 | /* Implement me :-) */ |
| 1003 | BUG(); |
| 1004 | } |
| 1005 | if (save_p) |
| 1006 | prom_ditlb_set = 1; |
| 1007 | } |
| 1008 | |
| 1009 | /* Give PROM back his world, done during reboots... */ |
| 1010 | void prom_reload_locked(void) |
| 1011 | { |
| 1012 | int i; |
| 1013 | |
| 1014 | for (i = 0; i < 16; i++) { |
| 1015 | if (prom_dtlb[i].tlb_ent != -1) { |
| 1016 | __asm__ __volatile__("stxa %0, [%1] %2\n\t" |
| 1017 | "membar #Sync" |
| 1018 | : : "r" (prom_dtlb[i].tlb_tag), "r" (TLB_TAG_ACCESS), |
| 1019 | "i" (ASI_DMMU)); |
| 1020 | if (tlb_type == spitfire) |
| 1021 | spitfire_put_dtlb_data(prom_dtlb[i].tlb_ent, |
| 1022 | prom_dtlb[i].tlb_data); |
| 1023 | else if (tlb_type == cheetah || tlb_type == cheetah_plus) |
| 1024 | cheetah_put_ldtlb_data(prom_dtlb[i].tlb_ent, |
| 1025 | prom_dtlb[i].tlb_data); |
| 1026 | } |
| 1027 | |
| 1028 | if (prom_itlb[i].tlb_ent != -1) { |
| 1029 | __asm__ __volatile__("stxa %0, [%1] %2\n\t" |
| 1030 | "membar #Sync" |
| 1031 | : : "r" (prom_itlb[i].tlb_tag), |
| 1032 | "r" (TLB_TAG_ACCESS), |
| 1033 | "i" (ASI_IMMU)); |
| 1034 | if (tlb_type == spitfire) |
| 1035 | spitfire_put_itlb_data(prom_itlb[i].tlb_ent, |
| 1036 | prom_itlb[i].tlb_data); |
| 1037 | else |
| 1038 | cheetah_put_litlb_data(prom_itlb[i].tlb_ent, |
| 1039 | prom_itlb[i].tlb_data); |
| 1040 | } |
| 1041 | } |
| 1042 | } |
| 1043 | |
| 1044 | #ifdef DCACHE_ALIASING_POSSIBLE |
| 1045 | void __flush_dcache_range(unsigned long start, unsigned long end) |
| 1046 | { |
| 1047 | unsigned long va; |
| 1048 | |
| 1049 | if (tlb_type == spitfire) { |
| 1050 | int n = 0; |
| 1051 | |
| 1052 | for (va = start; va < end; va += 32) { |
| 1053 | spitfire_put_dcache_tag(va & 0x3fe0, 0x0); |
| 1054 | if (++n >= 512) |
| 1055 | break; |
| 1056 | } |
| 1057 | } else { |
| 1058 | start = __pa(start); |
| 1059 | end = __pa(end); |
| 1060 | for (va = start; va < end; va += 32) |
| 1061 | __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" |
| 1062 | "membar #Sync" |
| 1063 | : /* no outputs */ |
| 1064 | : "r" (va), |
| 1065 | "i" (ASI_DCACHE_INVALIDATE)); |
| 1066 | } |
| 1067 | } |
| 1068 | #endif /* DCACHE_ALIASING_POSSIBLE */ |
| 1069 | |
| 1070 | /* If not locked, zap it. */ |
| 1071 | void __flush_tlb_all(void) |
| 1072 | { |
| 1073 | unsigned long pstate; |
| 1074 | int i; |
| 1075 | |
| 1076 | __asm__ __volatile__("flushw\n\t" |
| 1077 | "rdpr %%pstate, %0\n\t" |
| 1078 | "wrpr %0, %1, %%pstate" |
| 1079 | : "=r" (pstate) |
| 1080 | : "i" (PSTATE_IE)); |
| 1081 | if (tlb_type == spitfire) { |
| 1082 | for (i = 0; i < 64; i++) { |
| 1083 | /* Spitfire Errata #32 workaround */ |
| 1084 | /* NOTE: Always runs on spitfire, so no |
| 1085 | * cheetah+ page size encodings. |
| 1086 | */ |
| 1087 | __asm__ __volatile__("stxa %0, [%1] %2\n\t" |
| 1088 | "flush %%g6" |
| 1089 | : /* No outputs */ |
| 1090 | : "r" (0), |
| 1091 | "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU)); |
| 1092 | |
| 1093 | if (!(spitfire_get_dtlb_data(i) & _PAGE_L)) { |
| 1094 | __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" |
| 1095 | "membar #Sync" |
| 1096 | : /* no outputs */ |
| 1097 | : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU)); |
| 1098 | spitfire_put_dtlb_data(i, 0x0UL); |
| 1099 | } |
| 1100 | |
| 1101 | /* Spitfire Errata #32 workaround */ |
| 1102 | /* NOTE: Always runs on spitfire, so no |
| 1103 | * cheetah+ page size encodings. |
| 1104 | */ |
| 1105 | __asm__ __volatile__("stxa %0, [%1] %2\n\t" |
| 1106 | "flush %%g6" |
| 1107 | : /* No outputs */ |
| 1108 | : "r" (0), |
| 1109 | "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU)); |
| 1110 | |
| 1111 | if (!(spitfire_get_itlb_data(i) & _PAGE_L)) { |
| 1112 | __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" |
| 1113 | "membar #Sync" |
| 1114 | : /* no outputs */ |
| 1115 | : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU)); |
| 1116 | spitfire_put_itlb_data(i, 0x0UL); |
| 1117 | } |
| 1118 | } |
| 1119 | } else if (tlb_type == cheetah || tlb_type == cheetah_plus) { |
| 1120 | cheetah_flush_dtlb_all(); |
| 1121 | cheetah_flush_itlb_all(); |
| 1122 | } |
| 1123 | __asm__ __volatile__("wrpr %0, 0, %%pstate" |
| 1124 | : : "r" (pstate)); |
| 1125 | } |
| 1126 | |
| 1127 | /* Caller does TLB context flushing on local CPU if necessary. |
| 1128 | * The caller also ensures that CTX_VALID(mm->context) is false. |
| 1129 | * |
| 1130 | * We must be careful about boundary cases so that we never |
| 1131 | * let the user have CTX 0 (nucleus) or we ever use a CTX |
| 1132 | * version of zero (and thus NO_CONTEXT would not be caught |
| 1133 | * by version mis-match tests in mmu_context.h). |
| 1134 | */ |
| 1135 | void get_new_mmu_context(struct mm_struct *mm) |
| 1136 | { |
| 1137 | unsigned long ctx, new_ctx; |
| 1138 | unsigned long orig_pgsz_bits; |
| 1139 | |
| 1140 | |
| 1141 | spin_lock(&ctx_alloc_lock); |
| 1142 | orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK); |
| 1143 | ctx = (tlb_context_cache + 1) & CTX_NR_MASK; |
| 1144 | new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx); |
| 1145 | if (new_ctx >= (1 << CTX_NR_BITS)) { |
| 1146 | new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1); |
| 1147 | if (new_ctx >= ctx) { |
| 1148 | int i; |
| 1149 | new_ctx = (tlb_context_cache & CTX_VERSION_MASK) + |
| 1150 | CTX_FIRST_VERSION; |
| 1151 | if (new_ctx == 1) |
| 1152 | new_ctx = CTX_FIRST_VERSION; |
| 1153 | |
| 1154 | /* Don't call memset, for 16 entries that's just |
| 1155 | * plain silly... |
| 1156 | */ |
| 1157 | mmu_context_bmap[0] = 3; |
| 1158 | mmu_context_bmap[1] = 0; |
| 1159 | mmu_context_bmap[2] = 0; |
| 1160 | mmu_context_bmap[3] = 0; |
| 1161 | for (i = 4; i < CTX_BMAP_SLOTS; i += 4) { |
| 1162 | mmu_context_bmap[i + 0] = 0; |
| 1163 | mmu_context_bmap[i + 1] = 0; |
| 1164 | mmu_context_bmap[i + 2] = 0; |
| 1165 | mmu_context_bmap[i + 3] = 0; |
| 1166 | } |
| 1167 | goto out; |
| 1168 | } |
| 1169 | } |
| 1170 | mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63)); |
| 1171 | new_ctx |= (tlb_context_cache & CTX_VERSION_MASK); |
| 1172 | out: |
| 1173 | tlb_context_cache = new_ctx; |
| 1174 | mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits; |
| 1175 | spin_unlock(&ctx_alloc_lock); |
| 1176 | } |
| 1177 | |
| 1178 | #ifndef CONFIG_SMP |
| 1179 | struct pgtable_cache_struct pgt_quicklists; |
| 1180 | #endif |
| 1181 | |
| 1182 | /* OK, we have to color these pages. The page tables are accessed |
| 1183 | * by non-Dcache enabled mapping in the VPTE area by the dtlb_backend.S |
| 1184 | * code, as well as by PAGE_OFFSET range direct-mapped addresses by |
| 1185 | * other parts of the kernel. By coloring, we make sure that the tlbmiss |
| 1186 | * fast handlers do not get data from old/garbage dcache lines that |
| 1187 | * correspond to an old/stale virtual address (user/kernel) that |
| 1188 | * previously mapped the pagetable page while accessing vpte range |
| 1189 | * addresses. The idea is that if the vpte color and PAGE_OFFSET range |
| 1190 | * color is the same, then when the kernel initializes the pagetable |
| 1191 | * using the later address range, accesses with the first address |
| 1192 | * range will see the newly initialized data rather than the garbage. |
| 1193 | */ |
| 1194 | #ifdef DCACHE_ALIASING_POSSIBLE |
| 1195 | #define DC_ALIAS_SHIFT 1 |
| 1196 | #else |
| 1197 | #define DC_ALIAS_SHIFT 0 |
| 1198 | #endif |
Christoph Hellwig | 8edf72e | 2005-05-05 14:27:56 -0700 | [diff] [blame] | 1199 | pte_t *pte_alloc_one_kernel(struct mm_struct *mm, unsigned long address) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1200 | { |
| 1201 | struct page *page; |
| 1202 | unsigned long color; |
| 1203 | |
| 1204 | { |
| 1205 | pte_t *ptep = pte_alloc_one_fast(mm, address); |
| 1206 | |
| 1207 | if (ptep) |
| 1208 | return ptep; |
| 1209 | } |
| 1210 | |
| 1211 | color = VPTE_COLOR(address); |
| 1212 | page = alloc_pages(GFP_KERNEL|__GFP_REPEAT, DC_ALIAS_SHIFT); |
| 1213 | if (page) { |
| 1214 | unsigned long *to_free; |
| 1215 | unsigned long paddr; |
| 1216 | pte_t *pte; |
| 1217 | |
| 1218 | #ifdef DCACHE_ALIASING_POSSIBLE |
| 1219 | set_page_count(page, 1); |
| 1220 | ClearPageCompound(page); |
| 1221 | |
| 1222 | set_page_count((page + 1), 1); |
| 1223 | ClearPageCompound(page + 1); |
| 1224 | #endif |
| 1225 | paddr = (unsigned long) page_address(page); |
| 1226 | memset((char *)paddr, 0, (PAGE_SIZE << DC_ALIAS_SHIFT)); |
| 1227 | |
| 1228 | if (!color) { |
| 1229 | pte = (pte_t *) paddr; |
| 1230 | to_free = (unsigned long *) (paddr + PAGE_SIZE); |
| 1231 | } else { |
| 1232 | pte = (pte_t *) (paddr + PAGE_SIZE); |
| 1233 | to_free = (unsigned long *) paddr; |
| 1234 | } |
| 1235 | |
| 1236 | #ifdef DCACHE_ALIASING_POSSIBLE |
| 1237 | /* Now free the other one up, adjust cache size. */ |
| 1238 | preempt_disable(); |
| 1239 | *to_free = (unsigned long) pte_quicklist[color ^ 0x1]; |
| 1240 | pte_quicklist[color ^ 0x1] = to_free; |
| 1241 | pgtable_cache_size++; |
| 1242 | preempt_enable(); |
| 1243 | #endif |
| 1244 | |
| 1245 | return pte; |
| 1246 | } |
| 1247 | return NULL; |
| 1248 | } |
| 1249 | |
| 1250 | void sparc_ultra_dump_itlb(void) |
| 1251 | { |
| 1252 | int slot; |
| 1253 | |
| 1254 | if (tlb_type == spitfire) { |
| 1255 | printk ("Contents of itlb: "); |
| 1256 | for (slot = 0; slot < 14; slot++) printk (" "); |
| 1257 | printk ("%2x:%016lx,%016lx\n", |
| 1258 | 0, |
| 1259 | spitfire_get_itlb_tag(0), spitfire_get_itlb_data(0)); |
| 1260 | for (slot = 1; slot < 64; slot+=3) { |
| 1261 | printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx %2x:%016lx,%016lx\n", |
| 1262 | slot, |
| 1263 | spitfire_get_itlb_tag(slot), spitfire_get_itlb_data(slot), |
| 1264 | slot+1, |
| 1265 | spitfire_get_itlb_tag(slot+1), spitfire_get_itlb_data(slot+1), |
| 1266 | slot+2, |
| 1267 | spitfire_get_itlb_tag(slot+2), spitfire_get_itlb_data(slot+2)); |
| 1268 | } |
| 1269 | } else if (tlb_type == cheetah || tlb_type == cheetah_plus) { |
| 1270 | printk ("Contents of itlb0:\n"); |
| 1271 | for (slot = 0; slot < 16; slot+=2) { |
| 1272 | printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n", |
| 1273 | slot, |
| 1274 | cheetah_get_litlb_tag(slot), cheetah_get_litlb_data(slot), |
| 1275 | slot+1, |
| 1276 | cheetah_get_litlb_tag(slot+1), cheetah_get_litlb_data(slot+1)); |
| 1277 | } |
| 1278 | printk ("Contents of itlb2:\n"); |
| 1279 | for (slot = 0; slot < 128; slot+=2) { |
| 1280 | printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n", |
| 1281 | slot, |
| 1282 | cheetah_get_itlb_tag(slot), cheetah_get_itlb_data(slot), |
| 1283 | slot+1, |
| 1284 | cheetah_get_itlb_tag(slot+1), cheetah_get_itlb_data(slot+1)); |
| 1285 | } |
| 1286 | } |
| 1287 | } |
| 1288 | |
| 1289 | void sparc_ultra_dump_dtlb(void) |
| 1290 | { |
| 1291 | int slot; |
| 1292 | |
| 1293 | if (tlb_type == spitfire) { |
| 1294 | printk ("Contents of dtlb: "); |
| 1295 | for (slot = 0; slot < 14; slot++) printk (" "); |
| 1296 | printk ("%2x:%016lx,%016lx\n", 0, |
| 1297 | spitfire_get_dtlb_tag(0), spitfire_get_dtlb_data(0)); |
| 1298 | for (slot = 1; slot < 64; slot+=3) { |
| 1299 | printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx %2x:%016lx,%016lx\n", |
| 1300 | slot, |
| 1301 | spitfire_get_dtlb_tag(slot), spitfire_get_dtlb_data(slot), |
| 1302 | slot+1, |
| 1303 | spitfire_get_dtlb_tag(slot+1), spitfire_get_dtlb_data(slot+1), |
| 1304 | slot+2, |
| 1305 | spitfire_get_dtlb_tag(slot+2), spitfire_get_dtlb_data(slot+2)); |
| 1306 | } |
| 1307 | } else if (tlb_type == cheetah || tlb_type == cheetah_plus) { |
| 1308 | printk ("Contents of dtlb0:\n"); |
| 1309 | for (slot = 0; slot < 16; slot+=2) { |
| 1310 | printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n", |
| 1311 | slot, |
| 1312 | cheetah_get_ldtlb_tag(slot), cheetah_get_ldtlb_data(slot), |
| 1313 | slot+1, |
| 1314 | cheetah_get_ldtlb_tag(slot+1), cheetah_get_ldtlb_data(slot+1)); |
| 1315 | } |
| 1316 | printk ("Contents of dtlb2:\n"); |
| 1317 | for (slot = 0; slot < 512; slot+=2) { |
| 1318 | printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n", |
| 1319 | slot, |
| 1320 | cheetah_get_dtlb_tag(slot, 2), cheetah_get_dtlb_data(slot, 2), |
| 1321 | slot+1, |
| 1322 | cheetah_get_dtlb_tag(slot+1, 2), cheetah_get_dtlb_data(slot+1, 2)); |
| 1323 | } |
| 1324 | if (tlb_type == cheetah_plus) { |
| 1325 | printk ("Contents of dtlb3:\n"); |
| 1326 | for (slot = 0; slot < 512; slot+=2) { |
| 1327 | printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n", |
| 1328 | slot, |
| 1329 | cheetah_get_dtlb_tag(slot, 3), cheetah_get_dtlb_data(slot, 3), |
| 1330 | slot+1, |
| 1331 | cheetah_get_dtlb_tag(slot+1, 3), cheetah_get_dtlb_data(slot+1, 3)); |
| 1332 | } |
| 1333 | } |
| 1334 | } |
| 1335 | } |
| 1336 | |
| 1337 | extern unsigned long cmdline_memory_size; |
| 1338 | |
| 1339 | unsigned long __init bootmem_init(unsigned long *pages_avail) |
| 1340 | { |
| 1341 | unsigned long bootmap_size, start_pfn, end_pfn; |
| 1342 | unsigned long end_of_phys_memory = 0UL; |
| 1343 | unsigned long bootmap_pfn, bytes_avail, size; |
| 1344 | int i; |
| 1345 | |
| 1346 | #ifdef CONFIG_DEBUG_BOOTMEM |
| 1347 | prom_printf("bootmem_init: Scan sp_banks, "); |
| 1348 | #endif |
| 1349 | |
| 1350 | bytes_avail = 0UL; |
| 1351 | for (i = 0; sp_banks[i].num_bytes != 0; i++) { |
| 1352 | end_of_phys_memory = sp_banks[i].base_addr + |
| 1353 | sp_banks[i].num_bytes; |
| 1354 | bytes_avail += sp_banks[i].num_bytes; |
| 1355 | if (cmdline_memory_size) { |
| 1356 | if (bytes_avail > cmdline_memory_size) { |
| 1357 | unsigned long slack = bytes_avail - cmdline_memory_size; |
| 1358 | |
| 1359 | bytes_avail -= slack; |
| 1360 | end_of_phys_memory -= slack; |
| 1361 | |
| 1362 | sp_banks[i].num_bytes -= slack; |
| 1363 | if (sp_banks[i].num_bytes == 0) { |
| 1364 | sp_banks[i].base_addr = 0xdeadbeef; |
| 1365 | } else { |
| 1366 | sp_banks[i+1].num_bytes = 0; |
| 1367 | sp_banks[i+1].base_addr = 0xdeadbeef; |
| 1368 | } |
| 1369 | break; |
| 1370 | } |
| 1371 | } |
| 1372 | } |
| 1373 | |
| 1374 | *pages_avail = bytes_avail >> PAGE_SHIFT; |
| 1375 | |
| 1376 | /* Start with page aligned address of last symbol in kernel |
| 1377 | * image. The kernel is hard mapped below PAGE_OFFSET in a |
| 1378 | * 4MB locked TLB translation. |
| 1379 | */ |
| 1380 | start_pfn = PAGE_ALIGN(kern_base + kern_size) >> PAGE_SHIFT; |
| 1381 | |
| 1382 | bootmap_pfn = start_pfn; |
| 1383 | |
| 1384 | end_pfn = end_of_phys_memory >> PAGE_SHIFT; |
| 1385 | |
| 1386 | #ifdef CONFIG_BLK_DEV_INITRD |
| 1387 | /* Now have to check initial ramdisk, so that bootmap does not overwrite it */ |
| 1388 | if (sparc_ramdisk_image || sparc_ramdisk_image64) { |
| 1389 | unsigned long ramdisk_image = sparc_ramdisk_image ? |
| 1390 | sparc_ramdisk_image : sparc_ramdisk_image64; |
| 1391 | if (ramdisk_image >= (unsigned long)_end - 2 * PAGE_SIZE) |
| 1392 | ramdisk_image -= KERNBASE; |
| 1393 | initrd_start = ramdisk_image + phys_base; |
| 1394 | initrd_end = initrd_start + sparc_ramdisk_size; |
| 1395 | if (initrd_end > end_of_phys_memory) { |
| 1396 | printk(KERN_CRIT "initrd extends beyond end of memory " |
| 1397 | "(0x%016lx > 0x%016lx)\ndisabling initrd\n", |
| 1398 | initrd_end, end_of_phys_memory); |
| 1399 | initrd_start = 0; |
| 1400 | } |
| 1401 | if (initrd_start) { |
| 1402 | if (initrd_start >= (start_pfn << PAGE_SHIFT) && |
| 1403 | initrd_start < (start_pfn << PAGE_SHIFT) + 2 * PAGE_SIZE) |
| 1404 | bootmap_pfn = PAGE_ALIGN (initrd_end) >> PAGE_SHIFT; |
| 1405 | } |
| 1406 | } |
| 1407 | #endif |
| 1408 | /* Initialize the boot-time allocator. */ |
| 1409 | max_pfn = max_low_pfn = end_pfn; |
| 1410 | min_low_pfn = pfn_base; |
| 1411 | |
| 1412 | #ifdef CONFIG_DEBUG_BOOTMEM |
| 1413 | prom_printf("init_bootmem(min[%lx], bootmap[%lx], max[%lx])\n", |
| 1414 | min_low_pfn, bootmap_pfn, max_low_pfn); |
| 1415 | #endif |
| 1416 | bootmap_size = init_bootmem_node(NODE_DATA(0), bootmap_pfn, pfn_base, end_pfn); |
| 1417 | |
| 1418 | bootmap_base = bootmap_pfn << PAGE_SHIFT; |
| 1419 | |
| 1420 | /* Now register the available physical memory with the |
| 1421 | * allocator. |
| 1422 | */ |
| 1423 | for (i = 0; sp_banks[i].num_bytes != 0; i++) { |
| 1424 | #ifdef CONFIG_DEBUG_BOOTMEM |
| 1425 | prom_printf("free_bootmem(sp_banks:%d): base[%lx] size[%lx]\n", |
| 1426 | i, sp_banks[i].base_addr, sp_banks[i].num_bytes); |
| 1427 | #endif |
| 1428 | free_bootmem(sp_banks[i].base_addr, sp_banks[i].num_bytes); |
| 1429 | } |
| 1430 | |
| 1431 | #ifdef CONFIG_BLK_DEV_INITRD |
| 1432 | if (initrd_start) { |
| 1433 | size = initrd_end - initrd_start; |
| 1434 | |
| 1435 | /* Resert the initrd image area. */ |
| 1436 | #ifdef CONFIG_DEBUG_BOOTMEM |
| 1437 | prom_printf("reserve_bootmem(initrd): base[%llx] size[%lx]\n", |
| 1438 | initrd_start, initrd_end); |
| 1439 | #endif |
| 1440 | reserve_bootmem(initrd_start, size); |
| 1441 | *pages_avail -= PAGE_ALIGN(size) >> PAGE_SHIFT; |
| 1442 | |
| 1443 | initrd_start += PAGE_OFFSET; |
| 1444 | initrd_end += PAGE_OFFSET; |
| 1445 | } |
| 1446 | #endif |
| 1447 | /* Reserve the kernel text/data/bss. */ |
| 1448 | #ifdef CONFIG_DEBUG_BOOTMEM |
| 1449 | prom_printf("reserve_bootmem(kernel): base[%lx] size[%lx]\n", kern_base, kern_size); |
| 1450 | #endif |
| 1451 | reserve_bootmem(kern_base, kern_size); |
| 1452 | *pages_avail -= PAGE_ALIGN(kern_size) >> PAGE_SHIFT; |
| 1453 | |
| 1454 | /* Reserve the bootmem map. We do not account for it |
| 1455 | * in pages_avail because we will release that memory |
| 1456 | * in free_all_bootmem. |
| 1457 | */ |
| 1458 | size = bootmap_size; |
| 1459 | #ifdef CONFIG_DEBUG_BOOTMEM |
| 1460 | prom_printf("reserve_bootmem(bootmap): base[%lx] size[%lx]\n", |
| 1461 | (bootmap_pfn << PAGE_SHIFT), size); |
| 1462 | #endif |
| 1463 | reserve_bootmem((bootmap_pfn << PAGE_SHIFT), size); |
| 1464 | *pages_avail -= PAGE_ALIGN(size) >> PAGE_SHIFT; |
| 1465 | |
| 1466 | return end_pfn; |
| 1467 | } |
| 1468 | |
| 1469 | /* paging_init() sets up the page tables */ |
| 1470 | |
| 1471 | extern void cheetah_ecache_flush_init(void); |
| 1472 | |
| 1473 | static unsigned long last_valid_pfn; |
| 1474 | |
| 1475 | void __init paging_init(void) |
| 1476 | { |
| 1477 | extern pmd_t swapper_pmd_dir[1024]; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1478 | unsigned long alias_base = kern_base + PAGE_OFFSET; |
| 1479 | unsigned long second_alias_page = 0; |
| 1480 | unsigned long pt, flags, end_pfn, pages_avail; |
| 1481 | unsigned long shift = alias_base - ((unsigned long)KERNBASE); |
| 1482 | unsigned long real_end; |
| 1483 | |
| 1484 | set_bit(0, mmu_context_bmap); |
| 1485 | |
| 1486 | real_end = (unsigned long)_end; |
| 1487 | if ((real_end > ((unsigned long)KERNBASE + 0x400000))) |
| 1488 | bigkernel = 1; |
| 1489 | #ifdef CONFIG_BLK_DEV_INITRD |
| 1490 | if (sparc_ramdisk_image || sparc_ramdisk_image64) |
| 1491 | real_end = (PAGE_ALIGN(real_end) + PAGE_ALIGN(sparc_ramdisk_size)); |
| 1492 | #endif |
| 1493 | |
| 1494 | /* We assume physical memory starts at some 4mb multiple, |
| 1495 | * if this were not true we wouldn't boot up to this point |
| 1496 | * anyways. |
| 1497 | */ |
| 1498 | pt = kern_base | _PAGE_VALID | _PAGE_SZ4MB; |
| 1499 | pt |= _PAGE_CP | _PAGE_CV | _PAGE_P | _PAGE_L | _PAGE_W; |
| 1500 | local_irq_save(flags); |
| 1501 | if (tlb_type == spitfire) { |
| 1502 | __asm__ __volatile__( |
| 1503 | " stxa %1, [%0] %3\n" |
| 1504 | " stxa %2, [%5] %4\n" |
| 1505 | " membar #Sync\n" |
| 1506 | " flush %%g6\n" |
| 1507 | " nop\n" |
| 1508 | " nop\n" |
| 1509 | " nop\n" |
| 1510 | : /* No outputs */ |
| 1511 | : "r" (TLB_TAG_ACCESS), "r" (alias_base), "r" (pt), |
| 1512 | "i" (ASI_DMMU), "i" (ASI_DTLB_DATA_ACCESS), "r" (61 << 3) |
| 1513 | : "memory"); |
| 1514 | if (real_end >= KERNBASE + 0x340000) { |
| 1515 | second_alias_page = alias_base + 0x400000; |
| 1516 | __asm__ __volatile__( |
| 1517 | " stxa %1, [%0] %3\n" |
| 1518 | " stxa %2, [%5] %4\n" |
| 1519 | " membar #Sync\n" |
| 1520 | " flush %%g6\n" |
| 1521 | " nop\n" |
| 1522 | " nop\n" |
| 1523 | " nop\n" |
| 1524 | : /* No outputs */ |
| 1525 | : "r" (TLB_TAG_ACCESS), "r" (second_alias_page), "r" (pt + 0x400000), |
| 1526 | "i" (ASI_DMMU), "i" (ASI_DTLB_DATA_ACCESS), "r" (60 << 3) |
| 1527 | : "memory"); |
| 1528 | } |
| 1529 | } else if (tlb_type == cheetah || tlb_type == cheetah_plus) { |
| 1530 | __asm__ __volatile__( |
| 1531 | " stxa %1, [%0] %3\n" |
| 1532 | " stxa %2, [%5] %4\n" |
| 1533 | " membar #Sync\n" |
| 1534 | " flush %%g6\n" |
| 1535 | " nop\n" |
| 1536 | " nop\n" |
| 1537 | " nop\n" |
| 1538 | : /* No outputs */ |
| 1539 | : "r" (TLB_TAG_ACCESS), "r" (alias_base), "r" (pt), |
| 1540 | "i" (ASI_DMMU), "i" (ASI_DTLB_DATA_ACCESS), "r" ((0<<16) | (13<<3)) |
| 1541 | : "memory"); |
| 1542 | if (real_end >= KERNBASE + 0x340000) { |
| 1543 | second_alias_page = alias_base + 0x400000; |
| 1544 | __asm__ __volatile__( |
| 1545 | " stxa %1, [%0] %3\n" |
| 1546 | " stxa %2, [%5] %4\n" |
| 1547 | " membar #Sync\n" |
| 1548 | " flush %%g6\n" |
| 1549 | " nop\n" |
| 1550 | " nop\n" |
| 1551 | " nop\n" |
| 1552 | : /* No outputs */ |
| 1553 | : "r" (TLB_TAG_ACCESS), "r" (second_alias_page), "r" (pt + 0x400000), |
| 1554 | "i" (ASI_DMMU), "i" (ASI_DTLB_DATA_ACCESS), "r" ((0<<16) | (12<<3)) |
| 1555 | : "memory"); |
| 1556 | } |
| 1557 | } |
| 1558 | local_irq_restore(flags); |
| 1559 | |
| 1560 | /* Now set kernel pgd to upper alias so physical page computations |
| 1561 | * work. |
| 1562 | */ |
| 1563 | init_mm.pgd += ((shift) / (sizeof(pgd_t))); |
| 1564 | |
| 1565 | memset(swapper_pmd_dir, 0, sizeof(swapper_pmd_dir)); |
| 1566 | |
| 1567 | /* Now can init the kernel/bad page tables. */ |
| 1568 | pud_set(pud_offset(&swapper_pg_dir[0], 0), |
| 1569 | swapper_pmd_dir + (shift / sizeof(pgd_t))); |
| 1570 | |
David S. Miller | 1ac4f5e | 2005-09-21 21:49:32 -0700 | [diff] [blame] | 1571 | swapper_pgd_zero = pgd_val(init_mm.pgd[0]); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1572 | |
David S. Miller | 5085b4a | 2005-09-22 00:45:41 -0700 | [diff] [blame^] | 1573 | /* Inherit non-locked OBP mappings. */ |
| 1574 | inherit_prom_mappings(); |
| 1575 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1576 | /* Setup bootmem... */ |
| 1577 | pages_avail = 0; |
| 1578 | last_valid_pfn = end_pfn = bootmem_init(&pages_avail); |
| 1579 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1580 | /* Ok, we can use our TLB miss and window trap handlers safely. |
| 1581 | * We need to do a quick peek here to see if we are on StarFire |
| 1582 | * or not, so setup_tba can setup the IRQ globals correctly (it |
| 1583 | * needs to get the hard smp processor id correctly). |
| 1584 | */ |
| 1585 | { |
| 1586 | extern void setup_tba(int); |
| 1587 | setup_tba(this_is_starfire); |
| 1588 | } |
| 1589 | |
| 1590 | inherit_locked_prom_mappings(1); |
| 1591 | |
| 1592 | /* We only created DTLB mapping of this stuff. */ |
| 1593 | spitfire_flush_dtlb_nucleus_page(alias_base); |
| 1594 | if (second_alias_page) |
| 1595 | spitfire_flush_dtlb_nucleus_page(second_alias_page); |
| 1596 | |
| 1597 | __flush_tlb_all(); |
| 1598 | |
| 1599 | { |
| 1600 | unsigned long zones_size[MAX_NR_ZONES]; |
| 1601 | unsigned long zholes_size[MAX_NR_ZONES]; |
| 1602 | unsigned long npages; |
| 1603 | int znum; |
| 1604 | |
| 1605 | for (znum = 0; znum < MAX_NR_ZONES; znum++) |
| 1606 | zones_size[znum] = zholes_size[znum] = 0; |
| 1607 | |
| 1608 | npages = end_pfn - pfn_base; |
| 1609 | zones_size[ZONE_DMA] = npages; |
| 1610 | zholes_size[ZONE_DMA] = npages - pages_avail; |
| 1611 | |
| 1612 | free_area_init_node(0, &contig_page_data, zones_size, |
| 1613 | phys_base >> PAGE_SHIFT, zholes_size); |
| 1614 | } |
| 1615 | |
| 1616 | device_scan(); |
| 1617 | } |
| 1618 | |
| 1619 | /* Ok, it seems that the prom can allocate some more memory chunks |
| 1620 | * as a side effect of some prom calls we perform during the |
| 1621 | * boot sequence. My most likely theory is that it is from the |
| 1622 | * prom_set_traptable() call, and OBP is allocating a scratchpad |
| 1623 | * for saving client program register state etc. |
| 1624 | */ |
| 1625 | static void __init sort_memlist(struct linux_mlist_p1275 *thislist) |
| 1626 | { |
| 1627 | int swapi = 0; |
| 1628 | int i, mitr; |
| 1629 | unsigned long tmpaddr, tmpsize; |
| 1630 | unsigned long lowest; |
| 1631 | |
| 1632 | for (i = 0; thislist[i].theres_more != 0; i++) { |
| 1633 | lowest = thislist[i].start_adr; |
| 1634 | for (mitr = i+1; thislist[mitr-1].theres_more != 0; mitr++) |
| 1635 | if (thislist[mitr].start_adr < lowest) { |
| 1636 | lowest = thislist[mitr].start_adr; |
| 1637 | swapi = mitr; |
| 1638 | } |
| 1639 | if (lowest == thislist[i].start_adr) |
| 1640 | continue; |
| 1641 | tmpaddr = thislist[swapi].start_adr; |
| 1642 | tmpsize = thislist[swapi].num_bytes; |
| 1643 | for (mitr = swapi; mitr > i; mitr--) { |
| 1644 | thislist[mitr].start_adr = thislist[mitr-1].start_adr; |
| 1645 | thislist[mitr].num_bytes = thislist[mitr-1].num_bytes; |
| 1646 | } |
| 1647 | thislist[i].start_adr = tmpaddr; |
| 1648 | thislist[i].num_bytes = tmpsize; |
| 1649 | } |
| 1650 | } |
| 1651 | |
| 1652 | void __init rescan_sp_banks(void) |
| 1653 | { |
| 1654 | struct linux_prom64_registers memlist[64]; |
| 1655 | struct linux_mlist_p1275 avail[64], *mlist; |
| 1656 | unsigned long bytes, base_paddr; |
| 1657 | int num_regs, node = prom_finddevice("/memory"); |
| 1658 | int i; |
| 1659 | |
| 1660 | num_regs = prom_getproperty(node, "available", |
| 1661 | (char *) memlist, sizeof(memlist)); |
| 1662 | num_regs = (num_regs / sizeof(struct linux_prom64_registers)); |
| 1663 | for (i = 0; i < num_regs; i++) { |
| 1664 | avail[i].start_adr = memlist[i].phys_addr; |
| 1665 | avail[i].num_bytes = memlist[i].reg_size; |
| 1666 | avail[i].theres_more = &avail[i + 1]; |
| 1667 | } |
| 1668 | avail[i - 1].theres_more = NULL; |
| 1669 | sort_memlist(avail); |
| 1670 | |
| 1671 | mlist = &avail[0]; |
| 1672 | i = 0; |
| 1673 | bytes = mlist->num_bytes; |
| 1674 | base_paddr = mlist->start_adr; |
| 1675 | |
| 1676 | sp_banks[0].base_addr = base_paddr; |
| 1677 | sp_banks[0].num_bytes = bytes; |
| 1678 | |
| 1679 | while (mlist->theres_more != NULL){ |
| 1680 | i++; |
| 1681 | mlist = mlist->theres_more; |
| 1682 | bytes = mlist->num_bytes; |
| 1683 | if (i >= SPARC_PHYS_BANKS-1) { |
| 1684 | printk ("The machine has more banks than " |
| 1685 | "this kernel can support\n" |
| 1686 | "Increase the SPARC_PHYS_BANKS " |
| 1687 | "setting (currently %d)\n", |
| 1688 | SPARC_PHYS_BANKS); |
| 1689 | i = SPARC_PHYS_BANKS-1; |
| 1690 | break; |
| 1691 | } |
| 1692 | |
| 1693 | sp_banks[i].base_addr = mlist->start_adr; |
| 1694 | sp_banks[i].num_bytes = mlist->num_bytes; |
| 1695 | } |
| 1696 | |
| 1697 | i++; |
| 1698 | sp_banks[i].base_addr = 0xdeadbeefbeefdeadUL; |
| 1699 | sp_banks[i].num_bytes = 0; |
| 1700 | |
| 1701 | for (i = 0; sp_banks[i].num_bytes != 0; i++) |
| 1702 | sp_banks[i].num_bytes &= PAGE_MASK; |
| 1703 | } |
| 1704 | |
| 1705 | static void __init taint_real_pages(void) |
| 1706 | { |
| 1707 | struct sparc_phys_banks saved_sp_banks[SPARC_PHYS_BANKS]; |
| 1708 | int i; |
| 1709 | |
| 1710 | for (i = 0; i < SPARC_PHYS_BANKS; i++) { |
| 1711 | saved_sp_banks[i].base_addr = |
| 1712 | sp_banks[i].base_addr; |
| 1713 | saved_sp_banks[i].num_bytes = |
| 1714 | sp_banks[i].num_bytes; |
| 1715 | } |
| 1716 | |
| 1717 | rescan_sp_banks(); |
| 1718 | |
| 1719 | /* Find changes discovered in the sp_bank rescan and |
| 1720 | * reserve the lost portions in the bootmem maps. |
| 1721 | */ |
| 1722 | for (i = 0; saved_sp_banks[i].num_bytes; i++) { |
| 1723 | unsigned long old_start, old_end; |
| 1724 | |
| 1725 | old_start = saved_sp_banks[i].base_addr; |
| 1726 | old_end = old_start + |
| 1727 | saved_sp_banks[i].num_bytes; |
| 1728 | while (old_start < old_end) { |
| 1729 | int n; |
| 1730 | |
| 1731 | for (n = 0; sp_banks[n].num_bytes; n++) { |
| 1732 | unsigned long new_start, new_end; |
| 1733 | |
| 1734 | new_start = sp_banks[n].base_addr; |
| 1735 | new_end = new_start + sp_banks[n].num_bytes; |
| 1736 | |
| 1737 | if (new_start <= old_start && |
| 1738 | new_end >= (old_start + PAGE_SIZE)) { |
| 1739 | set_bit (old_start >> 22, |
| 1740 | sparc64_valid_addr_bitmap); |
| 1741 | goto do_next_page; |
| 1742 | } |
| 1743 | } |
| 1744 | reserve_bootmem(old_start, PAGE_SIZE); |
| 1745 | |
| 1746 | do_next_page: |
| 1747 | old_start += PAGE_SIZE; |
| 1748 | } |
| 1749 | } |
| 1750 | } |
| 1751 | |
| 1752 | void __init mem_init(void) |
| 1753 | { |
| 1754 | unsigned long codepages, datapages, initpages; |
| 1755 | unsigned long addr, last; |
| 1756 | int i; |
| 1757 | |
| 1758 | i = last_valid_pfn >> ((22 - PAGE_SHIFT) + 6); |
| 1759 | i += 1; |
| 1760 | sparc64_valid_addr_bitmap = (unsigned long *) |
| 1761 | __alloc_bootmem(i << 3, SMP_CACHE_BYTES, bootmap_base); |
| 1762 | if (sparc64_valid_addr_bitmap == NULL) { |
| 1763 | prom_printf("mem_init: Cannot alloc valid_addr_bitmap.\n"); |
| 1764 | prom_halt(); |
| 1765 | } |
| 1766 | memset(sparc64_valid_addr_bitmap, 0, i << 3); |
| 1767 | |
| 1768 | addr = PAGE_OFFSET + kern_base; |
| 1769 | last = PAGE_ALIGN(kern_size) + addr; |
| 1770 | while (addr < last) { |
| 1771 | set_bit(__pa(addr) >> 22, sparc64_valid_addr_bitmap); |
| 1772 | addr += PAGE_SIZE; |
| 1773 | } |
| 1774 | |
| 1775 | taint_real_pages(); |
| 1776 | |
| 1777 | max_mapnr = last_valid_pfn - pfn_base; |
| 1778 | high_memory = __va(last_valid_pfn << PAGE_SHIFT); |
| 1779 | |
| 1780 | #ifdef CONFIG_DEBUG_BOOTMEM |
| 1781 | prom_printf("mem_init: Calling free_all_bootmem().\n"); |
| 1782 | #endif |
| 1783 | totalram_pages = num_physpages = free_all_bootmem() - 1; |
| 1784 | |
| 1785 | /* |
| 1786 | * Set up the zero page, mark it reserved, so that page count |
| 1787 | * is not manipulated when freeing the page from user ptes. |
| 1788 | */ |
| 1789 | mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0); |
| 1790 | if (mem_map_zero == NULL) { |
| 1791 | prom_printf("paging_init: Cannot alloc zero page.\n"); |
| 1792 | prom_halt(); |
| 1793 | } |
| 1794 | SetPageReserved(mem_map_zero); |
| 1795 | |
| 1796 | codepages = (((unsigned long) _etext) - ((unsigned long) _start)); |
| 1797 | codepages = PAGE_ALIGN(codepages) >> PAGE_SHIFT; |
| 1798 | datapages = (((unsigned long) _edata) - ((unsigned long) _etext)); |
| 1799 | datapages = PAGE_ALIGN(datapages) >> PAGE_SHIFT; |
| 1800 | initpages = (((unsigned long) __init_end) - ((unsigned long) __init_begin)); |
| 1801 | initpages = PAGE_ALIGN(initpages) >> PAGE_SHIFT; |
| 1802 | |
| 1803 | printk("Memory: %uk available (%ldk kernel code, %ldk data, %ldk init) [%016lx,%016lx]\n", |
| 1804 | nr_free_pages() << (PAGE_SHIFT-10), |
| 1805 | codepages << (PAGE_SHIFT-10), |
| 1806 | datapages << (PAGE_SHIFT-10), |
| 1807 | initpages << (PAGE_SHIFT-10), |
| 1808 | PAGE_OFFSET, (last_valid_pfn << PAGE_SHIFT)); |
| 1809 | |
| 1810 | if (tlb_type == cheetah || tlb_type == cheetah_plus) |
| 1811 | cheetah_ecache_flush_init(); |
| 1812 | } |
| 1813 | |
| 1814 | void free_initmem (void) |
| 1815 | { |
| 1816 | unsigned long addr, initend; |
| 1817 | |
| 1818 | /* |
| 1819 | * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes. |
| 1820 | */ |
| 1821 | addr = PAGE_ALIGN((unsigned long)(__init_begin)); |
| 1822 | initend = (unsigned long)(__init_end) & PAGE_MASK; |
| 1823 | for (; addr < initend; addr += PAGE_SIZE) { |
| 1824 | unsigned long page; |
| 1825 | struct page *p; |
| 1826 | |
| 1827 | page = (addr + |
| 1828 | ((unsigned long) __va(kern_base)) - |
| 1829 | ((unsigned long) KERNBASE)); |
| 1830 | memset((void *)addr, 0xcc, PAGE_SIZE); |
| 1831 | p = virt_to_page(page); |
| 1832 | |
| 1833 | ClearPageReserved(p); |
| 1834 | set_page_count(p, 1); |
| 1835 | __free_page(p); |
| 1836 | num_physpages++; |
| 1837 | totalram_pages++; |
| 1838 | } |
| 1839 | } |
| 1840 | |
| 1841 | #ifdef CONFIG_BLK_DEV_INITRD |
| 1842 | void free_initrd_mem(unsigned long start, unsigned long end) |
| 1843 | { |
| 1844 | if (start < end) |
| 1845 | printk ("Freeing initrd memory: %ldk freed\n", (end - start) >> 10); |
| 1846 | for (; start < end; start += PAGE_SIZE) { |
| 1847 | struct page *p = virt_to_page(start); |
| 1848 | |
| 1849 | ClearPageReserved(p); |
| 1850 | set_page_count(p, 1); |
| 1851 | __free_page(p); |
| 1852 | num_physpages++; |
| 1853 | totalram_pages++; |
| 1854 | } |
| 1855 | } |
| 1856 | #endif |