Roland Stigge | 2944a44 | 2012-06-07 12:22:15 +0200 | [diff] [blame] | 1 | /* |
| 2 | * NXP LPC32XX NAND SLC driver |
| 3 | * |
| 4 | * Authors: |
| 5 | * Kevin Wells <kevin.wells@nxp.com> |
| 6 | * Roland Stigge <stigge@antcom.de> |
| 7 | * |
| 8 | * Copyright © 2011 NXP Semiconductors |
| 9 | * Copyright © 2012 Roland Stigge |
| 10 | * |
| 11 | * This program is free software; you can redistribute it and/or modify |
| 12 | * it under the terms of the GNU General Public License as published by |
| 13 | * the Free Software Foundation; either version 2 of the License, or |
| 14 | * (at your option) any later version. |
| 15 | * |
| 16 | * This program is distributed in the hope that it will be useful, |
| 17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 19 | * GNU General Public License for more details. |
| 20 | */ |
| 21 | |
| 22 | #include <linux/slab.h> |
| 23 | #include <linux/module.h> |
| 24 | #include <linux/platform_device.h> |
| 25 | #include <linux/mtd/mtd.h> |
| 26 | #include <linux/mtd/nand.h> |
| 27 | #include <linux/mtd/partitions.h> |
| 28 | #include <linux/clk.h> |
| 29 | #include <linux/err.h> |
| 30 | #include <linux/delay.h> |
| 31 | #include <linux/io.h> |
| 32 | #include <linux/mm.h> |
| 33 | #include <linux/dma-mapping.h> |
| 34 | #include <linux/dmaengine.h> |
| 35 | #include <linux/mtd/nand_ecc.h> |
| 36 | #include <linux/gpio.h> |
| 37 | #include <linux/of.h> |
| 38 | #include <linux/of_mtd.h> |
| 39 | #include <linux/of_gpio.h> |
Roland Stigge | de20c22 | 2012-08-16 15:15:34 +0200 | [diff] [blame] | 40 | #include <linux/mtd/lpc32xx_slc.h> |
Roland Stigge | 2944a44 | 2012-06-07 12:22:15 +0200 | [diff] [blame] | 41 | |
| 42 | #define LPC32XX_MODNAME "lpc32xx-nand" |
| 43 | |
| 44 | /********************************************************************** |
| 45 | * SLC NAND controller register offsets |
| 46 | **********************************************************************/ |
| 47 | |
| 48 | #define SLC_DATA(x) (x + 0x000) |
| 49 | #define SLC_ADDR(x) (x + 0x004) |
| 50 | #define SLC_CMD(x) (x + 0x008) |
| 51 | #define SLC_STOP(x) (x + 0x00C) |
| 52 | #define SLC_CTRL(x) (x + 0x010) |
| 53 | #define SLC_CFG(x) (x + 0x014) |
| 54 | #define SLC_STAT(x) (x + 0x018) |
| 55 | #define SLC_INT_STAT(x) (x + 0x01C) |
| 56 | #define SLC_IEN(x) (x + 0x020) |
| 57 | #define SLC_ISR(x) (x + 0x024) |
| 58 | #define SLC_ICR(x) (x + 0x028) |
| 59 | #define SLC_TAC(x) (x + 0x02C) |
| 60 | #define SLC_TC(x) (x + 0x030) |
| 61 | #define SLC_ECC(x) (x + 0x034) |
| 62 | #define SLC_DMA_DATA(x) (x + 0x038) |
| 63 | |
| 64 | /********************************************************************** |
| 65 | * slc_ctrl register definitions |
| 66 | **********************************************************************/ |
| 67 | #define SLCCTRL_SW_RESET (1 << 2) /* Reset the NAND controller bit */ |
| 68 | #define SLCCTRL_ECC_CLEAR (1 << 1) /* Reset ECC bit */ |
| 69 | #define SLCCTRL_DMA_START (1 << 0) /* Start DMA channel bit */ |
| 70 | |
| 71 | /********************************************************************** |
| 72 | * slc_cfg register definitions |
| 73 | **********************************************************************/ |
| 74 | #define SLCCFG_CE_LOW (1 << 5) /* Force CE low bit */ |
| 75 | #define SLCCFG_DMA_ECC (1 << 4) /* Enable DMA ECC bit */ |
| 76 | #define SLCCFG_ECC_EN (1 << 3) /* ECC enable bit */ |
| 77 | #define SLCCFG_DMA_BURST (1 << 2) /* DMA burst bit */ |
| 78 | #define SLCCFG_DMA_DIR (1 << 1) /* DMA write(0)/read(1) bit */ |
| 79 | #define SLCCFG_WIDTH (1 << 0) /* External device width, 0=8bit */ |
| 80 | |
| 81 | /********************************************************************** |
| 82 | * slc_stat register definitions |
| 83 | **********************************************************************/ |
| 84 | #define SLCSTAT_DMA_FIFO (1 << 2) /* DMA FIFO has data bit */ |
| 85 | #define SLCSTAT_SLC_FIFO (1 << 1) /* SLC FIFO has data bit */ |
| 86 | #define SLCSTAT_NAND_READY (1 << 0) /* NAND device is ready bit */ |
| 87 | |
| 88 | /********************************************************************** |
| 89 | * slc_int_stat, slc_ien, slc_isr, and slc_icr register definitions |
| 90 | **********************************************************************/ |
| 91 | #define SLCSTAT_INT_TC (1 << 1) /* Transfer count bit */ |
| 92 | #define SLCSTAT_INT_RDY_EN (1 << 0) /* Ready interrupt bit */ |
| 93 | |
| 94 | /********************************************************************** |
| 95 | * slc_tac register definitions |
| 96 | **********************************************************************/ |
| 97 | /* Clock setting for RDY write sample wait time in 2*n clocks */ |
| 98 | #define SLCTAC_WDR(n) (((n) & 0xF) << 28) |
| 99 | /* Write pulse width in clock cycles, 1 to 16 clocks */ |
| 100 | #define SLCTAC_WWIDTH(n) (((n) & 0xF) << 24) |
| 101 | /* Write hold time of control and data signals, 1 to 16 clocks */ |
| 102 | #define SLCTAC_WHOLD(n) (((n) & 0xF) << 20) |
| 103 | /* Write setup time of control and data signals, 1 to 16 clocks */ |
| 104 | #define SLCTAC_WSETUP(n) (((n) & 0xF) << 16) |
| 105 | /* Clock setting for RDY read sample wait time in 2*n clocks */ |
| 106 | #define SLCTAC_RDR(n) (((n) & 0xF) << 12) |
| 107 | /* Read pulse width in clock cycles, 1 to 16 clocks */ |
| 108 | #define SLCTAC_RWIDTH(n) (((n) & 0xF) << 8) |
| 109 | /* Read hold time of control and data signals, 1 to 16 clocks */ |
| 110 | #define SLCTAC_RHOLD(n) (((n) & 0xF) << 4) |
| 111 | /* Read setup time of control and data signals, 1 to 16 clocks */ |
| 112 | #define SLCTAC_RSETUP(n) (((n) & 0xF) << 0) |
| 113 | |
| 114 | /********************************************************************** |
| 115 | * slc_ecc register definitions |
| 116 | **********************************************************************/ |
| 117 | /* ECC line party fetch macro */ |
| 118 | #define SLCECC_TO_LINEPAR(n) (((n) >> 6) & 0x7FFF) |
| 119 | #define SLCECC_TO_COLPAR(n) ((n) & 0x3F) |
| 120 | |
| 121 | /* |
| 122 | * DMA requires storage space for the DMA local buffer and the hardware ECC |
| 123 | * storage area. The DMA local buffer is only used if DMA mapping fails |
| 124 | * during runtime. |
| 125 | */ |
| 126 | #define LPC32XX_DMA_DATA_SIZE 4096 |
| 127 | #define LPC32XX_ECC_SAVE_SIZE ((4096 / 256) * 4) |
| 128 | |
| 129 | /* Number of bytes used for ECC stored in NAND per 256 bytes */ |
| 130 | #define LPC32XX_SLC_DEV_ECC_BYTES 3 |
| 131 | |
| 132 | /* |
| 133 | * If the NAND base clock frequency can't be fetched, this frequency will be |
| 134 | * used instead as the base. This rate is used to setup the timing registers |
| 135 | * used for NAND accesses. |
| 136 | */ |
| 137 | #define LPC32XX_DEF_BUS_RATE 133250000 |
| 138 | |
| 139 | /* Milliseconds for DMA FIFO timeout (unlikely anyway) */ |
| 140 | #define LPC32XX_DMA_TIMEOUT 100 |
| 141 | |
| 142 | /* |
| 143 | * NAND ECC Layout for small page NAND devices |
| 144 | * Note: For large and huge page devices, the default layouts are used |
| 145 | */ |
| 146 | static struct nand_ecclayout lpc32xx_nand_oob_16 = { |
| 147 | .eccbytes = 6, |
| 148 | .eccpos = {10, 11, 12, 13, 14, 15}, |
| 149 | .oobfree = { |
| 150 | { .offset = 0, .length = 4 }, |
| 151 | { .offset = 6, .length = 4 }, |
| 152 | }, |
| 153 | }; |
| 154 | |
| 155 | static u8 bbt_pattern[] = {'B', 'b', 't', '0' }; |
| 156 | static u8 mirror_pattern[] = {'1', 't', 'b', 'B' }; |
| 157 | |
| 158 | /* |
| 159 | * Small page FLASH BBT descriptors, marker at offset 0, version at offset 6 |
| 160 | * Note: Large page devices used the default layout |
| 161 | */ |
| 162 | static struct nand_bbt_descr bbt_smallpage_main_descr = { |
| 163 | .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
| 164 | | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, |
| 165 | .offs = 0, |
| 166 | .len = 4, |
| 167 | .veroffs = 6, |
| 168 | .maxblocks = 4, |
| 169 | .pattern = bbt_pattern |
| 170 | }; |
| 171 | |
| 172 | static struct nand_bbt_descr bbt_smallpage_mirror_descr = { |
| 173 | .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
| 174 | | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, |
| 175 | .offs = 0, |
| 176 | .len = 4, |
| 177 | .veroffs = 6, |
| 178 | .maxblocks = 4, |
| 179 | .pattern = mirror_pattern |
| 180 | }; |
| 181 | |
| 182 | /* |
| 183 | * NAND platform configuration structure |
| 184 | */ |
| 185 | struct lpc32xx_nand_cfg_slc { |
| 186 | uint32_t wdr_clks; |
| 187 | uint32_t wwidth; |
| 188 | uint32_t whold; |
| 189 | uint32_t wsetup; |
| 190 | uint32_t rdr_clks; |
| 191 | uint32_t rwidth; |
| 192 | uint32_t rhold; |
| 193 | uint32_t rsetup; |
| 194 | bool use_bbt; |
Alexandre Pereira da Silva | df63fe7 | 2012-06-27 17:51:13 +0200 | [diff] [blame] | 195 | int wp_gpio; |
Roland Stigge | 2944a44 | 2012-06-07 12:22:15 +0200 | [diff] [blame] | 196 | struct mtd_partition *parts; |
| 197 | unsigned num_parts; |
| 198 | }; |
| 199 | |
| 200 | struct lpc32xx_nand_host { |
| 201 | struct nand_chip nand_chip; |
Roland Stigge | de20c22 | 2012-08-16 15:15:34 +0200 | [diff] [blame] | 202 | struct lpc32xx_slc_platform_data *pdata; |
Roland Stigge | 2944a44 | 2012-06-07 12:22:15 +0200 | [diff] [blame] | 203 | struct clk *clk; |
| 204 | struct mtd_info mtd; |
| 205 | void __iomem *io_base; |
| 206 | struct lpc32xx_nand_cfg_slc *ncfg; |
| 207 | |
| 208 | struct completion comp; |
| 209 | struct dma_chan *dma_chan; |
| 210 | uint32_t dma_buf_len; |
| 211 | struct dma_slave_config dma_slave_config; |
| 212 | struct scatterlist sgl; |
| 213 | |
| 214 | /* |
| 215 | * DMA and CPU addresses of ECC work area and data buffer |
| 216 | */ |
| 217 | uint32_t *ecc_buf; |
| 218 | uint8_t *data_buf; |
| 219 | dma_addr_t io_base_dma; |
| 220 | }; |
| 221 | |
| 222 | static void lpc32xx_nand_setup(struct lpc32xx_nand_host *host) |
| 223 | { |
| 224 | uint32_t clkrate, tmp; |
| 225 | |
| 226 | /* Reset SLC controller */ |
| 227 | writel(SLCCTRL_SW_RESET, SLC_CTRL(host->io_base)); |
| 228 | udelay(1000); |
| 229 | |
| 230 | /* Basic setup */ |
| 231 | writel(0, SLC_CFG(host->io_base)); |
| 232 | writel(0, SLC_IEN(host->io_base)); |
| 233 | writel((SLCSTAT_INT_TC | SLCSTAT_INT_RDY_EN), |
| 234 | SLC_ICR(host->io_base)); |
| 235 | |
| 236 | /* Get base clock for SLC block */ |
| 237 | clkrate = clk_get_rate(host->clk); |
| 238 | if (clkrate == 0) |
| 239 | clkrate = LPC32XX_DEF_BUS_RATE; |
| 240 | |
| 241 | /* Compute clock setup values */ |
| 242 | tmp = SLCTAC_WDR(host->ncfg->wdr_clks) | |
| 243 | SLCTAC_WWIDTH(1 + (clkrate / host->ncfg->wwidth)) | |
| 244 | SLCTAC_WHOLD(1 + (clkrate / host->ncfg->whold)) | |
| 245 | SLCTAC_WSETUP(1 + (clkrate / host->ncfg->wsetup)) | |
| 246 | SLCTAC_RDR(host->ncfg->rdr_clks) | |
| 247 | SLCTAC_RWIDTH(1 + (clkrate / host->ncfg->rwidth)) | |
| 248 | SLCTAC_RHOLD(1 + (clkrate / host->ncfg->rhold)) | |
| 249 | SLCTAC_RSETUP(1 + (clkrate / host->ncfg->rsetup)); |
| 250 | writel(tmp, SLC_TAC(host->io_base)); |
| 251 | } |
| 252 | |
| 253 | /* |
| 254 | * Hardware specific access to control lines |
| 255 | */ |
| 256 | static void lpc32xx_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, |
| 257 | unsigned int ctrl) |
| 258 | { |
| 259 | uint32_t tmp; |
| 260 | struct nand_chip *chip = mtd->priv; |
| 261 | struct lpc32xx_nand_host *host = chip->priv; |
| 262 | |
| 263 | /* Does CE state need to be changed? */ |
| 264 | tmp = readl(SLC_CFG(host->io_base)); |
| 265 | if (ctrl & NAND_NCE) |
| 266 | tmp |= SLCCFG_CE_LOW; |
| 267 | else |
| 268 | tmp &= ~SLCCFG_CE_LOW; |
| 269 | writel(tmp, SLC_CFG(host->io_base)); |
| 270 | |
| 271 | if (cmd != NAND_CMD_NONE) { |
| 272 | if (ctrl & NAND_CLE) |
| 273 | writel(cmd, SLC_CMD(host->io_base)); |
| 274 | else |
| 275 | writel(cmd, SLC_ADDR(host->io_base)); |
| 276 | } |
| 277 | } |
| 278 | |
| 279 | /* |
| 280 | * Read the Device Ready pin |
| 281 | */ |
| 282 | static int lpc32xx_nand_device_ready(struct mtd_info *mtd) |
| 283 | { |
| 284 | struct nand_chip *chip = mtd->priv; |
| 285 | struct lpc32xx_nand_host *host = chip->priv; |
| 286 | int rdy = 0; |
| 287 | |
| 288 | if ((readl(SLC_STAT(host->io_base)) & SLCSTAT_NAND_READY) != 0) |
| 289 | rdy = 1; |
| 290 | |
| 291 | return rdy; |
| 292 | } |
| 293 | |
| 294 | /* |
| 295 | * Enable NAND write protect |
| 296 | */ |
| 297 | static void lpc32xx_wp_enable(struct lpc32xx_nand_host *host) |
| 298 | { |
Alexandre Pereira da Silva | df63fe7 | 2012-06-27 17:51:13 +0200 | [diff] [blame] | 299 | if (gpio_is_valid(host->ncfg->wp_gpio)) |
| 300 | gpio_set_value(host->ncfg->wp_gpio, 0); |
Roland Stigge | 2944a44 | 2012-06-07 12:22:15 +0200 | [diff] [blame] | 301 | } |
| 302 | |
| 303 | /* |
| 304 | * Disable NAND write protect |
| 305 | */ |
| 306 | static void lpc32xx_wp_disable(struct lpc32xx_nand_host *host) |
| 307 | { |
Alexandre Pereira da Silva | df63fe7 | 2012-06-27 17:51:13 +0200 | [diff] [blame] | 308 | if (gpio_is_valid(host->ncfg->wp_gpio)) |
| 309 | gpio_set_value(host->ncfg->wp_gpio, 1); |
Roland Stigge | 2944a44 | 2012-06-07 12:22:15 +0200 | [diff] [blame] | 310 | } |
| 311 | |
| 312 | /* |
| 313 | * Prepares SLC for transfers with H/W ECC enabled |
| 314 | */ |
| 315 | static void lpc32xx_nand_ecc_enable(struct mtd_info *mtd, int mode) |
| 316 | { |
| 317 | /* Hardware ECC is enabled automatically in hardware as needed */ |
| 318 | } |
| 319 | |
| 320 | /* |
| 321 | * Calculates the ECC for the data |
| 322 | */ |
| 323 | static int lpc32xx_nand_ecc_calculate(struct mtd_info *mtd, |
| 324 | const unsigned char *buf, |
| 325 | unsigned char *code) |
| 326 | { |
| 327 | /* |
| 328 | * ECC is calculated automatically in hardware during syndrome read |
| 329 | * and write operations, so it doesn't need to be calculated here. |
| 330 | */ |
| 331 | return 0; |
| 332 | } |
| 333 | |
| 334 | /* |
| 335 | * Read a single byte from NAND device |
| 336 | */ |
| 337 | static uint8_t lpc32xx_nand_read_byte(struct mtd_info *mtd) |
| 338 | { |
| 339 | struct nand_chip *chip = mtd->priv; |
| 340 | struct lpc32xx_nand_host *host = chip->priv; |
| 341 | |
| 342 | return (uint8_t)readl(SLC_DATA(host->io_base)); |
| 343 | } |
| 344 | |
| 345 | /* |
| 346 | * Simple device read without ECC |
| 347 | */ |
| 348 | static void lpc32xx_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) |
| 349 | { |
| 350 | struct nand_chip *chip = mtd->priv; |
| 351 | struct lpc32xx_nand_host *host = chip->priv; |
| 352 | |
| 353 | /* Direct device read with no ECC */ |
| 354 | while (len-- > 0) |
| 355 | *buf++ = (uint8_t)readl(SLC_DATA(host->io_base)); |
| 356 | } |
| 357 | |
| 358 | /* |
| 359 | * Simple device write without ECC |
| 360 | */ |
| 361 | static void lpc32xx_nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) |
| 362 | { |
| 363 | struct nand_chip *chip = mtd->priv; |
| 364 | struct lpc32xx_nand_host *host = chip->priv; |
| 365 | |
| 366 | /* Direct device write with no ECC */ |
| 367 | while (len-- > 0) |
| 368 | writel((uint32_t)*buf++, SLC_DATA(host->io_base)); |
| 369 | } |
| 370 | |
| 371 | /* |
Roland Stigge | 2944a44 | 2012-06-07 12:22:15 +0200 | [diff] [blame] | 372 | * Read the OOB data from the device without ECC using FIFO method |
| 373 | */ |
| 374 | static int lpc32xx_nand_read_oob_syndrome(struct mtd_info *mtd, |
| 375 | struct nand_chip *chip, int page) |
| 376 | { |
| 377 | chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page); |
| 378 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); |
| 379 | |
| 380 | return 0; |
| 381 | } |
| 382 | |
| 383 | /* |
| 384 | * Write the OOB data to the device without ECC using FIFO method |
| 385 | */ |
| 386 | static int lpc32xx_nand_write_oob_syndrome(struct mtd_info *mtd, |
| 387 | struct nand_chip *chip, int page) |
| 388 | { |
| 389 | int status; |
| 390 | |
| 391 | chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page); |
| 392 | chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); |
| 393 | |
| 394 | /* Send command to program the OOB data */ |
| 395 | chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); |
| 396 | |
| 397 | status = chip->waitfunc(mtd, chip); |
| 398 | |
| 399 | return status & NAND_STATUS_FAIL ? -EIO : 0; |
| 400 | } |
| 401 | |
| 402 | /* |
| 403 | * Fills in the ECC fields in the OOB buffer with the hardware generated ECC |
| 404 | */ |
| 405 | static void lpc32xx_slc_ecc_copy(uint8_t *spare, const uint32_t *ecc, int count) |
| 406 | { |
| 407 | int i; |
| 408 | |
| 409 | for (i = 0; i < (count * 3); i += 3) { |
| 410 | uint32_t ce = ecc[i / 3]; |
| 411 | ce = ~(ce << 2) & 0xFFFFFF; |
| 412 | spare[i + 2] = (uint8_t)(ce & 0xFF); |
| 413 | ce >>= 8; |
| 414 | spare[i + 1] = (uint8_t)(ce & 0xFF); |
| 415 | ce >>= 8; |
| 416 | spare[i] = (uint8_t)(ce & 0xFF); |
| 417 | } |
| 418 | } |
| 419 | |
| 420 | static void lpc32xx_dma_complete_func(void *completion) |
| 421 | { |
| 422 | complete(completion); |
| 423 | } |
| 424 | |
| 425 | static int lpc32xx_xmit_dma(struct mtd_info *mtd, dma_addr_t dma, |
| 426 | void *mem, int len, enum dma_transfer_direction dir) |
| 427 | { |
| 428 | struct nand_chip *chip = mtd->priv; |
| 429 | struct lpc32xx_nand_host *host = chip->priv; |
| 430 | struct dma_async_tx_descriptor *desc; |
| 431 | int flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT; |
| 432 | int res; |
| 433 | |
| 434 | host->dma_slave_config.direction = dir; |
| 435 | host->dma_slave_config.src_addr = dma; |
| 436 | host->dma_slave_config.dst_addr = dma; |
| 437 | host->dma_slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; |
| 438 | host->dma_slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; |
| 439 | host->dma_slave_config.src_maxburst = 4; |
| 440 | host->dma_slave_config.dst_maxburst = 4; |
| 441 | /* DMA controller does flow control: */ |
| 442 | host->dma_slave_config.device_fc = false; |
| 443 | if (dmaengine_slave_config(host->dma_chan, &host->dma_slave_config)) { |
| 444 | dev_err(mtd->dev.parent, "Failed to setup DMA slave\n"); |
| 445 | return -ENXIO; |
| 446 | } |
| 447 | |
| 448 | sg_init_one(&host->sgl, mem, len); |
| 449 | |
| 450 | res = dma_map_sg(host->dma_chan->device->dev, &host->sgl, 1, |
| 451 | DMA_BIDIRECTIONAL); |
| 452 | if (res != 1) { |
| 453 | dev_err(mtd->dev.parent, "Failed to map sg list\n"); |
| 454 | return -ENXIO; |
| 455 | } |
| 456 | desc = dmaengine_prep_slave_sg(host->dma_chan, &host->sgl, 1, dir, |
| 457 | flags); |
| 458 | if (!desc) { |
| 459 | dev_err(mtd->dev.parent, "Failed to prepare slave sg\n"); |
| 460 | goto out1; |
| 461 | } |
| 462 | |
| 463 | init_completion(&host->comp); |
| 464 | desc->callback = lpc32xx_dma_complete_func; |
| 465 | desc->callback_param = &host->comp; |
| 466 | |
| 467 | dmaengine_submit(desc); |
| 468 | dma_async_issue_pending(host->dma_chan); |
| 469 | |
| 470 | wait_for_completion_timeout(&host->comp, msecs_to_jiffies(1000)); |
| 471 | |
| 472 | dma_unmap_sg(host->dma_chan->device->dev, &host->sgl, 1, |
| 473 | DMA_BIDIRECTIONAL); |
| 474 | |
| 475 | return 0; |
| 476 | out1: |
| 477 | dma_unmap_sg(host->dma_chan->device->dev, &host->sgl, 1, |
| 478 | DMA_BIDIRECTIONAL); |
| 479 | return -ENXIO; |
| 480 | } |
| 481 | |
| 482 | /* |
| 483 | * DMA read/write transfers with ECC support |
| 484 | */ |
| 485 | static int lpc32xx_xfer(struct mtd_info *mtd, uint8_t *buf, int eccsubpages, |
| 486 | int read) |
| 487 | { |
| 488 | struct nand_chip *chip = mtd->priv; |
| 489 | struct lpc32xx_nand_host *host = chip->priv; |
| 490 | int i, status = 0; |
| 491 | unsigned long timeout; |
| 492 | int res; |
| 493 | enum dma_transfer_direction dir = |
| 494 | read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV; |
| 495 | uint8_t *dma_buf; |
| 496 | bool dma_mapped; |
| 497 | |
| 498 | if ((void *)buf <= high_memory) { |
| 499 | dma_buf = buf; |
| 500 | dma_mapped = true; |
| 501 | } else { |
| 502 | dma_buf = host->data_buf; |
| 503 | dma_mapped = false; |
| 504 | if (!read) |
| 505 | memcpy(host->data_buf, buf, mtd->writesize); |
| 506 | } |
| 507 | |
| 508 | if (read) { |
| 509 | writel(readl(SLC_CFG(host->io_base)) | |
| 510 | SLCCFG_DMA_DIR | SLCCFG_ECC_EN | SLCCFG_DMA_ECC | |
| 511 | SLCCFG_DMA_BURST, SLC_CFG(host->io_base)); |
| 512 | } else { |
| 513 | writel((readl(SLC_CFG(host->io_base)) | |
| 514 | SLCCFG_ECC_EN | SLCCFG_DMA_ECC | SLCCFG_DMA_BURST) & |
| 515 | ~SLCCFG_DMA_DIR, |
| 516 | SLC_CFG(host->io_base)); |
| 517 | } |
| 518 | |
| 519 | /* Clear initial ECC */ |
| 520 | writel(SLCCTRL_ECC_CLEAR, SLC_CTRL(host->io_base)); |
| 521 | |
| 522 | /* Transfer size is data area only */ |
| 523 | writel(mtd->writesize, SLC_TC(host->io_base)); |
| 524 | |
| 525 | /* Start transfer in the NAND controller */ |
| 526 | writel(readl(SLC_CTRL(host->io_base)) | SLCCTRL_DMA_START, |
| 527 | SLC_CTRL(host->io_base)); |
| 528 | |
| 529 | for (i = 0; i < chip->ecc.steps; i++) { |
| 530 | /* Data */ |
| 531 | res = lpc32xx_xmit_dma(mtd, SLC_DMA_DATA(host->io_base_dma), |
| 532 | dma_buf + i * chip->ecc.size, |
| 533 | mtd->writesize / chip->ecc.steps, dir); |
| 534 | if (res) |
| 535 | return res; |
| 536 | |
| 537 | /* Always _read_ ECC */ |
| 538 | if (i == chip->ecc.steps - 1) |
| 539 | break; |
| 540 | if (!read) /* ECC availability delayed on write */ |
| 541 | udelay(10); |
| 542 | res = lpc32xx_xmit_dma(mtd, SLC_ECC(host->io_base_dma), |
| 543 | &host->ecc_buf[i], 4, DMA_DEV_TO_MEM); |
| 544 | if (res) |
| 545 | return res; |
| 546 | } |
| 547 | |
| 548 | /* |
| 549 | * According to NXP, the DMA can be finished here, but the NAND |
| 550 | * controller may still have buffered data. After porting to using the |
| 551 | * dmaengine DMA driver (amba-pl080), the condition (DMA_FIFO empty) |
| 552 | * appears to be always true, according to tests. Keeping the check for |
| 553 | * safety reasons for now. |
| 554 | */ |
| 555 | if (readl(SLC_STAT(host->io_base)) & SLCSTAT_DMA_FIFO) { |
| 556 | dev_warn(mtd->dev.parent, "FIFO not empty!\n"); |
| 557 | timeout = jiffies + msecs_to_jiffies(LPC32XX_DMA_TIMEOUT); |
| 558 | while ((readl(SLC_STAT(host->io_base)) & SLCSTAT_DMA_FIFO) && |
| 559 | time_before(jiffies, timeout)) |
| 560 | cpu_relax(); |
| 561 | if (!time_before(jiffies, timeout)) { |
| 562 | dev_err(mtd->dev.parent, "FIFO held data too long\n"); |
| 563 | status = -EIO; |
| 564 | } |
| 565 | } |
| 566 | |
| 567 | /* Read last calculated ECC value */ |
| 568 | if (!read) |
| 569 | udelay(10); |
| 570 | host->ecc_buf[chip->ecc.steps - 1] = |
| 571 | readl(SLC_ECC(host->io_base)); |
| 572 | |
| 573 | /* Flush DMA */ |
| 574 | dmaengine_terminate_all(host->dma_chan); |
| 575 | |
| 576 | if (readl(SLC_STAT(host->io_base)) & SLCSTAT_DMA_FIFO || |
| 577 | readl(SLC_TC(host->io_base))) { |
| 578 | /* Something is left in the FIFO, something is wrong */ |
| 579 | dev_err(mtd->dev.parent, "DMA FIFO failure\n"); |
| 580 | status = -EIO; |
| 581 | } |
| 582 | |
| 583 | /* Stop DMA & HW ECC */ |
| 584 | writel(readl(SLC_CTRL(host->io_base)) & ~SLCCTRL_DMA_START, |
| 585 | SLC_CTRL(host->io_base)); |
| 586 | writel(readl(SLC_CFG(host->io_base)) & |
| 587 | ~(SLCCFG_DMA_DIR | SLCCFG_ECC_EN | SLCCFG_DMA_ECC | |
| 588 | SLCCFG_DMA_BURST), SLC_CFG(host->io_base)); |
| 589 | |
| 590 | if (!dma_mapped && read) |
| 591 | memcpy(buf, host->data_buf, mtd->writesize); |
| 592 | |
| 593 | return status; |
| 594 | } |
| 595 | |
| 596 | /* |
| 597 | * Read the data and OOB data from the device, use ECC correction with the |
| 598 | * data, disable ECC for the OOB data |
| 599 | */ |
| 600 | static int lpc32xx_nand_read_page_syndrome(struct mtd_info *mtd, |
| 601 | struct nand_chip *chip, uint8_t *buf, |
| 602 | int oob_required, int page) |
| 603 | { |
| 604 | struct lpc32xx_nand_host *host = chip->priv; |
| 605 | int stat, i, status; |
| 606 | uint8_t *oobecc, tmpecc[LPC32XX_ECC_SAVE_SIZE]; |
| 607 | |
| 608 | /* Issue read command */ |
| 609 | chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page); |
| 610 | |
| 611 | /* Read data and oob, calculate ECC */ |
| 612 | status = lpc32xx_xfer(mtd, buf, chip->ecc.steps, 1); |
| 613 | |
| 614 | /* Get OOB data */ |
| 615 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); |
| 616 | |
| 617 | /* Convert to stored ECC format */ |
| 618 | lpc32xx_slc_ecc_copy(tmpecc, (uint32_t *) host->ecc_buf, chip->ecc.steps); |
| 619 | |
| 620 | /* Pointer to ECC data retrieved from NAND spare area */ |
| 621 | oobecc = chip->oob_poi + chip->ecc.layout->eccpos[0]; |
| 622 | |
| 623 | for (i = 0; i < chip->ecc.steps; i++) { |
| 624 | stat = chip->ecc.correct(mtd, buf, oobecc, |
| 625 | &tmpecc[i * chip->ecc.bytes]); |
| 626 | if (stat < 0) |
| 627 | mtd->ecc_stats.failed++; |
| 628 | else |
| 629 | mtd->ecc_stats.corrected += stat; |
| 630 | |
| 631 | buf += chip->ecc.size; |
| 632 | oobecc += chip->ecc.bytes; |
| 633 | } |
| 634 | |
| 635 | return status; |
| 636 | } |
| 637 | |
| 638 | /* |
| 639 | * Read the data and OOB data from the device, no ECC correction with the |
| 640 | * data or OOB data |
| 641 | */ |
| 642 | static int lpc32xx_nand_read_page_raw_syndrome(struct mtd_info *mtd, |
| 643 | struct nand_chip *chip, |
| 644 | uint8_t *buf, int oob_required, |
| 645 | int page) |
| 646 | { |
| 647 | /* Issue read command */ |
| 648 | chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page); |
| 649 | |
| 650 | /* Raw reads can just use the FIFO interface */ |
| 651 | chip->read_buf(mtd, buf, chip->ecc.size * chip->ecc.steps); |
| 652 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); |
| 653 | |
| 654 | return 0; |
| 655 | } |
| 656 | |
| 657 | /* |
| 658 | * Write the data and OOB data to the device, use ECC with the data, |
| 659 | * disable ECC for the OOB data |
| 660 | */ |
| 661 | static int lpc32xx_nand_write_page_syndrome(struct mtd_info *mtd, |
| 662 | struct nand_chip *chip, |
| 663 | const uint8_t *buf, int oob_required) |
| 664 | { |
| 665 | struct lpc32xx_nand_host *host = chip->priv; |
| 666 | uint8_t *pb = chip->oob_poi + chip->ecc.layout->eccpos[0]; |
| 667 | int error; |
| 668 | |
| 669 | /* Write data, calculate ECC on outbound data */ |
| 670 | error = lpc32xx_xfer(mtd, (uint8_t *)buf, chip->ecc.steps, 0); |
| 671 | if (error) |
| 672 | return error; |
| 673 | |
| 674 | /* |
| 675 | * The calculated ECC needs some manual work done to it before |
| 676 | * committing it to NAND. Process the calculated ECC and place |
| 677 | * the resultant values directly into the OOB buffer. */ |
| 678 | lpc32xx_slc_ecc_copy(pb, (uint32_t *)host->ecc_buf, chip->ecc.steps); |
| 679 | |
| 680 | /* Write ECC data to device */ |
| 681 | chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); |
| 682 | return 0; |
| 683 | } |
| 684 | |
| 685 | /* |
| 686 | * Write the data and OOB data to the device, no ECC correction with the |
| 687 | * data or OOB data |
| 688 | */ |
| 689 | static int lpc32xx_nand_write_page_raw_syndrome(struct mtd_info *mtd, |
| 690 | struct nand_chip *chip, |
| 691 | const uint8_t *buf, |
| 692 | int oob_required) |
| 693 | { |
| 694 | /* Raw writes can just use the FIFO interface */ |
| 695 | chip->write_buf(mtd, buf, chip->ecc.size * chip->ecc.steps); |
| 696 | chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); |
| 697 | return 0; |
| 698 | } |
| 699 | |
Roland Stigge | 2944a44 | 2012-06-07 12:22:15 +0200 | [diff] [blame] | 700 | static int lpc32xx_nand_dma_setup(struct lpc32xx_nand_host *host) |
| 701 | { |
| 702 | struct mtd_info *mtd = &host->mtd; |
| 703 | dma_cap_mask_t mask; |
| 704 | |
Roland Stigge | de20c22 | 2012-08-16 15:15:34 +0200 | [diff] [blame] | 705 | if (!host->pdata || !host->pdata->dma_filter) { |
| 706 | dev_err(mtd->dev.parent, "no DMA platform data\n"); |
| 707 | return -ENOENT; |
| 708 | } |
| 709 | |
Roland Stigge | 2944a44 | 2012-06-07 12:22:15 +0200 | [diff] [blame] | 710 | dma_cap_zero(mask); |
| 711 | dma_cap_set(DMA_SLAVE, mask); |
Roland Stigge | de20c22 | 2012-08-16 15:15:34 +0200 | [diff] [blame] | 712 | host->dma_chan = dma_request_channel(mask, host->pdata->dma_filter, |
| 713 | "nand-slc"); |
Roland Stigge | 2944a44 | 2012-06-07 12:22:15 +0200 | [diff] [blame] | 714 | if (!host->dma_chan) { |
| 715 | dev_err(mtd->dev.parent, "Failed to request DMA channel\n"); |
| 716 | return -EBUSY; |
| 717 | } |
| 718 | |
| 719 | return 0; |
| 720 | } |
| 721 | |
Roland Stigge | 2944a44 | 2012-06-07 12:22:15 +0200 | [diff] [blame] | 722 | static struct lpc32xx_nand_cfg_slc *lpc32xx_parse_dt(struct device *dev) |
| 723 | { |
Roland Stigge | 10594f6 | 2012-08-24 15:06:51 +0200 | [diff] [blame] | 724 | struct lpc32xx_nand_cfg_slc *ncfg; |
Roland Stigge | 2944a44 | 2012-06-07 12:22:15 +0200 | [diff] [blame] | 725 | struct device_node *np = dev->of_node; |
| 726 | |
Roland Stigge | 10594f6 | 2012-08-24 15:06:51 +0200 | [diff] [blame] | 727 | ncfg = devm_kzalloc(dev, sizeof(*ncfg), GFP_KERNEL); |
Jingoo Han | 8ecb66b | 2013-12-26 12:18:56 +0900 | [diff] [blame] | 728 | if (!ncfg) |
Roland Stigge | 2944a44 | 2012-06-07 12:22:15 +0200 | [diff] [blame] | 729 | return NULL; |
Roland Stigge | 2944a44 | 2012-06-07 12:22:15 +0200 | [diff] [blame] | 730 | |
Roland Stigge | 10594f6 | 2012-08-24 15:06:51 +0200 | [diff] [blame] | 731 | of_property_read_u32(np, "nxp,wdr-clks", &ncfg->wdr_clks); |
| 732 | of_property_read_u32(np, "nxp,wwidth", &ncfg->wwidth); |
| 733 | of_property_read_u32(np, "nxp,whold", &ncfg->whold); |
| 734 | of_property_read_u32(np, "nxp,wsetup", &ncfg->wsetup); |
| 735 | of_property_read_u32(np, "nxp,rdr-clks", &ncfg->rdr_clks); |
| 736 | of_property_read_u32(np, "nxp,rwidth", &ncfg->rwidth); |
| 737 | of_property_read_u32(np, "nxp,rhold", &ncfg->rhold); |
| 738 | of_property_read_u32(np, "nxp,rsetup", &ncfg->rsetup); |
Roland Stigge | 2944a44 | 2012-06-07 12:22:15 +0200 | [diff] [blame] | 739 | |
Roland Stigge | 10594f6 | 2012-08-24 15:06:51 +0200 | [diff] [blame] | 740 | if (!ncfg->wdr_clks || !ncfg->wwidth || !ncfg->whold || |
| 741 | !ncfg->wsetup || !ncfg->rdr_clks || !ncfg->rwidth || |
| 742 | !ncfg->rhold || !ncfg->rsetup) { |
Roland Stigge | 2944a44 | 2012-06-07 12:22:15 +0200 | [diff] [blame] | 743 | dev_err(dev, "chip parameters not specified correctly\n"); |
| 744 | return NULL; |
| 745 | } |
| 746 | |
Roland Stigge | 10594f6 | 2012-08-24 15:06:51 +0200 | [diff] [blame] | 747 | ncfg->use_bbt = of_get_nand_on_flash_bbt(np); |
| 748 | ncfg->wp_gpio = of_get_named_gpio(np, "gpios", 0); |
Roland Stigge | 2944a44 | 2012-06-07 12:22:15 +0200 | [diff] [blame] | 749 | |
Roland Stigge | 10594f6 | 2012-08-24 15:06:51 +0200 | [diff] [blame] | 750 | return ncfg; |
Roland Stigge | 2944a44 | 2012-06-07 12:22:15 +0200 | [diff] [blame] | 751 | } |
Roland Stigge | 2944a44 | 2012-06-07 12:22:15 +0200 | [diff] [blame] | 752 | |
| 753 | /* |
| 754 | * Probe for NAND controller |
| 755 | */ |
Bill Pemberton | 06f2551 | 2012-11-19 13:23:07 -0500 | [diff] [blame] | 756 | static int lpc32xx_nand_probe(struct platform_device *pdev) |
Roland Stigge | 2944a44 | 2012-06-07 12:22:15 +0200 | [diff] [blame] | 757 | { |
| 758 | struct lpc32xx_nand_host *host; |
| 759 | struct mtd_info *mtd; |
| 760 | struct nand_chip *chip; |
| 761 | struct resource *rc; |
| 762 | struct mtd_part_parser_data ppdata = {}; |
| 763 | int res; |
| 764 | |
| 765 | rc = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 766 | if (rc == NULL) { |
| 767 | dev_err(&pdev->dev, "No memory resource found for device\n"); |
| 768 | return -EBUSY; |
| 769 | } |
| 770 | |
| 771 | /* Allocate memory for the device structure (and zero it) */ |
| 772 | host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL); |
Jingoo Han | 8ecb66b | 2013-12-26 12:18:56 +0900 | [diff] [blame] | 773 | if (!host) |
Roland Stigge | 2944a44 | 2012-06-07 12:22:15 +0200 | [diff] [blame] | 774 | return -ENOMEM; |
Roland Stigge | 2944a44 | 2012-06-07 12:22:15 +0200 | [diff] [blame] | 775 | host->io_base_dma = rc->start; |
| 776 | |
Thierry Reding | b0de774 | 2013-01-21 11:09:12 +0100 | [diff] [blame] | 777 | host->io_base = devm_ioremap_resource(&pdev->dev, rc); |
| 778 | if (IS_ERR(host->io_base)) |
| 779 | return PTR_ERR(host->io_base); |
Roland Stigge | 2944a44 | 2012-06-07 12:22:15 +0200 | [diff] [blame] | 780 | |
| 781 | if (pdev->dev.of_node) |
| 782 | host->ncfg = lpc32xx_parse_dt(&pdev->dev); |
Roland Stigge | 2944a44 | 2012-06-07 12:22:15 +0200 | [diff] [blame] | 783 | if (!host->ncfg) { |
Roland Stigge | 10594f6 | 2012-08-24 15:06:51 +0200 | [diff] [blame] | 784 | dev_err(&pdev->dev, |
| 785 | "Missing or bad NAND config from device tree\n"); |
Roland Stigge | 2944a44 | 2012-06-07 12:22:15 +0200 | [diff] [blame] | 786 | return -ENOENT; |
| 787 | } |
Roland Stigge | d5842ab | 2012-06-27 17:51:15 +0200 | [diff] [blame] | 788 | if (host->ncfg->wp_gpio == -EPROBE_DEFER) |
| 789 | return -EPROBE_DEFER; |
Jingoo Han | 133432a | 2013-12-26 10:44:30 +0900 | [diff] [blame] | 790 | if (gpio_is_valid(host->ncfg->wp_gpio) && devm_gpio_request(&pdev->dev, |
| 791 | host->ncfg->wp_gpio, "NAND WP")) { |
Roland Stigge | 2944a44 | 2012-06-07 12:22:15 +0200 | [diff] [blame] | 792 | dev_err(&pdev->dev, "GPIO not available\n"); |
| 793 | return -EBUSY; |
| 794 | } |
| 795 | lpc32xx_wp_disable(host); |
| 796 | |
Jingoo Han | 453810b | 2013-07-30 17:18:33 +0900 | [diff] [blame] | 797 | host->pdata = dev_get_platdata(&pdev->dev); |
Roland Stigge | de20c22 | 2012-08-16 15:15:34 +0200 | [diff] [blame] | 798 | |
Roland Stigge | 2944a44 | 2012-06-07 12:22:15 +0200 | [diff] [blame] | 799 | mtd = &host->mtd; |
| 800 | chip = &host->nand_chip; |
| 801 | chip->priv = host; |
| 802 | mtd->priv = chip; |
| 803 | mtd->owner = THIS_MODULE; |
| 804 | mtd->dev.parent = &pdev->dev; |
| 805 | |
| 806 | /* Get NAND clock */ |
Jingoo Han | 133432a | 2013-12-26 10:44:30 +0900 | [diff] [blame] | 807 | host->clk = devm_clk_get(&pdev->dev, NULL); |
Roland Stigge | 2944a44 | 2012-06-07 12:22:15 +0200 | [diff] [blame] | 808 | if (IS_ERR(host->clk)) { |
| 809 | dev_err(&pdev->dev, "Clock failure\n"); |
| 810 | res = -ENOENT; |
| 811 | goto err_exit1; |
| 812 | } |
| 813 | clk_enable(host->clk); |
| 814 | |
| 815 | /* Set NAND IO addresses and command/ready functions */ |
| 816 | chip->IO_ADDR_R = SLC_DATA(host->io_base); |
| 817 | chip->IO_ADDR_W = SLC_DATA(host->io_base); |
| 818 | chip->cmd_ctrl = lpc32xx_nand_cmd_ctrl; |
| 819 | chip->dev_ready = lpc32xx_nand_device_ready; |
| 820 | chip->chip_delay = 20; /* 20us command delay time */ |
| 821 | |
| 822 | /* Init NAND controller */ |
| 823 | lpc32xx_nand_setup(host); |
| 824 | |
| 825 | platform_set_drvdata(pdev, host); |
| 826 | |
| 827 | /* NAND callbacks for LPC32xx SLC hardware */ |
| 828 | chip->ecc.mode = NAND_ECC_HW_SYNDROME; |
| 829 | chip->read_byte = lpc32xx_nand_read_byte; |
| 830 | chip->read_buf = lpc32xx_nand_read_buf; |
| 831 | chip->write_buf = lpc32xx_nand_write_buf; |
| 832 | chip->ecc.read_page_raw = lpc32xx_nand_read_page_raw_syndrome; |
| 833 | chip->ecc.read_page = lpc32xx_nand_read_page_syndrome; |
| 834 | chip->ecc.write_page_raw = lpc32xx_nand_write_page_raw_syndrome; |
| 835 | chip->ecc.write_page = lpc32xx_nand_write_page_syndrome; |
| 836 | chip->ecc.write_oob = lpc32xx_nand_write_oob_syndrome; |
| 837 | chip->ecc.read_oob = lpc32xx_nand_read_oob_syndrome; |
| 838 | chip->ecc.calculate = lpc32xx_nand_ecc_calculate; |
| 839 | chip->ecc.correct = nand_correct_data; |
| 840 | chip->ecc.strength = 1; |
| 841 | chip->ecc.hwctl = lpc32xx_nand_ecc_enable; |
Roland Stigge | 2944a44 | 2012-06-07 12:22:15 +0200 | [diff] [blame] | 842 | |
| 843 | /* bitflip_threshold's default is defined as ecc_strength anyway. |
| 844 | * Unfortunately, it is set only later at add_mtd_device(). Meanwhile |
| 845 | * being 0, it causes bad block table scanning errors in |
| 846 | * nand_scan_tail(), so preparing it here already. */ |
| 847 | mtd->bitflip_threshold = chip->ecc.strength; |
| 848 | |
| 849 | /* |
| 850 | * Allocate a large enough buffer for a single huge page plus |
| 851 | * extra space for the spare area and ECC storage area |
| 852 | */ |
| 853 | host->dma_buf_len = LPC32XX_DMA_DATA_SIZE + LPC32XX_ECC_SAVE_SIZE; |
| 854 | host->data_buf = devm_kzalloc(&pdev->dev, host->dma_buf_len, |
| 855 | GFP_KERNEL); |
| 856 | if (host->data_buf == NULL) { |
Roland Stigge | 2944a44 | 2012-06-07 12:22:15 +0200 | [diff] [blame] | 857 | res = -ENOMEM; |
| 858 | goto err_exit2; |
| 859 | } |
| 860 | |
| 861 | res = lpc32xx_nand_dma_setup(host); |
| 862 | if (res) { |
| 863 | res = -EIO; |
| 864 | goto err_exit2; |
| 865 | } |
| 866 | |
| 867 | /* Find NAND device */ |
| 868 | if (nand_scan_ident(mtd, 1, NULL)) { |
| 869 | res = -ENXIO; |
| 870 | goto err_exit3; |
| 871 | } |
| 872 | |
| 873 | /* OOB and ECC CPU and DMA work areas */ |
| 874 | host->ecc_buf = (uint32_t *)(host->data_buf + LPC32XX_DMA_DATA_SIZE); |
| 875 | |
| 876 | /* |
| 877 | * Small page FLASH has a unique OOB layout, but large and huge |
| 878 | * page FLASH use the standard layout. Small page FLASH uses a |
| 879 | * custom BBT marker layout. |
| 880 | */ |
| 881 | if (mtd->writesize <= 512) |
| 882 | chip->ecc.layout = &lpc32xx_nand_oob_16; |
| 883 | |
| 884 | /* These sizes remain the same regardless of page size */ |
| 885 | chip->ecc.size = 256; |
| 886 | chip->ecc.bytes = LPC32XX_SLC_DEV_ECC_BYTES; |
| 887 | chip->ecc.prepad = chip->ecc.postpad = 0; |
| 888 | |
| 889 | /* Avoid extra scan if using BBT, setup BBT support */ |
| 890 | if (host->ncfg->use_bbt) { |
Roland Stigge | 2944a44 | 2012-06-07 12:22:15 +0200 | [diff] [blame] | 891 | chip->bbt_options |= NAND_BBT_USE_FLASH; |
| 892 | |
| 893 | /* |
| 894 | * Use a custom BBT marker setup for small page FLASH that |
| 895 | * won't interfere with the ECC layout. Large and huge page |
| 896 | * FLASH use the standard layout. |
| 897 | */ |
| 898 | if (mtd->writesize <= 512) { |
| 899 | chip->bbt_td = &bbt_smallpage_main_descr; |
| 900 | chip->bbt_md = &bbt_smallpage_mirror_descr; |
| 901 | } |
| 902 | } |
| 903 | |
| 904 | /* |
| 905 | * Fills out all the uninitialized function pointers with the defaults |
| 906 | */ |
| 907 | if (nand_scan_tail(mtd)) { |
| 908 | res = -ENXIO; |
| 909 | goto err_exit3; |
| 910 | } |
| 911 | |
Roland Stigge | 2944a44 | 2012-06-07 12:22:15 +0200 | [diff] [blame] | 912 | mtd->name = "nxp_lpc3220_slc"; |
| 913 | ppdata.of_node = pdev->dev.of_node; |
| 914 | res = mtd_device_parse_register(mtd, NULL, &ppdata, host->ncfg->parts, |
| 915 | host->ncfg->num_parts); |
| 916 | if (!res) |
| 917 | return res; |
| 918 | |
| 919 | nand_release(mtd); |
| 920 | |
| 921 | err_exit3: |
| 922 | dma_release_channel(host->dma_chan); |
| 923 | err_exit2: |
| 924 | clk_disable(host->clk); |
Roland Stigge | 2944a44 | 2012-06-07 12:22:15 +0200 | [diff] [blame] | 925 | err_exit1: |
| 926 | lpc32xx_wp_enable(host); |
Roland Stigge | 2944a44 | 2012-06-07 12:22:15 +0200 | [diff] [blame] | 927 | |
| 928 | return res; |
| 929 | } |
| 930 | |
| 931 | /* |
| 932 | * Remove NAND device. |
| 933 | */ |
Bill Pemberton | 810b7e0 | 2012-11-19 13:26:04 -0500 | [diff] [blame] | 934 | static int lpc32xx_nand_remove(struct platform_device *pdev) |
Roland Stigge | 2944a44 | 2012-06-07 12:22:15 +0200 | [diff] [blame] | 935 | { |
| 936 | uint32_t tmp; |
| 937 | struct lpc32xx_nand_host *host = platform_get_drvdata(pdev); |
| 938 | struct mtd_info *mtd = &host->mtd; |
| 939 | |
| 940 | nand_release(mtd); |
| 941 | dma_release_channel(host->dma_chan); |
| 942 | |
| 943 | /* Force CE high */ |
| 944 | tmp = readl(SLC_CTRL(host->io_base)); |
| 945 | tmp &= ~SLCCFG_CE_LOW; |
| 946 | writel(tmp, SLC_CTRL(host->io_base)); |
| 947 | |
| 948 | clk_disable(host->clk); |
Roland Stigge | 2944a44 | 2012-06-07 12:22:15 +0200 | [diff] [blame] | 949 | lpc32xx_wp_enable(host); |
Roland Stigge | 2944a44 | 2012-06-07 12:22:15 +0200 | [diff] [blame] | 950 | |
| 951 | return 0; |
| 952 | } |
| 953 | |
| 954 | #ifdef CONFIG_PM |
| 955 | static int lpc32xx_nand_resume(struct platform_device *pdev) |
| 956 | { |
| 957 | struct lpc32xx_nand_host *host = platform_get_drvdata(pdev); |
| 958 | |
| 959 | /* Re-enable NAND clock */ |
| 960 | clk_enable(host->clk); |
| 961 | |
| 962 | /* Fresh init of NAND controller */ |
| 963 | lpc32xx_nand_setup(host); |
| 964 | |
| 965 | /* Disable write protect */ |
| 966 | lpc32xx_wp_disable(host); |
| 967 | |
| 968 | return 0; |
| 969 | } |
| 970 | |
| 971 | static int lpc32xx_nand_suspend(struct platform_device *pdev, pm_message_t pm) |
| 972 | { |
| 973 | uint32_t tmp; |
| 974 | struct lpc32xx_nand_host *host = platform_get_drvdata(pdev); |
| 975 | |
| 976 | /* Force CE high */ |
| 977 | tmp = readl(SLC_CTRL(host->io_base)); |
| 978 | tmp &= ~SLCCFG_CE_LOW; |
| 979 | writel(tmp, SLC_CTRL(host->io_base)); |
| 980 | |
| 981 | /* Enable write protect for safety */ |
| 982 | lpc32xx_wp_enable(host); |
| 983 | |
| 984 | /* Disable clock */ |
| 985 | clk_disable(host->clk); |
| 986 | |
| 987 | return 0; |
| 988 | } |
| 989 | |
| 990 | #else |
| 991 | #define lpc32xx_nand_resume NULL |
| 992 | #define lpc32xx_nand_suspend NULL |
| 993 | #endif |
| 994 | |
Roland Stigge | 2944a44 | 2012-06-07 12:22:15 +0200 | [diff] [blame] | 995 | static const struct of_device_id lpc32xx_nand_match[] = { |
| 996 | { .compatible = "nxp,lpc3220-slc" }, |
| 997 | { /* sentinel */ }, |
| 998 | }; |
| 999 | MODULE_DEVICE_TABLE(of, lpc32xx_nand_match); |
Roland Stigge | 2944a44 | 2012-06-07 12:22:15 +0200 | [diff] [blame] | 1000 | |
| 1001 | static struct platform_driver lpc32xx_nand_driver = { |
| 1002 | .probe = lpc32xx_nand_probe, |
Bill Pemberton | 5153b88 | 2012-11-19 13:21:24 -0500 | [diff] [blame] | 1003 | .remove = lpc32xx_nand_remove, |
Roland Stigge | 2944a44 | 2012-06-07 12:22:15 +0200 | [diff] [blame] | 1004 | .resume = lpc32xx_nand_resume, |
| 1005 | .suspend = lpc32xx_nand_suspend, |
| 1006 | .driver = { |
| 1007 | .name = LPC32XX_MODNAME, |
| 1008 | .owner = THIS_MODULE, |
Sachin Kamat | fea7b56 | 2013-09-30 15:10:23 +0530 | [diff] [blame] | 1009 | .of_match_table = lpc32xx_nand_match, |
Roland Stigge | 2944a44 | 2012-06-07 12:22:15 +0200 | [diff] [blame] | 1010 | }, |
| 1011 | }; |
| 1012 | |
| 1013 | module_platform_driver(lpc32xx_nand_driver); |
| 1014 | |
| 1015 | MODULE_LICENSE("GPL"); |
| 1016 | MODULE_AUTHOR("Kevin Wells <kevin.wells@nxp.com>"); |
| 1017 | MODULE_AUTHOR("Roland Stigge <stigge@antcom.de>"); |
| 1018 | MODULE_DESCRIPTION("NAND driver for the NXP LPC32XX SLC controller"); |