blob: e194bb32b27bb5f6fedc43afd2bbf6887ed2c773 [file] [log] [blame]
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001/*
Tomoya MORINAGAeca9dfa2011-10-28 09:38:50 +09002 *Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09003 *
4 *This program is free software; you can redistribute it and/or modify
5 *it under the terms of the GNU General Public License as published by
6 *the Free Software Foundation; version 2 of the License.
7 *
8 *This program is distributed in the hope that it will be useful,
9 *but WITHOUT ANY WARRANTY; without even the implied warranty of
10 *MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 *GNU General Public License for more details.
12 *
13 *You should have received a copy of the GNU General Public License
14 *along with this program; if not, write to the Free Software
15 *Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
16 */
Liang Li1f9db092013-01-19 17:52:11 +080017#if defined(CONFIG_SERIAL_PCH_UART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
18#define SUPPORT_SYSRQ
19#endif
Uwe Kleine-König0e2adc02011-05-26 10:41:17 +020020#include <linux/kernel.h>
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +090021#include <linux/serial_reg.h>
Andrew Morton023bc8e2011-05-24 17:13:44 -070022#include <linux/slab.h>
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +090023#include <linux/module.h>
24#include <linux/pci.h>
Liang Li1f9db092013-01-19 17:52:11 +080025#include <linux/console.h>
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +090026#include <linux/serial_core.h>
Jiri Slabyee160a32011-09-01 16:20:57 +020027#include <linux/tty.h>
28#include <linux/tty_flip.h>
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +090029#include <linux/interrupt.h>
30#include <linux/io.h>
Denis Turischev6ae705b2011-03-10 15:14:00 +020031#include <linux/dmi.h>
Alexander Steine30f8672011-11-15 15:04:07 -080032#include <linux/nmi.h>
33#include <linux/delay.h>
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +090034
Feng Tangd0114112012-02-06 17:24:43 +080035#include <linux/debugfs.h>
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +090036#include <linux/dmaengine.h>
37#include <linux/pch_dma.h>
38
39enum {
40 PCH_UART_HANDLED_RX_INT_SHIFT,
41 PCH_UART_HANDLED_TX_INT_SHIFT,
42 PCH_UART_HANDLED_RX_ERR_INT_SHIFT,
43 PCH_UART_HANDLED_RX_TRG_INT_SHIFT,
44 PCH_UART_HANDLED_MS_INT_SHIFT,
Tomoya MORINAGA04e2c2e2012-03-26 14:43:05 +090045 PCH_UART_HANDLED_LS_INT_SHIFT,
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +090046};
47
48enum {
49 PCH_UART_8LINE,
50 PCH_UART_2LINE,
51};
52
53#define PCH_UART_DRIVER_DEVICE "ttyPCH"
54
Tomoya MORINAGA4564e1e2011-01-28 18:00:01 +090055/* Set the max number of UART port
56 * Intel EG20T PCH: 4 port
Tomoya MORINAGAeca9dfa2011-10-28 09:38:50 +090057 * LAPIS Semiconductor ML7213 IOH: 3 port
58 * LAPIS Semiconductor ML7223 IOH: 2 port
Tomoya MORINAGA4564e1e2011-01-28 18:00:01 +090059*/
60#define PCH_UART_NR 4
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +090061
62#define PCH_UART_HANDLED_RX_INT (1<<((PCH_UART_HANDLED_RX_INT_SHIFT)<<1))
63#define PCH_UART_HANDLED_TX_INT (1<<((PCH_UART_HANDLED_TX_INT_SHIFT)<<1))
64#define PCH_UART_HANDLED_RX_ERR_INT (1<<((\
65 PCH_UART_HANDLED_RX_ERR_INT_SHIFT)<<1))
66#define PCH_UART_HANDLED_RX_TRG_INT (1<<((\
67 PCH_UART_HANDLED_RX_TRG_INT_SHIFT)<<1))
68#define PCH_UART_HANDLED_MS_INT (1<<((PCH_UART_HANDLED_MS_INT_SHIFT)<<1))
69
Tomoya MORINAGA04e2c2e2012-03-26 14:43:05 +090070#define PCH_UART_HANDLED_LS_INT (1<<((PCH_UART_HANDLED_LS_INT_SHIFT)<<1))
71
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +090072#define PCH_UART_RBR 0x00
73#define PCH_UART_THR 0x00
74
75#define PCH_UART_IER_MASK (PCH_UART_IER_ERBFI|PCH_UART_IER_ETBEI|\
76 PCH_UART_IER_ELSI|PCH_UART_IER_EDSSI)
77#define PCH_UART_IER_ERBFI 0x00000001
78#define PCH_UART_IER_ETBEI 0x00000002
79#define PCH_UART_IER_ELSI 0x00000004
80#define PCH_UART_IER_EDSSI 0x00000008
81
82#define PCH_UART_IIR_IP 0x00000001
83#define PCH_UART_IIR_IID 0x00000006
84#define PCH_UART_IIR_MSI 0x00000000
85#define PCH_UART_IIR_TRI 0x00000002
86#define PCH_UART_IIR_RRI 0x00000004
87#define PCH_UART_IIR_REI 0x00000006
88#define PCH_UART_IIR_TOI 0x00000008
89#define PCH_UART_IIR_FIFO256 0x00000020
90#define PCH_UART_IIR_FIFO64 PCH_UART_IIR_FIFO256
91#define PCH_UART_IIR_FE 0x000000C0
92
93#define PCH_UART_FCR_FIFOE 0x00000001
94#define PCH_UART_FCR_RFR 0x00000002
95#define PCH_UART_FCR_TFR 0x00000004
96#define PCH_UART_FCR_DMS 0x00000008
97#define PCH_UART_FCR_FIFO256 0x00000020
98#define PCH_UART_FCR_RFTL 0x000000C0
99
100#define PCH_UART_FCR_RFTL1 0x00000000
101#define PCH_UART_FCR_RFTL64 0x00000040
102#define PCH_UART_FCR_RFTL128 0x00000080
103#define PCH_UART_FCR_RFTL224 0x000000C0
104#define PCH_UART_FCR_RFTL16 PCH_UART_FCR_RFTL64
105#define PCH_UART_FCR_RFTL32 PCH_UART_FCR_RFTL128
106#define PCH_UART_FCR_RFTL56 PCH_UART_FCR_RFTL224
107#define PCH_UART_FCR_RFTL4 PCH_UART_FCR_RFTL64
108#define PCH_UART_FCR_RFTL8 PCH_UART_FCR_RFTL128
109#define PCH_UART_FCR_RFTL14 PCH_UART_FCR_RFTL224
110#define PCH_UART_FCR_RFTL_SHIFT 6
111
112#define PCH_UART_LCR_WLS 0x00000003
113#define PCH_UART_LCR_STB 0x00000004
114#define PCH_UART_LCR_PEN 0x00000008
115#define PCH_UART_LCR_EPS 0x00000010
116#define PCH_UART_LCR_SP 0x00000020
117#define PCH_UART_LCR_SB 0x00000040
118#define PCH_UART_LCR_DLAB 0x00000080
119#define PCH_UART_LCR_NP 0x00000000
120#define PCH_UART_LCR_OP PCH_UART_LCR_PEN
121#define PCH_UART_LCR_EP (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS)
122#define PCH_UART_LCR_1P (PCH_UART_LCR_PEN | PCH_UART_LCR_SP)
123#define PCH_UART_LCR_0P (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS |\
124 PCH_UART_LCR_SP)
125
126#define PCH_UART_LCR_5BIT 0x00000000
127#define PCH_UART_LCR_6BIT 0x00000001
128#define PCH_UART_LCR_7BIT 0x00000002
129#define PCH_UART_LCR_8BIT 0x00000003
130
131#define PCH_UART_MCR_DTR 0x00000001
132#define PCH_UART_MCR_RTS 0x00000002
133#define PCH_UART_MCR_OUT 0x0000000C
134#define PCH_UART_MCR_LOOP 0x00000010
135#define PCH_UART_MCR_AFE 0x00000020
136
137#define PCH_UART_LSR_DR 0x00000001
138#define PCH_UART_LSR_ERR (1<<7)
139
140#define PCH_UART_MSR_DCTS 0x00000001
141#define PCH_UART_MSR_DDSR 0x00000002
142#define PCH_UART_MSR_TERI 0x00000004
143#define PCH_UART_MSR_DDCD 0x00000008
144#define PCH_UART_MSR_CTS 0x00000010
145#define PCH_UART_MSR_DSR 0x00000020
146#define PCH_UART_MSR_RI 0x00000040
147#define PCH_UART_MSR_DCD 0x00000080
148#define PCH_UART_MSR_DELTA (PCH_UART_MSR_DCTS | PCH_UART_MSR_DDSR |\
149 PCH_UART_MSR_TERI | PCH_UART_MSR_DDCD)
150
151#define PCH_UART_DLL 0x00
152#define PCH_UART_DLM 0x01
153
Feng Tangd0114112012-02-06 17:24:43 +0800154#define PCH_UART_BRCSR 0x0E
155
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900156#define PCH_UART_IID_RLS (PCH_UART_IIR_REI)
157#define PCH_UART_IID_RDR (PCH_UART_IIR_RRI)
158#define PCH_UART_IID_RDR_TO (PCH_UART_IIR_RRI | PCH_UART_IIR_TOI)
159#define PCH_UART_IID_THRE (PCH_UART_IIR_TRI)
160#define PCH_UART_IID_MS (PCH_UART_IIR_MSI)
161
162#define PCH_UART_HAL_PARITY_NONE (PCH_UART_LCR_NP)
163#define PCH_UART_HAL_PARITY_ODD (PCH_UART_LCR_OP)
164#define PCH_UART_HAL_PARITY_EVEN (PCH_UART_LCR_EP)
165#define PCH_UART_HAL_PARITY_FIX1 (PCH_UART_LCR_1P)
166#define PCH_UART_HAL_PARITY_FIX0 (PCH_UART_LCR_0P)
167#define PCH_UART_HAL_5BIT (PCH_UART_LCR_5BIT)
168#define PCH_UART_HAL_6BIT (PCH_UART_LCR_6BIT)
169#define PCH_UART_HAL_7BIT (PCH_UART_LCR_7BIT)
170#define PCH_UART_HAL_8BIT (PCH_UART_LCR_8BIT)
171#define PCH_UART_HAL_STB1 0
172#define PCH_UART_HAL_STB2 (PCH_UART_LCR_STB)
173
174#define PCH_UART_HAL_CLR_TX_FIFO (PCH_UART_FCR_TFR)
175#define PCH_UART_HAL_CLR_RX_FIFO (PCH_UART_FCR_RFR)
176#define PCH_UART_HAL_CLR_ALL_FIFO (PCH_UART_HAL_CLR_TX_FIFO | \
177 PCH_UART_HAL_CLR_RX_FIFO)
178
179#define PCH_UART_HAL_DMA_MODE0 0
180#define PCH_UART_HAL_FIFO_DIS 0
181#define PCH_UART_HAL_FIFO16 (PCH_UART_FCR_FIFOE)
182#define PCH_UART_HAL_FIFO256 (PCH_UART_FCR_FIFOE | \
183 PCH_UART_FCR_FIFO256)
184#define PCH_UART_HAL_FIFO64 (PCH_UART_HAL_FIFO256)
185#define PCH_UART_HAL_TRIGGER1 (PCH_UART_FCR_RFTL1)
186#define PCH_UART_HAL_TRIGGER64 (PCH_UART_FCR_RFTL64)
187#define PCH_UART_HAL_TRIGGER128 (PCH_UART_FCR_RFTL128)
188#define PCH_UART_HAL_TRIGGER224 (PCH_UART_FCR_RFTL224)
189#define PCH_UART_HAL_TRIGGER16 (PCH_UART_FCR_RFTL16)
190#define PCH_UART_HAL_TRIGGER32 (PCH_UART_FCR_RFTL32)
191#define PCH_UART_HAL_TRIGGER56 (PCH_UART_FCR_RFTL56)
192#define PCH_UART_HAL_TRIGGER4 (PCH_UART_FCR_RFTL4)
193#define PCH_UART_HAL_TRIGGER8 (PCH_UART_FCR_RFTL8)
194#define PCH_UART_HAL_TRIGGER14 (PCH_UART_FCR_RFTL14)
195#define PCH_UART_HAL_TRIGGER_L (PCH_UART_FCR_RFTL64)
196#define PCH_UART_HAL_TRIGGER_M (PCH_UART_FCR_RFTL128)
197#define PCH_UART_HAL_TRIGGER_H (PCH_UART_FCR_RFTL224)
198
199#define PCH_UART_HAL_RX_INT (PCH_UART_IER_ERBFI)
200#define PCH_UART_HAL_TX_INT (PCH_UART_IER_ETBEI)
201#define PCH_UART_HAL_RX_ERR_INT (PCH_UART_IER_ELSI)
202#define PCH_UART_HAL_MS_INT (PCH_UART_IER_EDSSI)
203#define PCH_UART_HAL_ALL_INT (PCH_UART_IER_MASK)
204
205#define PCH_UART_HAL_DTR (PCH_UART_MCR_DTR)
206#define PCH_UART_HAL_RTS (PCH_UART_MCR_RTS)
207#define PCH_UART_HAL_OUT (PCH_UART_MCR_OUT)
208#define PCH_UART_HAL_LOOP (PCH_UART_MCR_LOOP)
209#define PCH_UART_HAL_AFE (PCH_UART_MCR_AFE)
210
Tomoya MORINAGA4564e1e2011-01-28 18:00:01 +0900211#define PCI_VENDOR_ID_ROHM 0x10DB
212
Alexander Steine30f8672011-11-15 15:04:07 -0800213#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
214
Darren Hart077175f2012-03-09 09:51:49 -0800215#define DEFAULT_UARTCLK 1843200 /* 1.8432 MHz */
216#define CMITC_UARTCLK 192000000 /* 192.0000 MHz */
217#define FRI2_64_UARTCLK 64000000 /* 64.0000 MHz */
218#define FRI2_48_UARTCLK 48000000 /* 48.0000 MHz */
Michael Brunner11bbd5b2012-03-23 11:06:37 +0100219#define NTC1_UARTCLK 64000000 /* 64.0000 MHz */
Darren Hart29692d02013-06-25 18:53:22 -0700220#define MINNOW_UARTCLK 50000000 /* 50.0000 MHz */
Alexander Steine30f8672011-11-15 15:04:07 -0800221
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900222struct pch_uart_buffer {
223 unsigned char *buf;
224 int size;
225};
226
227struct eg20t_port {
228 struct uart_port port;
229 int port_type;
230 void __iomem *membase;
231 resource_size_t mapbase;
232 unsigned int iobase;
233 struct pci_dev *pdev;
234 int fifo_size;
Darren Harte26439c2013-07-29 15:15:07 -0700235 unsigned int uartclk;
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900236 int start_tx;
237 int start_rx;
238 int tx_empty;
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900239 int trigger;
240 int trigger_level;
241 struct pch_uart_buffer rxbuf;
242 unsigned int dmsr;
243 unsigned int fcr;
Tomoya MORINAGA9af71552011-02-23 10:03:17 +0900244 unsigned int mcr;
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900245 unsigned int use_dma;
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900246 struct dma_async_tx_descriptor *desc_tx;
247 struct dma_async_tx_descriptor *desc_rx;
248 struct pch_dma_slave param_tx;
249 struct pch_dma_slave param_rx;
250 struct dma_chan *chan_tx;
251 struct dma_chan *chan_rx;
Tomoya MORINAGAda3564e2011-02-23 10:03:12 +0900252 struct scatterlist *sg_tx_p;
253 int nent;
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900254 struct scatterlist sg_rx;
255 int tx_dma_use;
256 void *rx_buf_virt;
257 dma_addr_t rx_buf_dma;
Feng Tangd0114112012-02-06 17:24:43 +0800258
259 struct dentry *debugfs;
Alexander Stein50d16ca2014-03-25 14:05:08 +0100260#define IRQ_NAME_SIZE 17
261 char irq_name[IRQ_NAME_SIZE];
Darren Hartfe89def2012-06-19 14:00:18 -0700262
263 /* protect the eg20t_port private structure and io access to membase */
264 spinlock_t lock;
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900265};
266
Tomoya MORINAGAfec38d12011-02-23 10:03:19 +0900267/**
268 * struct pch_uart_driver_data - private data structure for UART-DMA
269 * @port_type: The number of DMA channel
270 * @line_no: UART port line number (0, 1, 2...)
271 */
272struct pch_uart_driver_data {
273 int port_type;
274 int line_no;
275};
276
277enum pch_uart_num_t {
278 pch_et20t_uart0 = 0,
279 pch_et20t_uart1,
280 pch_et20t_uart2,
281 pch_et20t_uart3,
282 pch_ml7213_uart0,
283 pch_ml7213_uart1,
284 pch_ml7213_uart2,
Tomoya MORINAGA177c2cb2011-05-09 17:25:20 +0900285 pch_ml7223_uart0,
286 pch_ml7223_uart1,
Tomoya MORINAGA8249f742011-10-28 09:38:49 +0900287 pch_ml7831_uart0,
288 pch_ml7831_uart1,
Tomoya MORINAGAfec38d12011-02-23 10:03:19 +0900289};
290
291static struct pch_uart_driver_data drv_dat[] = {
292 [pch_et20t_uart0] = {PCH_UART_8LINE, 0},
293 [pch_et20t_uart1] = {PCH_UART_2LINE, 1},
294 [pch_et20t_uart2] = {PCH_UART_2LINE, 2},
295 [pch_et20t_uart3] = {PCH_UART_2LINE, 3},
296 [pch_ml7213_uart0] = {PCH_UART_8LINE, 0},
297 [pch_ml7213_uart1] = {PCH_UART_2LINE, 1},
298 [pch_ml7213_uart2] = {PCH_UART_2LINE, 2},
Tomoya MORINAGA177c2cb2011-05-09 17:25:20 +0900299 [pch_ml7223_uart0] = {PCH_UART_8LINE, 0},
300 [pch_ml7223_uart1] = {PCH_UART_2LINE, 1},
Tomoya MORINAGA8249f742011-10-28 09:38:49 +0900301 [pch_ml7831_uart0] = {PCH_UART_8LINE, 0},
302 [pch_ml7831_uart1] = {PCH_UART_2LINE, 1},
Tomoya MORINAGAfec38d12011-02-23 10:03:19 +0900303};
304
Alexander Steine30f8672011-11-15 15:04:07 -0800305#ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
306static struct eg20t_port *pch_uart_ports[PCH_UART_NR];
307#endif
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900308static unsigned int default_baud = 9600;
Darren Hart2a44feb2012-03-09 09:51:50 -0800309static unsigned int user_uartclk = 0;
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900310static const int trigger_level_256[4] = { 1, 64, 128, 224 };
311static const int trigger_level_64[4] = { 1, 16, 32, 56 };
312static const int trigger_level_16[4] = { 1, 4, 8, 14 };
313static const int trigger_level_1[4] = { 1, 1, 1, 1 };
314
Feng Tangd0114112012-02-06 17:24:43 +0800315#ifdef CONFIG_DEBUG_FS
316
317#define PCH_REGS_BUFSIZE 1024
Stephen Boyd234e3402012-04-05 14:25:11 -0700318
Feng Tangd0114112012-02-06 17:24:43 +0800319
320static ssize_t port_show_regs(struct file *file, char __user *user_buf,
321 size_t count, loff_t *ppos)
322{
323 struct eg20t_port *priv = file->private_data;
324 char *buf;
325 u32 len = 0;
326 ssize_t ret;
327 unsigned char lcr;
328
329 buf = kzalloc(PCH_REGS_BUFSIZE, GFP_KERNEL);
330 if (!buf)
331 return 0;
332
333 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
334 "PCH EG20T port[%d] regs:\n", priv->port.line);
335
336 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
337 "=================================\n");
338 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
339 "IER: \t0x%02x\n", ioread8(priv->membase + UART_IER));
340 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
341 "IIR: \t0x%02x\n", ioread8(priv->membase + UART_IIR));
342 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
343 "LCR: \t0x%02x\n", ioread8(priv->membase + UART_LCR));
344 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
345 "MCR: \t0x%02x\n", ioread8(priv->membase + UART_MCR));
346 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
347 "LSR: \t0x%02x\n", ioread8(priv->membase + UART_LSR));
348 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
349 "MSR: \t0x%02x\n", ioread8(priv->membase + UART_MSR));
350 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
351 "BRCSR: \t0x%02x\n",
352 ioread8(priv->membase + PCH_UART_BRCSR));
353
354 lcr = ioread8(priv->membase + UART_LCR);
355 iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR);
356 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
357 "DLL: \t0x%02x\n", ioread8(priv->membase + UART_DLL));
358 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
359 "DLM: \t0x%02x\n", ioread8(priv->membase + UART_DLM));
360 iowrite8(lcr, priv->membase + UART_LCR);
361
362 if (len > PCH_REGS_BUFSIZE)
363 len = PCH_REGS_BUFSIZE;
364
365 ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);
366 kfree(buf);
367 return ret;
368}
369
370static const struct file_operations port_regs_ops = {
371 .owner = THIS_MODULE,
Stephen Boyd234e3402012-04-05 14:25:11 -0700372 .open = simple_open,
Feng Tangd0114112012-02-06 17:24:43 +0800373 .read = port_show_regs,
374 .llseek = default_llseek,
375};
376#endif /* CONFIG_DEBUG_FS */
377
Darren Hart0a09ae92013-07-29 09:58:14 -0700378static struct dmi_system_id pch_uart_dmi_table[] = {
Darren Hart4e323482013-07-12 17:58:05 -0700379 {
380 .ident = "CM-iTC",
381 {
382 DMI_MATCH(DMI_BOARD_NAME, "CM-iTC"),
383 },
384 (void *)CMITC_UARTCLK,
385 },
386 {
387 .ident = "FRI2",
388 {
389 DMI_MATCH(DMI_BIOS_VERSION, "FRI2"),
390 },
391 (void *)FRI2_64_UARTCLK,
392 },
393 {
394 .ident = "Fish River Island II",
395 {
396 DMI_MATCH(DMI_PRODUCT_NAME, "Fish River Island II"),
397 },
398 (void *)FRI2_48_UARTCLK,
399 },
400 {
401 .ident = "COMe-mTT",
402 {
403 DMI_MATCH(DMI_BOARD_NAME, "COMe-mTT"),
404 },
405 (void *)NTC1_UARTCLK,
406 },
407 {
408 .ident = "nanoETXexpress-TT",
409 {
410 DMI_MATCH(DMI_BOARD_NAME, "nanoETXexpress-TT"),
411 },
412 (void *)NTC1_UARTCLK,
413 },
414 {
415 .ident = "MinnowBoard",
416 {
417 DMI_MATCH(DMI_BOARD_NAME, "MinnowBoard"),
418 },
419 (void *)MINNOW_UARTCLK,
420 },
421};
422
Darren Hart077175f2012-03-09 09:51:49 -0800423/* Return UART clock, checking for board specific clocks. */
Darren Harte26439c2013-07-29 15:15:07 -0700424static unsigned int pch_uart_get_uartclk(void)
Darren Hart077175f2012-03-09 09:51:49 -0800425{
Darren Hart4e323482013-07-12 17:58:05 -0700426 const struct dmi_system_id *d;
Darren Hart077175f2012-03-09 09:51:49 -0800427
Darren Hart2a44feb2012-03-09 09:51:50 -0800428 if (user_uartclk)
429 return user_uartclk;
430
Darren Hart4e323482013-07-12 17:58:05 -0700431 d = dmi_first_match(pch_uart_dmi_table);
432 if (d)
Darren Harte26439c2013-07-29 15:15:07 -0700433 return (unsigned long)d->driver_data;
Darren Hart29692d02013-06-25 18:53:22 -0700434
Darren Hart077175f2012-03-09 09:51:49 -0800435 return DEFAULT_UARTCLK;
436}
437
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900438static void pch_uart_hal_enable_interrupt(struct eg20t_port *priv,
439 unsigned int flag)
440{
441 u8 ier = ioread8(priv->membase + UART_IER);
442 ier |= flag & PCH_UART_IER_MASK;
443 iowrite8(ier, priv->membase + UART_IER);
444}
445
446static void pch_uart_hal_disable_interrupt(struct eg20t_port *priv,
447 unsigned int flag)
448{
449 u8 ier = ioread8(priv->membase + UART_IER);
450 ier &= ~(flag & PCH_UART_IER_MASK);
451 iowrite8(ier, priv->membase + UART_IER);
452}
453
Darren Harte26439c2013-07-29 15:15:07 -0700454static int pch_uart_hal_set_line(struct eg20t_port *priv, unsigned int baud,
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900455 unsigned int parity, unsigned int bits,
456 unsigned int stb)
457{
458 unsigned int dll, dlm, lcr;
459 int div;
460
Darren Harta8a3ec92012-03-09 09:51:48 -0800461 div = DIV_ROUND_CLOSEST(priv->uartclk / 16, baud);
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900462 if (div < 0 || USHRT_MAX <= div) {
Tomoya MORINAGA23877fd2011-02-23 10:03:15 +0900463 dev_err(priv->port.dev, "Invalid Baud(div=0x%x)\n", div);
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900464 return -EINVAL;
465 }
466
467 dll = (unsigned int)div & 0x00FFU;
468 dlm = ((unsigned int)div >> 8) & 0x00FFU;
469
470 if (parity & ~(PCH_UART_LCR_PEN | PCH_UART_LCR_EPS | PCH_UART_LCR_SP)) {
Tomoya MORINAGA23877fd2011-02-23 10:03:15 +0900471 dev_err(priv->port.dev, "Invalid parity(0x%x)\n", parity);
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900472 return -EINVAL;
473 }
474
475 if (bits & ~PCH_UART_LCR_WLS) {
Tomoya MORINAGA23877fd2011-02-23 10:03:15 +0900476 dev_err(priv->port.dev, "Invalid bits(0x%x)\n", bits);
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900477 return -EINVAL;
478 }
479
480 if (stb & ~PCH_UART_LCR_STB) {
Tomoya MORINAGA23877fd2011-02-23 10:03:15 +0900481 dev_err(priv->port.dev, "Invalid STB(0x%x)\n", stb);
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900482 return -EINVAL;
483 }
484
485 lcr = parity;
486 lcr |= bits;
487 lcr |= stb;
488
Darren Harte26439c2013-07-29 15:15:07 -0700489 dev_dbg(priv->port.dev, "%s:baud = %u, div = %04x, lcr = %02x (%lu)\n",
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900490 __func__, baud, div, lcr, jiffies);
491 iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR);
492 iowrite8(dll, priv->membase + PCH_UART_DLL);
493 iowrite8(dlm, priv->membase + PCH_UART_DLM);
494 iowrite8(lcr, priv->membase + UART_LCR);
495
496 return 0;
497}
498
499static int pch_uart_hal_fifo_reset(struct eg20t_port *priv,
500 unsigned int flag)
501{
502 if (flag & ~(PCH_UART_FCR_TFR | PCH_UART_FCR_RFR)) {
Tomoya MORINAGA23877fd2011-02-23 10:03:15 +0900503 dev_err(priv->port.dev, "%s:Invalid flag(0x%x)\n",
504 __func__, flag);
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900505 return -EINVAL;
506 }
507
508 iowrite8(PCH_UART_FCR_FIFOE | priv->fcr, priv->membase + UART_FCR);
509 iowrite8(PCH_UART_FCR_FIFOE | priv->fcr | flag,
510 priv->membase + UART_FCR);
511 iowrite8(priv->fcr, priv->membase + UART_FCR);
512
513 return 0;
514}
515
516static int pch_uart_hal_set_fifo(struct eg20t_port *priv,
517 unsigned int dmamode,
518 unsigned int fifo_size, unsigned int trigger)
519{
520 u8 fcr;
521
522 if (dmamode & ~PCH_UART_FCR_DMS) {
Tomoya MORINAGA23877fd2011-02-23 10:03:15 +0900523 dev_err(priv->port.dev, "%s:Invalid DMA Mode(0x%x)\n",
524 __func__, dmamode);
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900525 return -EINVAL;
526 }
527
528 if (fifo_size & ~(PCH_UART_FCR_FIFOE | PCH_UART_FCR_FIFO256)) {
Tomoya MORINAGA23877fd2011-02-23 10:03:15 +0900529 dev_err(priv->port.dev, "%s:Invalid FIFO SIZE(0x%x)\n",
530 __func__, fifo_size);
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900531 return -EINVAL;
532 }
533
534 if (trigger & ~PCH_UART_FCR_RFTL) {
Tomoya MORINAGA23877fd2011-02-23 10:03:15 +0900535 dev_err(priv->port.dev, "%s:Invalid TRIGGER(0x%x)\n",
536 __func__, trigger);
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900537 return -EINVAL;
538 }
539
540 switch (priv->fifo_size) {
541 case 256:
542 priv->trigger_level =
543 trigger_level_256[trigger >> PCH_UART_FCR_RFTL_SHIFT];
544 break;
545 case 64:
546 priv->trigger_level =
547 trigger_level_64[trigger >> PCH_UART_FCR_RFTL_SHIFT];
548 break;
549 case 16:
550 priv->trigger_level =
551 trigger_level_16[trigger >> PCH_UART_FCR_RFTL_SHIFT];
552 break;
553 default:
554 priv->trigger_level =
555 trigger_level_1[trigger >> PCH_UART_FCR_RFTL_SHIFT];
556 break;
557 }
558 fcr =
559 dmamode | fifo_size | trigger | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR;
560 iowrite8(PCH_UART_FCR_FIFOE, priv->membase + UART_FCR);
561 iowrite8(PCH_UART_FCR_FIFOE | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR,
562 priv->membase + UART_FCR);
563 iowrite8(fcr, priv->membase + UART_FCR);
564 priv->fcr = fcr;
565
566 return 0;
567}
568
569static u8 pch_uart_hal_get_modem(struct eg20t_port *priv)
570{
Feng Tang30c6c6b2012-02-06 17:24:44 +0800571 unsigned int msr = ioread8(priv->membase + UART_MSR);
572 priv->dmsr = msr & PCH_UART_MSR_DELTA;
573 return (u8)msr;
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900574}
575
Tomoya MORINAGA18220762011-02-23 10:03:14 +0900576static void pch_uart_hal_write(struct eg20t_port *priv,
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900577 const unsigned char *buf, int tx_size)
578{
579 int i;
580 unsigned int thr;
581
582 for (i = 0; i < tx_size;) {
583 thr = buf[i++];
584 iowrite8(thr, priv->membase + PCH_UART_THR);
585 }
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900586}
587
588static int pch_uart_hal_read(struct eg20t_port *priv, unsigned char *buf,
589 int rx_size)
590{
591 int i;
592 u8 rbr, lsr;
Liang Li1f9db092013-01-19 17:52:11 +0800593 struct uart_port *port = &priv->port;
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900594
595 lsr = ioread8(priv->membase + UART_LSR);
596 for (i = 0, lsr = ioread8(priv->membase + UART_LSR);
Liang Li1f9db092013-01-19 17:52:11 +0800597 i < rx_size && lsr & (UART_LSR_DR | UART_LSR_BI);
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900598 lsr = ioread8(priv->membase + UART_LSR)) {
599 rbr = ioread8(priv->membase + PCH_UART_RBR);
Liang Li1f9db092013-01-19 17:52:11 +0800600
601 if (lsr & UART_LSR_BI) {
602 port->icount.brk++;
603 if (uart_handle_break(port))
604 continue;
605 }
Liang Lie8c5b562013-01-24 12:31:27 +0800606#ifdef SUPPORT_SYSRQ
Liang Li1f9db092013-01-19 17:52:11 +0800607 if (port->sysrq) {
608 if (uart_handle_sysrq_char(port, rbr))
609 continue;
610 }
Liang Lie8c5b562013-01-24 12:31:27 +0800611#endif
Liang Li1f9db092013-01-19 17:52:11 +0800612
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900613 buf[i++] = rbr;
614 }
615 return i;
616}
617
Tomoya MORINAGA2a583642012-03-26 14:43:01 +0900618static unsigned char pch_uart_hal_get_iid(struct eg20t_port *priv)
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900619{
Tomoya MORINAGA2a583642012-03-26 14:43:01 +0900620 return ioread8(priv->membase + UART_IIR) &\
621 (PCH_UART_IIR_IID | PCH_UART_IIR_TOI | PCH_UART_IIR_IP);
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900622}
623
624static u8 pch_uart_hal_get_line_status(struct eg20t_port *priv)
625{
626 return ioread8(priv->membase + UART_LSR);
627}
628
629static void pch_uart_hal_set_break(struct eg20t_port *priv, int on)
630{
631 unsigned int lcr;
632
633 lcr = ioread8(priv->membase + UART_LCR);
634 if (on)
635 lcr |= PCH_UART_LCR_SB;
636 else
637 lcr &= ~PCH_UART_LCR_SB;
638
639 iowrite8(lcr, priv->membase + UART_LCR);
640}
641
642static int push_rx(struct eg20t_port *priv, const unsigned char *buf,
643 int size)
644{
Jiri Slaby05c7cd32013-01-03 15:53:04 +0100645 struct uart_port *port = &priv->port;
646 struct tty_port *tport = &port->state->port;
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900647
Jiri Slaby05c7cd32013-01-03 15:53:04 +0100648 tty_insert_flip_string(tport, buf, size);
Jiri Slaby2e124b42013-01-03 15:53:06 +0100649 tty_flip_buffer_push(tport);
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900650
651 return 0;
652}
653
654static int pop_tx_x(struct eg20t_port *priv, unsigned char *buf)
655{
Feng Tang30c6c6b2012-02-06 17:24:44 +0800656 int ret = 0;
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900657 struct uart_port *port = &priv->port;
658
659 if (port->x_char) {
Tomoya MORINAGA23877fd2011-02-23 10:03:15 +0900660 dev_dbg(priv->port.dev, "%s:X character send %02x (%lu)\n",
661 __func__, port->x_char, jiffies);
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900662 buf[0] = port->x_char;
663 port->x_char = 0;
664 ret = 1;
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900665 }
666
667 return ret;
668}
669
670static int dma_push_rx(struct eg20t_port *priv, int size)
671{
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900672 int room;
673 struct uart_port *port = &priv->port;
Jiri Slaby227434f2013-01-03 15:53:01 +0100674 struct tty_port *tport = &port->state->port;
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900675
Jiri Slaby227434f2013-01-03 15:53:01 +0100676 room = tty_buffer_request_room(tport, size);
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900677
678 if (room < size)
679 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n",
680 size - room);
681 if (!room)
Johan Hovold0b538612013-09-10 12:50:51 +0200682 return 0;
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900683
Jiri Slaby05c7cd32013-01-03 15:53:04 +0100684 tty_insert_flip_string(tport, sg_virt(&priv->sg_rx), size);
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900685
686 port->icount.rx += room;
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900687
688 return room;
689}
690
691static void pch_free_dma(struct uart_port *port)
692{
693 struct eg20t_port *priv;
694 priv = container_of(port, struct eg20t_port, port);
695
696 if (priv->chan_tx) {
697 dma_release_channel(priv->chan_tx);
698 priv->chan_tx = NULL;
699 }
700 if (priv->chan_rx) {
701 dma_release_channel(priv->chan_rx);
702 priv->chan_rx = NULL;
703 }
Tomoya MORINAGAef4f9d42012-03-26 14:43:06 +0900704
705 if (priv->rx_buf_dma) {
706 dma_free_coherent(port->dev, port->fifosize, priv->rx_buf_virt,
707 priv->rx_buf_dma);
708 priv->rx_buf_virt = NULL;
709 priv->rx_buf_dma = 0;
710 }
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900711
712 return;
713}
714
715static bool filter(struct dma_chan *chan, void *slave)
716{
717 struct pch_dma_slave *param = slave;
718
719 if ((chan->chan_id == param->chan_id) && (param->dma_dev ==
720 chan->device->dev)) {
721 chan->private = param;
722 return true;
723 } else {
724 return false;
725 }
726}
727
728static void pch_request_dma(struct uart_port *port)
729{
730 dma_cap_mask_t mask;
731 struct dma_chan *chan;
732 struct pci_dev *dma_dev;
733 struct pch_dma_slave *param;
734 struct eg20t_port *priv =
735 container_of(port, struct eg20t_port, port);
736 dma_cap_zero(mask);
737 dma_cap_set(DMA_SLAVE, mask);
738
Tomoya MORINAGA6c4b47d2011-07-20 20:17:49 +0900739 dma_dev = pci_get_bus_and_slot(priv->pdev->bus->number,
740 PCI_DEVFN(0xa, 0)); /* Get DMA's dev
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900741 information */
742 /* Set Tx DMA */
743 param = &priv->param_tx;
744 param->dma_dev = &dma_dev->dev;
Tomoya MORINAGAfec38d12011-02-23 10:03:19 +0900745 param->chan_id = priv->port.line * 2; /* Tx = 0, 2, 4, ... */
746
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900747 param->tx_reg = port->mapbase + UART_TX;
748 chan = dma_request_channel(mask, filter, param);
749 if (!chan) {
Tomoya MORINAGA23877fd2011-02-23 10:03:15 +0900750 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Tx)\n",
751 __func__);
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900752 return;
753 }
754 priv->chan_tx = chan;
755
756 /* Set Rx DMA */
757 param = &priv->param_rx;
758 param->dma_dev = &dma_dev->dev;
Tomoya MORINAGAfec38d12011-02-23 10:03:19 +0900759 param->chan_id = priv->port.line * 2 + 1; /* Rx = Tx + 1 */
760
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900761 param->rx_reg = port->mapbase + UART_RX;
762 chan = dma_request_channel(mask, filter, param);
763 if (!chan) {
Tomoya MORINAGA23877fd2011-02-23 10:03:15 +0900764 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Rx)\n",
765 __func__);
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900766 dma_release_channel(priv->chan_tx);
Tomoya MORINAGA90f04c22011-11-11 10:55:27 +0900767 priv->chan_tx = NULL;
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900768 return;
769 }
770
771 /* Get Consistent memory for DMA */
772 priv->rx_buf_virt = dma_alloc_coherent(port->dev, port->fifosize,
773 &priv->rx_buf_dma, GFP_KERNEL);
774 priv->chan_rx = chan;
775}
776
777static void pch_dma_rx_complete(void *arg)
778{
779 struct eg20t_port *priv = arg;
780 struct uart_port *port = &priv->port;
Tomoya MORINAGAda3564e2011-02-23 10:03:12 +0900781 int count;
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900782
Tomoya MORINAGAda3564e2011-02-23 10:03:12 +0900783 dma_sync_sg_for_cpu(port->dev, &priv->sg_rx, 1, DMA_FROM_DEVICE);
784 count = dma_push_rx(priv, priv->trigger_level);
785 if (count)
Jiri Slaby2e124b42013-01-03 15:53:06 +0100786 tty_flip_buffer_push(&port->state->port);
Tomoya MORINAGAda3564e2011-02-23 10:03:12 +0900787 async_tx_ack(priv->desc_rx);
Tomoya MORINAGAae213f32012-07-06 17:19:42 +0900788 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT |
789 PCH_UART_HAL_RX_ERR_INT);
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900790}
791
792static void pch_dma_tx_complete(void *arg)
793{
794 struct eg20t_port *priv = arg;
795 struct uart_port *port = &priv->port;
796 struct circ_buf *xmit = &port->state->xmit;
Tomoya MORINAGAda3564e2011-02-23 10:03:12 +0900797 struct scatterlist *sg = priv->sg_tx_p;
798 int i;
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900799
Tomoya MORINAGAda3564e2011-02-23 10:03:12 +0900800 for (i = 0; i < priv->nent; i++, sg++) {
801 xmit->tail += sg_dma_len(sg);
802 port->icount.tx += sg_dma_len(sg);
803 }
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900804 xmit->tail &= UART_XMIT_SIZE - 1;
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900805 async_tx_ack(priv->desc_tx);
Tomoya MORINAGAda3564e2011-02-23 10:03:12 +0900806 dma_unmap_sg(port->dev, sg, priv->nent, DMA_TO_DEVICE);
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900807 priv->tx_dma_use = 0;
Tomoya MORINAGAda3564e2011-02-23 10:03:12 +0900808 priv->nent = 0;
809 kfree(priv->sg_tx_p);
Tomoya MORINAGA60d10312011-02-23 10:03:18 +0900810 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900811}
812
Tomoya MORINAGA18220762011-02-23 10:03:14 +0900813static int pop_tx(struct eg20t_port *priv, int size)
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900814{
815 int count = 0;
816 struct uart_port *port = &priv->port;
817 struct circ_buf *xmit = &port->state->xmit;
818
819 if (uart_tx_stopped(port) || uart_circ_empty(xmit) || count >= size)
820 goto pop_tx_end;
821
822 do {
823 int cnt_to_end =
824 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
825 int sz = min(size - count, cnt_to_end);
Tomoya MORINAGA18220762011-02-23 10:03:14 +0900826 pch_uart_hal_write(priv, &xmit->buf[xmit->tail], sz);
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900827 xmit->tail = (xmit->tail + sz) & (UART_XMIT_SIZE - 1);
828 count += sz;
829 } while (!uart_circ_empty(xmit) && count < size);
830
831pop_tx_end:
Tomoya MORINAGA23877fd2011-02-23 10:03:15 +0900832 dev_dbg(priv->port.dev, "%d characters. Remained %d characters.(%lu)\n",
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900833 count, size - count, jiffies);
834
835 return count;
836}
837
838static int handle_rx_to(struct eg20t_port *priv)
839{
840 struct pch_uart_buffer *buf;
841 int rx_size;
842 int ret;
843 if (!priv->start_rx) {
Tomoya MORINAGAae213f32012-07-06 17:19:42 +0900844 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT |
845 PCH_UART_HAL_RX_ERR_INT);
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900846 return 0;
847 }
848 buf = &priv->rxbuf;
849 do {
850 rx_size = pch_uart_hal_read(priv, buf->buf, buf->size);
851 ret = push_rx(priv, buf->buf, rx_size);
852 if (ret)
853 return 0;
854 } while (rx_size == buf->size);
855
856 return PCH_UART_HANDLED_RX_INT;
857}
858
859static int handle_rx(struct eg20t_port *priv)
860{
861 return handle_rx_to(priv);
862}
863
864static int dma_handle_rx(struct eg20t_port *priv)
865{
866 struct uart_port *port = &priv->port;
867 struct dma_async_tx_descriptor *desc;
868 struct scatterlist *sg;
869
870 priv = container_of(port, struct eg20t_port, port);
871 sg = &priv->sg_rx;
872
873 sg_init_table(&priv->sg_rx, 1); /* Initialize SG table */
874
Tomoya MORINAGAda3564e2011-02-23 10:03:12 +0900875 sg_dma_len(sg) = priv->trigger_level;
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900876
877 sg_set_page(&priv->sg_rx, virt_to_page(priv->rx_buf_virt),
Tomoya MORINAGA1c518992010-12-16 16:13:29 +0900878 sg_dma_len(sg), (unsigned long)priv->rx_buf_virt &
879 ~PAGE_MASK);
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900880
881 sg_dma_address(sg) = priv->rx_buf_dma;
882
Alexandre Bounine16052822012-03-08 16:11:18 -0500883 desc = dmaengine_prep_slave_sg(priv->chan_rx,
Vinod Koula485df42011-10-14 10:47:38 +0530884 sg, 1, DMA_DEV_TO_MEM,
Tomoya MORINAGAda3564e2011-02-23 10:03:12 +0900885 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
886
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900887 if (!desc)
888 return 0;
889
890 priv->desc_rx = desc;
891 desc->callback = pch_dma_rx_complete;
892 desc->callback_param = priv;
893 desc->tx_submit(desc);
894 dma_async_issue_pending(priv->chan_rx);
895
896 return PCH_UART_HANDLED_RX_INT;
897}
898
899static unsigned int handle_tx(struct eg20t_port *priv)
900{
901 struct uart_port *port = &priv->port;
902 struct circ_buf *xmit = &port->state->xmit;
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900903 int fifo_size;
904 int tx_size;
905 int size;
906 int tx_empty;
907
908 if (!priv->start_tx) {
Tomoya MORINAGA23877fd2011-02-23 10:03:15 +0900909 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
910 __func__, jiffies);
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900911 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
912 priv->tx_empty = 1;
913 return 0;
914 }
915
916 fifo_size = max(priv->fifo_size, 1);
917 tx_empty = 1;
918 if (pop_tx_x(priv, xmit->buf)) {
919 pch_uart_hal_write(priv, xmit->buf, 1);
920 port->icount.tx++;
921 tx_empty = 0;
922 fifo_size--;
923 }
924 size = min(xmit->head - xmit->tail, fifo_size);
Tomoya MORINAGAda3564e2011-02-23 10:03:12 +0900925 if (size < 0)
926 size = fifo_size;
927
Tomoya MORINAGA18220762011-02-23 10:03:14 +0900928 tx_size = pop_tx(priv, size);
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900929 if (tx_size > 0) {
Tomoya MORINAGA18220762011-02-23 10:03:14 +0900930 port->icount.tx += tx_size;
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900931 tx_empty = 0;
932 }
933
934 priv->tx_empty = tx_empty;
935
Tomoya MORINAGAda3564e2011-02-23 10:03:12 +0900936 if (tx_empty) {
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900937 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
Tomoya MORINAGAda3564e2011-02-23 10:03:12 +0900938 uart_write_wakeup(port);
939 }
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900940
941 return PCH_UART_HANDLED_TX_INT;
942}
943
944static unsigned int dma_handle_tx(struct eg20t_port *priv)
945{
946 struct uart_port *port = &priv->port;
947 struct circ_buf *xmit = &port->state->xmit;
Tomoya MORINAGAda3564e2011-02-23 10:03:12 +0900948 struct scatterlist *sg;
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900949 int nent;
950 int fifo_size;
951 int tx_empty;
952 struct dma_async_tx_descriptor *desc;
Tomoya MORINAGAda3564e2011-02-23 10:03:12 +0900953 int num;
954 int i;
955 int bytes;
956 int size;
957 int rem;
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900958
959 if (!priv->start_tx) {
Tomoya MORINAGA23877fd2011-02-23 10:03:15 +0900960 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
961 __func__, jiffies);
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900962 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
963 priv->tx_empty = 1;
964 return 0;
965 }
966
Tomoya MORINAGA60d10312011-02-23 10:03:18 +0900967 if (priv->tx_dma_use) {
968 dev_dbg(priv->port.dev, "%s:Tx is not completed. (%lu)\n",
969 __func__, jiffies);
970 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
971 priv->tx_empty = 1;
972 return 0;
973 }
974
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900975 fifo_size = max(priv->fifo_size, 1);
976 tx_empty = 1;
977 if (pop_tx_x(priv, xmit->buf)) {
978 pch_uart_hal_write(priv, xmit->buf, 1);
979 port->icount.tx++;
980 tx_empty = 0;
981 fifo_size--;
982 }
983
Tomoya MORINAGAda3564e2011-02-23 10:03:12 +0900984 bytes = min((int)CIRC_CNT(xmit->head, xmit->tail,
985 UART_XMIT_SIZE), CIRC_CNT_TO_END(xmit->head,
986 xmit->tail, UART_XMIT_SIZE));
987 if (!bytes) {
Tomoya MORINAGA23877fd2011-02-23 10:03:15 +0900988 dev_dbg(priv->port.dev, "%s 0 bytes return\n", __func__);
Tomoya MORINAGAda3564e2011-02-23 10:03:12 +0900989 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
990 uart_write_wakeup(port);
991 return 0;
992 }
993
994 if (bytes > fifo_size) {
995 num = bytes / fifo_size + 1;
996 size = fifo_size;
997 rem = bytes % fifo_size;
998 } else {
999 num = 1;
1000 size = bytes;
1001 rem = bytes;
1002 }
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001003
Tomoya MORINAGA23877fd2011-02-23 10:03:15 +09001004 dev_dbg(priv->port.dev, "%s num=%d size=%d rem=%d\n",
1005 __func__, num, size, rem);
1006
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001007 priv->tx_dma_use = 1;
1008
Tomoya MORINAGAda3564e2011-02-23 10:03:12 +09001009 priv->sg_tx_p = kzalloc(sizeof(struct scatterlist)*num, GFP_ATOMIC);
Fengguang Wua92098a2012-07-28 20:43:57 +08001010 if (!priv->sg_tx_p) {
1011 dev_err(priv->port.dev, "%s:kzalloc Failed\n", __func__);
1012 return 0;
1013 }
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001014
Tomoya MORINAGAda3564e2011-02-23 10:03:12 +09001015 sg_init_table(priv->sg_tx_p, num); /* Initialize SG table */
1016 sg = priv->sg_tx_p;
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001017
Tomoya MORINAGAda3564e2011-02-23 10:03:12 +09001018 for (i = 0; i < num; i++, sg++) {
1019 if (i == (num - 1))
1020 sg_set_page(sg, virt_to_page(xmit->buf),
1021 rem, fifo_size * i);
1022 else
1023 sg_set_page(sg, virt_to_page(xmit->buf),
1024 size, fifo_size * i);
1025 }
1026
1027 sg = priv->sg_tx_p;
1028 nent = dma_map_sg(port->dev, sg, num, DMA_TO_DEVICE);
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001029 if (!nent) {
Tomoya MORINAGA23877fd2011-02-23 10:03:15 +09001030 dev_err(priv->port.dev, "%s:dma_map_sg Failed\n", __func__);
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001031 return 0;
1032 }
Tomoya MORINAGAda3564e2011-02-23 10:03:12 +09001033 priv->nent = nent;
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001034
Tomoya MORINAGAda3564e2011-02-23 10:03:12 +09001035 for (i = 0; i < nent; i++, sg++) {
1036 sg->offset = (xmit->tail & (UART_XMIT_SIZE - 1)) +
1037 fifo_size * i;
1038 sg_dma_address(sg) = (sg_dma_address(sg) &
1039 ~(UART_XMIT_SIZE - 1)) + sg->offset;
1040 if (i == (nent - 1))
1041 sg_dma_len(sg) = rem;
1042 else
1043 sg_dma_len(sg) = size;
1044 }
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001045
Alexandre Bounine16052822012-03-08 16:11:18 -05001046 desc = dmaengine_prep_slave_sg(priv->chan_tx,
Vinod Koula485df42011-10-14 10:47:38 +05301047 priv->sg_tx_p, nent, DMA_MEM_TO_DEV,
Tomoya MORINAGAda3564e2011-02-23 10:03:12 +09001048 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001049 if (!desc) {
Tomoya MORINAGA23877fd2011-02-23 10:03:15 +09001050 dev_err(priv->port.dev, "%s:device_prep_slave_sg Failed\n",
1051 __func__);
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001052 return 0;
1053 }
Tomoya MORINAGAda3564e2011-02-23 10:03:12 +09001054 dma_sync_sg_for_device(port->dev, priv->sg_tx_p, nent, DMA_TO_DEVICE);
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001055 priv->desc_tx = desc;
1056 desc->callback = pch_dma_tx_complete;
1057 desc->callback_param = priv;
1058
1059 desc->tx_submit(desc);
1060
1061 dma_async_issue_pending(priv->chan_tx);
1062
1063 return PCH_UART_HANDLED_TX_INT;
1064}
1065
1066static void pch_uart_err_ir(struct eg20t_port *priv, unsigned int lsr)
1067{
Liang Li384e3012013-01-19 17:52:10 +08001068 struct uart_port *port = &priv->port;
1069 struct tty_struct *tty = tty_port_tty_get(&port->state->port);
1070 char *error_msg[5] = {};
1071 int i = 0;
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001072
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001073 if (lsr & PCH_UART_LSR_ERR)
Liang Li384e3012013-01-19 17:52:10 +08001074 error_msg[i++] = "Error data in FIFO\n";
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001075
Liang Li384e3012013-01-19 17:52:10 +08001076 if (lsr & UART_LSR_FE) {
1077 port->icount.frame++;
1078 error_msg[i++] = " Framing Error\n";
1079 }
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001080
Liang Li384e3012013-01-19 17:52:10 +08001081 if (lsr & UART_LSR_PE) {
1082 port->icount.parity++;
1083 error_msg[i++] = " Parity Error\n";
1084 }
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001085
Liang Li384e3012013-01-19 17:52:10 +08001086 if (lsr & UART_LSR_OE) {
1087 port->icount.overrun++;
1088 error_msg[i++] = " Overrun Error\n";
1089 }
1090
1091 if (tty == NULL) {
1092 for (i = 0; error_msg[i] != NULL; i++)
1093 dev_err(&priv->pdev->dev, error_msg[i]);
Johan Hovoldfc0919c2013-09-10 12:50:49 +02001094 } else {
1095 tty_kref_put(tty);
Liang Li384e3012013-01-19 17:52:10 +08001096 }
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001097}
1098
1099static irqreturn_t pch_uart_interrupt(int irq, void *dev_id)
1100{
1101 struct eg20t_port *priv = dev_id;
1102 unsigned int handled;
1103 u8 lsr;
1104 int ret = 0;
Tomoya MORINAGA2a583642012-03-26 14:43:01 +09001105 unsigned char iid;
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001106 unsigned long flags;
Tomoya MORINAGA5181fb32012-03-26 14:43:03 +09001107 int next = 1;
1108 u8 msr;
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001109
Darren Hartfe89def2012-06-19 14:00:18 -07001110 spin_lock_irqsave(&priv->lock, flags);
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001111 handled = 0;
Tomoya MORINAGA5181fb32012-03-26 14:43:03 +09001112 while (next) {
1113 iid = pch_uart_hal_get_iid(priv);
1114 if (iid & PCH_UART_IIR_IP) /* No Interrupt */
1115 break;
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001116 switch (iid) {
1117 case PCH_UART_IID_RLS: /* Receiver Line Status */
1118 lsr = pch_uart_hal_get_line_status(priv);
1119 if (lsr & (PCH_UART_LSR_ERR | UART_LSR_FE |
1120 UART_LSR_PE | UART_LSR_OE)) {
1121 pch_uart_err_ir(priv, lsr);
1122 ret = PCH_UART_HANDLED_RX_ERR_INT;
Tomoya MORINAGA04e2c2e2012-03-26 14:43:05 +09001123 } else {
1124 ret = PCH_UART_HANDLED_LS_INT;
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001125 }
1126 break;
1127 case PCH_UART_IID_RDR: /* Received Data Ready */
Tomoya MORINAGAda3564e2011-02-23 10:03:12 +09001128 if (priv->use_dma) {
1129 pch_uart_hal_disable_interrupt(priv,
Tomoya MORINAGAae213f32012-07-06 17:19:42 +09001130 PCH_UART_HAL_RX_INT |
1131 PCH_UART_HAL_RX_ERR_INT);
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001132 ret = dma_handle_rx(priv);
Tomoya MORINAGAda3564e2011-02-23 10:03:12 +09001133 if (!ret)
1134 pch_uart_hal_enable_interrupt(priv,
Tomoya MORINAGAae213f32012-07-06 17:19:42 +09001135 PCH_UART_HAL_RX_INT |
1136 PCH_UART_HAL_RX_ERR_INT);
Tomoya MORINAGAda3564e2011-02-23 10:03:12 +09001137 } else {
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001138 ret = handle_rx(priv);
Tomoya MORINAGAda3564e2011-02-23 10:03:12 +09001139 }
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001140 break;
1141 case PCH_UART_IID_RDR_TO: /* Received Data Ready
1142 (FIFO Timeout) */
1143 ret = handle_rx_to(priv);
1144 break;
1145 case PCH_UART_IID_THRE: /* Transmitter Holding Register
1146 Empty */
1147 if (priv->use_dma)
1148 ret = dma_handle_tx(priv);
1149 else
1150 ret = handle_tx(priv);
1151 break;
1152 case PCH_UART_IID_MS: /* Modem Status */
Tomoya MORINAGA5181fb32012-03-26 14:43:03 +09001153 msr = pch_uart_hal_get_modem(priv);
1154 next = 0; /* MS ir prioirty is the lowest. So, MS ir
1155 means final interrupt */
1156 if ((msr & UART_MSR_ANY_DELTA) == 0)
1157 break;
1158 ret |= PCH_UART_HANDLED_MS_INT;
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001159 break;
1160 default: /* Never junp to this label */
Tomoya MORINAGAb23954a32012-03-26 14:43:02 +09001161 dev_err(priv->port.dev, "%s:iid=%02x (%lu)\n", __func__,
Tomoya MORINAGA23877fd2011-02-23 10:03:15 +09001162 iid, jiffies);
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001163 ret = -1;
Tomoya MORINAGA5181fb32012-03-26 14:43:03 +09001164 next = 0;
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001165 break;
1166 }
1167 handled |= (unsigned int)ret;
1168 }
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001169
Darren Hartfe89def2012-06-19 14:00:18 -07001170 spin_unlock_irqrestore(&priv->lock, flags);
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001171 return IRQ_RETVAL(handled);
1172}
1173
1174/* This function tests whether the transmitter fifo and shifter for the port
1175 described by 'port' is empty. */
1176static unsigned int pch_uart_tx_empty(struct uart_port *port)
1177{
1178 struct eg20t_port *priv;
Feng Tang30c6c6b2012-02-06 17:24:44 +08001179
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001180 priv = container_of(port, struct eg20t_port, port);
1181 if (priv->tx_empty)
Feng Tang30c6c6b2012-02-06 17:24:44 +08001182 return TIOCSER_TEMT;
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001183 else
Feng Tang30c6c6b2012-02-06 17:24:44 +08001184 return 0;
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001185}
1186
1187/* Returns the current state of modem control inputs. */
1188static unsigned int pch_uart_get_mctrl(struct uart_port *port)
1189{
1190 struct eg20t_port *priv;
1191 u8 modem;
1192 unsigned int ret = 0;
1193
1194 priv = container_of(port, struct eg20t_port, port);
1195 modem = pch_uart_hal_get_modem(priv);
1196
1197 if (modem & UART_MSR_DCD)
1198 ret |= TIOCM_CAR;
1199
1200 if (modem & UART_MSR_RI)
1201 ret |= TIOCM_RNG;
1202
1203 if (modem & UART_MSR_DSR)
1204 ret |= TIOCM_DSR;
1205
1206 if (modem & UART_MSR_CTS)
1207 ret |= TIOCM_CTS;
1208
1209 return ret;
1210}
1211
1212static void pch_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1213{
1214 u32 mcr = 0;
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001215 struct eg20t_port *priv = container_of(port, struct eg20t_port, port);
1216
1217 if (mctrl & TIOCM_DTR)
1218 mcr |= UART_MCR_DTR;
1219 if (mctrl & TIOCM_RTS)
1220 mcr |= UART_MCR_RTS;
1221 if (mctrl & TIOCM_LOOP)
1222 mcr |= UART_MCR_LOOP;
1223
Tomoya MORINAGA9af71552011-02-23 10:03:17 +09001224 if (priv->mcr & UART_MCR_AFE)
1225 mcr |= UART_MCR_AFE;
1226
1227 if (mctrl)
1228 iowrite8(mcr, priv->membase + UART_MCR);
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001229}
1230
1231static void pch_uart_stop_tx(struct uart_port *port)
1232{
1233 struct eg20t_port *priv;
1234 priv = container_of(port, struct eg20t_port, port);
1235 priv->start_tx = 0;
1236 priv->tx_dma_use = 0;
1237}
1238
1239static void pch_uart_start_tx(struct uart_port *port)
1240{
1241 struct eg20t_port *priv;
1242
1243 priv = container_of(port, struct eg20t_port, port);
1244
Tomoya MORINAGA23877fd2011-02-23 10:03:15 +09001245 if (priv->use_dma) {
1246 if (priv->tx_dma_use) {
1247 dev_dbg(priv->port.dev, "%s : Tx DMA is NOT empty.\n",
1248 __func__);
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001249 return;
Tomoya MORINAGA23877fd2011-02-23 10:03:15 +09001250 }
1251 }
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001252
1253 priv->start_tx = 1;
1254 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
1255}
1256
1257static void pch_uart_stop_rx(struct uart_port *port)
1258{
1259 struct eg20t_port *priv;
1260 priv = container_of(port, struct eg20t_port, port);
1261 priv->start_rx = 0;
Tomoya MORINAGAae213f32012-07-06 17:19:42 +09001262 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT |
1263 PCH_UART_HAL_RX_ERR_INT);
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001264}
1265
1266/* Enable the modem status interrupts. */
1267static void pch_uart_enable_ms(struct uart_port *port)
1268{
1269 struct eg20t_port *priv;
1270 priv = container_of(port, struct eg20t_port, port);
1271 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_MS_INT);
1272}
1273
1274/* Control the transmission of a break signal. */
1275static void pch_uart_break_ctl(struct uart_port *port, int ctl)
1276{
1277 struct eg20t_port *priv;
1278 unsigned long flags;
1279
1280 priv = container_of(port, struct eg20t_port, port);
Darren Hartfe89def2012-06-19 14:00:18 -07001281 spin_lock_irqsave(&priv->lock, flags);
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001282 pch_uart_hal_set_break(priv, ctl);
Darren Hartfe89def2012-06-19 14:00:18 -07001283 spin_unlock_irqrestore(&priv->lock, flags);
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001284}
1285
1286/* Grab any interrupt resources and initialise any low level driver state. */
1287static int pch_uart_startup(struct uart_port *port)
1288{
1289 struct eg20t_port *priv;
1290 int ret;
1291 int fifo_size;
1292 int trigger_level;
1293
1294 priv = container_of(port, struct eg20t_port, port);
1295 priv->tx_empty = 1;
Tomoya MORINAGAaac6c0b2011-02-23 10:03:16 +09001296
1297 if (port->uartclk)
Darren Harta8a3ec92012-03-09 09:51:48 -08001298 priv->uartclk = port->uartclk;
Tomoya MORINAGAaac6c0b2011-02-23 10:03:16 +09001299 else
Darren Harta8a3ec92012-03-09 09:51:48 -08001300 port->uartclk = priv->uartclk;
Tomoya MORINAGAaac6c0b2011-02-23 10:03:16 +09001301
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001302 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1303 ret = pch_uart_hal_set_line(priv, default_baud,
1304 PCH_UART_HAL_PARITY_NONE, PCH_UART_HAL_8BIT,
1305 PCH_UART_HAL_STB1);
1306 if (ret)
1307 return ret;
1308
1309 switch (priv->fifo_size) {
1310 case 256:
1311 fifo_size = PCH_UART_HAL_FIFO256;
1312 break;
1313 case 64:
1314 fifo_size = PCH_UART_HAL_FIFO64;
1315 break;
1316 case 16:
1317 fifo_size = PCH_UART_HAL_FIFO16;
Alan Cox669bd452012-07-02 18:51:38 +01001318 break;
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001319 case 1:
1320 default:
1321 fifo_size = PCH_UART_HAL_FIFO_DIS;
1322 break;
1323 }
1324
1325 switch (priv->trigger) {
1326 case PCH_UART_HAL_TRIGGER1:
1327 trigger_level = 1;
1328 break;
1329 case PCH_UART_HAL_TRIGGER_L:
1330 trigger_level = priv->fifo_size / 4;
1331 break;
1332 case PCH_UART_HAL_TRIGGER_M:
1333 trigger_level = priv->fifo_size / 2;
1334 break;
1335 case PCH_UART_HAL_TRIGGER_H:
1336 default:
1337 trigger_level = priv->fifo_size - (priv->fifo_size / 8);
1338 break;
1339 }
1340
1341 priv->trigger_level = trigger_level;
1342 ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1343 fifo_size, priv->trigger);
1344 if (ret < 0)
1345 return ret;
1346
1347 ret = request_irq(priv->port.irq, pch_uart_interrupt, IRQF_SHARED,
Alexander Stein50d16ca2014-03-25 14:05:08 +01001348 priv->irq_name, priv);
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001349 if (ret < 0)
1350 return ret;
1351
1352 if (priv->use_dma)
1353 pch_request_dma(port);
1354
1355 priv->start_rx = 1;
Tomoya MORINAGAae213f32012-07-06 17:19:42 +09001356 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT |
1357 PCH_UART_HAL_RX_ERR_INT);
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001358 uart_update_timeout(port, CS8, default_baud);
1359
1360 return 0;
1361}
1362
1363static void pch_uart_shutdown(struct uart_port *port)
1364{
1365 struct eg20t_port *priv;
1366 int ret;
1367
1368 priv = container_of(port, struct eg20t_port, port);
1369 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1370 pch_uart_hal_fifo_reset(priv, PCH_UART_HAL_CLR_ALL_FIFO);
1371 ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1372 PCH_UART_HAL_FIFO_DIS, PCH_UART_HAL_TRIGGER1);
1373 if (ret)
Tomoya MORINAGA23877fd2011-02-23 10:03:15 +09001374 dev_err(priv->port.dev,
1375 "pch_uart_hal_set_fifo Failed(ret=%d)\n", ret);
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001376
Tomoya MORINAGA90f04c22011-11-11 10:55:27 +09001377 pch_free_dma(port);
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001378
1379 free_irq(priv->port.irq, priv);
1380}
1381
1382/* Change the port parameters, including word length, parity, stop
1383 *bits. Update read_status_mask and ignore_status_mask to indicate
1384 *the types of events we are interested in receiving. */
1385static void pch_uart_set_termios(struct uart_port *port,
1386 struct ktermios *termios, struct ktermios *old)
1387{
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001388 int rtn;
Darren Harte26439c2013-07-29 15:15:07 -07001389 unsigned int baud, parity, bits, stb;
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001390 struct eg20t_port *priv;
1391 unsigned long flags;
1392
1393 priv = container_of(port, struct eg20t_port, port);
1394 switch (termios->c_cflag & CSIZE) {
1395 case CS5:
1396 bits = PCH_UART_HAL_5BIT;
1397 break;
1398 case CS6:
1399 bits = PCH_UART_HAL_6BIT;
1400 break;
1401 case CS7:
1402 bits = PCH_UART_HAL_7BIT;
1403 break;
1404 default: /* CS8 */
1405 bits = PCH_UART_HAL_8BIT;
1406 break;
1407 }
1408 if (termios->c_cflag & CSTOPB)
1409 stb = PCH_UART_HAL_STB2;
1410 else
1411 stb = PCH_UART_HAL_STB1;
1412
1413 if (termios->c_cflag & PARENB) {
Tomoya MORINAGA2fc39ae2012-07-06 17:19:43 +09001414 if (termios->c_cflag & PARODD)
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001415 parity = PCH_UART_HAL_PARITY_ODD;
1416 else
1417 parity = PCH_UART_HAL_PARITY_EVEN;
1418
Feng Tang30c6c6b2012-02-06 17:24:44 +08001419 } else
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001420 parity = PCH_UART_HAL_PARITY_NONE;
Tomoya MORINAGA9af71552011-02-23 10:03:17 +09001421
1422 /* Only UART0 has auto hardware flow function */
1423 if ((termios->c_cflag & CRTSCTS) && (priv->fifo_size == 256))
1424 priv->mcr |= UART_MCR_AFE;
1425 else
1426 priv->mcr &= ~UART_MCR_AFE;
1427
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001428 termios->c_cflag &= ~CMSPAR; /* Mark/Space parity is not supported */
1429
1430 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
1431
Darren Hartfe89def2012-06-19 14:00:18 -07001432 spin_lock_irqsave(&priv->lock, flags);
1433 spin_lock(&port->lock);
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001434
1435 uart_update_timeout(port, termios->c_cflag, baud);
1436 rtn = pch_uart_hal_set_line(priv, baud, parity, bits, stb);
1437 if (rtn)
1438 goto out;
1439
Tomoya MORINAGAa1d7cfe2011-10-27 15:45:18 +09001440 pch_uart_set_mctrl(&priv->port, priv->port.mctrl);
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001441 /* Don't rewrite B0 */
1442 if (tty_termios_baud_rate(termios))
1443 tty_termios_encode_baud_rate(termios, baud, baud);
1444
1445out:
Darren Hartfe89def2012-06-19 14:00:18 -07001446 spin_unlock(&port->lock);
1447 spin_unlock_irqrestore(&priv->lock, flags);
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001448}
1449
1450static const char *pch_uart_type(struct uart_port *port)
1451{
1452 return KBUILD_MODNAME;
1453}
1454
1455static void pch_uart_release_port(struct uart_port *port)
1456{
1457 struct eg20t_port *priv;
1458
1459 priv = container_of(port, struct eg20t_port, port);
1460 pci_iounmap(priv->pdev, priv->membase);
1461 pci_release_regions(priv->pdev);
1462}
1463
1464static int pch_uart_request_port(struct uart_port *port)
1465{
1466 struct eg20t_port *priv;
1467 int ret;
1468 void __iomem *membase;
1469
1470 priv = container_of(port, struct eg20t_port, port);
1471 ret = pci_request_regions(priv->pdev, KBUILD_MODNAME);
1472 if (ret < 0)
1473 return -EBUSY;
1474
1475 membase = pci_iomap(priv->pdev, 1, 0);
1476 if (!membase) {
1477 pci_release_regions(priv->pdev);
1478 return -EBUSY;
1479 }
1480 priv->membase = port->membase = membase;
1481
1482 return 0;
1483}
1484
1485static void pch_uart_config_port(struct uart_port *port, int type)
1486{
1487 struct eg20t_port *priv;
1488
1489 priv = container_of(port, struct eg20t_port, port);
1490 if (type & UART_CONFIG_TYPE) {
1491 port->type = priv->port_type;
1492 pch_uart_request_port(port);
1493 }
1494}
1495
1496static int pch_uart_verify_port(struct uart_port *port,
1497 struct serial_struct *serinfo)
1498{
1499 struct eg20t_port *priv;
1500
1501 priv = container_of(port, struct eg20t_port, port);
1502 if (serinfo->flags & UPF_LOW_LATENCY) {
Tomoya MORINAGA23877fd2011-02-23 10:03:15 +09001503 dev_info(priv->port.dev,
1504 "PCH UART : Use PIO Mode (without DMA)\n");
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001505 priv->use_dma = 0;
1506 serinfo->flags &= ~UPF_LOW_LATENCY;
1507 } else {
1508#ifndef CONFIG_PCH_DMA
Tomoya MORINAGA23877fd2011-02-23 10:03:15 +09001509 dev_err(priv->port.dev, "%s : PCH DMA is not Loaded.\n",
1510 __func__);
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001511 return -EOPNOTSUPP;
1512#endif
Sebastian Andrzej Siewiore41c0982013-12-04 20:52:49 +01001513 if (!priv->use_dma) {
Tomoya MORINAGAaf6d17c2012-04-12 10:47:50 +09001514 pch_request_dma(port);
Sebastian Andrzej Siewiore41c0982013-12-04 20:52:49 +01001515 if (priv->chan_rx)
1516 priv->use_dma = 1;
1517 }
1518 dev_info(priv->port.dev, "PCH UART: %s\n",
1519 priv->use_dma ?
1520 "Use DMA Mode" : "No DMA");
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001521 }
1522
1523 return 0;
1524}
1525
Luis Henriques09a51632013-08-14 23:18:37 +01001526#if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_PCH_UART_CONSOLE)
Alexander Steine30f8672011-11-15 15:04:07 -08001527/*
1528 * Wait for transmitter & holding register to empty
1529 */
1530static void wait_for_xmitr(struct eg20t_port *up, int bits)
1531{
1532 unsigned int status, tmout = 10000;
1533
1534 /* Wait up to 10ms for the character(s) to be sent. */
1535 for (;;) {
1536 status = ioread8(up->membase + UART_LSR);
1537
1538 if ((status & bits) == bits)
1539 break;
1540 if (--tmout == 0)
1541 break;
1542 udelay(1);
1543 }
1544
1545 /* Wait up to 1s for flow control if necessary */
1546 if (up->port.flags & UPF_CONS_FLOW) {
1547 unsigned int tmout;
1548 for (tmout = 1000000; tmout; tmout--) {
1549 unsigned int msr = ioread8(up->membase + UART_MSR);
1550 if (msr & UART_MSR_CTS)
1551 break;
1552 udelay(1);
1553 touch_nmi_watchdog();
1554 }
1555 }
1556}
Luis Henriques09a51632013-08-14 23:18:37 +01001557#endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_PCH_UART_CONSOLE */
Alexander Steine30f8672011-11-15 15:04:07 -08001558
Liang Lief44d282013-03-05 22:30:38 +08001559#ifdef CONFIG_CONSOLE_POLL
1560/*
1561 * Console polling routines for communicate via uart while
1562 * in an interrupt or debug context.
1563 */
1564static int pch_uart_get_poll_char(struct uart_port *port)
1565{
1566 struct eg20t_port *priv =
1567 container_of(port, struct eg20t_port, port);
1568 u8 lsr = ioread8(priv->membase + UART_LSR);
1569
1570 if (!(lsr & UART_LSR_DR))
1571 return NO_POLL_CHAR;
1572
1573 return ioread8(priv->membase + PCH_UART_RBR);
1574}
1575
1576
1577static void pch_uart_put_poll_char(struct uart_port *port,
1578 unsigned char c)
1579{
1580 unsigned int ier;
1581 struct eg20t_port *priv =
1582 container_of(port, struct eg20t_port, port);
1583
1584 /*
1585 * First save the IER then disable the interrupts
1586 */
1587 ier = ioread8(priv->membase + UART_IER);
1588 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1589
1590 wait_for_xmitr(priv, UART_LSR_THRE);
1591 /*
1592 * Send the character out.
1593 * If a LF, also do CR...
1594 */
1595 iowrite8(c, priv->membase + PCH_UART_THR);
1596 if (c == 10) {
1597 wait_for_xmitr(priv, UART_LSR_THRE);
1598 iowrite8(13, priv->membase + PCH_UART_THR);
1599 }
1600
1601 /*
1602 * Finally, wait for transmitter to become empty
1603 * and restore the IER
1604 */
1605 wait_for_xmitr(priv, BOTH_EMPTY);
1606 iowrite8(ier, priv->membase + UART_IER);
1607}
1608#endif /* CONFIG_CONSOLE_POLL */
1609
1610static struct uart_ops pch_uart_ops = {
1611 .tx_empty = pch_uart_tx_empty,
1612 .set_mctrl = pch_uart_set_mctrl,
1613 .get_mctrl = pch_uart_get_mctrl,
1614 .stop_tx = pch_uart_stop_tx,
1615 .start_tx = pch_uart_start_tx,
1616 .stop_rx = pch_uart_stop_rx,
1617 .enable_ms = pch_uart_enable_ms,
1618 .break_ctl = pch_uart_break_ctl,
1619 .startup = pch_uart_startup,
1620 .shutdown = pch_uart_shutdown,
1621 .set_termios = pch_uart_set_termios,
1622/* .pm = pch_uart_pm, Not supported yet */
Liang Lief44d282013-03-05 22:30:38 +08001623 .type = pch_uart_type,
1624 .release_port = pch_uart_release_port,
1625 .request_port = pch_uart_request_port,
1626 .config_port = pch_uart_config_port,
1627 .verify_port = pch_uart_verify_port,
1628#ifdef CONFIG_CONSOLE_POLL
1629 .poll_get_char = pch_uart_get_poll_char,
1630 .poll_put_char = pch_uart_put_poll_char,
1631#endif
1632};
1633
1634#ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1635
Alexander Steine30f8672011-11-15 15:04:07 -08001636static void pch_console_putchar(struct uart_port *port, int ch)
1637{
1638 struct eg20t_port *priv =
1639 container_of(port, struct eg20t_port, port);
1640
1641 wait_for_xmitr(priv, UART_LSR_THRE);
1642 iowrite8(ch, priv->membase + PCH_UART_THR);
1643}
1644
1645/*
1646 * Print a string to the serial port trying not to disturb
1647 * any possible real use of the port...
1648 *
1649 * The console_lock must be held when we get here.
1650 */
1651static void
1652pch_console_write(struct console *co, const char *s, unsigned int count)
1653{
1654 struct eg20t_port *priv;
Alexander Steine30f8672011-11-15 15:04:07 -08001655 unsigned long flags;
Darren Hartfe89def2012-06-19 14:00:18 -07001656 int priv_locked = 1;
1657 int port_locked = 1;
Alexander Steine30f8672011-11-15 15:04:07 -08001658 u8 ier;
Alexander Steine30f8672011-11-15 15:04:07 -08001659
1660 priv = pch_uart_ports[co->index];
1661
1662 touch_nmi_watchdog();
1663
1664 local_irq_save(flags);
1665 if (priv->port.sysrq) {
Liang Li1f9db092013-01-19 17:52:11 +08001666 /* call to uart_handle_sysrq_char already took the priv lock */
1667 priv_locked = 0;
Darren Hartfe89def2012-06-19 14:00:18 -07001668 /* serial8250_handle_port() already took the port lock */
1669 port_locked = 0;
Alexander Steine30f8672011-11-15 15:04:07 -08001670 } else if (oops_in_progress) {
Darren Hartfe89def2012-06-19 14:00:18 -07001671 priv_locked = spin_trylock(&priv->lock);
1672 port_locked = spin_trylock(&priv->port.lock);
1673 } else {
1674 spin_lock(&priv->lock);
Alexander Steine30f8672011-11-15 15:04:07 -08001675 spin_lock(&priv->port.lock);
Darren Hartfe89def2012-06-19 14:00:18 -07001676 }
Alexander Steine30f8672011-11-15 15:04:07 -08001677
1678 /*
1679 * First save the IER then disable the interrupts
1680 */
1681 ier = ioread8(priv->membase + UART_IER);
1682
1683 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1684
1685 uart_console_write(&priv->port, s, count, pch_console_putchar);
1686
1687 /*
1688 * Finally, wait for transmitter to become empty
1689 * and restore the IER
1690 */
1691 wait_for_xmitr(priv, BOTH_EMPTY);
1692 iowrite8(ier, priv->membase + UART_IER);
1693
Darren Hartfe89def2012-06-19 14:00:18 -07001694 if (port_locked)
Alexander Steine30f8672011-11-15 15:04:07 -08001695 spin_unlock(&priv->port.lock);
Darren Hartfe89def2012-06-19 14:00:18 -07001696 if (priv_locked)
1697 spin_unlock(&priv->lock);
Alexander Steine30f8672011-11-15 15:04:07 -08001698 local_irq_restore(flags);
1699}
1700
1701static int __init pch_console_setup(struct console *co, char *options)
1702{
1703 struct uart_port *port;
Darren Hart7ce92512012-03-09 09:51:51 -08001704 int baud = default_baud;
Alexander Steine30f8672011-11-15 15:04:07 -08001705 int bits = 8;
1706 int parity = 'n';
1707 int flow = 'n';
1708
1709 /*
1710 * Check whether an invalid uart number has been specified, and
1711 * if so, search for the first available port that does have
1712 * console support.
1713 */
1714 if (co->index >= PCH_UART_NR)
1715 co->index = 0;
1716 port = &pch_uart_ports[co->index]->port;
1717
1718 if (!port || (!port->iobase && !port->membase))
1719 return -ENODEV;
1720
Darren Hart077175f2012-03-09 09:51:49 -08001721 port->uartclk = pch_uart_get_uartclk();
Alexander Steine30f8672011-11-15 15:04:07 -08001722
1723 if (options)
1724 uart_parse_options(options, &baud, &parity, &bits, &flow);
1725
1726 return uart_set_options(port, co, baud, parity, bits, flow);
1727}
1728
1729static struct uart_driver pch_uart_driver;
1730
1731static struct console pch_console = {
1732 .name = PCH_UART_DRIVER_DEVICE,
1733 .write = pch_console_write,
1734 .device = uart_console_device,
1735 .setup = pch_console_setup,
1736 .flags = CON_PRINTBUFFER | CON_ANYTIME,
1737 .index = -1,
1738 .data = &pch_uart_driver,
1739};
1740
1741#define PCH_CONSOLE (&pch_console)
1742#else
1743#define PCH_CONSOLE NULL
Liang Lief44d282013-03-05 22:30:38 +08001744#endif /* CONFIG_SERIAL_PCH_UART_CONSOLE */
Alexander Steine30f8672011-11-15 15:04:07 -08001745
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001746static struct uart_driver pch_uart_driver = {
1747 .owner = THIS_MODULE,
1748 .driver_name = KBUILD_MODNAME,
1749 .dev_name = PCH_UART_DRIVER_DEVICE,
1750 .major = 0,
1751 .minor = 0,
1752 .nr = PCH_UART_NR,
Alexander Steine30f8672011-11-15 15:04:07 -08001753 .cons = PCH_CONSOLE,
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001754};
1755
1756static struct eg20t_port *pch_uart_init_port(struct pci_dev *pdev,
Tomoya MORINAGA4564e1e2011-01-28 18:00:01 +09001757 const struct pci_device_id *id)
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001758{
1759 struct eg20t_port *priv;
1760 int ret;
1761 unsigned int iobase;
1762 unsigned int mapbase;
Tomoya MORINAGA1c518992010-12-16 16:13:29 +09001763 unsigned char *rxbuf;
Darren Hart077175f2012-03-09 09:51:49 -08001764 int fifosize;
Tomoya MORINAGAfec38d12011-02-23 10:03:19 +09001765 int port_type;
1766 struct pch_uart_driver_data *board;
Jingoo Han6ec06562014-02-05 09:58:02 +09001767#ifdef CONFIG_DEBUG_FS
Feng Tangd0114112012-02-06 17:24:43 +08001768 char name[32]; /* for debugfs file name */
Jingoo Han6ec06562014-02-05 09:58:02 +09001769#endif
Tomoya MORINAGAfec38d12011-02-23 10:03:19 +09001770
1771 board = &drv_dat[id->driver_data];
1772 port_type = board->port_type;
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001773
1774 priv = kzalloc(sizeof(struct eg20t_port), GFP_KERNEL);
1775 if (priv == NULL)
1776 goto init_port_alloc_err;
1777
Tomoya MORINAGA1c518992010-12-16 16:13:29 +09001778 rxbuf = (unsigned char *)__get_free_page(GFP_KERNEL);
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001779 if (!rxbuf)
1780 goto init_port_free_txbuf;
1781
1782 switch (port_type) {
1783 case PORT_UNKNOWN:
Tomoya MORINAGA4564e1e2011-01-28 18:00:01 +09001784 fifosize = 256; /* EG20T/ML7213: UART0 */
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001785 break;
1786 case PORT_8250:
Tomoya MORINAGA4564e1e2011-01-28 18:00:01 +09001787 fifosize = 64; /* EG20T:UART1~3 ML7213: UART1~2*/
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001788 break;
1789 default:
1790 dev_err(&pdev->dev, "Invalid Port Type(=%d)\n", port_type);
1791 goto init_port_hal_free;
1792 }
1793
Alexander Steine4635952011-07-04 08:58:31 +02001794 pci_enable_msi(pdev);
Tomoya MORINAGA867c9022012-04-02 14:36:22 +09001795 pci_set_master(pdev);
Alexander Steine4635952011-07-04 08:58:31 +02001796
Darren Hartfe89def2012-06-19 14:00:18 -07001797 spin_lock_init(&priv->lock);
1798
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001799 iobase = pci_resource_start(pdev, 0);
1800 mapbase = pci_resource_start(pdev, 1);
1801 priv->mapbase = mapbase;
1802 priv->iobase = iobase;
1803 priv->pdev = pdev;
1804 priv->tx_empty = 1;
Tomoya MORINAGA1c518992010-12-16 16:13:29 +09001805 priv->rxbuf.buf = rxbuf;
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001806 priv->rxbuf.size = PAGE_SIZE;
1807
1808 priv->fifo_size = fifosize;
Darren Hart077175f2012-03-09 09:51:49 -08001809 priv->uartclk = pch_uart_get_uartclk();
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001810 priv->port_type = PORT_MAX_8250 + port_type + 1;
1811 priv->port.dev = &pdev->dev;
1812 priv->port.iobase = iobase;
1813 priv->port.membase = NULL;
1814 priv->port.mapbase = mapbase;
1815 priv->port.irq = pdev->irq;
1816 priv->port.iotype = UPIO_PORT;
1817 priv->port.ops = &pch_uart_ops;
1818 priv->port.flags = UPF_BOOT_AUTOCONF;
1819 priv->port.fifosize = fifosize;
Tomoya MORINAGAfec38d12011-02-23 10:03:19 +09001820 priv->port.line = board->line_no;
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001821 priv->trigger = PCH_UART_HAL_TRIGGER_M;
1822
Alexander Stein50d16ca2014-03-25 14:05:08 +01001823 snprintf(priv->irq_name, IRQ_NAME_SIZE,
1824 KBUILD_MODNAME ":" PCH_UART_DRIVER_DEVICE "%d",
1825 priv->port.line);
1826
Tomoya MORINAGA7e461322011-02-23 10:03:13 +09001827 spin_lock_init(&priv->port.lock);
1828
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001829 pci_set_drvdata(pdev, priv);
Feng Tang6f56d0f2012-02-06 17:24:45 +08001830 priv->trigger_level = 1;
1831 priv->fcr = 0;
Tomoya MORINAGA4564e1e2011-01-28 18:00:01 +09001832
Alexander Steine30f8672011-11-15 15:04:07 -08001833#ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1834 pch_uart_ports[board->line_no] = priv;
1835#endif
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001836 ret = uart_add_one_port(&pch_uart_driver, &priv->port);
1837 if (ret < 0)
1838 goto init_port_hal_free;
1839
Feng Tangd0114112012-02-06 17:24:43 +08001840#ifdef CONFIG_DEBUG_FS
1841 snprintf(name, sizeof(name), "uart%d_regs", board->line_no);
1842 priv->debugfs = debugfs_create_file(name, S_IFREG | S_IRUGO,
1843 NULL, priv, &port_regs_ops);
1844#endif
1845
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001846 return priv;
1847
1848init_port_hal_free:
Alexander Steine30f8672011-11-15 15:04:07 -08001849#ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1850 pch_uart_ports[board->line_no] = NULL;
1851#endif
Tomoya MORINAGA1c518992010-12-16 16:13:29 +09001852 free_page((unsigned long)rxbuf);
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001853init_port_free_txbuf:
1854 kfree(priv);
1855init_port_alloc_err:
1856
1857 return NULL;
1858}
1859
1860static void pch_uart_exit_port(struct eg20t_port *priv)
1861{
Feng Tangd0114112012-02-06 17:24:43 +08001862
1863#ifdef CONFIG_DEBUG_FS
1864 if (priv->debugfs)
1865 debugfs_remove(priv->debugfs);
1866#endif
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001867 uart_remove_one_port(&pch_uart_driver, &priv->port);
Tomoya MORINAGA1c518992010-12-16 16:13:29 +09001868 free_page((unsigned long)priv->rxbuf.buf);
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001869}
1870
1871static void pch_uart_pci_remove(struct pci_dev *pdev)
1872{
Feng Tang6f56d0f2012-02-06 17:24:45 +08001873 struct eg20t_port *priv = pci_get_drvdata(pdev);
Alexander Steine4635952011-07-04 08:58:31 +02001874
1875 pci_disable_msi(pdev);
Alexander Steine30f8672011-11-15 15:04:07 -08001876
1877#ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1878 pch_uart_ports[priv->port.line] = NULL;
1879#endif
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001880 pch_uart_exit_port(priv);
1881 pci_disable_device(pdev);
1882 kfree(priv);
1883 return;
1884}
1885#ifdef CONFIG_PM
1886static int pch_uart_pci_suspend(struct pci_dev *pdev, pm_message_t state)
1887{
1888 struct eg20t_port *priv = pci_get_drvdata(pdev);
1889
1890 uart_suspend_port(&pch_uart_driver, &priv->port);
1891
1892 pci_save_state(pdev);
1893 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1894 return 0;
1895}
1896
1897static int pch_uart_pci_resume(struct pci_dev *pdev)
1898{
1899 struct eg20t_port *priv = pci_get_drvdata(pdev);
1900 int ret;
1901
1902 pci_set_power_state(pdev, PCI_D0);
1903 pci_restore_state(pdev);
1904
1905 ret = pci_enable_device(pdev);
1906 if (ret) {
1907 dev_err(&pdev->dev,
1908 "%s-pci_enable_device failed(ret=%d) ", __func__, ret);
1909 return ret;
1910 }
1911
1912 uart_resume_port(&pch_uart_driver, &priv->port);
1913
1914 return 0;
1915}
1916#else
1917#define pch_uart_pci_suspend NULL
1918#define pch_uart_pci_resume NULL
1919#endif
1920
Jingoo Han311df742013-12-03 08:26:37 +09001921static const struct pci_device_id pch_uart_pci_id[] = {
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001922 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8811),
Tomoya MORINAGAfec38d12011-02-23 10:03:19 +09001923 .driver_data = pch_et20t_uart0},
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001924 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8812),
Tomoya MORINAGAfec38d12011-02-23 10:03:19 +09001925 .driver_data = pch_et20t_uart1},
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001926 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8813),
Tomoya MORINAGAfec38d12011-02-23 10:03:19 +09001927 .driver_data = pch_et20t_uart2},
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001928 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8814),
Tomoya MORINAGAfec38d12011-02-23 10:03:19 +09001929 .driver_data = pch_et20t_uart3},
Tomoya MORINAGA4564e1e2011-01-28 18:00:01 +09001930 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8027),
Tomoya MORINAGAfec38d12011-02-23 10:03:19 +09001931 .driver_data = pch_ml7213_uart0},
Tomoya MORINAGA4564e1e2011-01-28 18:00:01 +09001932 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8028),
Tomoya MORINAGAfec38d12011-02-23 10:03:19 +09001933 .driver_data = pch_ml7213_uart1},
Tomoya MORINAGA4564e1e2011-01-28 18:00:01 +09001934 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8029),
Tomoya MORINAGAfec38d12011-02-23 10:03:19 +09001935 .driver_data = pch_ml7213_uart2},
Tomoya MORINAGA177c2cb2011-05-09 17:25:20 +09001936 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800C),
1937 .driver_data = pch_ml7223_uart0},
1938 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800D),
1939 .driver_data = pch_ml7223_uart1},
Tomoya MORINAGA8249f742011-10-28 09:38:49 +09001940 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8811),
1941 .driver_data = pch_ml7831_uart0},
1942 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8812),
1943 .driver_data = pch_ml7831_uart1},
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001944 {0,},
1945};
1946
Bill Pemberton9671f092012-11-19 13:21:50 -05001947static int pch_uart_pci_probe(struct pci_dev *pdev,
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001948 const struct pci_device_id *id)
1949{
1950 int ret;
1951 struct eg20t_port *priv;
1952
1953 ret = pci_enable_device(pdev);
1954 if (ret < 0)
1955 goto probe_error;
1956
Tomoya MORINAGA4564e1e2011-01-28 18:00:01 +09001957 priv = pch_uart_init_port(pdev, id);
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001958 if (!priv) {
1959 ret = -EBUSY;
1960 goto probe_disable_device;
1961 }
1962 pci_set_drvdata(pdev, priv);
1963
1964 return ret;
1965
1966probe_disable_device:
Alexander Steine4635952011-07-04 08:58:31 +02001967 pci_disable_msi(pdev);
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001968 pci_disable_device(pdev);
1969probe_error:
1970 return ret;
1971}
1972
1973static struct pci_driver pch_uart_pci_driver = {
1974 .name = "pch_uart",
1975 .id_table = pch_uart_pci_id,
1976 .probe = pch_uart_pci_probe,
Bill Pemberton2d47b712012-11-19 13:21:34 -05001977 .remove = pch_uart_pci_remove,
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001978 .suspend = pch_uart_pci_suspend,
1979 .resume = pch_uart_pci_resume,
1980};
1981
1982static int __init pch_uart_module_init(void)
1983{
1984 int ret;
1985
1986 /* register as UART driver */
1987 ret = uart_register_driver(&pch_uart_driver);
1988 if (ret < 0)
1989 return ret;
1990
1991 /* register as PCI driver */
1992 ret = pci_register_driver(&pch_uart_pci_driver);
1993 if (ret < 0)
1994 uart_unregister_driver(&pch_uart_driver);
1995
1996 return ret;
1997}
1998module_init(pch_uart_module_init);
1999
2000static void __exit pch_uart_module_exit(void)
2001{
2002 pci_unregister_driver(&pch_uart_pci_driver);
2003 uart_unregister_driver(&pch_uart_driver);
2004}
2005module_exit(pch_uart_module_exit);
2006
2007MODULE_LICENSE("GPL v2");
2008MODULE_DESCRIPTION("Intel EG20T PCH UART PCI Driver");
Ben Hutchings52592da2013-09-01 19:26:37 +01002009MODULE_DEVICE_TABLE(pci, pch_uart_pci_id);
2010
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09002011module_param(default_baud, uint, S_IRUGO);
Darren Harta46f5532012-03-09 09:51:52 -08002012MODULE_PARM_DESC(default_baud,
2013 "Default BAUD for initial driver state and console (default 9600)");
Darren Hart2a44feb2012-03-09 09:51:50 -08002014module_param(user_uartclk, uint, S_IRUGO);
Darren Harta46f5532012-03-09 09:51:52 -08002015MODULE_PARM_DESC(user_uartclk,
2016 "Override UART default or board specific UART clock");