Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * PCI Express PCI Hot Plug Driver |
| 3 | * |
| 4 | * Copyright (C) 1995,2001 Compaq Computer Corporation |
| 5 | * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com) |
| 6 | * Copyright (C) 2001 IBM Corp. |
| 7 | * Copyright (C) 2003-2004 Intel Corporation |
| 8 | * |
| 9 | * All rights reserved. |
| 10 | * |
| 11 | * This program is free software; you can redistribute it and/or modify |
| 12 | * it under the terms of the GNU General Public License as published by |
| 13 | * the Free Software Foundation; either version 2 of the License, or (at |
| 14 | * your option) any later version. |
| 15 | * |
| 16 | * This program is distributed in the hope that it will be useful, but |
| 17 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
| 18 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or |
| 19 | * NON INFRINGEMENT. See the GNU General Public License for more |
| 20 | * details. |
| 21 | * |
| 22 | * You should have received a copy of the GNU General Public License |
| 23 | * along with this program; if not, write to the Free Software |
| 24 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
| 25 | * |
Kristen Accardi | 8cf4c19 | 2005-08-16 15:16:10 -0700 | [diff] [blame] | 26 | * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 27 | * |
| 28 | */ |
| 29 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 30 | #include <linux/kernel.h> |
| 31 | #include <linux/module.h> |
| 32 | #include <linux/types.h> |
Tim Schmielau | de25968 | 2006-01-08 01:02:05 -0800 | [diff] [blame] | 33 | #include <linux/signal.h> |
| 34 | #include <linux/jiffies.h> |
| 35 | #include <linux/timer.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 36 | #include <linux/pci.h> |
Andrew Morton | 5d1b8c9 | 2005-11-13 16:06:39 -0800 | [diff] [blame] | 37 | #include <linux/interrupt.h> |
Kristen Carlson Accardi | 34d0341 | 2007-01-09 13:02:36 -0800 | [diff] [blame] | 38 | #include <linux/time.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 39 | #include <linux/slab.h> |
Andrew Morton | 5d1b8c9 | 2005-11-13 16:06:39 -0800 | [diff] [blame] | 40 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 41 | #include "../pci.h" |
| 42 | #include "pciehp.h" |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 43 | |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 44 | static inline int pciehp_readw(struct controller *ctrl, int reg, u16 *value) |
| 45 | { |
Kenji Kaneshige | 385e249 | 2009-09-15 17:30:14 +0900 | [diff] [blame] | 46 | struct pci_dev *dev = ctrl->pcie->port; |
Jiang Liu | 537a77e | 2012-07-24 17:20:09 +0800 | [diff] [blame] | 47 | return pcie_capability_read_word(dev, reg, value); |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 48 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 49 | |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 50 | static inline int pciehp_readl(struct controller *ctrl, int reg, u32 *value) |
| 51 | { |
Kenji Kaneshige | 385e249 | 2009-09-15 17:30:14 +0900 | [diff] [blame] | 52 | struct pci_dev *dev = ctrl->pcie->port; |
Jiang Liu | 537a77e | 2012-07-24 17:20:09 +0800 | [diff] [blame] | 53 | return pcie_capability_read_dword(dev, reg, value); |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 54 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 55 | |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 56 | static inline int pciehp_writew(struct controller *ctrl, int reg, u16 value) |
| 57 | { |
Kenji Kaneshige | 385e249 | 2009-09-15 17:30:14 +0900 | [diff] [blame] | 58 | struct pci_dev *dev = ctrl->pcie->port; |
Jiang Liu | 537a77e | 2012-07-24 17:20:09 +0800 | [diff] [blame] | 59 | return pcie_capability_write_word(dev, reg, value); |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 60 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 61 | |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 62 | static inline int pciehp_writel(struct controller *ctrl, int reg, u32 value) |
| 63 | { |
Kenji Kaneshige | 385e249 | 2009-09-15 17:30:14 +0900 | [diff] [blame] | 64 | struct pci_dev *dev = ctrl->pcie->port; |
Jiang Liu | 537a77e | 2012-07-24 17:20:09 +0800 | [diff] [blame] | 65 | return pcie_capability_write_dword(dev, reg, value); |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 66 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 67 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 68 | /* Power Control Command */ |
| 69 | #define POWER_ON 0 |
Kenji Kaneshige | 322162a | 2008-12-19 15:19:02 +0900 | [diff] [blame] | 70 | #define POWER_OFF PCI_EXP_SLTCTL_PCC |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 71 | |
Kenji Kaneshige | 48fe391 | 2006-12-21 17:01:04 -0800 | [diff] [blame] | 72 | static irqreturn_t pcie_isr(int irq, void *dev_id); |
| 73 | static void start_int_poll_timer(struct controller *ctrl, int sec); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 74 | |
| 75 | /* This is the interrupt polling timeout function. */ |
Kenji Kaneshige | 48fe391 | 2006-12-21 17:01:04 -0800 | [diff] [blame] | 76 | static void int_poll_timeout(unsigned long data) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 77 | { |
Kenji Kaneshige | 48fe391 | 2006-12-21 17:01:04 -0800 | [diff] [blame] | 78 | struct controller *ctrl = (struct controller *)data; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 79 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 80 | /* Poll for interrupt events. regs == NULL => polling */ |
Kenji Kaneshige | 48fe391 | 2006-12-21 17:01:04 -0800 | [diff] [blame] | 81 | pcie_isr(0, ctrl); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 82 | |
Kenji Kaneshige | 48fe391 | 2006-12-21 17:01:04 -0800 | [diff] [blame] | 83 | init_timer(&ctrl->poll_timer); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 84 | if (!pciehp_poll_time) |
Kenji Kaneshige | 40730d1 | 2007-08-09 16:09:38 -0700 | [diff] [blame] | 85 | pciehp_poll_time = 2; /* default polling interval is 2 sec */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 86 | |
Kenji Kaneshige | 48fe391 | 2006-12-21 17:01:04 -0800 | [diff] [blame] | 87 | start_int_poll_timer(ctrl, pciehp_poll_time); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 88 | } |
| 89 | |
| 90 | /* This function starts the interrupt polling timer. */ |
Kenji Kaneshige | 48fe391 | 2006-12-21 17:01:04 -0800 | [diff] [blame] | 91 | static void start_int_poll_timer(struct controller *ctrl, int sec) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 92 | { |
Kenji Kaneshige | 48fe391 | 2006-12-21 17:01:04 -0800 | [diff] [blame] | 93 | /* Clamp to sane value */ |
| 94 | if ((sec <= 0) || (sec > 60)) |
| 95 | sec = 2; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 96 | |
Kenji Kaneshige | 48fe391 | 2006-12-21 17:01:04 -0800 | [diff] [blame] | 97 | ctrl->poll_timer.function = &int_poll_timeout; |
| 98 | ctrl->poll_timer.data = (unsigned long)ctrl; |
| 99 | ctrl->poll_timer.expires = jiffies + sec * HZ; |
| 100 | add_timer(&ctrl->poll_timer); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 101 | } |
| 102 | |
Kenji Kaneshige | 2aeeef1 | 2008-04-25 14:39:08 -0700 | [diff] [blame] | 103 | static inline int pciehp_request_irq(struct controller *ctrl) |
| 104 | { |
Kenji Kaneshige | f7a10e3 | 2008-08-22 17:16:48 +0900 | [diff] [blame] | 105 | int retval, irq = ctrl->pcie->irq; |
Kenji Kaneshige | 2aeeef1 | 2008-04-25 14:39:08 -0700 | [diff] [blame] | 106 | |
| 107 | /* Install interrupt polling timer. Start with 10 sec delay */ |
| 108 | if (pciehp_poll_mode) { |
| 109 | init_timer(&ctrl->poll_timer); |
| 110 | start_int_poll_timer(ctrl, 10); |
| 111 | return 0; |
| 112 | } |
| 113 | |
| 114 | /* Installs the interrupt handler */ |
| 115 | retval = request_irq(irq, pcie_isr, IRQF_SHARED, MY_NAME, ctrl); |
| 116 | if (retval) |
Taku Izumi | 7f2feec | 2008-09-05 12:11:26 +0900 | [diff] [blame] | 117 | ctrl_err(ctrl, "Cannot get irq %d for the hotplug controller\n", |
| 118 | irq); |
Kenji Kaneshige | 2aeeef1 | 2008-04-25 14:39:08 -0700 | [diff] [blame] | 119 | return retval; |
| 120 | } |
| 121 | |
| 122 | static inline void pciehp_free_irq(struct controller *ctrl) |
| 123 | { |
| 124 | if (pciehp_poll_mode) |
| 125 | del_timer_sync(&ctrl->poll_timer); |
| 126 | else |
Kenji Kaneshige | f7a10e3 | 2008-08-22 17:16:48 +0900 | [diff] [blame] | 127 | free_irq(ctrl->pcie->irq, ctrl); |
Kenji Kaneshige | 2aeeef1 | 2008-04-25 14:39:08 -0700 | [diff] [blame] | 128 | } |
| 129 | |
Kenji Kaneshige | 563f119 | 2008-06-20 12:05:52 +0900 | [diff] [blame] | 130 | static int pcie_poll_cmd(struct controller *ctrl) |
Kenji Kaneshige | 6592e02 | 2008-05-27 19:05:26 +0900 | [diff] [blame] | 131 | { |
| 132 | u16 slot_status; |
Kenji Kaneshige | 322162a | 2008-12-19 15:19:02 +0900 | [diff] [blame] | 133 | int err, timeout = 1000; |
Kenji Kaneshige | 6592e02 | 2008-05-27 19:05:26 +0900 | [diff] [blame] | 134 | |
Kenji Kaneshige | 322162a | 2008-12-19 15:19:02 +0900 | [diff] [blame] | 135 | err = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); |
| 136 | if (!err && (slot_status & PCI_EXP_SLTSTA_CC)) { |
| 137 | pciehp_writew(ctrl, PCI_EXP_SLTSTA, PCI_EXP_SLTSTA_CC); |
| 138 | return 1; |
Kenji Kaneshige | 820943b | 2008-06-20 12:04:33 +0900 | [diff] [blame] | 139 | } |
Adrian Bunk | a5827f4 | 2008-08-28 01:05:26 +0300 | [diff] [blame] | 140 | while (timeout > 0) { |
Kenji Kaneshige | 66618ba | 2008-06-20 12:05:12 +0900 | [diff] [blame] | 141 | msleep(10); |
| 142 | timeout -= 10; |
Kenji Kaneshige | 322162a | 2008-12-19 15:19:02 +0900 | [diff] [blame] | 143 | err = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); |
| 144 | if (!err && (slot_status & PCI_EXP_SLTSTA_CC)) { |
| 145 | pciehp_writew(ctrl, PCI_EXP_SLTSTA, PCI_EXP_SLTSTA_CC); |
| 146 | return 1; |
Kenji Kaneshige | 820943b | 2008-06-20 12:04:33 +0900 | [diff] [blame] | 147 | } |
Kenji Kaneshige | 6592e02 | 2008-05-27 19:05:26 +0900 | [diff] [blame] | 148 | } |
| 149 | return 0; /* timeout */ |
Kenji Kaneshige | 6592e02 | 2008-05-27 19:05:26 +0900 | [diff] [blame] | 150 | } |
| 151 | |
Kenji Kaneshige | 563f119 | 2008-06-20 12:05:52 +0900 | [diff] [blame] | 152 | static void pcie_wait_cmd(struct controller *ctrl, int poll) |
Kenji Kaneshige | 44ef4ce | 2006-12-21 17:01:09 -0800 | [diff] [blame] | 153 | { |
Kenji Kaneshige | 262303fe | 2006-12-21 17:01:10 -0800 | [diff] [blame] | 154 | unsigned int msecs = pciehp_poll_mode ? 2500 : 1000; |
| 155 | unsigned long timeout = msecs_to_jiffies(msecs); |
| 156 | int rc; |
Kenji Kaneshige | 44ef4ce | 2006-12-21 17:01:09 -0800 | [diff] [blame] | 157 | |
Kenji Kaneshige | 6592e02 | 2008-05-27 19:05:26 +0900 | [diff] [blame] | 158 | if (poll) |
| 159 | rc = pcie_poll_cmd(ctrl); |
| 160 | else |
Kenji Kaneshige | d737bdc | 2008-05-28 14:59:44 +0900 | [diff] [blame] | 161 | rc = wait_event_timeout(ctrl->queue, !ctrl->cmd_busy, timeout); |
Kenji Kaneshige | 262303fe | 2006-12-21 17:01:10 -0800 | [diff] [blame] | 162 | if (!rc) |
Taku Izumi | 7f2feec | 2008-09-05 12:11:26 +0900 | [diff] [blame] | 163 | ctrl_dbg(ctrl, "Command not completed in 1000 msec\n"); |
Kenji Kaneshige | 44ef4ce | 2006-12-21 17:01:09 -0800 | [diff] [blame] | 164 | } |
| 165 | |
Kenji Kaneshige | f477836 | 2007-05-31 09:43:34 -0700 | [diff] [blame] | 166 | /** |
| 167 | * pcie_write_cmd - Issue controller command |
Kenji Kaneshige | c27fb883 | 2008-04-25 14:39:05 -0700 | [diff] [blame] | 168 | * @ctrl: controller to which the command is issued |
Kenji Kaneshige | f477836 | 2007-05-31 09:43:34 -0700 | [diff] [blame] | 169 | * @cmd: command value written to slot control register |
| 170 | * @mask: bitmask of slot control register to be modified |
| 171 | */ |
Kenji Kaneshige | c27fb883 | 2008-04-25 14:39:05 -0700 | [diff] [blame] | 172 | static int pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 173 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 174 | int retval = 0; |
| 175 | u16 slot_status; |
Kenji Kaneshige | f477836 | 2007-05-31 09:43:34 -0700 | [diff] [blame] | 176 | u16 slot_ctrl; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 177 | |
Kenji Kaneshige | 44ef4ce | 2006-12-21 17:01:09 -0800 | [diff] [blame] | 178 | mutex_lock(&ctrl->ctrl_lock); |
| 179 | |
Kenji Kaneshige | 322162a | 2008-12-19 15:19:02 +0900 | [diff] [blame] | 180 | retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 181 | if (retval) { |
Taku Izumi | 7f2feec | 2008-09-05 12:11:26 +0900 | [diff] [blame] | 182 | ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n", |
| 183 | __func__); |
Kenji Kaneshige | 44ef4ce | 2006-12-21 17:01:09 -0800 | [diff] [blame] | 184 | goto out; |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 185 | } |
| 186 | |
Kenji Kaneshige | 322162a | 2008-12-19 15:19:02 +0900 | [diff] [blame] | 187 | if (slot_status & PCI_EXP_SLTSTA_CC) { |
Kenji Kaneshige | 5808639 | 2008-05-27 19:04:30 +0900 | [diff] [blame] | 188 | if (!ctrl->no_cmd_complete) { |
| 189 | /* |
| 190 | * After 1 sec and CMD_COMPLETED still not set, just |
| 191 | * proceed forward to issue the next command according |
| 192 | * to spec. Just print out the error message. |
| 193 | */ |
Taku Izumi | 18b341b | 2008-10-23 11:47:32 +0900 | [diff] [blame] | 194 | ctrl_dbg(ctrl, "CMD_COMPLETED not clear after 1 sec\n"); |
Kenji Kaneshige | 5808639 | 2008-05-27 19:04:30 +0900 | [diff] [blame] | 195 | } else if (!NO_CMD_CMPL(ctrl)) { |
| 196 | /* |
| 197 | * This controller semms to notify of command completed |
| 198 | * event even though it supports none of power |
| 199 | * controller, attention led, power led and EMI. |
| 200 | */ |
Taku Izumi | 18b341b | 2008-10-23 11:47:32 +0900 | [diff] [blame] | 201 | ctrl_dbg(ctrl, "Unexpected CMD_COMPLETED. Need to " |
| 202 | "wait for command completed event.\n"); |
Kenji Kaneshige | 5808639 | 2008-05-27 19:04:30 +0900 | [diff] [blame] | 203 | ctrl->no_cmd_complete = 0; |
| 204 | } else { |
Taku Izumi | 18b341b | 2008-10-23 11:47:32 +0900 | [diff] [blame] | 205 | ctrl_dbg(ctrl, "Unexpected CMD_COMPLETED. Maybe " |
| 206 | "the controller is broken.\n"); |
Kenji Kaneshige | 5808639 | 2008-05-27 19:04:30 +0900 | [diff] [blame] | 207 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 208 | } |
| 209 | |
Kenji Kaneshige | 322162a | 2008-12-19 15:19:02 +0900 | [diff] [blame] | 210 | retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 211 | if (retval) { |
Taku Izumi | 7f2feec | 2008-09-05 12:11:26 +0900 | [diff] [blame] | 212 | ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__); |
Kenji Kaneshige | c6b069e | 2008-04-25 14:38:57 -0700 | [diff] [blame] | 213 | goto out; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 214 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 215 | |
Kenji Kaneshige | f477836 | 2007-05-31 09:43:34 -0700 | [diff] [blame] | 216 | slot_ctrl &= ~mask; |
Kenji Kaneshige | b7aa1f1 | 2008-04-25 14:39:14 -0700 | [diff] [blame] | 217 | slot_ctrl |= (cmd & mask); |
Kenji Kaneshige | f477836 | 2007-05-31 09:43:34 -0700 | [diff] [blame] | 218 | ctrl->cmd_busy = 1; |
Kenji Kaneshige | 2d32a9a | 2008-04-25 14:39:02 -0700 | [diff] [blame] | 219 | smp_mb(); |
Kenji Kaneshige | 322162a | 2008-12-19 15:19:02 +0900 | [diff] [blame] | 220 | retval = pciehp_writew(ctrl, PCI_EXP_SLTCTL, slot_ctrl); |
Kenji Kaneshige | f477836 | 2007-05-31 09:43:34 -0700 | [diff] [blame] | 221 | if (retval) |
Taku Izumi | 18b341b | 2008-10-23 11:47:32 +0900 | [diff] [blame] | 222 | ctrl_err(ctrl, "Cannot write to SLOTCTRL register\n"); |
Kenji Kaneshige | f477836 | 2007-05-31 09:43:34 -0700 | [diff] [blame] | 223 | |
Kenji Kaneshige | 44ef4ce | 2006-12-21 17:01:09 -0800 | [diff] [blame] | 224 | /* |
| 225 | * Wait for command completion. |
| 226 | */ |
Kenji Kaneshige | 6592e02 | 2008-05-27 19:05:26 +0900 | [diff] [blame] | 227 | if (!retval && !ctrl->no_cmd_complete) { |
| 228 | int poll = 0; |
| 229 | /* |
| 230 | * if hotplug interrupt is not enabled or command |
| 231 | * completed interrupt is not enabled, we need to poll |
| 232 | * command completed event. |
| 233 | */ |
Kenji Kaneshige | 322162a | 2008-12-19 15:19:02 +0900 | [diff] [blame] | 234 | if (!(slot_ctrl & PCI_EXP_SLTCTL_HPIE) || |
| 235 | !(slot_ctrl & PCI_EXP_SLTCTL_CCIE)) |
Kenji Kaneshige | 6592e02 | 2008-05-27 19:05:26 +0900 | [diff] [blame] | 236 | poll = 1; |
Kenji Kaneshige | d737bdc | 2008-05-28 14:59:44 +0900 | [diff] [blame] | 237 | pcie_wait_cmd(ctrl, poll); |
Kenji Kaneshige | 6592e02 | 2008-05-27 19:05:26 +0900 | [diff] [blame] | 238 | } |
Kenji Kaneshige | 44ef4ce | 2006-12-21 17:01:09 -0800 | [diff] [blame] | 239 | out: |
| 240 | mutex_unlock(&ctrl->ctrl_lock); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 241 | return retval; |
| 242 | } |
| 243 | |
Yinghai Lu | 4e2ce40 | 2012-01-27 10:55:12 -0800 | [diff] [blame] | 244 | static bool check_link_active(struct controller *ctrl) |
Kenji Kaneshige | f18e962 | 2008-10-22 14:31:44 +0900 | [diff] [blame] | 245 | { |
Yinghai Lu | 4e2ce40 | 2012-01-27 10:55:12 -0800 | [diff] [blame] | 246 | bool ret = false; |
| 247 | u16 lnk_status; |
Kenji Kaneshige | f18e962 | 2008-10-22 14:31:44 +0900 | [diff] [blame] | 248 | |
Yinghai Lu | 4e2ce40 | 2012-01-27 10:55:12 -0800 | [diff] [blame] | 249 | if (pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status)) |
| 250 | return ret; |
| 251 | |
| 252 | ret = !!(lnk_status & PCI_EXP_LNKSTA_DLLLA); |
| 253 | |
| 254 | if (ret) |
| 255 | ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status); |
| 256 | |
| 257 | return ret; |
Kenji Kaneshige | f18e962 | 2008-10-22 14:31:44 +0900 | [diff] [blame] | 258 | } |
| 259 | |
Yinghai Lu | bffe4f7 | 2012-01-27 10:55:13 -0800 | [diff] [blame] | 260 | static void __pcie_wait_link_active(struct controller *ctrl, bool active) |
Kenji Kaneshige | f18e962 | 2008-10-22 14:31:44 +0900 | [diff] [blame] | 261 | { |
| 262 | int timeout = 1000; |
| 263 | |
Yinghai Lu | bffe4f7 | 2012-01-27 10:55:13 -0800 | [diff] [blame] | 264 | if (check_link_active(ctrl) == active) |
Kenji Kaneshige | f18e962 | 2008-10-22 14:31:44 +0900 | [diff] [blame] | 265 | return; |
| 266 | while (timeout > 0) { |
| 267 | msleep(10); |
| 268 | timeout -= 10; |
Yinghai Lu | bffe4f7 | 2012-01-27 10:55:13 -0800 | [diff] [blame] | 269 | if (check_link_active(ctrl) == active) |
Kenji Kaneshige | f18e962 | 2008-10-22 14:31:44 +0900 | [diff] [blame] | 270 | return; |
| 271 | } |
Yinghai Lu | bffe4f7 | 2012-01-27 10:55:13 -0800 | [diff] [blame] | 272 | ctrl_dbg(ctrl, "Data Link Layer Link Active not %s in 1000 msec\n", |
| 273 | active ? "set" : "cleared"); |
| 274 | } |
| 275 | |
| 276 | static void pcie_wait_link_active(struct controller *ctrl) |
| 277 | { |
| 278 | __pcie_wait_link_active(ctrl, true); |
| 279 | } |
| 280 | |
| 281 | static void pcie_wait_link_not_active(struct controller *ctrl) |
| 282 | { |
| 283 | __pcie_wait_link_active(ctrl, false); |
Kenji Kaneshige | f18e962 | 2008-10-22 14:31:44 +0900 | [diff] [blame] | 284 | } |
| 285 | |
Yinghai Lu | 2f5d8e4 | 2012-01-27 10:55:11 -0800 | [diff] [blame] | 286 | static bool pci_bus_check_dev(struct pci_bus *bus, int devfn) |
| 287 | { |
| 288 | u32 l; |
| 289 | int count = 0; |
| 290 | int delay = 1000, step = 20; |
| 291 | bool found = false; |
| 292 | |
| 293 | do { |
| 294 | found = pci_bus_read_dev_vendor_id(bus, devfn, &l, 0); |
| 295 | count++; |
| 296 | |
| 297 | if (found) |
| 298 | break; |
| 299 | |
| 300 | msleep(step); |
| 301 | delay -= step; |
| 302 | } while (delay > 0); |
| 303 | |
| 304 | if (count > 1 && pciehp_debug) |
| 305 | printk(KERN_DEBUG "pci %04x:%02x:%02x.%d id reading try %d times with interval %d ms to get %08x\n", |
| 306 | pci_domain_nr(bus), bus->number, PCI_SLOT(devfn), |
| 307 | PCI_FUNC(devfn), count, step, l); |
| 308 | |
| 309 | return found; |
| 310 | } |
| 311 | |
Kenji Kaneshige | 82a9e79 | 2009-09-15 17:30:48 +0900 | [diff] [blame] | 312 | int pciehp_check_link_status(struct controller *ctrl) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 313 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 314 | u16 lnk_status; |
| 315 | int retval = 0; |
Yinghai Lu | 2f5d8e4 | 2012-01-27 10:55:11 -0800 | [diff] [blame] | 316 | bool found = false; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 317 | |
Kenji Kaneshige | f18e962 | 2008-10-22 14:31:44 +0900 | [diff] [blame] | 318 | /* |
| 319 | * Data Link Layer Link Active Reporting must be capable for |
| 320 | * hot-plug capable downstream port. But old controller might |
| 321 | * not implement it. In this case, we wait for 1000 ms. |
| 322 | */ |
Kenji Kaneshige | 0cab084 | 2011-07-11 10:15:45 +0900 | [diff] [blame] | 323 | if (ctrl->link_active_reporting) |
Kenji Kaneshige | f18e962 | 2008-10-22 14:31:44 +0900 | [diff] [blame] | 324 | pcie_wait_link_active(ctrl); |
Kenji Kaneshige | 0cab084 | 2011-07-11 10:15:45 +0900 | [diff] [blame] | 325 | else |
Kenji Kaneshige | f18e962 | 2008-10-22 14:31:44 +0900 | [diff] [blame] | 326 | msleep(1000); |
| 327 | |
Yinghai Lu | 2f5d8e4 | 2012-01-27 10:55:11 -0800 | [diff] [blame] | 328 | /* wait 100ms before read pci conf, and try in 1s */ |
| 329 | msleep(100); |
| 330 | found = pci_bus_check_dev(ctrl->pcie->port->subordinate, |
| 331 | PCI_DEVFN(0, 0)); |
Kenji Kaneshige | 0027cb3 | 2011-11-10 16:40:37 +0900 | [diff] [blame] | 332 | |
Kenji Kaneshige | 322162a | 2008-12-19 15:19:02 +0900 | [diff] [blame] | 333 | retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 334 | if (retval) { |
Taku Izumi | 18b341b | 2008-10-23 11:47:32 +0900 | [diff] [blame] | 335 | ctrl_err(ctrl, "Cannot read LNKSTATUS register\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 336 | return retval; |
| 337 | } |
| 338 | |
Taku Izumi | 7f2feec | 2008-09-05 12:11:26 +0900 | [diff] [blame] | 339 | ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status); |
Kenji Kaneshige | 322162a | 2008-12-19 15:19:02 +0900 | [diff] [blame] | 340 | if ((lnk_status & PCI_EXP_LNKSTA_LT) || |
| 341 | !(lnk_status & PCI_EXP_LNKSTA_NLW)) { |
Taku Izumi | 18b341b | 2008-10-23 11:47:32 +0900 | [diff] [blame] | 342 | ctrl_err(ctrl, "Link Training Error occurs \n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 343 | retval = -1; |
| 344 | return retval; |
| 345 | } |
| 346 | |
Yinghai Lu | fdbd3ce | 2011-11-07 07:53:23 -0800 | [diff] [blame] | 347 | pcie_update_link_speed(ctrl->pcie->port->subordinate, lnk_status); |
| 348 | |
Yinghai Lu | 2f5d8e4 | 2012-01-27 10:55:11 -0800 | [diff] [blame] | 349 | if (!found && !retval) |
| 350 | retval = -1; |
| 351 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 352 | return retval; |
| 353 | } |
| 354 | |
Yinghai Lu | 7f82299 | 2012-01-27 10:55:14 -0800 | [diff] [blame] | 355 | static int __pciehp_link_set(struct controller *ctrl, bool enable) |
| 356 | { |
| 357 | u16 lnk_ctrl; |
| 358 | int retval = 0; |
| 359 | |
| 360 | retval = pciehp_readw(ctrl, PCI_EXP_LNKCTL, &lnk_ctrl); |
| 361 | if (retval) { |
| 362 | ctrl_err(ctrl, "Cannot read LNKCTRL register\n"); |
| 363 | return retval; |
| 364 | } |
| 365 | |
| 366 | if (enable) |
| 367 | lnk_ctrl &= ~PCI_EXP_LNKCTL_LD; |
| 368 | else |
| 369 | lnk_ctrl |= PCI_EXP_LNKCTL_LD; |
| 370 | |
| 371 | retval = pciehp_writew(ctrl, PCI_EXP_LNKCTL, lnk_ctrl); |
| 372 | if (retval) { |
| 373 | ctrl_err(ctrl, "Cannot write LNKCTRL register\n"); |
| 374 | return retval; |
| 375 | } |
| 376 | ctrl_dbg(ctrl, "%s: lnk_ctrl = %x\n", __func__, lnk_ctrl); |
| 377 | |
| 378 | return retval; |
| 379 | } |
| 380 | |
| 381 | static int pciehp_link_enable(struct controller *ctrl) |
| 382 | { |
| 383 | return __pciehp_link_set(ctrl, true); |
| 384 | } |
| 385 | |
| 386 | static int pciehp_link_disable(struct controller *ctrl) |
| 387 | { |
| 388 | return __pciehp_link_set(ctrl, false); |
| 389 | } |
| 390 | |
Kenji Kaneshige | 82a9e79 | 2009-09-15 17:30:48 +0900 | [diff] [blame] | 391 | int pciehp_get_attention_status(struct slot *slot, u8 *status) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 392 | { |
Kenji Kaneshige | 48fe391 | 2006-12-21 17:01:04 -0800 | [diff] [blame] | 393 | struct controller *ctrl = slot->ctrl; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 394 | u16 slot_ctrl; |
| 395 | u8 atten_led_state; |
| 396 | int retval = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 397 | |
Kenji Kaneshige | 322162a | 2008-12-19 15:19:02 +0900 | [diff] [blame] | 398 | retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 399 | if (retval) { |
Taku Izumi | 7f2feec | 2008-09-05 12:11:26 +0900 | [diff] [blame] | 400 | ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 401 | return retval; |
| 402 | } |
| 403 | |
Kenji Kaneshige | 1518c17 | 2009-11-11 14:34:52 +0900 | [diff] [blame] | 404 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x, value read %x\n", __func__, |
| 405 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 406 | |
Kenji Kaneshige | 322162a | 2008-12-19 15:19:02 +0900 | [diff] [blame] | 407 | atten_led_state = (slot_ctrl & PCI_EXP_SLTCTL_AIC) >> 6; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 408 | |
| 409 | switch (atten_led_state) { |
| 410 | case 0: |
| 411 | *status = 0xFF; /* Reserved */ |
| 412 | break; |
| 413 | case 1: |
| 414 | *status = 1; /* On */ |
| 415 | break; |
| 416 | case 2: |
| 417 | *status = 2; /* Blink */ |
| 418 | break; |
| 419 | case 3: |
| 420 | *status = 0; /* Off */ |
| 421 | break; |
| 422 | default: |
| 423 | *status = 0xFF; |
| 424 | break; |
| 425 | } |
| 426 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 427 | return 0; |
| 428 | } |
| 429 | |
Kenji Kaneshige | 82a9e79 | 2009-09-15 17:30:48 +0900 | [diff] [blame] | 430 | int pciehp_get_power_status(struct slot *slot, u8 *status) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 431 | { |
Kenji Kaneshige | 48fe391 | 2006-12-21 17:01:04 -0800 | [diff] [blame] | 432 | struct controller *ctrl = slot->ctrl; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 433 | u16 slot_ctrl; |
| 434 | u8 pwr_state; |
| 435 | int retval = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 436 | |
Kenji Kaneshige | 322162a | 2008-12-19 15:19:02 +0900 | [diff] [blame] | 437 | retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 438 | if (retval) { |
Taku Izumi | 7f2feec | 2008-09-05 12:11:26 +0900 | [diff] [blame] | 439 | ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 440 | return retval; |
| 441 | } |
Kenji Kaneshige | 1518c17 | 2009-11-11 14:34:52 +0900 | [diff] [blame] | 442 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x value read %x\n", __func__, |
| 443 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 444 | |
Kenji Kaneshige | 322162a | 2008-12-19 15:19:02 +0900 | [diff] [blame] | 445 | pwr_state = (slot_ctrl & PCI_EXP_SLTCTL_PCC) >> 10; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 446 | |
| 447 | switch (pwr_state) { |
| 448 | case 0: |
| 449 | *status = 1; |
| 450 | break; |
| 451 | case 1: |
Kenji Kaneshige | 71ad556 | 2007-08-09 16:09:34 -0700 | [diff] [blame] | 452 | *status = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 453 | break; |
| 454 | default: |
| 455 | *status = 0xFF; |
| 456 | break; |
| 457 | } |
| 458 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 459 | return retval; |
| 460 | } |
| 461 | |
Kenji Kaneshige | 82a9e79 | 2009-09-15 17:30:48 +0900 | [diff] [blame] | 462 | int pciehp_get_latch_status(struct slot *slot, u8 *status) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 463 | { |
Kenji Kaneshige | 48fe391 | 2006-12-21 17:01:04 -0800 | [diff] [blame] | 464 | struct controller *ctrl = slot->ctrl; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 465 | u16 slot_status; |
Kenji Kaneshige | 322162a | 2008-12-19 15:19:02 +0900 | [diff] [blame] | 466 | int retval; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 467 | |
Kenji Kaneshige | 322162a | 2008-12-19 15:19:02 +0900 | [diff] [blame] | 468 | retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 469 | if (retval) { |
Taku Izumi | 7f2feec | 2008-09-05 12:11:26 +0900 | [diff] [blame] | 470 | ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n", |
| 471 | __func__); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 472 | return retval; |
| 473 | } |
Kenji Kaneshige | 322162a | 2008-12-19 15:19:02 +0900 | [diff] [blame] | 474 | *status = !!(slot_status & PCI_EXP_SLTSTA_MRLSS); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 475 | return 0; |
| 476 | } |
| 477 | |
Kenji Kaneshige | 82a9e79 | 2009-09-15 17:30:48 +0900 | [diff] [blame] | 478 | int pciehp_get_adapter_status(struct slot *slot, u8 *status) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 479 | { |
Kenji Kaneshige | 48fe391 | 2006-12-21 17:01:04 -0800 | [diff] [blame] | 480 | struct controller *ctrl = slot->ctrl; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 481 | u16 slot_status; |
Kenji Kaneshige | 322162a | 2008-12-19 15:19:02 +0900 | [diff] [blame] | 482 | int retval; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 483 | |
Kenji Kaneshige | 322162a | 2008-12-19 15:19:02 +0900 | [diff] [blame] | 484 | retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 485 | if (retval) { |
Taku Izumi | 7f2feec | 2008-09-05 12:11:26 +0900 | [diff] [blame] | 486 | ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n", |
| 487 | __func__); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 488 | return retval; |
| 489 | } |
Kenji Kaneshige | 322162a | 2008-12-19 15:19:02 +0900 | [diff] [blame] | 490 | *status = !!(slot_status & PCI_EXP_SLTSTA_PDS); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 491 | return 0; |
| 492 | } |
| 493 | |
Kenji Kaneshige | 82a9e79 | 2009-09-15 17:30:48 +0900 | [diff] [blame] | 494 | int pciehp_query_power_fault(struct slot *slot) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 495 | { |
Kenji Kaneshige | 48fe391 | 2006-12-21 17:01:04 -0800 | [diff] [blame] | 496 | struct controller *ctrl = slot->ctrl; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 497 | u16 slot_status; |
Kenji Kaneshige | 322162a | 2008-12-19 15:19:02 +0900 | [diff] [blame] | 498 | int retval; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 499 | |
Kenji Kaneshige | 322162a | 2008-12-19 15:19:02 +0900 | [diff] [blame] | 500 | retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 501 | if (retval) { |
Taku Izumi | 18b341b | 2008-10-23 11:47:32 +0900 | [diff] [blame] | 502 | ctrl_err(ctrl, "Cannot check for power fault\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 503 | return retval; |
| 504 | } |
Kenji Kaneshige | 322162a | 2008-12-19 15:19:02 +0900 | [diff] [blame] | 505 | return !!(slot_status & PCI_EXP_SLTSTA_PFD); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 506 | } |
| 507 | |
Kenji Kaneshige | 82a9e79 | 2009-09-15 17:30:48 +0900 | [diff] [blame] | 508 | int pciehp_set_attention_status(struct slot *slot, u8 value) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 509 | { |
Kenji Kaneshige | 48fe391 | 2006-12-21 17:01:04 -0800 | [diff] [blame] | 510 | struct controller *ctrl = slot->ctrl; |
Kenji Kaneshige | f477836 | 2007-05-31 09:43:34 -0700 | [diff] [blame] | 511 | u16 slot_cmd; |
| 512 | u16 cmd_mask; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 513 | |
Kenji Kaneshige | 322162a | 2008-12-19 15:19:02 +0900 | [diff] [blame] | 514 | cmd_mask = PCI_EXP_SLTCTL_AIC; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 515 | switch (value) { |
Kenji Kaneshige | 445f798 | 2009-10-05 17:42:59 +0900 | [diff] [blame] | 516 | case 0 : /* turn off */ |
| 517 | slot_cmd = 0x00C0; |
| 518 | break; |
| 519 | case 1: /* turn on */ |
| 520 | slot_cmd = 0x0040; |
| 521 | break; |
| 522 | case 2: /* turn blink */ |
| 523 | slot_cmd = 0x0080; |
| 524 | break; |
| 525 | default: |
| 526 | return -EINVAL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 527 | } |
Kenji Kaneshige | 1518c17 | 2009-11-11 14:34:52 +0900 | [diff] [blame] | 528 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, |
| 529 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd); |
Kenji Kaneshige | 445f798 | 2009-10-05 17:42:59 +0900 | [diff] [blame] | 530 | return pcie_write_cmd(ctrl, slot_cmd, cmd_mask); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 531 | } |
| 532 | |
Kenji Kaneshige | 82a9e79 | 2009-09-15 17:30:48 +0900 | [diff] [blame] | 533 | void pciehp_green_led_on(struct slot *slot) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 534 | { |
Kenji Kaneshige | 48fe391 | 2006-12-21 17:01:04 -0800 | [diff] [blame] | 535 | struct controller *ctrl = slot->ctrl; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 536 | u16 slot_cmd; |
Kenji Kaneshige | f477836 | 2007-05-31 09:43:34 -0700 | [diff] [blame] | 537 | u16 cmd_mask; |
Kenji Kaneshige | 71ad556 | 2007-08-09 16:09:34 -0700 | [diff] [blame] | 538 | |
Kenji Kaneshige | f477836 | 2007-05-31 09:43:34 -0700 | [diff] [blame] | 539 | slot_cmd = 0x0100; |
Kenji Kaneshige | 322162a | 2008-12-19 15:19:02 +0900 | [diff] [blame] | 540 | cmd_mask = PCI_EXP_SLTCTL_PIC; |
Kenji Kaneshige | c27fb883 | 2008-04-25 14:39:05 -0700 | [diff] [blame] | 541 | pcie_write_cmd(ctrl, slot_cmd, cmd_mask); |
Kenji Kaneshige | 1518c17 | 2009-11-11 14:34:52 +0900 | [diff] [blame] | 542 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, |
| 543 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 544 | } |
| 545 | |
Kenji Kaneshige | 82a9e79 | 2009-09-15 17:30:48 +0900 | [diff] [blame] | 546 | void pciehp_green_led_off(struct slot *slot) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 547 | { |
Kenji Kaneshige | 48fe391 | 2006-12-21 17:01:04 -0800 | [diff] [blame] | 548 | struct controller *ctrl = slot->ctrl; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 549 | u16 slot_cmd; |
Kenji Kaneshige | f477836 | 2007-05-31 09:43:34 -0700 | [diff] [blame] | 550 | u16 cmd_mask; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 551 | |
Kenji Kaneshige | f477836 | 2007-05-31 09:43:34 -0700 | [diff] [blame] | 552 | slot_cmd = 0x0300; |
Kenji Kaneshige | 322162a | 2008-12-19 15:19:02 +0900 | [diff] [blame] | 553 | cmd_mask = PCI_EXP_SLTCTL_PIC; |
Kenji Kaneshige | c27fb883 | 2008-04-25 14:39:05 -0700 | [diff] [blame] | 554 | pcie_write_cmd(ctrl, slot_cmd, cmd_mask); |
Kenji Kaneshige | 1518c17 | 2009-11-11 14:34:52 +0900 | [diff] [blame] | 555 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, |
| 556 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 557 | } |
| 558 | |
Kenji Kaneshige | 82a9e79 | 2009-09-15 17:30:48 +0900 | [diff] [blame] | 559 | void pciehp_green_led_blink(struct slot *slot) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 560 | { |
Kenji Kaneshige | 48fe391 | 2006-12-21 17:01:04 -0800 | [diff] [blame] | 561 | struct controller *ctrl = slot->ctrl; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 562 | u16 slot_cmd; |
Kenji Kaneshige | f477836 | 2007-05-31 09:43:34 -0700 | [diff] [blame] | 563 | u16 cmd_mask; |
Kenji Kaneshige | 71ad556 | 2007-08-09 16:09:34 -0700 | [diff] [blame] | 564 | |
Kenji Kaneshige | f477836 | 2007-05-31 09:43:34 -0700 | [diff] [blame] | 565 | slot_cmd = 0x0200; |
Kenji Kaneshige | 322162a | 2008-12-19 15:19:02 +0900 | [diff] [blame] | 566 | cmd_mask = PCI_EXP_SLTCTL_PIC; |
Kenji Kaneshige | c27fb883 | 2008-04-25 14:39:05 -0700 | [diff] [blame] | 567 | pcie_write_cmd(ctrl, slot_cmd, cmd_mask); |
Kenji Kaneshige | 1518c17 | 2009-11-11 14:34:52 +0900 | [diff] [blame] | 568 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, |
| 569 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 570 | } |
| 571 | |
Kenji Kaneshige | 82a9e79 | 2009-09-15 17:30:48 +0900 | [diff] [blame] | 572 | int pciehp_power_on_slot(struct slot * slot) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 573 | { |
Kenji Kaneshige | 48fe391 | 2006-12-21 17:01:04 -0800 | [diff] [blame] | 574 | struct controller *ctrl = slot->ctrl; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 575 | u16 slot_cmd; |
Kenji Kaneshige | f477836 | 2007-05-31 09:43:34 -0700 | [diff] [blame] | 576 | u16 cmd_mask; |
| 577 | u16 slot_status; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 578 | int retval = 0; |
| 579 | |
Rajesh Shah | 5a49f20 | 2005-11-23 15:44:54 -0800 | [diff] [blame] | 580 | /* Clear sticky power-fault bit from previous power failures */ |
Kenji Kaneshige | 322162a | 2008-12-19 15:19:02 +0900 | [diff] [blame] | 581 | retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 582 | if (retval) { |
Taku Izumi | 7f2feec | 2008-09-05 12:11:26 +0900 | [diff] [blame] | 583 | ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n", |
| 584 | __func__); |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 585 | return retval; |
| 586 | } |
Kenji Kaneshige | 322162a | 2008-12-19 15:19:02 +0900 | [diff] [blame] | 587 | slot_status &= PCI_EXP_SLTSTA_PFD; |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 588 | if (slot_status) { |
Kenji Kaneshige | 322162a | 2008-12-19 15:19:02 +0900 | [diff] [blame] | 589 | retval = pciehp_writew(ctrl, PCI_EXP_SLTSTA, slot_status); |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 590 | if (retval) { |
Taku Izumi | 7f2feec | 2008-09-05 12:11:26 +0900 | [diff] [blame] | 591 | ctrl_err(ctrl, |
| 592 | "%s: Cannot write to SLOTSTATUS register\n", |
| 593 | __func__); |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 594 | return retval; |
| 595 | } |
| 596 | } |
Kenji Kaneshige | 5651c48 | 2009-11-13 15:14:10 +0900 | [diff] [blame] | 597 | ctrl->power_fault_detected = 0; |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 598 | |
Kenji Kaneshige | f477836 | 2007-05-31 09:43:34 -0700 | [diff] [blame] | 599 | slot_cmd = POWER_ON; |
Kenji Kaneshige | 322162a | 2008-12-19 15:19:02 +0900 | [diff] [blame] | 600 | cmd_mask = PCI_EXP_SLTCTL_PCC; |
Kenji Kaneshige | c27fb883 | 2008-04-25 14:39:05 -0700 | [diff] [blame] | 601 | retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 602 | if (retval) { |
Taku Izumi | 18b341b | 2008-10-23 11:47:32 +0900 | [diff] [blame] | 603 | ctrl_err(ctrl, "Write %x command failed!\n", slot_cmd); |
Kenji Kaneshige | 99f0169 | 2009-02-03 15:06:16 +0900 | [diff] [blame] | 604 | return retval; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 605 | } |
Kenji Kaneshige | 1518c17 | 2009-11-11 14:34:52 +0900 | [diff] [blame] | 606 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, |
| 607 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 608 | |
Yinghai Lu | 2debd92 | 2012-01-27 10:55:15 -0800 | [diff] [blame] | 609 | retval = pciehp_link_enable(ctrl); |
| 610 | if (retval) |
| 611 | ctrl_err(ctrl, "%s: Can not enable the link!\n", __func__); |
| 612 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 613 | return retval; |
| 614 | } |
| 615 | |
Kenji Kaneshige | 82a9e79 | 2009-09-15 17:30:48 +0900 | [diff] [blame] | 616 | int pciehp_power_off_slot(struct slot * slot) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 617 | { |
Kenji Kaneshige | 48fe391 | 2006-12-21 17:01:04 -0800 | [diff] [blame] | 618 | struct controller *ctrl = slot->ctrl; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 619 | u16 slot_cmd; |
Kenji Kaneshige | f477836 | 2007-05-31 09:43:34 -0700 | [diff] [blame] | 620 | u16 cmd_mask; |
Kenji Kaneshige | 3c3a1b1 | 2009-10-05 17:40:48 +0900 | [diff] [blame] | 621 | int retval; |
Kenji Kaneshige | f1050a3 | 2007-12-20 19:45:09 +0900 | [diff] [blame] | 622 | |
Yinghai Lu | 2debd92 | 2012-01-27 10:55:15 -0800 | [diff] [blame] | 623 | /* Disable the link at first */ |
| 624 | pciehp_link_disable(ctrl); |
| 625 | /* wait the link is down */ |
| 626 | if (ctrl->link_active_reporting) |
| 627 | pcie_wait_link_not_active(ctrl); |
| 628 | else |
| 629 | msleep(1000); |
| 630 | |
Kenji Kaneshige | f477836 | 2007-05-31 09:43:34 -0700 | [diff] [blame] | 631 | slot_cmd = POWER_OFF; |
Kenji Kaneshige | 322162a | 2008-12-19 15:19:02 +0900 | [diff] [blame] | 632 | cmd_mask = PCI_EXP_SLTCTL_PCC; |
Kenji Kaneshige | c27fb883 | 2008-04-25 14:39:05 -0700 | [diff] [blame] | 633 | retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 634 | if (retval) { |
Taku Izumi | 18b341b | 2008-10-23 11:47:32 +0900 | [diff] [blame] | 635 | ctrl_err(ctrl, "Write command failed!\n"); |
Kenji Kaneshige | 3c3a1b1 | 2009-10-05 17:40:48 +0900 | [diff] [blame] | 636 | return retval; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 637 | } |
Kenji Kaneshige | 1518c17 | 2009-11-11 14:34:52 +0900 | [diff] [blame] | 638 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, |
| 639 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd); |
Kenji Kaneshige | 3c3a1b1 | 2009-10-05 17:40:48 +0900 | [diff] [blame] | 640 | return 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 641 | } |
| 642 | |
Kenji Kaneshige | 48fe391 | 2006-12-21 17:01:04 -0800 | [diff] [blame] | 643 | static irqreturn_t pcie_isr(int irq, void *dev_id) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 644 | { |
Kenji Kaneshige | 48fe391 | 2006-12-21 17:01:04 -0800 | [diff] [blame] | 645 | struct controller *ctrl = (struct controller *)dev_id; |
Kenji Kaneshige | 8720d27 | 2009-09-15 17:24:46 +0900 | [diff] [blame] | 646 | struct slot *slot = ctrl->slot; |
Kenji Kaneshige | c6b069e | 2008-04-25 14:38:57 -0700 | [diff] [blame] | 647 | u16 detected, intr_loc; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 648 | |
Kenji Kaneshige | c6b069e | 2008-04-25 14:38:57 -0700 | [diff] [blame] | 649 | /* |
| 650 | * In order to guarantee that all interrupt events are |
| 651 | * serviced, we need to re-inspect Slot Status register after |
| 652 | * clearing what is presumed to be the last pending interrupt. |
| 653 | */ |
| 654 | intr_loc = 0; |
| 655 | do { |
Kenji Kaneshige | 322162a | 2008-12-19 15:19:02 +0900 | [diff] [blame] | 656 | if (pciehp_readw(ctrl, PCI_EXP_SLTSTA, &detected)) { |
Taku Izumi | 7f2feec | 2008-09-05 12:11:26 +0900 | [diff] [blame] | 657 | ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS\n", |
| 658 | __func__); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 659 | return IRQ_NONE; |
| 660 | } |
| 661 | |
Kenji Kaneshige | 322162a | 2008-12-19 15:19:02 +0900 | [diff] [blame] | 662 | detected &= (PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD | |
| 663 | PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC | |
| 664 | PCI_EXP_SLTSTA_CC); |
Kenji Kaneshige | 81b840c | 2009-02-03 15:06:13 +0900 | [diff] [blame] | 665 | detected &= ~intr_loc; |
Kenji Kaneshige | c6b069e | 2008-04-25 14:38:57 -0700 | [diff] [blame] | 666 | intr_loc |= detected; |
| 667 | if (!intr_loc) |
| 668 | return IRQ_NONE; |
Kenji Kaneshige | 81b840c | 2009-02-03 15:06:13 +0900 | [diff] [blame] | 669 | if (detected && pciehp_writew(ctrl, PCI_EXP_SLTSTA, intr_loc)) { |
Taku Izumi | 7f2feec | 2008-09-05 12:11:26 +0900 | [diff] [blame] | 670 | ctrl_err(ctrl, "%s: Cannot write to SLOTSTATUS\n", |
| 671 | __func__); |
Kenji Kaneshige | a0f018d | 2006-12-21 17:01:06 -0800 | [diff] [blame] | 672 | return IRQ_NONE; |
| 673 | } |
Kenji Kaneshige | c6b069e | 2008-04-25 14:38:57 -0700 | [diff] [blame] | 674 | } while (detected); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 675 | |
Taku Izumi | 7f2feec | 2008-09-05 12:11:26 +0900 | [diff] [blame] | 676 | ctrl_dbg(ctrl, "%s: intr_loc %x\n", __func__, intr_loc); |
Kenji Kaneshige | 71ad556 | 2007-08-09 16:09:34 -0700 | [diff] [blame] | 677 | |
Kenji Kaneshige | c6b069e | 2008-04-25 14:38:57 -0700 | [diff] [blame] | 678 | /* Check Command Complete Interrupt Pending */ |
Kenji Kaneshige | 322162a | 2008-12-19 15:19:02 +0900 | [diff] [blame] | 679 | if (intr_loc & PCI_EXP_SLTSTA_CC) { |
Kenji Kaneshige | 262303fe | 2006-12-21 17:01:10 -0800 | [diff] [blame] | 680 | ctrl->cmd_busy = 0; |
Kenji Kaneshige | 2d32a9a | 2008-04-25 14:39:02 -0700 | [diff] [blame] | 681 | smp_mb(); |
Kenji Kaneshige | d737bdc | 2008-05-28 14:59:44 +0900 | [diff] [blame] | 682 | wake_up(&ctrl->queue); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 683 | } |
| 684 | |
Kenji Kaneshige | 322162a | 2008-12-19 15:19:02 +0900 | [diff] [blame] | 685 | if (!(intr_loc & ~PCI_EXP_SLTSTA_CC)) |
Kenji Kaneshige | dbd79ae | 2008-05-27 19:03:16 +0900 | [diff] [blame] | 686 | return IRQ_HANDLED; |
| 687 | |
Kenji Kaneshige | c6b069e | 2008-04-25 14:38:57 -0700 | [diff] [blame] | 688 | /* Check MRL Sensor Changed */ |
Kenji Kaneshige | 322162a | 2008-12-19 15:19:02 +0900 | [diff] [blame] | 689 | if (intr_loc & PCI_EXP_SLTSTA_MRLSC) |
Kenji Kaneshige | 8720d27 | 2009-09-15 17:24:46 +0900 | [diff] [blame] | 690 | pciehp_handle_switch_change(slot); |
Kenji Kaneshige | 48fe391 | 2006-12-21 17:01:04 -0800 | [diff] [blame] | 691 | |
Kenji Kaneshige | c6b069e | 2008-04-25 14:38:57 -0700 | [diff] [blame] | 692 | /* Check Attention Button Pressed */ |
Kenji Kaneshige | 322162a | 2008-12-19 15:19:02 +0900 | [diff] [blame] | 693 | if (intr_loc & PCI_EXP_SLTSTA_ABP) |
Kenji Kaneshige | 8720d27 | 2009-09-15 17:24:46 +0900 | [diff] [blame] | 694 | pciehp_handle_attention_button(slot); |
Kenji Kaneshige | 48fe391 | 2006-12-21 17:01:04 -0800 | [diff] [blame] | 695 | |
Kenji Kaneshige | c6b069e | 2008-04-25 14:38:57 -0700 | [diff] [blame] | 696 | /* Check Presence Detect Changed */ |
Kenji Kaneshige | 322162a | 2008-12-19 15:19:02 +0900 | [diff] [blame] | 697 | if (intr_loc & PCI_EXP_SLTSTA_PDC) |
Kenji Kaneshige | 8720d27 | 2009-09-15 17:24:46 +0900 | [diff] [blame] | 698 | pciehp_handle_presence_change(slot); |
Kenji Kaneshige | 48fe391 | 2006-12-21 17:01:04 -0800 | [diff] [blame] | 699 | |
Kenji Kaneshige | c6b069e | 2008-04-25 14:38:57 -0700 | [diff] [blame] | 700 | /* Check Power Fault Detected */ |
Kenji Kaneshige | 99f0169 | 2009-02-03 15:06:16 +0900 | [diff] [blame] | 701 | if ((intr_loc & PCI_EXP_SLTSTA_PFD) && !ctrl->power_fault_detected) { |
| 702 | ctrl->power_fault_detected = 1; |
Kenji Kaneshige | 8720d27 | 2009-09-15 17:24:46 +0900 | [diff] [blame] | 703 | pciehp_handle_power_fault(slot); |
Kenji Kaneshige | 99f0169 | 2009-02-03 15:06:16 +0900 | [diff] [blame] | 704 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 705 | return IRQ_HANDLED; |
| 706 | } |
| 707 | |
Kenji Kaneshige | c4635eb | 2008-06-20 12:07:08 +0900 | [diff] [blame] | 708 | int pcie_enable_notification(struct controller *ctrl) |
Mark Lord | ecdde93 | 2007-11-21 15:07:55 -0800 | [diff] [blame] | 709 | { |
Kenji Kaneshige | c27fb883 | 2008-04-25 14:39:05 -0700 | [diff] [blame] | 710 | u16 cmd, mask; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 711 | |
Kenji Kaneshige | 5651c48 | 2009-11-13 15:14:10 +0900 | [diff] [blame] | 712 | /* |
| 713 | * TBD: Power fault detected software notification support. |
| 714 | * |
| 715 | * Power fault detected software notification is not enabled |
| 716 | * now, because it caused power fault detected interrupt storm |
| 717 | * on some machines. On those machines, power fault detected |
| 718 | * bit in the slot status register was set again immediately |
| 719 | * when it is cleared in the interrupt service routine, and |
| 720 | * next power fault detected interrupt was notified again. |
| 721 | */ |
Kenji Kaneshige | 322162a | 2008-12-19 15:19:02 +0900 | [diff] [blame] | 722 | cmd = PCI_EXP_SLTCTL_PDCE; |
Kenji Kaneshige | ae416e6 | 2008-04-25 14:39:06 -0700 | [diff] [blame] | 723 | if (ATTN_BUTTN(ctrl)) |
Kenji Kaneshige | 322162a | 2008-12-19 15:19:02 +0900 | [diff] [blame] | 724 | cmd |= PCI_EXP_SLTCTL_ABPE; |
Kenji Kaneshige | ae416e6 | 2008-04-25 14:39:06 -0700 | [diff] [blame] | 725 | if (MRL_SENS(ctrl)) |
Kenji Kaneshige | 322162a | 2008-12-19 15:19:02 +0900 | [diff] [blame] | 726 | cmd |= PCI_EXP_SLTCTL_MRLSCE; |
Kenji Kaneshige | c27fb883 | 2008-04-25 14:39:05 -0700 | [diff] [blame] | 727 | if (!pciehp_poll_mode) |
Kenji Kaneshige | 322162a | 2008-12-19 15:19:02 +0900 | [diff] [blame] | 728 | cmd |= PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE; |
Kenji Kaneshige | c27fb883 | 2008-04-25 14:39:05 -0700 | [diff] [blame] | 729 | |
Kenji Kaneshige | 322162a | 2008-12-19 15:19:02 +0900 | [diff] [blame] | 730 | mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE | |
| 731 | PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE | |
| 732 | PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE); |
Kenji Kaneshige | c27fb883 | 2008-04-25 14:39:05 -0700 | [diff] [blame] | 733 | |
| 734 | if (pcie_write_cmd(ctrl, cmd, mask)) { |
Taku Izumi | 18b341b | 2008-10-23 11:47:32 +0900 | [diff] [blame] | 735 | ctrl_err(ctrl, "Cannot enable software notification\n"); |
Kenji Kaneshige | 125c39f | 2008-05-28 14:57:30 +0900 | [diff] [blame] | 736 | return -1; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 737 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 738 | return 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 739 | } |
Mark Lord | 08e7a7d | 2007-11-28 15:11:46 -0800 | [diff] [blame] | 740 | |
Kenji Kaneshige | c4635eb | 2008-06-20 12:07:08 +0900 | [diff] [blame] | 741 | static void pcie_disable_notification(struct controller *ctrl) |
| 742 | { |
| 743 | u16 mask; |
Kenji Kaneshige | 322162a | 2008-12-19 15:19:02 +0900 | [diff] [blame] | 744 | mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE | |
| 745 | PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE | |
Kenji Kaneshige | f22daf1 | 2009-10-05 17:40:02 +0900 | [diff] [blame] | 746 | PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE | |
| 747 | PCI_EXP_SLTCTL_DLLSCE); |
Kenji Kaneshige | c4635eb | 2008-06-20 12:07:08 +0900 | [diff] [blame] | 748 | if (pcie_write_cmd(ctrl, 0, mask)) |
Taku Izumi | 18b341b | 2008-10-23 11:47:32 +0900 | [diff] [blame] | 749 | ctrl_warn(ctrl, "Cannot disable software notification\n"); |
Kenji Kaneshige | c4635eb | 2008-06-20 12:07:08 +0900 | [diff] [blame] | 750 | } |
| 751 | |
Alex Williamson | 2e35afa | 2013-08-08 14:09:37 -0600 | [diff] [blame] | 752 | /* |
| 753 | * pciehp has a 1:1 bus:slot relationship so we ultimately want a secondary |
| 754 | * bus reset of the bridge, but if the slot supports surprise removal we need |
| 755 | * to disable presence detection around the bus reset and clear any spurious |
| 756 | * events after. |
| 757 | */ |
| 758 | int pciehp_reset_slot(struct slot *slot, int probe) |
| 759 | { |
| 760 | struct controller *ctrl = slot->ctrl; |
| 761 | |
| 762 | if (probe) |
| 763 | return 0; |
| 764 | |
| 765 | if (HP_SUPR_RM(ctrl)) { |
| 766 | pcie_write_cmd(ctrl, 0, PCI_EXP_SLTCTL_PDCE); |
| 767 | if (pciehp_poll_mode) |
| 768 | del_timer_sync(&ctrl->poll_timer); |
| 769 | } |
| 770 | |
| 771 | pci_reset_bridge_secondary_bus(ctrl->pcie->port); |
| 772 | |
| 773 | if (HP_SUPR_RM(ctrl)) { |
| 774 | pciehp_writew(ctrl, PCI_EXP_SLTSTA, PCI_EXP_SLTSTA_PDC); |
| 775 | pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PDCE, PCI_EXP_SLTCTL_PDCE); |
| 776 | if (pciehp_poll_mode) |
| 777 | int_poll_timeout(ctrl->poll_timer.data); |
| 778 | } |
| 779 | |
| 780 | return 0; |
| 781 | } |
| 782 | |
Eric W. Biederman | dbc7e1e | 2009-01-28 19:31:18 -0800 | [diff] [blame] | 783 | int pcie_init_notification(struct controller *ctrl) |
Kenji Kaneshige | c4635eb | 2008-06-20 12:07:08 +0900 | [diff] [blame] | 784 | { |
| 785 | if (pciehp_request_irq(ctrl)) |
| 786 | return -1; |
| 787 | if (pcie_enable_notification(ctrl)) { |
| 788 | pciehp_free_irq(ctrl); |
| 789 | return -1; |
| 790 | } |
Eric W. Biederman | dbc7e1e | 2009-01-28 19:31:18 -0800 | [diff] [blame] | 791 | ctrl->notification_enabled = 1; |
Kenji Kaneshige | c4635eb | 2008-06-20 12:07:08 +0900 | [diff] [blame] | 792 | return 0; |
| 793 | } |
| 794 | |
| 795 | static void pcie_shutdown_notification(struct controller *ctrl) |
| 796 | { |
Eric W. Biederman | dbc7e1e | 2009-01-28 19:31:18 -0800 | [diff] [blame] | 797 | if (ctrl->notification_enabled) { |
| 798 | pcie_disable_notification(ctrl); |
| 799 | pciehp_free_irq(ctrl); |
| 800 | ctrl->notification_enabled = 0; |
| 801 | } |
Kenji Kaneshige | c4635eb | 2008-06-20 12:07:08 +0900 | [diff] [blame] | 802 | } |
| 803 | |
Kenji Kaneshige | c4635eb | 2008-06-20 12:07:08 +0900 | [diff] [blame] | 804 | static int pcie_init_slot(struct controller *ctrl) |
| 805 | { |
| 806 | struct slot *slot; |
| 807 | |
| 808 | slot = kzalloc(sizeof(*slot), GFP_KERNEL); |
| 809 | if (!slot) |
| 810 | return -ENOMEM; |
| 811 | |
Kees Cook | d853754 | 2013-07-03 15:04:57 -0700 | [diff] [blame] | 812 | slot->wq = alloc_workqueue("pciehp-%u", 0, 0, PSN(ctrl)); |
Yijing Wang | c2be6f9 | 2013-01-11 10:15:54 +0800 | [diff] [blame] | 813 | if (!slot->wq) |
| 814 | goto abort; |
| 815 | |
Kenji Kaneshige | c4635eb | 2008-06-20 12:07:08 +0900 | [diff] [blame] | 816 | slot->ctrl = ctrl; |
Kenji Kaneshige | c4635eb | 2008-06-20 12:07:08 +0900 | [diff] [blame] | 817 | mutex_init(&slot->lock); |
| 818 | INIT_DELAYED_WORK(&slot->work, pciehp_queue_pushbutton_work); |
Kenji Kaneshige | 8720d27 | 2009-09-15 17:24:46 +0900 | [diff] [blame] | 819 | ctrl->slot = slot; |
Kenji Kaneshige | c4635eb | 2008-06-20 12:07:08 +0900 | [diff] [blame] | 820 | return 0; |
Yijing Wang | c2be6f9 | 2013-01-11 10:15:54 +0800 | [diff] [blame] | 821 | abort: |
| 822 | kfree(slot); |
| 823 | return -ENOMEM; |
Kenji Kaneshige | c4635eb | 2008-06-20 12:07:08 +0900 | [diff] [blame] | 824 | } |
| 825 | |
| 826 | static void pcie_cleanup_slot(struct controller *ctrl) |
| 827 | { |
Kenji Kaneshige | 8720d27 | 2009-09-15 17:24:46 +0900 | [diff] [blame] | 828 | struct slot *slot = ctrl->slot; |
Kenji Kaneshige | c4635eb | 2008-06-20 12:07:08 +0900 | [diff] [blame] | 829 | cancel_delayed_work(&slot->work); |
Yijing Wang | c2be6f9 | 2013-01-11 10:15:54 +0800 | [diff] [blame] | 830 | destroy_workqueue(slot->wq); |
Kenji Kaneshige | c4635eb | 2008-06-20 12:07:08 +0900 | [diff] [blame] | 831 | kfree(slot); |
| 832 | } |
| 833 | |
Kenji Kaneshige | 2aeeef1 | 2008-04-25 14:39:08 -0700 | [diff] [blame] | 834 | static inline void dbg_ctrl(struct controller *ctrl) |
| 835 | { |
| 836 | int i; |
| 837 | u16 reg16; |
Kenji Kaneshige | 385e249 | 2009-09-15 17:30:14 +0900 | [diff] [blame] | 838 | struct pci_dev *pdev = ctrl->pcie->port; |
Kenji Kaneshige | 2aeeef1 | 2008-04-25 14:39:08 -0700 | [diff] [blame] | 839 | |
| 840 | if (!pciehp_debug) |
| 841 | return; |
| 842 | |
Taku Izumi | 7f2feec | 2008-09-05 12:11:26 +0900 | [diff] [blame] | 843 | ctrl_info(ctrl, "Hotplug Controller:\n"); |
| 844 | ctrl_info(ctrl, " Seg/Bus/Dev/Func/IRQ : %s IRQ %d\n", |
| 845 | pci_name(pdev), pdev->irq); |
| 846 | ctrl_info(ctrl, " Vendor ID : 0x%04x\n", pdev->vendor); |
| 847 | ctrl_info(ctrl, " Device ID : 0x%04x\n", pdev->device); |
| 848 | ctrl_info(ctrl, " Subsystem ID : 0x%04x\n", |
| 849 | pdev->subsystem_device); |
| 850 | ctrl_info(ctrl, " Subsystem Vendor ID : 0x%04x\n", |
| 851 | pdev->subsystem_vendor); |
Kenji Kaneshige | 1518c17 | 2009-11-11 14:34:52 +0900 | [diff] [blame] | 852 | ctrl_info(ctrl, " PCIe Cap offset : 0x%02x\n", |
| 853 | pci_pcie_cap(pdev)); |
Kenji Kaneshige | 2aeeef1 | 2008-04-25 14:39:08 -0700 | [diff] [blame] | 854 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { |
| 855 | if (!pci_resource_len(pdev, i)) |
| 856 | continue; |
Bjorn Helgaas | e1944c6 | 2010-03-16 15:53:08 -0600 | [diff] [blame] | 857 | ctrl_info(ctrl, " PCI resource [%d] : %pR\n", |
| 858 | i, &pdev->resource[i]); |
Kenji Kaneshige | 2aeeef1 | 2008-04-25 14:39:08 -0700 | [diff] [blame] | 859 | } |
Taku Izumi | 7f2feec | 2008-09-05 12:11:26 +0900 | [diff] [blame] | 860 | ctrl_info(ctrl, "Slot Capabilities : 0x%08x\n", ctrl->slot_cap); |
Kenji Kaneshige | d54798f | 2009-09-15 17:28:53 +0900 | [diff] [blame] | 861 | ctrl_info(ctrl, " Physical Slot Number : %d\n", PSN(ctrl)); |
Taku Izumi | 7f2feec | 2008-09-05 12:11:26 +0900 | [diff] [blame] | 862 | ctrl_info(ctrl, " Attention Button : %3s\n", |
| 863 | ATTN_BUTTN(ctrl) ? "yes" : "no"); |
| 864 | ctrl_info(ctrl, " Power Controller : %3s\n", |
| 865 | POWER_CTRL(ctrl) ? "yes" : "no"); |
| 866 | ctrl_info(ctrl, " MRL Sensor : %3s\n", |
| 867 | MRL_SENS(ctrl) ? "yes" : "no"); |
| 868 | ctrl_info(ctrl, " Attention Indicator : %3s\n", |
| 869 | ATTN_LED(ctrl) ? "yes" : "no"); |
| 870 | ctrl_info(ctrl, " Power Indicator : %3s\n", |
| 871 | PWR_LED(ctrl) ? "yes" : "no"); |
| 872 | ctrl_info(ctrl, " Hot-Plug Surprise : %3s\n", |
| 873 | HP_SUPR_RM(ctrl) ? "yes" : "no"); |
| 874 | ctrl_info(ctrl, " EMI Present : %3s\n", |
| 875 | EMI(ctrl) ? "yes" : "no"); |
| 876 | ctrl_info(ctrl, " Command Completed : %3s\n", |
| 877 | NO_CMD_CMPL(ctrl) ? "no" : "yes"); |
Kenji Kaneshige | 322162a | 2008-12-19 15:19:02 +0900 | [diff] [blame] | 878 | pciehp_readw(ctrl, PCI_EXP_SLTSTA, ®16); |
Taku Izumi | 7f2feec | 2008-09-05 12:11:26 +0900 | [diff] [blame] | 879 | ctrl_info(ctrl, "Slot Status : 0x%04x\n", reg16); |
Kenji Kaneshige | 322162a | 2008-12-19 15:19:02 +0900 | [diff] [blame] | 880 | pciehp_readw(ctrl, PCI_EXP_SLTCTL, ®16); |
Taku Izumi | 7f2feec | 2008-09-05 12:11:26 +0900 | [diff] [blame] | 881 | ctrl_info(ctrl, "Slot Control : 0x%04x\n", reg16); |
Kenji Kaneshige | 2aeeef1 | 2008-04-25 14:39:08 -0700 | [diff] [blame] | 882 | } |
| 883 | |
Kenji Kaneshige | c4635eb | 2008-06-20 12:07:08 +0900 | [diff] [blame] | 884 | struct controller *pcie_init(struct pcie_device *dev) |
Mark Lord | 08e7a7d | 2007-11-28 15:11:46 -0800 | [diff] [blame] | 885 | { |
Kenji Kaneshige | c4635eb | 2008-06-20 12:07:08 +0900 | [diff] [blame] | 886 | struct controller *ctrl; |
Kenji Kaneshige | f18e962 | 2008-10-22 14:31:44 +0900 | [diff] [blame] | 887 | u32 slot_cap, link_cap; |
Kenji Kaneshige | 2aeeef1 | 2008-04-25 14:39:08 -0700 | [diff] [blame] | 888 | struct pci_dev *pdev = dev->port; |
Mark Lord | 08e7a7d | 2007-11-28 15:11:46 -0800 | [diff] [blame] | 889 | |
Kenji Kaneshige | c4635eb | 2008-06-20 12:07:08 +0900 | [diff] [blame] | 890 | ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL); |
| 891 | if (!ctrl) { |
Taku Izumi | 18b341b | 2008-10-23 11:47:32 +0900 | [diff] [blame] | 892 | dev_err(&dev->device, "%s: Out of memory\n", __func__); |
Kenji Kaneshige | c4635eb | 2008-06-20 12:07:08 +0900 | [diff] [blame] | 893 | goto abort; |
| 894 | } |
Kenji Kaneshige | f7a10e3 | 2008-08-22 17:16:48 +0900 | [diff] [blame] | 895 | ctrl->pcie = dev; |
Kenji Kaneshige | 322162a | 2008-12-19 15:19:02 +0900 | [diff] [blame] | 896 | if (pciehp_readl(ctrl, PCI_EXP_SLTCAP, &slot_cap)) { |
Taku Izumi | 18b341b | 2008-10-23 11:47:32 +0900 | [diff] [blame] | 897 | ctrl_err(ctrl, "Cannot read SLOTCAP register\n"); |
Kenji Kaneshige | b84346e | 2008-10-22 14:30:15 +0900 | [diff] [blame] | 898 | goto abort_ctrl; |
Mark Lord | 08e7a7d | 2007-11-28 15:11:46 -0800 | [diff] [blame] | 899 | } |
Mark Lord | 08e7a7d | 2007-11-28 15:11:46 -0800 | [diff] [blame] | 900 | |
Kenji Kaneshige | 2aeeef1 | 2008-04-25 14:39:08 -0700 | [diff] [blame] | 901 | ctrl->slot_cap = slot_cap; |
Kenji Kaneshige | 2aeeef1 | 2008-04-25 14:39:08 -0700 | [diff] [blame] | 902 | mutex_init(&ctrl->ctrl_lock); |
| 903 | init_waitqueue_head(&ctrl->queue); |
| 904 | dbg_ctrl(ctrl); |
Kenji Kaneshige | 5808639 | 2008-05-27 19:04:30 +0900 | [diff] [blame] | 905 | /* |
| 906 | * Controller doesn't notify of command completion if the "No |
| 907 | * Command Completed Support" bit is set in Slot Capability |
| 908 | * register or the controller supports none of power |
| 909 | * controller, attention led, power led and EMI. |
| 910 | */ |
| 911 | if (NO_CMD_CMPL(ctrl) || |
| 912 | !(POWER_CTRL(ctrl) | ATTN_LED(ctrl) | PWR_LED(ctrl) | EMI(ctrl))) |
| 913 | ctrl->no_cmd_complete = 1; |
Mark Lord | 08e7a7d | 2007-11-28 15:11:46 -0800 | [diff] [blame] | 914 | |
Kenji Kaneshige | f18e962 | 2008-10-22 14:31:44 +0900 | [diff] [blame] | 915 | /* Check if Data Link Layer Link Active Reporting is implemented */ |
Kenji Kaneshige | 322162a | 2008-12-19 15:19:02 +0900 | [diff] [blame] | 916 | if (pciehp_readl(ctrl, PCI_EXP_LNKCAP, &link_cap)) { |
Kenji Kaneshige | f18e962 | 2008-10-22 14:31:44 +0900 | [diff] [blame] | 917 | ctrl_err(ctrl, "%s: Cannot read LNKCAP register\n", __func__); |
| 918 | goto abort_ctrl; |
| 919 | } |
Kenji Kaneshige | 322162a | 2008-12-19 15:19:02 +0900 | [diff] [blame] | 920 | if (link_cap & PCI_EXP_LNKCAP_DLLLARC) { |
Kenji Kaneshige | f18e962 | 2008-10-22 14:31:44 +0900 | [diff] [blame] | 921 | ctrl_dbg(ctrl, "Link Active Reporting supported\n"); |
| 922 | ctrl->link_active_reporting = 1; |
| 923 | } |
| 924 | |
Kenji Kaneshige | c4635eb | 2008-06-20 12:07:08 +0900 | [diff] [blame] | 925 | /* Clear all remaining event bits in Slot Status register */ |
Kenji Kaneshige | 322162a | 2008-12-19 15:19:02 +0900 | [diff] [blame] | 926 | if (pciehp_writew(ctrl, PCI_EXP_SLTSTA, 0x1f)) |
Kenji Kaneshige | c4635eb | 2008-06-20 12:07:08 +0900 | [diff] [blame] | 927 | goto abort_ctrl; |
Mark Lord | 08e7a7d | 2007-11-28 15:11:46 -0800 | [diff] [blame] | 928 | |
Kenji Kaneshige | c4635eb | 2008-06-20 12:07:08 +0900 | [diff] [blame] | 929 | /* Disable sotfware notification */ |
| 930 | pcie_disable_notification(ctrl); |
Mark Lord | ecdde93 | 2007-11-21 15:07:55 -0800 | [diff] [blame] | 931 | |
Taku Izumi | 7f2feec | 2008-09-05 12:11:26 +0900 | [diff] [blame] | 932 | ctrl_info(ctrl, "HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n", |
| 933 | pdev->vendor, pdev->device, pdev->subsystem_vendor, |
| 934 | pdev->subsystem_device); |
Kenji Kaneshige | 2aeeef1 | 2008-04-25 14:39:08 -0700 | [diff] [blame] | 935 | |
Kenji Kaneshige | c4635eb | 2008-06-20 12:07:08 +0900 | [diff] [blame] | 936 | if (pcie_init_slot(ctrl)) |
| 937 | goto abort_ctrl; |
Kenji Kaneshige | 2aeeef1 | 2008-04-25 14:39:08 -0700 | [diff] [blame] | 938 | |
Kenji Kaneshige | c4635eb | 2008-06-20 12:07:08 +0900 | [diff] [blame] | 939 | return ctrl; |
| 940 | |
Kenji Kaneshige | c4635eb | 2008-06-20 12:07:08 +0900 | [diff] [blame] | 941 | abort_ctrl: |
| 942 | kfree(ctrl); |
Mark Lord | 08e7a7d | 2007-11-28 15:11:46 -0800 | [diff] [blame] | 943 | abort: |
Kenji Kaneshige | c4635eb | 2008-06-20 12:07:08 +0900 | [diff] [blame] | 944 | return NULL; |
| 945 | } |
| 946 | |
Kenji Kaneshige | 82a9e79 | 2009-09-15 17:30:48 +0900 | [diff] [blame] | 947 | void pciehp_release_ctrl(struct controller *ctrl) |
Kenji Kaneshige | c4635eb | 2008-06-20 12:07:08 +0900 | [diff] [blame] | 948 | { |
| 949 | pcie_shutdown_notification(ctrl); |
| 950 | pcie_cleanup_slot(ctrl); |
Kenji Kaneshige | c4635eb | 2008-06-20 12:07:08 +0900 | [diff] [blame] | 951 | kfree(ctrl); |
Mark Lord | 08e7a7d | 2007-11-28 15:11:46 -0800 | [diff] [blame] | 952 | } |