blob: b8064bf3aee43d45f086ddbf3675fae71a696c25 [file] [log] [blame]
David Woodhousec9ac5972006-11-30 08:17:38 +00001/*
David Woodhousefbad5692006-10-22 15:09:33 +01002 * Driver for One Laptop Per Child ‘CAFÉ’ controller, aka Marvell 88ALP01
David Woodhouse5467fb02006-10-06 15:36:29 +01003 *
David Woodhouse514fca42008-09-03 09:47:17 +01004 * The data sheet for this device can be found at:
5 * http://www.marvell.com/products/pcconn/88ALP01.jsp
6 *
David Woodhouse5467fb02006-10-06 15:36:29 +01007 * Copyright © 2006 Red Hat, Inc.
8 * Copyright © 2006 David Woodhouse <dwmw2@infradead.org>
9 */
10
David Woodhouse8dd851d2006-10-20 02:11:40 +010011#define DEBUG
David Woodhouse5467fb02006-10-06 15:36:29 +010012
13#include <linux/device.h>
14#undef DEBUG
15#include <linux/mtd/mtd.h>
16#include <linux/mtd/nand.h>
David Woodhouse9c37f332007-10-28 21:56:39 -040017#include <linux/mtd/partitions.h>
Segher Boessenkool8c61b7a2007-05-02 12:18:49 +020018#include <linux/rslib.h>
David Woodhouse5467fb02006-10-06 15:36:29 +010019#include <linux/pci.h>
20#include <linux/delay.h>
21#include <linux/interrupt.h>
Al Viroa1274302007-01-30 13:23:30 +000022#include <linux/dma-mapping.h>
David Woodhouse5467fb02006-10-06 15:36:29 +010023#include <asm/io.h>
24
25#define CAFE_NAND_CTRL1 0x00
26#define CAFE_NAND_CTRL2 0x04
27#define CAFE_NAND_CTRL3 0x08
28#define CAFE_NAND_STATUS 0x0c
29#define CAFE_NAND_IRQ 0x10
30#define CAFE_NAND_IRQ_MASK 0x14
31#define CAFE_NAND_DATA_LEN 0x18
32#define CAFE_NAND_ADDR1 0x1c
33#define CAFE_NAND_ADDR2 0x20
34#define CAFE_NAND_TIMING1 0x24
35#define CAFE_NAND_TIMING2 0x28
36#define CAFE_NAND_TIMING3 0x2c
37#define CAFE_NAND_NONMEM 0x30
David Woodhouse04459d72006-10-22 02:18:48 +010038#define CAFE_NAND_ECC_RESULT 0x3C
David Woodhousefbad5692006-10-22 15:09:33 +010039#define CAFE_NAND_DMA_CTRL 0x40
40#define CAFE_NAND_DMA_ADDR0 0x44
41#define CAFE_NAND_DMA_ADDR1 0x48
David Woodhouse04459d72006-10-22 02:18:48 +010042#define CAFE_NAND_ECC_SYN01 0x50
43#define CAFE_NAND_ECC_SYN23 0x54
44#define CAFE_NAND_ECC_SYN45 0x58
45#define CAFE_NAND_ECC_SYN67 0x5c
David Woodhouse5467fb02006-10-06 15:36:29 +010046#define CAFE_NAND_READ_DATA 0x1000
47#define CAFE_NAND_WRITE_DATA 0x2000
48
David Woodhouse195a2532006-10-31 12:30:11 +080049#define CAFE_GLOBAL_CTRL 0x3004
50#define CAFE_GLOBAL_IRQ 0x3008
51#define CAFE_GLOBAL_IRQ_MASK 0x300c
52#define CAFE_NAND_RESET 0x3034
53
David Woodhouse048c37b2007-05-02 12:26:37 +010054/* Missing from the datasheet: bit 19 of CTRL1 sets CE0 vs. CE1 */
55#define CTRL1_CHIPSELECT (1<<19)
56
David Woodhouse5467fb02006-10-06 15:36:29 +010057struct cafe_priv {
58 struct nand_chip nand;
David Woodhouse9c37f332007-10-28 21:56:39 -040059 struct mtd_partition *parts;
David Woodhouse5467fb02006-10-06 15:36:29 +010060 struct pci_dev *pdev;
61 void __iomem *mmio;
Segher Boessenkool8c61b7a2007-05-02 12:18:49 +020062 struct rs_control *rs;
David Woodhouse5467fb02006-10-06 15:36:29 +010063 uint32_t ctl1;
64 uint32_t ctl2;
65 int datalen;
66 int nr_data;
67 int data_pos;
68 int page_addr;
69 dma_addr_t dmaaddr;
70 unsigned char *dmabuf;
David Woodhouse5467fb02006-10-06 15:36:29 +010071};
72
David Woodhouseb478c772006-10-27 14:50:04 +030073static int usedma = 1;
David Woodhouse5467fb02006-10-06 15:36:29 +010074module_param(usedma, int, 0644);
75
David Woodhouse8dd851d2006-10-20 02:11:40 +010076static int skipbbt = 0;
77module_param(skipbbt, int, 0644);
78
79static int debug = 0;
80module_param(debug, int, 0644);
81
David Woodhousebe8444b2006-10-31 12:36:04 +080082static int regdebug = 0;
83module_param(regdebug, int, 0644);
84
David Woodhouseb478c772006-10-27 14:50:04 +030085static int checkecc = 1;
David Woodhouse470b0a92006-10-23 14:29:04 +010086module_param(checkecc, int, 0644);
87
Al Viro64a6f952007-10-14 19:35:30 +010088static unsigned int numtimings;
David Woodhouse527a4f42007-01-23 15:35:27 +080089static int timing[3];
90module_param_array(timing, int, &numtimings, 0644);
David Woodhouseb478c772006-10-27 14:50:04 +030091
David Woodhouse9c37f332007-10-28 21:56:39 -040092#ifdef CONFIG_MTD_PARTITIONS
93static const char *part_probes[] = { "RedBoot", NULL };
94#endif
95
David Woodhouse04459d72006-10-22 02:18:48 +010096/* Hrm. Why isn't this already conditional on something in the struct device? */
David Woodhouse8dd851d2006-10-20 02:11:40 +010097#define cafe_dev_dbg(dev, args...) do { if (debug) dev_dbg(dev, ##args); } while(0)
98
David Woodhouse195a2532006-10-31 12:30:11 +080099/* Make it easier to switch to PIO if we need to */
100#define cafe_readl(cafe, addr) readl((cafe)->mmio + CAFE_##addr)
101#define cafe_writel(cafe, datum, addr) writel(datum, (cafe)->mmio + CAFE_##addr)
David Woodhouse8dd851d2006-10-20 02:11:40 +0100102
David Woodhouse5467fb02006-10-06 15:36:29 +0100103static int cafe_device_ready(struct mtd_info *mtd)
104{
105 struct cafe_priv *cafe = mtd->priv;
David Woodhouse195a2532006-10-31 12:30:11 +0800106 int result = !!(cafe_readl(cafe, NAND_STATUS) | 0x40000000);
107 uint32_t irqs = cafe_readl(cafe, NAND_IRQ);
David Woodhousefbad5692006-10-22 15:09:33 +0100108
David Woodhouse195a2532006-10-31 12:30:11 +0800109 cafe_writel(cafe, irqs, NAND_IRQ);
David Woodhousefbad5692006-10-22 15:09:33 +0100110
David Woodhouse8dd851d2006-10-20 02:11:40 +0100111 cafe_dev_dbg(&cafe->pdev->dev, "NAND device is%s ready, IRQ %x (%x) (%x,%x)\n",
David Woodhouse195a2532006-10-31 12:30:11 +0800112 result?"":" not", irqs, cafe_readl(cafe, NAND_IRQ),
113 cafe_readl(cafe, GLOBAL_IRQ), cafe_readl(cafe, GLOBAL_IRQ_MASK));
David Woodhousefbad5692006-10-22 15:09:33 +0100114
David Woodhouse5467fb02006-10-06 15:36:29 +0100115 return result;
116}
117
118
119static void cafe_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
120{
121 struct cafe_priv *cafe = mtd->priv;
122
123 if (usedma)
124 memcpy(cafe->dmabuf + cafe->datalen, buf, len);
125 else
126 memcpy_toio(cafe->mmio + CAFE_NAND_WRITE_DATA + cafe->datalen, buf, len);
David Woodhousefbad5692006-10-22 15:09:33 +0100127
David Woodhouse5467fb02006-10-06 15:36:29 +0100128 cafe->datalen += len;
129
David Woodhouse8dd851d2006-10-20 02:11:40 +0100130 cafe_dev_dbg(&cafe->pdev->dev, "Copy 0x%x bytes to write buffer. datalen 0x%x\n",
David Woodhouse5467fb02006-10-06 15:36:29 +0100131 len, cafe->datalen);
132}
133
134static void cafe_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
135{
136 struct cafe_priv *cafe = mtd->priv;
137
138 if (usedma)
139 memcpy(buf, cafe->dmabuf + cafe->datalen, len);
140 else
141 memcpy_fromio(buf, cafe->mmio + CAFE_NAND_READ_DATA + cafe->datalen, len);
142
David Woodhouse8dd851d2006-10-20 02:11:40 +0100143 cafe_dev_dbg(&cafe->pdev->dev, "Copy 0x%x bytes from position 0x%x in read buffer.\n",
David Woodhouse5467fb02006-10-06 15:36:29 +0100144 len, cafe->datalen);
145 cafe->datalen += len;
146}
147
148static uint8_t cafe_read_byte(struct mtd_info *mtd)
149{
150 struct cafe_priv *cafe = mtd->priv;
151 uint8_t d;
152
153 cafe_read_buf(mtd, &d, 1);
David Woodhouse8dd851d2006-10-20 02:11:40 +0100154 cafe_dev_dbg(&cafe->pdev->dev, "Read %02x\n", d);
David Woodhouse5467fb02006-10-06 15:36:29 +0100155
156 return d;
157}
158
159static void cafe_nand_cmdfunc(struct mtd_info *mtd, unsigned command,
160 int column, int page_addr)
161{
162 struct cafe_priv *cafe = mtd->priv;
163 int adrbytes = 0;
164 uint32_t ctl1;
165 uint32_t doneint = 0x80000000;
David Woodhouse5467fb02006-10-06 15:36:29 +0100166
David Woodhouse8dd851d2006-10-20 02:11:40 +0100167 cafe_dev_dbg(&cafe->pdev->dev, "cmdfunc %02x, 0x%x, 0x%x\n",
David Woodhouse5467fb02006-10-06 15:36:29 +0100168 command, column, page_addr);
169
170 if (command == NAND_CMD_ERASE2 || command == NAND_CMD_PAGEPROG) {
171 /* Second half of a command we already calculated */
David Woodhouse195a2532006-10-31 12:30:11 +0800172 cafe_writel(cafe, cafe->ctl2 | 0x100 | command, NAND_CTRL2);
David Woodhouse5467fb02006-10-06 15:36:29 +0100173 ctl1 = cafe->ctl1;
David Woodhousecad40652006-11-01 08:19:20 +0800174 cafe->ctl2 &= ~(1<<30);
David Woodhouse8dd851d2006-10-20 02:11:40 +0100175 cafe_dev_dbg(&cafe->pdev->dev, "Continue command, ctl1 %08x, #data %d\n",
David Woodhouse5467fb02006-10-06 15:36:29 +0100176 cafe->ctl1, cafe->nr_data);
177 goto do_command;
178 }
179 /* Reset ECC engine */
David Woodhouse195a2532006-10-31 12:30:11 +0800180 cafe_writel(cafe, 0, NAND_CTRL2);
David Woodhouse5467fb02006-10-06 15:36:29 +0100181
182 /* Emulate NAND_CMD_READOOB on large-page chips */
183 if (mtd->writesize > 512 &&
184 command == NAND_CMD_READOOB) {
185 column += mtd->writesize;
186 command = NAND_CMD_READ0;
187 }
188
189 /* FIXME: Do we need to send read command before sending data
190 for small-page chips, to position the buffer correctly? */
191
192 if (column != -1) {
David Woodhouse195a2532006-10-31 12:30:11 +0800193 cafe_writel(cafe, column, NAND_ADDR1);
David Woodhouse5467fb02006-10-06 15:36:29 +0100194 adrbytes = 2;
195 if (page_addr != -1)
196 goto write_adr2;
197 } else if (page_addr != -1) {
David Woodhouse195a2532006-10-31 12:30:11 +0800198 cafe_writel(cafe, page_addr & 0xffff, NAND_ADDR1);
David Woodhouse5467fb02006-10-06 15:36:29 +0100199 page_addr >>= 16;
200 write_adr2:
David Woodhouse195a2532006-10-31 12:30:11 +0800201 cafe_writel(cafe, page_addr, NAND_ADDR2);
David Woodhouse5467fb02006-10-06 15:36:29 +0100202 adrbytes += 2;
203 if (mtd->size > mtd->writesize << 16)
204 adrbytes++;
205 }
206
207 cafe->data_pos = cafe->datalen = 0;
208
David Woodhouse048c37b2007-05-02 12:26:37 +0100209 /* Set command valid bit, mask in the chip select bit */
210 ctl1 = 0x80000000 | command | (cafe->ctl1 & CTRL1_CHIPSELECT);
David Woodhouse5467fb02006-10-06 15:36:29 +0100211
212 /* Set RD or WR bits as appropriate */
213 if (command == NAND_CMD_READID || command == NAND_CMD_STATUS) {
214 ctl1 |= (1<<26); /* rd */
215 /* Always 5 bytes, for now */
David Woodhouse8dd851d2006-10-20 02:11:40 +0100216 cafe->datalen = 4;
David Woodhouse5467fb02006-10-06 15:36:29 +0100217 /* And one address cycle -- even for STATUS, since the controller doesn't work without */
218 adrbytes = 1;
219 } else if (command == NAND_CMD_READ0 || command == NAND_CMD_READ1 ||
220 command == NAND_CMD_READOOB || command == NAND_CMD_RNDOUT) {
221 ctl1 |= 1<<26; /* rd */
222 /* For now, assume just read to end of page */
223 cafe->datalen = mtd->writesize + mtd->oobsize - column;
224 } else if (command == NAND_CMD_SEQIN)
225 ctl1 |= 1<<25; /* wr */
226
227 /* Set number of address bytes */
228 if (adrbytes)
229 ctl1 |= ((adrbytes-1)|8) << 27;
230
231 if (command == NAND_CMD_SEQIN || command == NAND_CMD_ERASE1) {
David Woodhousec9ac5972006-11-30 08:17:38 +0000232 /* Ignore the first command of a pair; the hardware
David Woodhouse5467fb02006-10-06 15:36:29 +0100233 deals with them both at once, later */
234 cafe->ctl1 = ctl1;
David Woodhouse8dd851d2006-10-20 02:11:40 +0100235 cafe_dev_dbg(&cafe->pdev->dev, "Setup for delayed command, ctl1 %08x, dlen %x\n",
David Woodhouse5467fb02006-10-06 15:36:29 +0100236 cafe->ctl1, cafe->datalen);
237 return;
238 }
239 /* RNDOUT and READ0 commands need a following byte */
240 if (command == NAND_CMD_RNDOUT)
David Woodhouse195a2532006-10-31 12:30:11 +0800241 cafe_writel(cafe, cafe->ctl2 | 0x100 | NAND_CMD_RNDOUTSTART, NAND_CTRL2);
David Woodhouse5467fb02006-10-06 15:36:29 +0100242 else if (command == NAND_CMD_READ0 && mtd->writesize > 512)
David Woodhouse195a2532006-10-31 12:30:11 +0800243 cafe_writel(cafe, cafe->ctl2 | 0x100 | NAND_CMD_READSTART, NAND_CTRL2);
David Woodhouse5467fb02006-10-06 15:36:29 +0100244
245 do_command:
David Woodhousec9ac5972006-11-30 08:17:38 +0000246 cafe_dev_dbg(&cafe->pdev->dev, "dlen %x, ctl1 %x, ctl2 %x\n",
David Woodhouse195a2532006-10-31 12:30:11 +0800247 cafe->datalen, ctl1, cafe_readl(cafe, NAND_CTRL2));
David Woodhousefbad5692006-10-22 15:09:33 +0100248
David Woodhouse5467fb02006-10-06 15:36:29 +0100249 /* NB: The datasheet lies -- we really should be subtracting 1 here */
David Woodhouse195a2532006-10-31 12:30:11 +0800250 cafe_writel(cafe, cafe->datalen, NAND_DATA_LEN);
251 cafe_writel(cafe, 0x90000000, NAND_IRQ);
David Woodhouse5467fb02006-10-06 15:36:29 +0100252 if (usedma && (ctl1 & (3<<25))) {
253 uint32_t dmactl = 0xc0000000 + cafe->datalen;
254 /* If WR or RD bits set, set up DMA */
255 if (ctl1 & (1<<26)) {
256 /* It's a read */
257 dmactl |= (1<<29);
258 /* ... so it's done when the DMA is done, not just
259 the command. */
260 doneint = 0x10000000;
261 }
David Woodhouse195a2532006-10-31 12:30:11 +0800262 cafe_writel(cafe, dmactl, NAND_DMA_CTRL);
David Woodhouse5467fb02006-10-06 15:36:29 +0100263 }
David Woodhouse5467fb02006-10-06 15:36:29 +0100264 cafe->datalen = 0;
265
David Woodhousebe8444b2006-10-31 12:36:04 +0800266 if (unlikely(regdebug)) {
267 int i;
268 printk("About to write command %08x to register 0\n", ctl1);
269 for (i=4; i< 0x5c; i+=4)
270 printk("Register %x: %08x\n", i, readl(cafe->mmio + i));
David Woodhousefbad5692006-10-22 15:09:33 +0100271 }
David Woodhousebe8444b2006-10-31 12:36:04 +0800272
David Woodhouse195a2532006-10-31 12:30:11 +0800273 cafe_writel(cafe, ctl1, NAND_CTRL1);
David Woodhouse5467fb02006-10-06 15:36:29 +0100274 /* Apply this short delay always to ensure that we do wait tWB in
275 * any case on any machine. */
276 ndelay(100);
277
278 if (1) {
Andrew Morton2a7295b22007-02-17 16:02:11 -0800279 int c;
David Woodhouse5467fb02006-10-06 15:36:29 +0100280 uint32_t irqs;
281
Andrew Morton2a7295b22007-02-17 16:02:11 -0800282 for (c = 500000; c != 0; c--) {
David Woodhouse195a2532006-10-31 12:30:11 +0800283 irqs = cafe_readl(cafe, NAND_IRQ);
David Woodhouse5467fb02006-10-06 15:36:29 +0100284 if (irqs & doneint)
285 break;
286 udelay(1);
David Woodhouse8dd851d2006-10-20 02:11:40 +0100287 if (!(c % 100000))
288 cafe_dev_dbg(&cafe->pdev->dev, "Wait for ready, IRQ %x\n", irqs);
David Woodhouse5467fb02006-10-06 15:36:29 +0100289 cpu_relax();
290 }
David Woodhouse195a2532006-10-31 12:30:11 +0800291 cafe_writel(cafe, doneint, NAND_IRQ);
David Woodhousea0207272006-10-28 17:08:38 +0300292 cafe_dev_dbg(&cafe->pdev->dev, "Command %x completed after %d usec, irqs %x (%x)\n",
David Woodhouse195a2532006-10-31 12:30:11 +0800293 command, 500000-c, irqs, cafe_readl(cafe, NAND_IRQ));
David Woodhouse5467fb02006-10-06 15:36:29 +0100294 }
295
David Woodhousecad40652006-11-01 08:19:20 +0800296 WARN_ON(cafe->ctl2 & (1<<30));
David Woodhouse5467fb02006-10-06 15:36:29 +0100297
298 switch (command) {
299
300 case NAND_CMD_CACHEDPROG:
301 case NAND_CMD_PAGEPROG:
302 case NAND_CMD_ERASE1:
303 case NAND_CMD_ERASE2:
304 case NAND_CMD_SEQIN:
305 case NAND_CMD_RNDIN:
306 case NAND_CMD_STATUS:
307 case NAND_CMD_DEPLETE1:
308 case NAND_CMD_RNDOUT:
309 case NAND_CMD_STATUS_ERROR:
310 case NAND_CMD_STATUS_ERROR0:
311 case NAND_CMD_STATUS_ERROR1:
312 case NAND_CMD_STATUS_ERROR2:
313 case NAND_CMD_STATUS_ERROR3:
David Woodhouse195a2532006-10-31 12:30:11 +0800314 cafe_writel(cafe, cafe->ctl2, NAND_CTRL2);
David Woodhouse5467fb02006-10-06 15:36:29 +0100315 return;
316 }
317 nand_wait_ready(mtd);
David Woodhouse195a2532006-10-31 12:30:11 +0800318 cafe_writel(cafe, cafe->ctl2, NAND_CTRL2);
David Woodhouse5467fb02006-10-06 15:36:29 +0100319}
320
321static void cafe_select_chip(struct mtd_info *mtd, int chipnr)
322{
David Woodhouse048c37b2007-05-02 12:26:37 +0100323 struct cafe_priv *cafe = mtd->priv;
324
325 cafe_dev_dbg(&cafe->pdev->dev, "select_chip %d\n", chipnr);
326
327 /* Mask the appropriate bit into the stored value of ctl1
328 which will be used by cafe_nand_cmdfunc() */
329 if (chipnr)
330 cafe->ctl1 |= CTRL1_CHIPSELECT;
331 else
332 cafe->ctl1 &= ~CTRL1_CHIPSELECT;
David Woodhouse5467fb02006-10-06 15:36:29 +0100333}
David Woodhousefbad5692006-10-22 15:09:33 +0100334
David Woodhouse28bdd4a2006-11-29 00:04:59 +0000335static int cafe_nand_interrupt(int irq, void *id)
David Woodhouse5467fb02006-10-06 15:36:29 +0100336{
337 struct mtd_info *mtd = id;
338 struct cafe_priv *cafe = mtd->priv;
David Woodhouse195a2532006-10-31 12:30:11 +0800339 uint32_t irqs = cafe_readl(cafe, NAND_IRQ);
340 cafe_writel(cafe, irqs & ~0x90000000, NAND_IRQ);
David Woodhouse5467fb02006-10-06 15:36:29 +0100341 if (!irqs)
342 return IRQ_NONE;
343
David Woodhouse195a2532006-10-31 12:30:11 +0800344 cafe_dev_dbg(&cafe->pdev->dev, "irq, bits %x (%x)\n", irqs, cafe_readl(cafe, NAND_IRQ));
David Woodhouse5467fb02006-10-06 15:36:29 +0100345 return IRQ_HANDLED;
346}
347
348static void cafe_nand_bug(struct mtd_info *mtd)
349{
350 BUG();
351}
352
353static int cafe_nand_write_oob(struct mtd_info *mtd,
354 struct nand_chip *chip, int page)
355{
356 int status = 0;
357
David Woodhouse5467fb02006-10-06 15:36:29 +0100358 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
359 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
360 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
361 status = chip->waitfunc(mtd, chip);
362
363 return status & NAND_STATUS_FAIL ? -EIO : 0;
364}
365
366/* Don't use -- use nand_read_oob_std for now */
367static int cafe_nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
368 int page, int sndcmd)
369{
370 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
371 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
372 return 1;
373}
374/**
375 * cafe_nand_read_page_syndrome - {REPLACABLE] hardware ecc syndrom based page read
376 * @mtd: mtd info structure
377 * @chip: nand chip info structure
378 * @buf: buffer to store read data
379 *
380 * The hw generator calculates the error syndrome automatically. Therefor
381 * we need a special oob layout and handling.
382 */
383static int cafe_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
384 uint8_t *buf)
385{
386 struct cafe_priv *cafe = mtd->priv;
387
David Woodhousefbad5692006-10-22 15:09:33 +0100388 cafe_dev_dbg(&cafe->pdev->dev, "ECC result %08x SYN1,2 %08x\n",
David Woodhouse195a2532006-10-31 12:30:11 +0800389 cafe_readl(cafe, NAND_ECC_RESULT),
390 cafe_readl(cafe, NAND_ECC_SYN01));
David Woodhouse5467fb02006-10-06 15:36:29 +0100391
392 chip->read_buf(mtd, buf, mtd->writesize);
393 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
394
David Woodhouse195a2532006-10-31 12:30:11 +0800395 if (checkecc && cafe_readl(cafe, NAND_ECC_RESULT) & (1<<18)) {
Segher Boessenkool8c61b7a2007-05-02 12:18:49 +0200396 unsigned short syn[8], pat[4];
397 int pos[4];
398 u8 *oob = chip->oob_poi;
399 int i, n;
David Woodhouse04459d72006-10-22 02:18:48 +0100400
401 for (i=0; i<8; i+=2) {
David Woodhouse195a2532006-10-31 12:30:11 +0800402 uint32_t tmp = cafe_readl(cafe, NAND_ECC_SYN01 + (i*2));
Segher Boessenkool8c61b7a2007-05-02 12:18:49 +0200403 syn[i] = cafe->rs->index_of[tmp & 0xfff];
404 syn[i+1] = cafe->rs->index_of[(tmp >> 16) & 0xfff];
David Woodhousec9ac5972006-11-30 08:17:38 +0000405 }
David Woodhouse04459d72006-10-22 02:18:48 +0100406
Segher Boessenkool8c61b7a2007-05-02 12:18:49 +0200407 n = decode_rs16(cafe->rs, NULL, NULL, 1367, syn, 0, pos, 0,
408 pat);
409
410 for (i = 0; i < n; i++) {
411 int p = pos[i];
412
413 /* The 12-bit symbols are mapped to bytes here */
414
415 if (p > 1374) {
416 /* out of range */
417 n = -1374;
418 } else if (p == 0) {
419 /* high four bits do not correspond to data */
420 if (pat[i] > 0xff)
421 n = -2048;
422 else
423 buf[0] ^= pat[i];
424 } else if (p == 1365) {
425 buf[2047] ^= pat[i] >> 4;
426 oob[0] ^= pat[i] << 4;
427 } else if (p > 1365) {
428 if ((p & 1) == 1) {
429 oob[3*p/2 - 2048] ^= pat[i] >> 4;
430 oob[3*p/2 - 2047] ^= pat[i] << 4;
431 } else {
432 oob[3*p/2 - 2049] ^= pat[i] >> 8;
433 oob[3*p/2 - 2048] ^= pat[i];
434 }
435 } else if ((p & 1) == 1) {
436 buf[3*p/2] ^= pat[i] >> 4;
437 buf[3*p/2 + 1] ^= pat[i] << 4;
438 } else {
439 buf[3*p/2 - 1] ^= pat[i] >> 8;
440 buf[3*p/2] ^= pat[i];
441 }
442 }
443
444 if (n < 0) {
David Woodhousebe8444b2006-10-31 12:36:04 +0800445 dev_dbg(&cafe->pdev->dev, "Failed to correct ECC at %08x\n",
446 cafe_readl(cafe, NAND_ADDR2) * 2048);
Segher Boessenkool8c61b7a2007-05-02 12:18:49 +0200447 for (i = 0; i < 0x5c; i += 4)
David Woodhousebe8444b2006-10-31 12:36:04 +0800448 printk("Register %x: %08x\n", i, readl(cafe->mmio + i));
David Woodhouse04459d72006-10-22 02:18:48 +0100449 mtd->ecc_stats.failed++;
450 } else {
Segher Boessenkool8c61b7a2007-05-02 12:18:49 +0200451 dev_dbg(&cafe->pdev->dev, "Corrected %d symbol errors\n", n);
452 mtd->ecc_stats.corrected += n;
David Woodhouse04459d72006-10-22 02:18:48 +0100453 }
454 }
455
David Woodhouse5467fb02006-10-06 15:36:29 +0100456 return 0;
457}
458
David Woodhouse8dd851d2006-10-20 02:11:40 +0100459static struct nand_ecclayout cafe_oobinfo_2048 = {
460 .eccbytes = 14,
461 .eccpos = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13},
462 .oobfree = {{14, 50}}
463};
464
David Woodhousec9ac5972006-11-30 08:17:38 +0000465/* Ick. The BBT code really ought to be able to work this bit out
David Woodhousefbad5692006-10-22 15:09:33 +0100466 for itself from the above, at least for the 2KiB case */
467static uint8_t cafe_bbt_pattern_2048[] = { 'B', 'b', 't', '0' };
468static uint8_t cafe_mirror_pattern_2048[] = { '1', 't', 'b', 'B' };
469
470static uint8_t cafe_bbt_pattern_512[] = { 0xBB };
471static uint8_t cafe_mirror_pattern_512[] = { 0xBC };
472
David Woodhouse8dd851d2006-10-20 02:11:40 +0100473
474static struct nand_bbt_descr cafe_bbt_main_descr_2048 = {
475 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
David Woodhouse048c37b2007-05-02 12:26:37 +0100476 | NAND_BBT_2BIT | NAND_BBT_VERSION,
David Woodhouse8dd851d2006-10-20 02:11:40 +0100477 .offs = 14,
478 .len = 4,
479 .veroffs = 18,
480 .maxblocks = 4,
David Woodhousefbad5692006-10-22 15:09:33 +0100481 .pattern = cafe_bbt_pattern_2048
David Woodhouse8dd851d2006-10-20 02:11:40 +0100482};
483
484static struct nand_bbt_descr cafe_bbt_mirror_descr_2048 = {
485 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
David Woodhouse048c37b2007-05-02 12:26:37 +0100486 | NAND_BBT_2BIT | NAND_BBT_VERSION,
David Woodhouse8dd851d2006-10-20 02:11:40 +0100487 .offs = 14,
488 .len = 4,
489 .veroffs = 18,
490 .maxblocks = 4,
David Woodhousefbad5692006-10-22 15:09:33 +0100491 .pattern = cafe_mirror_pattern_2048
David Woodhouse8dd851d2006-10-20 02:11:40 +0100492};
493
494static struct nand_ecclayout cafe_oobinfo_512 = {
495 .eccbytes = 14,
496 .eccpos = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13},
497 .oobfree = {{14, 2}}
498};
499
David Woodhousefbad5692006-10-22 15:09:33 +0100500static struct nand_bbt_descr cafe_bbt_main_descr_512 = {
501 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
David Woodhouse048c37b2007-05-02 12:26:37 +0100502 | NAND_BBT_2BIT | NAND_BBT_VERSION,
David Woodhousefbad5692006-10-22 15:09:33 +0100503 .offs = 14,
504 .len = 1,
505 .veroffs = 15,
506 .maxblocks = 4,
507 .pattern = cafe_bbt_pattern_512
508};
509
510static struct nand_bbt_descr cafe_bbt_mirror_descr_512 = {
511 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
David Woodhouse048c37b2007-05-02 12:26:37 +0100512 | NAND_BBT_2BIT | NAND_BBT_VERSION,
David Woodhousefbad5692006-10-22 15:09:33 +0100513 .offs = 14,
514 .len = 1,
515 .veroffs = 15,
516 .maxblocks = 4,
517 .pattern = cafe_mirror_pattern_512
518};
519
520
David Woodhouse5467fb02006-10-06 15:36:29 +0100521static void cafe_nand_write_page_lowlevel(struct mtd_info *mtd,
522 struct nand_chip *chip, const uint8_t *buf)
523{
524 struct cafe_priv *cafe = mtd->priv;
525
David Woodhouse5467fb02006-10-06 15:36:29 +0100526 chip->write_buf(mtd, buf, mtd->writesize);
David Woodhouse8dd851d2006-10-20 02:11:40 +0100527 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
David Woodhouse5467fb02006-10-06 15:36:29 +0100528
529 /* Set up ECC autogeneration */
David Woodhousecad40652006-11-01 08:19:20 +0800530 cafe->ctl2 |= (1<<30);
David Woodhouse5467fb02006-10-06 15:36:29 +0100531}
532
533static int cafe_nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
534 const uint8_t *buf, int page, int cached, int raw)
535{
536 int status;
537
David Woodhouse5467fb02006-10-06 15:36:29 +0100538 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
539
540 if (unlikely(raw))
541 chip->ecc.write_page_raw(mtd, chip, buf);
542 else
543 chip->ecc.write_page(mtd, chip, buf);
544
545 /*
546 * Cached progamming disabled for now, Not sure if its worth the
547 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s)
548 */
549 cached = 0;
550
551 if (!cached || !(chip->options & NAND_CACHEPRG)) {
552
553 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
554 status = chip->waitfunc(mtd, chip);
555 /*
556 * See if operation failed and additional status checks are
557 * available
558 */
559 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
560 status = chip->errstat(mtd, chip, FL_WRITING, status,
561 page);
562
563 if (status & NAND_STATUS_FAIL)
564 return -EIO;
565 } else {
566 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
567 status = chip->waitfunc(mtd, chip);
568 }
569
570#ifdef CONFIG_MTD_NAND_VERIFY_WRITE
571 /* Send command to read back the data */
572 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
573
574 if (chip->verify_buf(mtd, buf, mtd->writesize))
575 return -EIO;
576#endif
577 return 0;
578}
579
David Woodhouse8dd851d2006-10-20 02:11:40 +0100580static int cafe_nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
581{
582 return 0;
583}
David Woodhouse5467fb02006-10-06 15:36:29 +0100584
Segher Boessenkool8c61b7a2007-05-02 12:18:49 +0200585/* F_2[X]/(X**6+X+1) */
586static unsigned short __devinit gf64_mul(u8 a, u8 b)
587{
588 u8 c;
589 unsigned int i;
590
591 c = 0;
592 for (i = 0; i < 6; i++) {
593 if (a & 1)
594 c ^= b;
595 a >>= 1;
596 b <<= 1;
597 if ((b & 0x40) != 0)
598 b ^= 0x43;
599 }
600
601 return c;
602}
603
604/* F_64[X]/(X**2+X+A**-1) with A the generator of F_64[X] */
605static u16 __devinit gf4096_mul(u16 a, u16 b)
606{
607 u8 ah, al, bh, bl, ch, cl;
608
609 ah = a >> 6;
610 al = a & 0x3f;
611 bh = b >> 6;
612 bl = b & 0x3f;
613
614 ch = gf64_mul(ah ^ al, bh ^ bl) ^ gf64_mul(al, bl);
615 cl = gf64_mul(gf64_mul(ah, bh), 0x21) ^ gf64_mul(al, bl);
616
617 return (ch << 6) ^ cl;
618}
619
620static int __devinit cafe_mul(int x)
621{
622 if (x == 0)
623 return 1;
624 return gf4096_mul(x, 0xe01);
625}
626
David Woodhouse5467fb02006-10-06 15:36:29 +0100627static int __devinit cafe_nand_probe(struct pci_dev *pdev,
628 const struct pci_device_id *ent)
629{
630 struct mtd_info *mtd;
631 struct cafe_priv *cafe;
632 uint32_t ctrl;
633 int err = 0;
Toralf Förster437d0d22008-05-26 20:35:46 +0200634#ifdef CONFIG_MTD_PARTITIONS
635 struct mtd_partition *parts;
636 int nr_parts;
637#endif
David Woodhouse5467fb02006-10-06 15:36:29 +0100638
David Woodhouse06ed24e2007-10-06 14:44:12 -0400639 /* Very old versions shared the same PCI ident for all three
640 functions on the chip. Verify the class too... */
641 if ((pdev->class >> 8) != PCI_CLASS_MEMORY_FLASH)
642 return -ENODEV;
643
David Woodhouse5467fb02006-10-06 15:36:29 +0100644 err = pci_enable_device(pdev);
645 if (err)
646 return err;
647
648 pci_set_master(pdev);
649
650 mtd = kzalloc(sizeof(*mtd) + sizeof(struct cafe_priv), GFP_KERNEL);
651 if (!mtd) {
652 dev_warn(&pdev->dev, "failed to alloc mtd_info\n");
653 return -ENOMEM;
654 }
655 cafe = (void *)(&mtd[1]);
656
657 mtd->priv = cafe;
658 mtd->owner = THIS_MODULE;
659
660 cafe->pdev = pdev;
661 cafe->mmio = pci_iomap(pdev, 0, 0);
662 if (!cafe->mmio) {
663 dev_warn(&pdev->dev, "failed to iomap\n");
664 err = -ENOMEM;
665 goto out_free_mtd;
666 }
667 cafe->dmabuf = dma_alloc_coherent(&cafe->pdev->dev, 2112 + sizeof(struct nand_buffers),
668 &cafe->dmaaddr, GFP_KERNEL);
669 if (!cafe->dmabuf) {
670 err = -ENOMEM;
671 goto out_ior;
672 }
673 cafe->nand.buffers = (void *)cafe->dmabuf + 2112;
674
Segher Boessenkool8c61b7a2007-05-02 12:18:49 +0200675 cafe->rs = init_rs_non_canonical(12, &cafe_mul, 0, 1, 8);
676 if (!cafe->rs) {
677 err = -ENOMEM;
678 goto out_ior;
679 }
680
David Woodhouse5467fb02006-10-06 15:36:29 +0100681 cafe->nand.cmdfunc = cafe_nand_cmdfunc;
682 cafe->nand.dev_ready = cafe_device_ready;
683 cafe->nand.read_byte = cafe_read_byte;
684 cafe->nand.read_buf = cafe_read_buf;
685 cafe->nand.write_buf = cafe_write_buf;
686 cafe->nand.select_chip = cafe_select_chip;
687
688 cafe->nand.chip_delay = 0;
689
690 /* Enable the following for a flash based bad block table */
691 cafe->nand.options = NAND_USE_FLASH_BBT | NAND_NO_AUTOINCR | NAND_OWN_BUFFERS;
David Woodhouse8dd851d2006-10-20 02:11:40 +0100692
693 if (skipbbt) {
694 cafe->nand.options |= NAND_SKIP_BBTSCAN;
695 cafe->nand.block_bad = cafe_nand_block_bad;
696 }
David Woodhousec9ac5972006-11-30 08:17:38 +0000697
David Woodhouse527a4f42007-01-23 15:35:27 +0800698 if (numtimings && numtimings != 3) {
699 dev_warn(&cafe->pdev->dev, "%d timing register values ignored; precisely three are required\n", numtimings);
700 }
701
702 if (numtimings == 3) {
David Woodhouse527a4f42007-01-23 15:35:27 +0800703 cafe_dev_dbg(&cafe->pdev->dev, "Using provided timings (%08x %08x %08x)\n",
David Woodhouse8e5368a2007-03-23 10:40:04 +0000704 timing[0], timing[1], timing[2]);
David Woodhouse527a4f42007-01-23 15:35:27 +0800705 } else {
David Woodhouse8e5368a2007-03-23 10:40:04 +0000706 timing[0] = cafe_readl(cafe, NAND_TIMING1);
707 timing[1] = cafe_readl(cafe, NAND_TIMING2);
708 timing[2] = cafe_readl(cafe, NAND_TIMING3);
David Woodhouse527a4f42007-01-23 15:35:27 +0800709
David Woodhouse8e5368a2007-03-23 10:40:04 +0000710 if (timing[0] | timing[1] | timing[2]) {
711 cafe_dev_dbg(&cafe->pdev->dev, "Timing registers already set (%08x %08x %08x)\n",
712 timing[0], timing[1], timing[2]);
David Woodhouse527a4f42007-01-23 15:35:27 +0800713 } else {
714 dev_warn(&cafe->pdev->dev, "Timing registers unset; using most conservative defaults\n");
David Woodhouse8e5368a2007-03-23 10:40:04 +0000715 timing[0] = timing[1] = timing[2] = 0xffffffff;
David Woodhouse527a4f42007-01-23 15:35:27 +0800716 }
717 }
718
David Woodhousedcc41bc2006-10-27 09:55:34 +0300719 /* Start off by resetting the NAND controller completely */
David Woodhouse195a2532006-10-31 12:30:11 +0800720 cafe_writel(cafe, 1, NAND_RESET);
721 cafe_writel(cafe, 0, NAND_RESET);
722
David Woodhouse8e5368a2007-03-23 10:40:04 +0000723 cafe_writel(cafe, timing[0], NAND_TIMING1);
724 cafe_writel(cafe, timing[1], NAND_TIMING2);
725 cafe_writel(cafe, timing[2], NAND_TIMING3);
David Woodhousedcc41bc2006-10-27 09:55:34 +0300726
David Woodhouse195a2532006-10-31 12:30:11 +0800727 cafe_writel(cafe, 0xffffffff, NAND_IRQ_MASK);
Thomas Gleixner2db63462007-02-14 00:33:20 -0800728 err = request_irq(pdev->irq, &cafe_nand_interrupt, IRQF_SHARED,
729 "CAFE NAND", mtd);
David Woodhouse5467fb02006-10-06 15:36:29 +0100730 if (err) {
731 dev_warn(&pdev->dev, "Could not register IRQ %d\n", pdev->irq);
David Woodhouse5467fb02006-10-06 15:36:29 +0100732 goto out_free_dma;
733 }
David Woodhousef7c37d72007-01-23 15:44:10 +0800734
David Woodhouse5467fb02006-10-06 15:36:29 +0100735 /* Disable master reset, enable NAND clock */
David Woodhouse195a2532006-10-31 12:30:11 +0800736 ctrl = cafe_readl(cafe, GLOBAL_CTRL);
David Woodhouse5467fb02006-10-06 15:36:29 +0100737 ctrl &= 0xffffeff0;
738 ctrl |= 0x00007000;
David Woodhouse195a2532006-10-31 12:30:11 +0800739 cafe_writel(cafe, ctrl | 0x05, GLOBAL_CTRL);
740 cafe_writel(cafe, ctrl | 0x0a, GLOBAL_CTRL);
741 cafe_writel(cafe, 0, NAND_DMA_CTRL);
David Woodhouse5467fb02006-10-06 15:36:29 +0100742
David Woodhouse195a2532006-10-31 12:30:11 +0800743 cafe_writel(cafe, 0x7006, GLOBAL_CTRL);
744 cafe_writel(cafe, 0x700a, GLOBAL_CTRL);
David Woodhouse5467fb02006-10-06 15:36:29 +0100745
746 /* Set up DMA address */
David Woodhouse195a2532006-10-31 12:30:11 +0800747 cafe_writel(cafe, cafe->dmaaddr & 0xffffffff, NAND_DMA_ADDR0);
David Woodhouse5467fb02006-10-06 15:36:29 +0100748 if (sizeof(cafe->dmaaddr) > 4)
David Woodhousefbad5692006-10-22 15:09:33 +0100749 /* Shift in two parts to shut the compiler up */
David Woodhouse195a2532006-10-31 12:30:11 +0800750 cafe_writel(cafe, (cafe->dmaaddr >> 16) >> 16, NAND_DMA_ADDR1);
David Woodhouse5467fb02006-10-06 15:36:29 +0100751 else
David Woodhouse195a2532006-10-31 12:30:11 +0800752 cafe_writel(cafe, 0, NAND_DMA_ADDR1);
David Woodhousefbad5692006-10-22 15:09:33 +0100753
David Woodhouse8dd851d2006-10-20 02:11:40 +0100754 cafe_dev_dbg(&cafe->pdev->dev, "Set DMA address to %x (virt %p)\n",
David Woodhouse195a2532006-10-31 12:30:11 +0800755 cafe_readl(cafe, NAND_DMA_ADDR0), cafe->dmabuf);
David Woodhouse5467fb02006-10-06 15:36:29 +0100756
757 /* Enable NAND IRQ in global IRQ mask register */
David Woodhouse195a2532006-10-31 12:30:11 +0800758 cafe_writel(cafe, 0x80000007, GLOBAL_IRQ_MASK);
David Woodhouse8dd851d2006-10-20 02:11:40 +0100759 cafe_dev_dbg(&cafe->pdev->dev, "Control %x, IRQ mask %x\n",
David Woodhouse195a2532006-10-31 12:30:11 +0800760 cafe_readl(cafe, GLOBAL_CTRL), cafe_readl(cafe, GLOBAL_IRQ_MASK));
David Woodhousef7c37d72007-01-23 15:44:10 +0800761
762 /* Scan to find existence of the device */
David Woodhouse048c37b2007-05-02 12:26:37 +0100763 if (nand_scan_ident(mtd, 2)) {
David Woodhouse5467fb02006-10-06 15:36:29 +0100764 err = -ENXIO;
765 goto out_irq;
766 }
767
768 cafe->ctl2 = 1<<27; /* Reed-Solomon ECC */
769 if (mtd->writesize == 2048)
770 cafe->ctl2 |= 1<<29; /* 2KiB page size */
771
772 /* Set up ECC according to the type of chip we found */
David Woodhousefbad5692006-10-22 15:09:33 +0100773 if (mtd->writesize == 2048) {
David Woodhouse8dd851d2006-10-20 02:11:40 +0100774 cafe->nand.ecc.layout = &cafe_oobinfo_2048;
775 cafe->nand.bbt_td = &cafe_bbt_main_descr_2048;
776 cafe->nand.bbt_md = &cafe_bbt_mirror_descr_2048;
David Woodhousefbad5692006-10-22 15:09:33 +0100777 } else if (mtd->writesize == 512) {
778 cafe->nand.ecc.layout = &cafe_oobinfo_512;
779 cafe->nand.bbt_td = &cafe_bbt_main_descr_512;
780 cafe->nand.bbt_md = &cafe_bbt_mirror_descr_512;
David Woodhouse5467fb02006-10-06 15:36:29 +0100781 } else {
David Woodhousefbad5692006-10-22 15:09:33 +0100782 printk(KERN_WARNING "Unexpected NAND flash writesize %d. Aborting\n",
David Woodhouse5467fb02006-10-06 15:36:29 +0100783 mtd->writesize);
David Woodhousefbad5692006-10-22 15:09:33 +0100784 goto out_irq;
David Woodhouse5467fb02006-10-06 15:36:29 +0100785 }
David Woodhousefbad5692006-10-22 15:09:33 +0100786 cafe->nand.ecc.mode = NAND_ECC_HW_SYNDROME;
787 cafe->nand.ecc.size = mtd->writesize;
788 cafe->nand.ecc.bytes = 14;
789 cafe->nand.ecc.hwctl = (void *)cafe_nand_bug;
790 cafe->nand.ecc.calculate = (void *)cafe_nand_bug;
791 cafe->nand.ecc.correct = (void *)cafe_nand_bug;
792 cafe->nand.write_page = cafe_nand_write_page;
793 cafe->nand.ecc.write_page = cafe_nand_write_page_lowlevel;
794 cafe->nand.ecc.write_oob = cafe_nand_write_oob;
795 cafe->nand.ecc.read_page = cafe_nand_read_page;
796 cafe->nand.ecc.read_oob = cafe_nand_read_oob;
David Woodhouse5467fb02006-10-06 15:36:29 +0100797
798 err = nand_scan_tail(mtd);
799 if (err)
800 goto out_irq;
801
David Woodhouse5467fb02006-10-06 15:36:29 +0100802 pci_set_drvdata(pdev, mtd);
David Woodhouse9c37f332007-10-28 21:56:39 -0400803
804 /* We register the whole device first, separate from the partitions */
David Woodhouse5467fb02006-10-06 15:36:29 +0100805 add_mtd_device(mtd);
David Woodhouse9c37f332007-10-28 21:56:39 -0400806
807#ifdef CONFIG_MTD_PARTITIONS
808 nr_parts = parse_mtd_partitions(mtd, part_probes, &parts, 0);
809 if (nr_parts > 0) {
810 cafe->parts = parts;
811 dev_info(&cafe->pdev->dev, "%d RedBoot partitions found\n", nr_parts);
812 add_mtd_partitions(mtd, parts, nr_parts);
813 }
814#endif
David Woodhouse5467fb02006-10-06 15:36:29 +0100815 goto out;
816
817 out_irq:
818 /* Disable NAND IRQ in global IRQ mask register */
David Woodhouse195a2532006-10-31 12:30:11 +0800819 cafe_writel(cafe, ~1 & cafe_readl(cafe, GLOBAL_IRQ_MASK), GLOBAL_IRQ_MASK);
David Woodhouse5467fb02006-10-06 15:36:29 +0100820 free_irq(pdev->irq, mtd);
821 out_free_dma:
822 dma_free_coherent(&cafe->pdev->dev, 2112, cafe->dmabuf, cafe->dmaaddr);
823 out_ior:
824 pci_iounmap(pdev, cafe->mmio);
825 out_free_mtd:
826 kfree(mtd);
827 out:
828 return err;
829}
830
831static void __devexit cafe_nand_remove(struct pci_dev *pdev)
832{
833 struct mtd_info *mtd = pci_get_drvdata(pdev);
834 struct cafe_priv *cafe = mtd->priv;
835
836 del_mtd_device(mtd);
837 /* Disable NAND IRQ in global IRQ mask register */
David Woodhouse195a2532006-10-31 12:30:11 +0800838 cafe_writel(cafe, ~1 & cafe_readl(cafe, GLOBAL_IRQ_MASK), GLOBAL_IRQ_MASK);
David Woodhouse5467fb02006-10-06 15:36:29 +0100839 free_irq(pdev->irq, mtd);
840 nand_release(mtd);
Segher Boessenkool8c61b7a2007-05-02 12:18:49 +0200841 free_rs(cafe->rs);
David Woodhouse5467fb02006-10-06 15:36:29 +0100842 pci_iounmap(pdev, cafe->mmio);
843 dma_free_coherent(&cafe->pdev->dev, 2112, cafe->dmabuf, cafe->dmaaddr);
844 kfree(mtd);
845}
846
847static struct pci_device_id cafe_nand_tbl[] = {
David Woodhouse514fca42008-09-03 09:47:17 +0100848 { PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_88ALP01_NAND,
849 PCI_ANY_ID, PCI_ANY_ID },
David Woodhouse06ed24e2007-10-06 14:44:12 -0400850 { }
David Woodhouse5467fb02006-10-06 15:36:29 +0100851};
852
853MODULE_DEVICE_TABLE(pci, cafe_nand_tbl);
854
David Woodhouse1fcf8ce2007-10-06 14:59:32 -0400855static int cafe_nand_resume(struct pci_dev *pdev)
856{
857 uint32_t ctrl;
858 struct mtd_info *mtd = pci_get_drvdata(pdev);
859 struct cafe_priv *cafe = mtd->priv;
860
861 /* Start off by resetting the NAND controller completely */
862 cafe_writel(cafe, 1, NAND_RESET);
863 cafe_writel(cafe, 0, NAND_RESET);
864 cafe_writel(cafe, 0xffffffff, NAND_IRQ_MASK);
865
866 /* Restore timing configuration */
867 cafe_writel(cafe, timing[0], NAND_TIMING1);
868 cafe_writel(cafe, timing[1], NAND_TIMING2);
869 cafe_writel(cafe, timing[2], NAND_TIMING3);
870
871 /* Disable master reset, enable NAND clock */
872 ctrl = cafe_readl(cafe, GLOBAL_CTRL);
873 ctrl &= 0xffffeff0;
874 ctrl |= 0x00007000;
875 cafe_writel(cafe, ctrl | 0x05, GLOBAL_CTRL);
876 cafe_writel(cafe, ctrl | 0x0a, GLOBAL_CTRL);
877 cafe_writel(cafe, 0, NAND_DMA_CTRL);
878 cafe_writel(cafe, 0x7006, GLOBAL_CTRL);
879 cafe_writel(cafe, 0x700a, GLOBAL_CTRL);
880
881 /* Set up DMA address */
882 cafe_writel(cafe, cafe->dmaaddr & 0xffffffff, NAND_DMA_ADDR0);
883 if (sizeof(cafe->dmaaddr) > 4)
884 /* Shift in two parts to shut the compiler up */
885 cafe_writel(cafe, (cafe->dmaaddr >> 16) >> 16, NAND_DMA_ADDR1);
886 else
887 cafe_writel(cafe, 0, NAND_DMA_ADDR1);
888
889 /* Enable NAND IRQ in global IRQ mask register */
890 cafe_writel(cafe, 0x80000007, GLOBAL_IRQ_MASK);
891 return 0;
892}
893
David Woodhouse5467fb02006-10-06 15:36:29 +0100894static struct pci_driver cafe_nand_pci_driver = {
895 .name = "CAFÉ NAND",
896 .id_table = cafe_nand_tbl,
897 .probe = cafe_nand_probe,
898 .remove = __devexit_p(cafe_nand_remove),
David Woodhouse5467fb02006-10-06 15:36:29 +0100899 .resume = cafe_nand_resume,
David Woodhouse5467fb02006-10-06 15:36:29 +0100900};
901
902static int cafe_nand_init(void)
903{
904 return pci_register_driver(&cafe_nand_pci_driver);
905}
906
907static void cafe_nand_exit(void)
908{
909 pci_unregister_driver(&cafe_nand_pci_driver);
910}
911module_init(cafe_nand_init);
912module_exit(cafe_nand_exit);
913
914MODULE_LICENSE("GPL");
915MODULE_AUTHOR("David Woodhouse <dwmw2@infradead.org>");
David Woodhousef7c37d72007-01-23 15:44:10 +0800916MODULE_DESCRIPTION("NAND flash driver for OLPC CAFÉ chip");