blob: ece84fde76a6c4281e0250dba1515900d619034a [file] [log] [blame]
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __RADEON_H__
29#define __RADEON_H__
30
Jerome Glisse771fe6b2009-06-05 14:42:42 +020031/* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
Jerome Glissed39c3b82009-09-28 18:34:43 +020045/* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
Jerome Glisse771fe6b2009-06-05 14:42:42 +020063#include <asm/atomic.h>
64#include <linux/wait.h>
65#include <linux/list.h>
66#include <linux/kref.h>
67
Jerome Glisse4c788672009-11-20 14:29:23 +010068#include <ttm/ttm_bo_api.h>
69#include <ttm/ttm_bo_driver.h>
70#include <ttm/ttm_placement.h>
71#include <ttm/ttm_module.h>
72
Dave Airliec2142712009-09-22 08:50:10 +100073#include "radeon_family.h"
Jerome Glisse771fe6b2009-06-05 14:42:42 +020074#include "radeon_mode.h"
75#include "radeon_reg.h"
Jerome Glisse771fe6b2009-06-05 14:42:42 +020076
77/*
78 * Modules parameters.
79 */
80extern int radeon_no_wb;
81extern int radeon_modeset;
82extern int radeon_dynclks;
83extern int radeon_r4xx_atom;
84extern int radeon_agpmode;
85extern int radeon_vram_limit;
86extern int radeon_gart_size;
87extern int radeon_benchmarking;
Michel Dänzerecc0b322009-07-21 11:23:57 +020088extern int radeon_testing;
Jerome Glisse771fe6b2009-06-05 14:42:42 +020089extern int radeon_connector_table;
Dave Airlie4ce001a2009-08-13 16:32:14 +100090extern int radeon_tv;
Alex Deucherb27b6372009-12-09 17:44:25 -050091extern int radeon_new_pll;
Rafał Miłeckic913e232009-12-22 23:02:16 +010092extern int radeon_dynpm;
Christian Koenigdafc3bd2009-10-11 23:49:13 +020093extern int radeon_audio;
Jerome Glisse771fe6b2009-06-05 14:42:42 +020094
95/*
96 * Copy from radeon_drv.h so we don't have to include both and have conflicting
97 * symbol;
98 */
99#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
100#define RADEON_IB_POOL_SIZE 16
101#define RADEON_DEBUGFS_MAX_NUM_FILES 32
102#define RADEONFB_CONN_LIMIT 4
Yang Zhaof657c2a2009-09-15 12:21:01 +1000103#define RADEON_BIOS_NUM_SCRATCH 8
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200104
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200105/*
106 * Errata workarounds.
107 */
108enum radeon_pll_errata {
109 CHIP_ERRATA_R300_CG = 0x00000001,
110 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
111 CHIP_ERRATA_PLL_DELAY = 0x00000004
112};
113
114
115struct radeon_device;
116
117
118/*
119 * BIOS.
120 */
121bool radeon_get_bios(struct radeon_device *rdev);
122
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000123
124/*
125 * Dummy page
126 */
127struct radeon_dummy_page {
128 struct page *page;
129 dma_addr_t addr;
130};
131int radeon_dummy_page_init(struct radeon_device *rdev);
132void radeon_dummy_page_fini(struct radeon_device *rdev);
133
134
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200135/*
136 * Clocks
137 */
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200138struct radeon_clock {
139 struct radeon_pll p1pll;
140 struct radeon_pll p2pll;
141 struct radeon_pll spll;
142 struct radeon_pll mpll;
143 /* 10 Khz units */
144 uint32_t default_mclk;
145 uint32_t default_sclk;
146};
147
Rafał Miłecki74338742009-11-03 00:53:02 +0100148/*
149 * Power management
150 */
151int radeon_pm_init(struct radeon_device *rdev);
Rafał Miłeckic913e232009-12-22 23:02:16 +0100152void radeon_pm_compute_clocks(struct radeon_device *rdev);
Alex Deucher56278a82009-12-28 13:58:44 -0500153void radeon_combios_get_power_modes(struct radeon_device *rdev);
154void radeon_atombios_get_power_modes(struct radeon_device *rdev);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000155
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200156/*
157 * Fences.
158 */
159struct radeon_fence_driver {
160 uint32_t scratch_reg;
161 atomic_t seq;
162 uint32_t last_seq;
163 unsigned long count_timeout;
164 wait_queue_head_t queue;
165 rwlock_t lock;
166 struct list_head created;
167 struct list_head emited;
168 struct list_head signaled;
Jerome Glisse0a0c7592009-12-11 20:36:19 +0100169 bool initialized;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200170};
171
172struct radeon_fence {
173 struct radeon_device *rdev;
174 struct kref kref;
175 struct list_head list;
176 /* protected by radeon_fence.lock */
177 uint32_t seq;
178 unsigned long timeout;
179 bool emited;
180 bool signaled;
181};
182
183int radeon_fence_driver_init(struct radeon_device *rdev);
184void radeon_fence_driver_fini(struct radeon_device *rdev);
185int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence);
186int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence);
187void radeon_fence_process(struct radeon_device *rdev);
188bool radeon_fence_signaled(struct radeon_fence *fence);
189int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
190int radeon_fence_wait_next(struct radeon_device *rdev);
191int radeon_fence_wait_last(struct radeon_device *rdev);
192struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
193void radeon_fence_unref(struct radeon_fence **fence);
194
Dave Airliee024e112009-06-24 09:48:08 +1000195/*
196 * Tiling registers
197 */
198struct radeon_surface_reg {
Jerome Glisse4c788672009-11-20 14:29:23 +0100199 struct radeon_bo *bo;
Dave Airliee024e112009-06-24 09:48:08 +1000200};
201
202#define RADEON_GEM_MAX_SURFACES 8
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200203
204/*
Jerome Glisse4c788672009-11-20 14:29:23 +0100205 * TTM.
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200206 */
Jerome Glisse4c788672009-11-20 14:29:23 +0100207struct radeon_mman {
208 struct ttm_bo_global_ref bo_global_ref;
209 struct ttm_global_reference mem_global_ref;
Jerome Glisse4c788672009-11-20 14:29:23 +0100210 struct ttm_bo_device bdev;
Jerome Glisse0a0c7592009-12-11 20:36:19 +0100211 bool mem_global_referenced;
212 bool initialized;
Jerome Glisse4c788672009-11-20 14:29:23 +0100213};
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200214
Jerome Glisse4c788672009-11-20 14:29:23 +0100215struct radeon_bo {
216 /* Protected by gem.mutex */
217 struct list_head list;
218 /* Protected by tbo.reserved */
Jerome Glisse312ea8d2009-12-07 15:52:58 +0100219 u32 placements[3];
220 struct ttm_placement placement;
Jerome Glisse4c788672009-11-20 14:29:23 +0100221 struct ttm_buffer_object tbo;
222 struct ttm_bo_kmap_obj kmap;
223 unsigned pin_count;
224 void *kptr;
225 u32 tiling_flags;
226 u32 pitch;
227 int surface_reg;
228 /* Constant after initialization */
229 struct radeon_device *rdev;
230 struct drm_gem_object *gobj;
231};
232
233struct radeon_bo_list {
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200234 struct list_head list;
Jerome Glisse4c788672009-11-20 14:29:23 +0100235 struct radeon_bo *bo;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200236 uint64_t gpu_offset;
237 unsigned rdomain;
238 unsigned wdomain;
Jerome Glisse4c788672009-11-20 14:29:23 +0100239 u32 tiling_flags;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200240};
241
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200242/*
243 * GEM objects.
244 */
245struct radeon_gem {
Jerome Glisse4c788672009-11-20 14:29:23 +0100246 struct mutex mutex;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200247 struct list_head objects;
248};
249
250int radeon_gem_init(struct radeon_device *rdev);
251void radeon_gem_fini(struct radeon_device *rdev);
252int radeon_gem_object_create(struct radeon_device *rdev, int size,
Jerome Glisse4c788672009-11-20 14:29:23 +0100253 int alignment, int initial_domain,
254 bool discardable, bool kernel,
255 struct drm_gem_object **obj);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200256int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain,
257 uint64_t *gpu_addr);
258void radeon_gem_object_unpin(struct drm_gem_object *obj);
259
260
261/*
262 * GART structures, functions & helpers
263 */
264struct radeon_mc;
265
266struct radeon_gart_table_ram {
267 volatile uint32_t *ptr;
268};
269
270struct radeon_gart_table_vram {
Jerome Glisse4c788672009-11-20 14:29:23 +0100271 struct radeon_bo *robj;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200272 volatile uint32_t *ptr;
273};
274
275union radeon_gart_table {
276 struct radeon_gart_table_ram ram;
277 struct radeon_gart_table_vram vram;
278};
279
Matt Turnera77f1712009-10-14 00:34:41 -0400280#define RADEON_GPU_PAGE_SIZE 4096
281
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200282struct radeon_gart {
283 dma_addr_t table_addr;
284 unsigned num_gpu_pages;
285 unsigned num_cpu_pages;
286 unsigned table_size;
287 union radeon_gart_table table;
288 struct page **pages;
289 dma_addr_t *pages_addr;
290 bool ready;
291};
292
293int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
294void radeon_gart_table_ram_free(struct radeon_device *rdev);
295int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
296void radeon_gart_table_vram_free(struct radeon_device *rdev);
297int radeon_gart_init(struct radeon_device *rdev);
298void radeon_gart_fini(struct radeon_device *rdev);
299void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
300 int pages);
301int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
302 int pages, struct page **pagelist);
303
304
305/*
306 * GPU MC structures, functions & helpers
307 */
308struct radeon_mc {
309 resource_size_t aper_size;
310 resource_size_t aper_base;
311 resource_size_t agp_base;
Dave Airlie7a50f012009-07-21 20:39:30 +1000312 /* for some chips with <= 32MB we need to lie
313 * about vram size near mc fb location */
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000314 u64 mc_vram_size;
315 u64 gtt_location;
316 u64 gtt_size;
317 u64 gtt_start;
318 u64 gtt_end;
319 u64 vram_location;
320 u64 vram_start;
321 u64 vram_end;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200322 unsigned vram_width;
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000323 u64 real_vram_size;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200324 int vram_mtrr;
325 bool vram_is_ddr;
Alex Deucher06b64762010-01-05 11:27:29 -0500326 bool igp_sideport_enabled;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200327};
328
329int radeon_mc_setup(struct radeon_device *rdev);
Alex Deucher06b64762010-01-05 11:27:29 -0500330bool radeon_combios_sideport_present(struct radeon_device *rdev);
331bool radeon_atombios_sideport_present(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200332
333/*
334 * GPU scratch registers structures, functions & helpers
335 */
336struct radeon_scratch {
337 unsigned num_reg;
338 bool free[32];
339 uint32_t reg[32];
340};
341
342int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
343void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
344
345
346/*
347 * IRQS.
348 */
349struct radeon_irq {
350 bool installed;
351 bool sw_int;
352 /* FIXME: use a define max crtc rather than hardcode it */
353 bool crtc_vblank_int[2];
Alex Deucherb500f682009-12-03 13:08:53 -0500354 /* FIXME: use defines for max hpd/dacs */
355 bool hpd[6];
Dave Airlie1614f8b2009-12-01 16:04:56 +1000356 spinlock_t sw_lock;
357 int sw_refcount;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200358};
359
360int radeon_irq_kms_init(struct radeon_device *rdev);
361void radeon_irq_kms_fini(struct radeon_device *rdev);
Dave Airlie1614f8b2009-12-01 16:04:56 +1000362void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev);
363void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200364
365/*
366 * CP & ring.
367 */
368struct radeon_ib {
369 struct list_head list;
370 unsigned long idx;
371 uint64_t gpu_addr;
372 struct radeon_fence *fence;
Dave Airlie513bcb42009-09-23 16:56:27 +1000373 uint32_t *ptr;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200374 uint32_t length_dw;
375};
376
Dave Airlieecb114a2009-09-15 11:12:56 +1000377/*
378 * locking -
379 * mutex protects scheduled_ibs, ready, alloc_bm
380 */
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200381struct radeon_ib_pool {
382 struct mutex mutex;
Jerome Glisse4c788672009-11-20 14:29:23 +0100383 struct radeon_bo *robj;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200384 struct list_head scheduled_ibs;
385 struct radeon_ib ibs[RADEON_IB_POOL_SIZE];
386 bool ready;
387 DECLARE_BITMAP(alloc_bm, RADEON_IB_POOL_SIZE);
388};
389
390struct radeon_cp {
Jerome Glisse4c788672009-11-20 14:29:23 +0100391 struct radeon_bo *ring_obj;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200392 volatile uint32_t *ring;
393 unsigned rptr;
394 unsigned wptr;
395 unsigned wptr_old;
396 unsigned ring_size;
397 unsigned ring_free_dw;
398 int count_dw;
399 uint64_t gpu_addr;
400 uint32_t align_mask;
401 uint32_t ptr_mask;
402 struct mutex mutex;
403 bool ready;
404};
405
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500406/*
407 * R6xx+ IH ring
408 */
409struct r600_ih {
Jerome Glisse4c788672009-11-20 14:29:23 +0100410 struct radeon_bo *ring_obj;
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500411 volatile uint32_t *ring;
412 unsigned rptr;
413 unsigned wptr;
414 unsigned wptr_old;
415 unsigned ring_size;
416 uint64_t gpu_addr;
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500417 uint32_t ptr_mask;
418 spinlock_t lock;
419 bool enabled;
420};
421
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000422struct r600_blit {
Jerome Glisseff82f052010-01-22 15:19:00 +0100423 struct mutex mutex;
Jerome Glisse4c788672009-11-20 14:29:23 +0100424 struct radeon_bo *shader_obj;
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000425 u64 shader_gpu_addr;
426 u32 vs_offset, ps_offset;
427 u32 state_offset;
428 u32 state_len;
429 u32 vb_used, vb_total;
430 struct radeon_ib *vb_ib;
431};
432
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200433int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib);
434void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib);
435int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
436int radeon_ib_pool_init(struct radeon_device *rdev);
437void radeon_ib_pool_fini(struct radeon_device *rdev);
438int radeon_ib_test(struct radeon_device *rdev);
439/* Ring access between begin & end cannot sleep */
440void radeon_ring_free_size(struct radeon_device *rdev);
441int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw);
442void radeon_ring_unlock_commit(struct radeon_device *rdev);
443void radeon_ring_unlock_undo(struct radeon_device *rdev);
444int radeon_ring_test(struct radeon_device *rdev);
445int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size);
446void radeon_ring_fini(struct radeon_device *rdev);
447
448
449/*
450 * CS.
451 */
452struct radeon_cs_reloc {
453 struct drm_gem_object *gobj;
Jerome Glisse4c788672009-11-20 14:29:23 +0100454 struct radeon_bo *robj;
455 struct radeon_bo_list lobj;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200456 uint32_t handle;
457 uint32_t flags;
458};
459
460struct radeon_cs_chunk {
461 uint32_t chunk_id;
462 uint32_t length_dw;
Dave Airlie513bcb42009-09-23 16:56:27 +1000463 int kpage_idx[2];
464 uint32_t *kpage[2];
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200465 uint32_t *kdata;
Dave Airlie513bcb42009-09-23 16:56:27 +1000466 void __user *user_ptr;
467 int last_copied_page;
468 int last_page_index;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200469};
470
471struct radeon_cs_parser {
Jerome Glissec8c15ff2010-01-18 13:01:36 +0100472 struct device *dev;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200473 struct radeon_device *rdev;
474 struct drm_file *filp;
475 /* chunks */
476 unsigned nchunks;
477 struct radeon_cs_chunk *chunks;
478 uint64_t *chunks_array;
479 /* IB */
480 unsigned idx;
481 /* relocations */
482 unsigned nrelocs;
483 struct radeon_cs_reloc *relocs;
484 struct radeon_cs_reloc **relocs_ptr;
485 struct list_head validated;
486 /* indices of various chunks */
487 int chunk_ib_idx;
488 int chunk_relocs_idx;
489 struct radeon_ib *ib;
490 void *track;
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000491 unsigned family;
Dave Airlie513bcb42009-09-23 16:56:27 +1000492 int parser_error;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200493};
494
Dave Airlie513bcb42009-09-23 16:56:27 +1000495extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx);
496extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
497
498
499static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
500{
501 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
502 u32 pg_idx, pg_offset;
503 u32 idx_value = 0;
504 int new_page;
505
506 pg_idx = (idx * 4) / PAGE_SIZE;
507 pg_offset = (idx * 4) % PAGE_SIZE;
508
509 if (ibc->kpage_idx[0] == pg_idx)
510 return ibc->kpage[0][pg_offset/4];
511 if (ibc->kpage_idx[1] == pg_idx)
512 return ibc->kpage[1][pg_offset/4];
513
514 new_page = radeon_cs_update_pages(p, pg_idx);
515 if (new_page < 0) {
516 p->parser_error = new_page;
517 return 0;
518 }
519
520 idx_value = ibc->kpage[new_page][pg_offset/4];
521 return idx_value;
522}
523
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200524struct radeon_cs_packet {
525 unsigned idx;
526 unsigned type;
527 unsigned reg;
528 unsigned opcode;
529 int count;
530 unsigned one_reg_wr;
531};
532
533typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
534 struct radeon_cs_packet *pkt,
535 unsigned idx, unsigned reg);
536typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
537 struct radeon_cs_packet *pkt);
538
539
540/*
541 * AGP
542 */
543int radeon_agp_init(struct radeon_device *rdev);
Dave Airlie0ebf1712009-11-05 15:39:10 +1000544void radeon_agp_resume(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200545void radeon_agp_fini(struct radeon_device *rdev);
546
547
548/*
549 * Writeback
550 */
551struct radeon_wb {
Jerome Glisse4c788672009-11-20 14:29:23 +0100552 struct radeon_bo *wb_obj;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200553 volatile uint32_t *wb;
554 uint64_t gpu_addr;
555};
556
Jerome Glissec93bb852009-07-13 21:04:08 +0200557/**
558 * struct radeon_pm - power management datas
559 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
560 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
561 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
562 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
563 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
564 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
565 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
566 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
567 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
568 * @sclk: GPU clock Mhz (core bandwith depends of this clock)
569 * @needed_bandwidth: current bandwidth needs
570 *
571 * It keeps track of various data needed to take powermanagement decision.
572 * Bandwith need is used to determine minimun clock of the GPU and memory.
573 * Equation between gpu/memory clock and available bandwidth is hw dependent
574 * (type of memory, bus size, efficiency, ...)
575 */
Rafał Miłeckic913e232009-12-22 23:02:16 +0100576enum radeon_pm_state {
577 PM_STATE_DISABLED,
578 PM_STATE_MINIMUM,
579 PM_STATE_PAUSED,
580 PM_STATE_ACTIVE
581};
582enum radeon_pm_action {
583 PM_ACTION_NONE,
584 PM_ACTION_MINIMUM,
585 PM_ACTION_DOWNCLOCK,
586 PM_ACTION_UPCLOCK
587};
Alex Deucher56278a82009-12-28 13:58:44 -0500588
589enum radeon_voltage_type {
590 VOLTAGE_NONE = 0,
591 VOLTAGE_GPIO,
592 VOLTAGE_VDDC,
593 VOLTAGE_SW
594};
595
Alex Deucher0ec0e742009-12-23 13:21:58 -0500596enum radeon_pm_state_type {
597 POWER_STATE_TYPE_DEFAULT,
598 POWER_STATE_TYPE_POWERSAVE,
599 POWER_STATE_TYPE_BATTERY,
600 POWER_STATE_TYPE_BALANCED,
601 POWER_STATE_TYPE_PERFORMANCE,
602};
603
Alex Deucher516d0e42009-12-23 14:28:05 -0500604enum radeon_pm_clock_mode_type {
605 POWER_MODE_TYPE_DEFAULT,
606 POWER_MODE_TYPE_LOW,
607 POWER_MODE_TYPE_MID,
608 POWER_MODE_TYPE_HIGH,
609};
610
Alex Deucher56278a82009-12-28 13:58:44 -0500611struct radeon_voltage {
612 enum radeon_voltage_type type;
613 /* gpio voltage */
614 struct radeon_gpio_rec gpio;
615 u32 delay; /* delay in usec from voltage drop to sclk change */
616 bool active_high; /* voltage drop is active when bit is high */
617 /* VDDC voltage */
618 u8 vddc_id; /* index into vddc voltage table */
619 u8 vddci_id; /* index into vddci voltage table */
620 bool vddci_enabled;
621 /* r6xx+ sw */
622 u32 voltage;
623};
624
625struct radeon_pm_non_clock_info {
626 /* pcie lanes */
627 int pcie_lanes;
628 /* standardized non-clock flags */
629 u32 flags;
630};
631
632struct radeon_pm_clock_info {
633 /* memory clock */
634 u32 mclk;
635 /* engine clock */
636 u32 sclk;
637 /* voltage info */
638 struct radeon_voltage voltage;
639 /* standardized clock flags - not sure we'll need these */
640 u32 flags;
641};
642
643struct radeon_power_state {
Alex Deucher0ec0e742009-12-23 13:21:58 -0500644 enum radeon_pm_state_type type;
Alex Deucher56278a82009-12-28 13:58:44 -0500645 /* XXX: use a define for num clock modes */
646 struct radeon_pm_clock_info clock_info[8];
647 /* number of valid clock modes in this power state */
648 int num_clock_modes;
649 /* currently selected clock mode */
650 struct radeon_pm_clock_info *current_clock_mode;
Alex Deucher516d0e42009-12-23 14:28:05 -0500651 struct radeon_pm_clock_info *requested_clock_mode;
Alex Deucher56278a82009-12-28 13:58:44 -0500652 struct radeon_pm_clock_info *default_clock_mode;
653 /* non clock info about this state */
654 struct radeon_pm_non_clock_info non_clock_info;
655 bool voltage_drop_active;
656};
657
Jerome Glissec93bb852009-07-13 21:04:08 +0200658struct radeon_pm {
Rafał Miłeckic913e232009-12-22 23:02:16 +0100659 struct mutex mutex;
660 struct work_struct reclock_work;
661 struct delayed_work idle_work;
662 enum radeon_pm_state state;
663 enum radeon_pm_action planned_action;
664 unsigned long action_timeout;
665 bool downclocked;
666 bool vblank_callback;
667 int active_crtcs;
668 int req_vblank;
669 uint32_t min_gpu_engine_clock;
670 uint32_t min_gpu_memory_clock;
671 uint32_t min_mode_engine_clock;
672 uint32_t min_mode_memory_clock;
Jerome Glissec93bb852009-07-13 21:04:08 +0200673 fixed20_12 max_bandwidth;
674 fixed20_12 igp_sideport_mclk;
675 fixed20_12 igp_system_mclk;
676 fixed20_12 igp_ht_link_clk;
677 fixed20_12 igp_ht_link_width;
678 fixed20_12 k8_bandwidth;
679 fixed20_12 sideport_bandwidth;
680 fixed20_12 ht_bandwidth;
681 fixed20_12 core_bandwidth;
682 fixed20_12 sclk;
683 fixed20_12 needed_bandwidth;
Alex Deucher56278a82009-12-28 13:58:44 -0500684 /* XXX: use a define for num power modes */
685 struct radeon_power_state power_state[8];
686 /* number of valid power states */
687 int num_power_states;
688 struct radeon_power_state *current_power_state;
Alex Deucher516d0e42009-12-23 14:28:05 -0500689 struct radeon_power_state *requested_power_state;
Alex Deucher56278a82009-12-28 13:58:44 -0500690 struct radeon_power_state *default_power_state;
Jerome Glissec93bb852009-07-13 21:04:08 +0200691};
692
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200693
694/*
695 * Benchmarking
696 */
697void radeon_benchmark(struct radeon_device *rdev);
698
699
700/*
Michel Dänzerecc0b322009-07-21 11:23:57 +0200701 * Testing
702 */
703void radeon_test_moves(struct radeon_device *rdev);
704
705
706/*
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200707 * Debugfs
708 */
709int radeon_debugfs_add_files(struct radeon_device *rdev,
710 struct drm_info_list *files,
711 unsigned nfiles);
712int radeon_debugfs_fence_init(struct radeon_device *rdev);
713int r100_debugfs_rbbm_init(struct radeon_device *rdev);
714int r100_debugfs_cp_init(struct radeon_device *rdev);
715
716
717/*
718 * ASIC specific functions.
719 */
720struct radeon_asic {
Jerome Glisse068a1172009-06-17 13:28:30 +0200721 int (*init)(struct radeon_device *rdev);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000722 void (*fini)(struct radeon_device *rdev);
723 int (*resume)(struct radeon_device *rdev);
724 int (*suspend)(struct radeon_device *rdev);
Dave Airlie28d52042009-09-21 14:33:58 +1000725 void (*vga_set_state)(struct radeon_device *rdev, bool state);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200726 int (*gpu_reset)(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200727 void (*gart_tlb_flush)(struct radeon_device *rdev);
728 int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr);
729 int (*cp_init)(struct radeon_device *rdev, unsigned ring_size);
730 void (*cp_fini)(struct radeon_device *rdev);
731 void (*cp_disable)(struct radeon_device *rdev);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000732 void (*cp_commit)(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200733 void (*ring_start)(struct radeon_device *rdev);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000734 int (*ring_test)(struct radeon_device *rdev);
735 void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200736 int (*irq_set)(struct radeon_device *rdev);
737 int (*irq_process)(struct radeon_device *rdev);
Michel Dänzer7ed220d2009-08-13 11:10:51 +0200738 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200739 void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence);
740 int (*cs_parse)(struct radeon_cs_parser *p);
741 int (*copy_blit)(struct radeon_device *rdev,
742 uint64_t src_offset,
743 uint64_t dst_offset,
744 unsigned num_pages,
745 struct radeon_fence *fence);
746 int (*copy_dma)(struct radeon_device *rdev,
747 uint64_t src_offset,
748 uint64_t dst_offset,
749 unsigned num_pages,
750 struct radeon_fence *fence);
751 int (*copy)(struct radeon_device *rdev,
752 uint64_t src_offset,
753 uint64_t dst_offset,
754 unsigned num_pages,
755 struct radeon_fence *fence);
Rafał Miłecki74338742009-11-03 00:53:02 +0100756 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200757 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
Rafał Miłecki74338742009-11-03 00:53:02 +0100758 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200759 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
Alex Deucherc836a412009-12-23 10:07:50 -0500760 int (*get_pcie_lanes)(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200761 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
762 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
Dave Airliee024e112009-06-24 09:48:08 +1000763 int (*set_surface_reg)(struct radeon_device *rdev, int reg,
764 uint32_t tiling_flags, uint32_t pitch,
765 uint32_t offset, uint32_t obj_size);
766 int (*clear_surface_reg)(struct radeon_device *rdev, int reg);
Jerome Glissec93bb852009-07-13 21:04:08 +0200767 void (*bandwidth_update)(struct radeon_device *rdev);
Alex Deucher429770b2009-12-04 15:26:55 -0500768 void (*hpd_init)(struct radeon_device *rdev);
769 void (*hpd_fini)(struct radeon_device *rdev);
770 bool (*hpd_sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
771 void (*hpd_set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
Jerome Glisse062b3892010-02-04 20:36:39 +0100772 /* ioctl hw specific callback. Some hw might want to perform special
773 * operation on specific ioctl. For instance on wait idle some hw
774 * might want to perform and HDP flush through MMIO as it seems that
775 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
776 * through ring.
777 */
778 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200779};
780
Jerome Glisse21f9a432009-09-11 15:55:33 +0200781/*
782 * Asic structures
783 */
Dave Airlie551ebd82009-09-01 15:25:57 +1000784struct r100_asic {
785 const unsigned *reg_safe_bm;
786 unsigned reg_safe_bm_size;
Jerome Glissecafe6602010-01-07 12:39:21 +0100787 u32 hdp_cntl;
Dave Airlie551ebd82009-09-01 15:25:57 +1000788};
789
Jerome Glisse21f9a432009-09-11 15:55:33 +0200790struct r300_asic {
791 const unsigned *reg_safe_bm;
792 unsigned reg_safe_bm_size;
Corbin Simpson62cdc0c2010-01-06 19:28:48 +0100793 u32 resync_scratch;
Jerome Glissecafe6602010-01-07 12:39:21 +0100794 u32 hdp_cntl;
Jerome Glisse21f9a432009-09-11 15:55:33 +0200795};
796
797struct r600_asic {
798 unsigned max_pipes;
799 unsigned max_tile_pipes;
800 unsigned max_simds;
801 unsigned max_backends;
802 unsigned max_gprs;
803 unsigned max_threads;
804 unsigned max_stack_entries;
805 unsigned max_hw_contexts;
806 unsigned max_gs_threads;
807 unsigned sx_max_export_size;
808 unsigned sx_max_export_pos_size;
809 unsigned sx_max_export_smx_size;
810 unsigned sq_num_cf_insts;
811};
812
813struct rv770_asic {
814 unsigned max_pipes;
815 unsigned max_tile_pipes;
816 unsigned max_simds;
817 unsigned max_backends;
818 unsigned max_gprs;
819 unsigned max_threads;
820 unsigned max_stack_entries;
821 unsigned max_hw_contexts;
822 unsigned max_gs_threads;
823 unsigned sx_max_export_size;
824 unsigned sx_max_export_pos_size;
825 unsigned sx_max_export_smx_size;
826 unsigned sq_num_cf_insts;
827 unsigned sx_num_of_sets;
828 unsigned sc_prim_fifo_size;
829 unsigned sc_hiz_tile_fifo_size;
830 unsigned sc_earlyz_tile_fifo_fize;
831};
832
Jerome Glisse068a1172009-06-17 13:28:30 +0200833union radeon_asic_config {
834 struct r300_asic r300;
Dave Airlie551ebd82009-09-01 15:25:57 +1000835 struct r100_asic r100;
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000836 struct r600_asic r600;
837 struct rv770_asic rv770;
Jerome Glisse068a1172009-06-17 13:28:30 +0200838};
839
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200840
841/*
842 * IOCTL.
843 */
844int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
845 struct drm_file *filp);
846int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
847 struct drm_file *filp);
848int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
849 struct drm_file *file_priv);
850int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
851 struct drm_file *file_priv);
852int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
853 struct drm_file *file_priv);
854int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
855 struct drm_file *file_priv);
856int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
857 struct drm_file *filp);
858int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
859 struct drm_file *filp);
860int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
861 struct drm_file *filp);
862int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
863 struct drm_file *filp);
864int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
Dave Airliee024e112009-06-24 09:48:08 +1000865int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
866 struct drm_file *filp);
867int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
868 struct drm_file *filp);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200869
870
871/*
872 * Core structure, functions and helpers.
873 */
874typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
875typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
876
877struct radeon_device {
Jerome Glisse9f022dd2009-09-11 15:35:22 +0200878 struct device *dev;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200879 struct drm_device *ddev;
880 struct pci_dev *pdev;
881 /* ASIC */
Jerome Glisse068a1172009-06-17 13:28:30 +0200882 union radeon_asic_config config;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200883 enum radeon_family family;
884 unsigned long flags;
885 int usec_timeout;
886 enum radeon_pll_errata pll_errata;
887 int num_gb_pipes;
Alex Deucherf779b3e2009-08-19 19:11:39 -0400888 int num_z_pipes;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200889 int disp_priority;
890 /* BIOS */
891 uint8_t *bios;
892 bool is_atom_bios;
893 uint16_t bios_header_start;
Jerome Glisse4c788672009-11-20 14:29:23 +0100894 struct radeon_bo *stollen_vga_memory;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200895 struct fb_info *fbdev_info;
Jerome Glisse4c788672009-11-20 14:29:23 +0100896 struct radeon_bo *fbdev_rbo;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200897 struct radeon_framebuffer *fbdev_rfb;
898 /* Register mmio */
Dave Airlie4c9bc752009-06-29 18:29:12 +1000899 resource_size_t rmmio_base;
900 resource_size_t rmmio_size;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200901 void *rmmio;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200902 radeon_rreg_t mc_rreg;
903 radeon_wreg_t mc_wreg;
904 radeon_rreg_t pll_rreg;
905 radeon_wreg_t pll_wreg;
Dave Airliede1b2892009-08-12 18:43:14 +1000906 uint32_t pcie_reg_mask;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200907 radeon_rreg_t pciep_rreg;
908 radeon_wreg_t pciep_wreg;
909 struct radeon_clock clock;
910 struct radeon_mc mc;
911 struct radeon_gart gart;
912 struct radeon_mode_info mode_info;
913 struct radeon_scratch scratch;
914 struct radeon_mman mman;
915 struct radeon_fence_driver fence_drv;
916 struct radeon_cp cp;
917 struct radeon_ib_pool ib_pool;
918 struct radeon_irq irq;
919 struct radeon_asic *asic;
920 struct radeon_gem gem;
Jerome Glissec93bb852009-07-13 21:04:08 +0200921 struct radeon_pm pm;
Yang Zhaof657c2a2009-09-15 12:21:01 +1000922 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200923 struct mutex cs_mutex;
924 struct radeon_wb wb;
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000925 struct radeon_dummy_page dummy_page;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200926 bool gpu_lockup;
927 bool shutdown;
928 bool suspend;
Dave Airliead49f502009-07-10 22:36:26 +1000929 bool need_dma32;
Jerome Glisse733289c2009-09-16 15:24:21 +0200930 bool accel_working;
Dave Airliee024e112009-06-24 09:48:08 +1000931 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000932 const struct firmware *me_fw; /* all family ME firmware */
933 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500934 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000935 struct r600_blit r600_blit;
Alex Deucher3e5cb982009-10-16 12:21:24 -0400936 int msi_enabled; /* msi enabled */
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500937 struct r600_ih ih; /* r6/700 interrupt ring */
Alex Deucherd4877cf2009-12-04 16:56:37 -0500938 struct workqueue_struct *wq;
939 struct work_struct hotplug_work;
Alex Deucher18917b62010-02-01 16:02:25 -0500940 int num_crtc; /* number of crtcs */
Alex Deucher40bacf12009-12-23 03:23:21 -0500941 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
Christian Koenigdafc3bd2009-10-11 23:49:13 +0200942
943 /* audio stuff */
944 struct timer_list audio_timer;
945 int audio_channels;
946 int audio_rate;
947 int audio_bits_per_sample;
948 uint8_t audio_status_bits;
949 uint8_t audio_category_code;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200950};
951
952int radeon_device_init(struct radeon_device *rdev,
953 struct drm_device *ddev,
954 struct pci_dev *pdev,
955 uint32_t flags);
956void radeon_device_fini(struct radeon_device *rdev);
957int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
958
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000959/* r600 blit */
960int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes);
961void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence);
962void r600_kms_blit_copy(struct radeon_device *rdev,
963 u64 src_gpu_addr, u64 dst_gpu_addr,
964 int size_bytes);
965
Dave Airliede1b2892009-08-12 18:43:14 +1000966static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
967{
Alex Deucher07bec2d2010-01-13 19:09:12 -0500968 if (reg < rdev->rmmio_size)
Dave Airliede1b2892009-08-12 18:43:14 +1000969 return readl(((void __iomem *)rdev->rmmio) + reg);
970 else {
971 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
972 return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
973 }
974}
975
976static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
977{
Alex Deucher07bec2d2010-01-13 19:09:12 -0500978 if (reg < rdev->rmmio_size)
Dave Airliede1b2892009-08-12 18:43:14 +1000979 writel(v, ((void __iomem *)rdev->rmmio) + reg);
980 else {
981 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
982 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
983 }
984}
985
Jerome Glisse4c788672009-11-20 14:29:23 +0100986/*
987 * Cast helper
988 */
989#define to_radeon_fence(p) ((struct radeon_fence *)(p))
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200990
991/*
992 * Registers read & write functions.
993 */
994#define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg))
995#define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg))
Dave Airliede1b2892009-08-12 18:43:14 +1000996#define RREG32(reg) r100_mm_rreg(rdev, (reg))
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000997#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg)))
Dave Airliede1b2892009-08-12 18:43:14 +1000998#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200999#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1000#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1001#define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
1002#define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
1003#define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
1004#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
Dave Airliede1b2892009-08-12 18:43:14 +10001005#define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
1006#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001007#define WREG32_P(reg, val, mask) \
1008 do { \
1009 uint32_t tmp_ = RREG32(reg); \
1010 tmp_ &= (mask); \
1011 tmp_ |= ((val) & ~(mask)); \
1012 WREG32(reg, tmp_); \
1013 } while (0)
1014#define WREG32_PLL_P(reg, val, mask) \
1015 do { \
1016 uint32_t tmp_ = RREG32_PLL(reg); \
1017 tmp_ &= (mask); \
1018 tmp_ |= ((val) & ~(mask)); \
1019 WREG32_PLL(reg, tmp_); \
1020 } while (0)
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001021#define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg)))
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001022
Dave Airliede1b2892009-08-12 18:43:14 +10001023/*
1024 * Indirect registers accessor
1025 */
1026static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
1027{
1028 uint32_t r;
1029
1030 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1031 r = RREG32(RADEON_PCIE_DATA);
1032 return r;
1033}
1034
1035static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1036{
1037 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1038 WREG32(RADEON_PCIE_DATA, (v));
1039}
1040
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001041void r100_pll_errata_after_index(struct radeon_device *rdev);
1042
1043
1044/*
1045 * ASICs helpers.
1046 */
Dave Airlieb995e432009-07-14 02:02:32 +10001047#define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
1048 (rdev->pdev->device == 0x5969))
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001049#define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
1050 (rdev->family == CHIP_RV200) || \
1051 (rdev->family == CHIP_RS100) || \
1052 (rdev->family == CHIP_RS200) || \
1053 (rdev->family == CHIP_RV250) || \
1054 (rdev->family == CHIP_RV280) || \
1055 (rdev->family == CHIP_RS300))
1056#define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
1057 (rdev->family == CHIP_RV350) || \
1058 (rdev->family == CHIP_R350) || \
1059 (rdev->family == CHIP_RV380) || \
1060 (rdev->family == CHIP_R420) || \
1061 (rdev->family == CHIP_R423) || \
1062 (rdev->family == CHIP_RV410) || \
1063 (rdev->family == CHIP_RS400) || \
1064 (rdev->family == CHIP_RS480))
1065#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
1066#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
1067#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
1068
1069
1070/*
1071 * BIOS helpers.
1072 */
1073#define RBIOS8(i) (rdev->bios[i])
1074#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1075#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1076
1077int radeon_combios_init(struct radeon_device *rdev);
1078void radeon_combios_fini(struct radeon_device *rdev);
1079int radeon_atombios_init(struct radeon_device *rdev);
1080void radeon_atombios_fini(struct radeon_device *rdev);
1081
1082
1083/*
1084 * RING helpers.
1085 */
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001086static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
1087{
1088#if DRM_DEBUG_CODE
1089 if (rdev->cp.count_dw <= 0) {
1090 DRM_ERROR("radeon: writting more dword to ring than expected !\n");
1091 }
1092#endif
1093 rdev->cp.ring[rdev->cp.wptr++] = v;
1094 rdev->cp.wptr &= rdev->cp.ptr_mask;
1095 rdev->cp.count_dw--;
1096 rdev->cp.ring_free_dw--;
1097}
1098
1099
1100/*
1101 * ASICs macro.
1102 */
Jerome Glisse068a1172009-06-17 13:28:30 +02001103#define radeon_init(rdev) (rdev)->asic->init((rdev))
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001104#define radeon_fini(rdev) (rdev)->asic->fini((rdev))
1105#define radeon_resume(rdev) (rdev)->asic->resume((rdev))
1106#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001107#define radeon_cs_parse(p) rdev->asic->cs_parse((p))
Dave Airlie28d52042009-09-21 14:33:58 +10001108#define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001109#define radeon_gpu_reset(rdev) (rdev)->asic->gpu_reset((rdev))
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001110#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev))
1111#define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p))
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001112#define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev))
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001113#define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev))
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001114#define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev))
1115#define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib))
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001116#define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev))
1117#define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev))
Michel Dänzer7ed220d2009-08-13 11:10:51 +02001118#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc))
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001119#define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence))
1120#define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f))
1121#define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f))
1122#define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f))
Rafał Miłecki74338742009-11-03 00:53:02 +01001123#define radeon_get_engine_clock(rdev) (rdev)->asic->get_engine_clock((rdev))
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001124#define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
Rafał Miłecki74338742009-11-03 00:53:02 +01001125#define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev))
Rafał Miłecki93e7de72009-11-04 23:34:10 +01001126#define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_memory_clock((rdev), (e))
Alex Deucherc836a412009-12-23 10:07:50 -05001127#define radeon_get_pcie_lanes(rdev) (rdev)->asic->get_pcie_lanes((rdev))
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001128#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l))
1129#define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e))
Dave Airliee024e112009-06-24 09:48:08 +10001130#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s)))
1131#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
Jerome Glissec93bb852009-07-13 21:04:08 +02001132#define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
Alex Deucher429770b2009-12-04 15:26:55 -05001133#define radeon_hpd_init(rdev) (rdev)->asic->hpd_init((rdev))
1134#define radeon_hpd_fini(rdev) (rdev)->asic->hpd_fini((rdev))
1135#define radeon_hpd_sense(rdev, hpd) (rdev)->asic->hpd_sense((rdev), (hpd))
1136#define radeon_hpd_set_polarity(rdev, hpd) (rdev)->asic->hpd_set_polarity((rdev), (hpd))
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001137
Jerome Glisse6cf8a3f2009-09-10 21:46:48 +02001138/* Common functions */
Jerome Glisse700a0cc2010-01-13 15:16:38 +01001139/* AGP */
1140extern void radeon_agp_disable(struct radeon_device *rdev);
Jerome Glisse4aac0472009-09-14 18:29:49 +02001141extern int radeon_gart_table_vram_pin(struct radeon_device *rdev);
Jerome Glisse21f9a432009-09-11 15:55:33 +02001142extern int radeon_modeset_init(struct radeon_device *rdev);
1143extern void radeon_modeset_fini(struct radeon_device *rdev);
Jerome Glisse9f022dd2009-09-11 15:35:22 +02001144extern bool radeon_card_posted(struct radeon_device *rdev);
Dave Airlie72542d72009-12-01 14:06:31 +10001145extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
Jerome Glisse21f9a432009-09-11 15:55:33 +02001146extern int radeon_clocks_init(struct radeon_device *rdev);
1147extern void radeon_clocks_fini(struct radeon_device *rdev);
1148extern void radeon_scratch_init(struct radeon_device *rdev);
1149extern void radeon_surface_init(struct radeon_device *rdev);
1150extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
Jerome Glisseca6ffc62009-10-01 10:20:52 +02001151extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
Jerome Glissed39c3b82009-09-28 18:34:43 +02001152extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
Jerome Glisse312ea8d2009-12-07 15:52:58 +01001153extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
Jerome Glissed03d8582009-12-14 21:02:09 +01001154extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
Jerome Glisse6cf8a3f2009-09-10 21:46:48 +02001155
Jerome Glissea18d7ea2009-09-09 22:23:27 +02001156/* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */
Jerome Glisse9f022dd2009-09-11 15:35:22 +02001157struct r100_mc_save {
1158 u32 GENMO_WT;
1159 u32 CRTC_EXT_CNTL;
1160 u32 CRTC_GEN_CNTL;
1161 u32 CRTC2_GEN_CNTL;
1162 u32 CUR_OFFSET;
1163 u32 CUR2_OFFSET;
1164};
1165extern void r100_cp_disable(struct radeon_device *rdev);
1166extern int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
1167extern void r100_cp_fini(struct radeon_device *rdev);
Jerome Glisse21f9a432009-09-11 15:55:33 +02001168extern void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
Jerome Glisse4aac0472009-09-14 18:29:49 +02001169extern int r100_pci_gart_init(struct radeon_device *rdev);
1170extern void r100_pci_gart_fini(struct radeon_device *rdev);
Jerome Glisse21f9a432009-09-11 15:55:33 +02001171extern int r100_pci_gart_enable(struct radeon_device *rdev);
1172extern void r100_pci_gart_disable(struct radeon_device *rdev);
1173extern int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
Jerome Glisse9f022dd2009-09-11 15:35:22 +02001174extern int r100_debugfs_mc_info_init(struct radeon_device *rdev);
1175extern int r100_gui_wait_for_idle(struct radeon_device *rdev);
1176extern void r100_ib_fini(struct radeon_device *rdev);
1177extern int r100_ib_init(struct radeon_device *rdev);
1178extern void r100_irq_disable(struct radeon_device *rdev);
1179extern int r100_irq_set(struct radeon_device *rdev);
1180extern void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save);
1181extern void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save);
Jerome Glisse21f9a432009-09-11 15:55:33 +02001182extern void r100_vram_init_sizes(struct radeon_device *rdev);
Jerome Glisse9f022dd2009-09-11 15:35:22 +02001183extern void r100_wb_disable(struct radeon_device *rdev);
1184extern void r100_wb_fini(struct radeon_device *rdev);
1185extern int r100_wb_init(struct radeon_device *rdev);
Jerome Glissed39c3b82009-09-28 18:34:43 +02001186extern void r100_hdp_reset(struct radeon_device *rdev);
1187extern int r100_rb2d_reset(struct radeon_device *rdev);
1188extern int r100_cp_reset(struct radeon_device *rdev);
Jerome Glisseca6ffc62009-10-01 10:20:52 +02001189extern void r100_vga_render_disable(struct radeon_device *rdev);
Jerome Glisse207bf9e2009-09-30 15:35:32 +02001190extern int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1191 struct radeon_cs_packet *pkt,
Jerome Glisse4c788672009-11-20 14:29:23 +01001192 struct radeon_bo *robj);
Jerome Glisse207bf9e2009-09-30 15:35:32 +02001193extern int r100_cs_parse_packet0(struct radeon_cs_parser *p,
1194 struct radeon_cs_packet *pkt,
1195 const unsigned *auth, unsigned n,
1196 radeon_packet0_check_t check);
1197extern int r100_cs_packet_parse(struct radeon_cs_parser *p,
1198 struct radeon_cs_packet *pkt,
1199 unsigned idx);
Dave Airlie17e15b02009-11-05 15:36:53 +10001200extern void r100_enable_bm(struct radeon_device *rdev);
Alex Deucher92cde002009-12-04 10:55:12 -05001201extern void r100_set_common_regs(struct radeon_device *rdev);
Jerome Glisse9f022dd2009-09-11 15:35:22 +02001202
Jerome Glissed4550902009-10-01 10:12:06 +02001203/* rv200,rv250,rv280 */
1204extern void r200_set_safe_registers(struct radeon_device *rdev);
Jerome Glisse9f022dd2009-09-11 15:35:22 +02001205
1206/* r300,r350,rv350,rv370,rv380 */
1207extern void r300_set_reg_safe(struct radeon_device *rdev);
1208extern void r300_mc_program(struct radeon_device *rdev);
1209extern void r300_vram_info(struct radeon_device *rdev);
Jerome Glisseca6ffc62009-10-01 10:20:52 +02001210extern void r300_clock_startup(struct radeon_device *rdev);
1211extern int r300_mc_wait_for_idle(struct radeon_device *rdev);
Jerome Glisse4aac0472009-09-14 18:29:49 +02001212extern int rv370_pcie_gart_init(struct radeon_device *rdev);
1213extern void rv370_pcie_gart_fini(struct radeon_device *rdev);
1214extern int rv370_pcie_gart_enable(struct radeon_device *rdev);
Jerome Glisse9f022dd2009-09-11 15:35:22 +02001215extern void rv370_pcie_gart_disable(struct radeon_device *rdev);
Jerome Glissea18d7ea2009-09-09 22:23:27 +02001216
Jerome Glisse905b6822009-09-09 22:24:20 +02001217/* r420,r423,rv410 */
Jerome Glissed39c3b82009-09-28 18:34:43 +02001218extern int r420_mc_init(struct radeon_device *rdev);
Jerome Glisse21f9a432009-09-11 15:55:33 +02001219extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg);
1220extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
Jerome Glisse9f022dd2009-09-11 15:35:22 +02001221extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev);
Jerome Glissed39c3b82009-09-28 18:34:43 +02001222extern void r420_pipes_init(struct radeon_device *rdev);
Jerome Glisse905b6822009-09-09 22:24:20 +02001223
Jerome Glisse21f9a432009-09-11 15:55:33 +02001224/* rv515 */
Jerome Glissed39c3b82009-09-28 18:34:43 +02001225struct rv515_mc_save {
1226 u32 d1vga_control;
1227 u32 d2vga_control;
1228 u32 vga_render_control;
1229 u32 vga_hdp_control;
1230 u32 d1crtc_control;
1231 u32 d2crtc_control;
1232};
Jerome Glisse21f9a432009-09-11 15:55:33 +02001233extern void rv515_bandwidth_avivo_update(struct radeon_device *rdev);
Jerome Glissed39c3b82009-09-28 18:34:43 +02001234extern void rv515_vga_render_disable(struct radeon_device *rdev);
1235extern void rv515_set_safe_registers(struct radeon_device *rdev);
Jerome Glissef0ed1f62009-09-28 20:39:19 +02001236extern void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save);
1237extern void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save);
1238extern void rv515_clock_startup(struct radeon_device *rdev);
1239extern void rv515_debugfs(struct radeon_device *rdev);
1240extern int rv515_suspend(struct radeon_device *rdev);
Jerome Glisse21f9a432009-09-11 15:55:33 +02001241
Jerome Glisse3bc68532009-10-01 09:39:24 +02001242/* rs400 */
1243extern int rs400_gart_init(struct radeon_device *rdev);
1244extern int rs400_gart_enable(struct radeon_device *rdev);
1245extern void rs400_gart_adjust_size(struct radeon_device *rdev);
1246extern void rs400_gart_disable(struct radeon_device *rdev);
1247extern void rs400_gart_fini(struct radeon_device *rdev);
1248
1249/* rs600 */
1250extern void rs600_set_safe_registers(struct radeon_device *rdev);
Jerome Glisseac447df2009-09-30 22:18:43 +02001251extern int rs600_irq_set(struct radeon_device *rdev);
1252extern void rs600_irq_disable(struct radeon_device *rdev);
Jerome Glisse3bc68532009-10-01 09:39:24 +02001253
Jerome Glisse21f9a432009-09-11 15:55:33 +02001254/* rs690, rs740 */
1255extern void rs690_line_buffer_adjust(struct radeon_device *rdev,
1256 struct drm_display_mode *mode1,
1257 struct drm_display_mode *mode2);
1258
1259/* r600, rv610, rv630, rv620, rv635, rv670, rs780, rs880 */
1260extern bool r600_card_posted(struct radeon_device *rdev);
1261extern void r600_cp_stop(struct radeon_device *rdev);
1262extern void r600_ring_init(struct radeon_device *rdev, unsigned ring_size);
1263extern int r600_cp_resume(struct radeon_device *rdev);
Jerome Glisse655efd32010-02-02 11:51:45 +01001264extern void r600_cp_fini(struct radeon_device *rdev);
Jerome Glisse21f9a432009-09-11 15:55:33 +02001265extern int r600_count_pipe_bits(uint32_t val);
1266extern int r600_gart_clear_page(struct radeon_device *rdev, int i);
1267extern int r600_mc_wait_for_idle(struct radeon_device *rdev);
Jerome Glisse4aac0472009-09-14 18:29:49 +02001268extern int r600_pcie_gart_init(struct radeon_device *rdev);
Jerome Glisse21f9a432009-09-11 15:55:33 +02001269extern void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
1270extern int r600_ib_test(struct radeon_device *rdev);
1271extern int r600_ring_test(struct radeon_device *rdev);
Jerome Glisse21f9a432009-09-11 15:55:33 +02001272extern void r600_wb_fini(struct radeon_device *rdev);
Jerome Glisse81cc35b2009-10-01 18:02:12 +02001273extern int r600_wb_enable(struct radeon_device *rdev);
1274extern void r600_wb_disable(struct radeon_device *rdev);
Jerome Glisse21f9a432009-09-11 15:55:33 +02001275extern void r600_scratch_init(struct radeon_device *rdev);
1276extern int r600_blit_init(struct radeon_device *rdev);
1277extern void r600_blit_fini(struct radeon_device *rdev);
Alex Deucherd8f60cf2009-12-01 13:43:46 -05001278extern int r600_init_microcode(struct radeon_device *rdev);
Dave Airliefe62e1a2009-09-21 14:06:30 +10001279extern int r600_gpu_reset(struct radeon_device *rdev);
Alex Deucherd8f60cf2009-12-01 13:43:46 -05001280/* r600 irq */
1281extern int r600_irq_init(struct radeon_device *rdev);
1282extern void r600_irq_fini(struct radeon_device *rdev);
1283extern void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size);
1284extern int r600_irq_set(struct radeon_device *rdev);
Jerome Glisse0c452492010-01-15 14:44:37 +01001285extern void r600_irq_suspend(struct radeon_device *rdev);
1286/* r600 audio */
Christian Koenigdafc3bd2009-10-11 23:49:13 +02001287extern int r600_audio_init(struct radeon_device *rdev);
1288extern int r600_audio_tmds_index(struct drm_encoder *encoder);
1289extern void r600_audio_set_clock(struct drm_encoder *encoder, int clock);
1290extern void r600_audio_fini(struct radeon_device *rdev);
1291extern void r600_hdmi_init(struct drm_encoder *encoder);
1292extern void r600_hdmi_enable(struct drm_encoder *encoder, int enable);
1293extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
1294extern int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder);
1295extern void r600_hdmi_update_audio_settings(struct drm_encoder *encoder,
1296 int channels,
1297 int rate,
1298 int bps,
1299 uint8_t status_bits,
1300 uint8_t category_code);
1301
Jerome Glisse4c788672009-11-20 14:29:23 +01001302#include "radeon_object.h"
1303
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001304#endif