blob: cf1213de7865ecb95e20c9d273a57ec1981203a7 [file] [log] [blame]
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001/*
2 * Driver for the Atmel Extensible DMA Controller (aka XDMAC on AT91 systems)
3 *
4 * Copyright (C) 2014 Atmel Corporation
5 *
6 * Author: Ludovic Desroches <ludovic.desroches@atmel.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License version 2 as published by
10 * the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program. If not, see <http://www.gnu.org/licenses/>.
19 */
20
21#include <asm/barrier.h>
22#include <dt-bindings/dma/at91.h>
23#include <linux/clk.h>
24#include <linux/dmaengine.h>
25#include <linux/dmapool.h>
26#include <linux/interrupt.h>
27#include <linux/irq.h>
Ludovic Desroches6d3a7d92015-01-27 16:30:32 +010028#include <linux/kernel.h>
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +020029#include <linux/list.h>
30#include <linux/module.h>
31#include <linux/of_dma.h>
32#include <linux/of_platform.h>
33#include <linux/platform_device.h>
34#include <linux/pm.h>
35
36#include "dmaengine.h"
37
38/* Global registers */
39#define AT_XDMAC_GTYPE 0x00 /* Global Type Register */
40#define AT_XDMAC_NB_CH(i) (((i) & 0x1F) + 1) /* Number of Channels Minus One */
41#define AT_XDMAC_FIFO_SZ(i) (((i) >> 5) & 0x7FF) /* Number of Bytes */
42#define AT_XDMAC_NB_REQ(i) ((((i) >> 16) & 0x3F) + 1) /* Number of Peripheral Requests Minus One */
43#define AT_XDMAC_GCFG 0x04 /* Global Configuration Register */
44#define AT_XDMAC_GWAC 0x08 /* Global Weighted Arbiter Configuration Register */
45#define AT_XDMAC_GIE 0x0C /* Global Interrupt Enable Register */
46#define AT_XDMAC_GID 0x10 /* Global Interrupt Disable Register */
47#define AT_XDMAC_GIM 0x14 /* Global Interrupt Mask Register */
48#define AT_XDMAC_GIS 0x18 /* Global Interrupt Status Register */
49#define AT_XDMAC_GE 0x1C /* Global Channel Enable Register */
50#define AT_XDMAC_GD 0x20 /* Global Channel Disable Register */
51#define AT_XDMAC_GS 0x24 /* Global Channel Status Register */
52#define AT_XDMAC_GRS 0x28 /* Global Channel Read Suspend Register */
53#define AT_XDMAC_GWS 0x2C /* Global Write Suspend Register */
54#define AT_XDMAC_GRWS 0x30 /* Global Channel Read Write Suspend Register */
55#define AT_XDMAC_GRWR 0x34 /* Global Channel Read Write Resume Register */
56#define AT_XDMAC_GSWR 0x38 /* Global Channel Software Request Register */
57#define AT_XDMAC_GSWS 0x3C /* Global channel Software Request Status Register */
58#define AT_XDMAC_GSWF 0x40 /* Global Channel Software Flush Request Register */
59#define AT_XDMAC_VERSION 0xFFC /* XDMAC Version Register */
60
61/* Channel relative registers offsets */
62#define AT_XDMAC_CIE 0x00 /* Channel Interrupt Enable Register */
63#define AT_XDMAC_CIE_BIE BIT(0) /* End of Block Interrupt Enable Bit */
64#define AT_XDMAC_CIE_LIE BIT(1) /* End of Linked List Interrupt Enable Bit */
65#define AT_XDMAC_CIE_DIE BIT(2) /* End of Disable Interrupt Enable Bit */
66#define AT_XDMAC_CIE_FIE BIT(3) /* End of Flush Interrupt Enable Bit */
67#define AT_XDMAC_CIE_RBEIE BIT(4) /* Read Bus Error Interrupt Enable Bit */
68#define AT_XDMAC_CIE_WBEIE BIT(5) /* Write Bus Error Interrupt Enable Bit */
69#define AT_XDMAC_CIE_ROIE BIT(6) /* Request Overflow Interrupt Enable Bit */
70#define AT_XDMAC_CID 0x04 /* Channel Interrupt Disable Register */
71#define AT_XDMAC_CID_BID BIT(0) /* End of Block Interrupt Disable Bit */
72#define AT_XDMAC_CID_LID BIT(1) /* End of Linked List Interrupt Disable Bit */
73#define AT_XDMAC_CID_DID BIT(2) /* End of Disable Interrupt Disable Bit */
74#define AT_XDMAC_CID_FID BIT(3) /* End of Flush Interrupt Disable Bit */
75#define AT_XDMAC_CID_RBEID BIT(4) /* Read Bus Error Interrupt Disable Bit */
76#define AT_XDMAC_CID_WBEID BIT(5) /* Write Bus Error Interrupt Disable Bit */
77#define AT_XDMAC_CID_ROID BIT(6) /* Request Overflow Interrupt Disable Bit */
78#define AT_XDMAC_CIM 0x08 /* Channel Interrupt Mask Register */
79#define AT_XDMAC_CIM_BIM BIT(0) /* End of Block Interrupt Mask Bit */
80#define AT_XDMAC_CIM_LIM BIT(1) /* End of Linked List Interrupt Mask Bit */
81#define AT_XDMAC_CIM_DIM BIT(2) /* End of Disable Interrupt Mask Bit */
82#define AT_XDMAC_CIM_FIM BIT(3) /* End of Flush Interrupt Mask Bit */
83#define AT_XDMAC_CIM_RBEIM BIT(4) /* Read Bus Error Interrupt Mask Bit */
84#define AT_XDMAC_CIM_WBEIM BIT(5) /* Write Bus Error Interrupt Mask Bit */
85#define AT_XDMAC_CIM_ROIM BIT(6) /* Request Overflow Interrupt Mask Bit */
86#define AT_XDMAC_CIS 0x0C /* Channel Interrupt Status Register */
87#define AT_XDMAC_CIS_BIS BIT(0) /* End of Block Interrupt Status Bit */
88#define AT_XDMAC_CIS_LIS BIT(1) /* End of Linked List Interrupt Status Bit */
89#define AT_XDMAC_CIS_DIS BIT(2) /* End of Disable Interrupt Status Bit */
90#define AT_XDMAC_CIS_FIS BIT(3) /* End of Flush Interrupt Status Bit */
91#define AT_XDMAC_CIS_RBEIS BIT(4) /* Read Bus Error Interrupt Status Bit */
92#define AT_XDMAC_CIS_WBEIS BIT(5) /* Write Bus Error Interrupt Status Bit */
93#define AT_XDMAC_CIS_ROIS BIT(6) /* Request Overflow Interrupt Status Bit */
94#define AT_XDMAC_CSA 0x10 /* Channel Source Address Register */
95#define AT_XDMAC_CDA 0x14 /* Channel Destination Address Register */
96#define AT_XDMAC_CNDA 0x18 /* Channel Next Descriptor Address Register */
97#define AT_XDMAC_CNDA_NDAIF(i) ((i) & 0x1) /* Channel x Next Descriptor Interface */
98#define AT_XDMAC_CNDA_NDA(i) ((i) & 0xfffffffc) /* Channel x Next Descriptor Address */
99#define AT_XDMAC_CNDC 0x1C /* Channel Next Descriptor Control Register */
100#define AT_XDMAC_CNDC_NDE (0x1 << 0) /* Channel x Next Descriptor Enable */
101#define AT_XDMAC_CNDC_NDSUP (0x1 << 1) /* Channel x Next Descriptor Source Update */
102#define AT_XDMAC_CNDC_NDDUP (0x1 << 2) /* Channel x Next Descriptor Destination Update */
103#define AT_XDMAC_CNDC_NDVIEW_NDV0 (0x0 << 3) /* Channel x Next Descriptor View 0 */
104#define AT_XDMAC_CNDC_NDVIEW_NDV1 (0x1 << 3) /* Channel x Next Descriptor View 1 */
105#define AT_XDMAC_CNDC_NDVIEW_NDV2 (0x2 << 3) /* Channel x Next Descriptor View 2 */
106#define AT_XDMAC_CNDC_NDVIEW_NDV3 (0x3 << 3) /* Channel x Next Descriptor View 3 */
107#define AT_XDMAC_CUBC 0x20 /* Channel Microblock Control Register */
108#define AT_XDMAC_CBC 0x24 /* Channel Block Control Register */
109#define AT_XDMAC_CC 0x28 /* Channel Configuration Register */
110#define AT_XDMAC_CC_TYPE (0x1 << 0) /* Channel Transfer Type */
111#define AT_XDMAC_CC_TYPE_MEM_TRAN (0x0 << 0) /* Memory to Memory Transfer */
112#define AT_XDMAC_CC_TYPE_PER_TRAN (0x1 << 0) /* Peripheral to Memory or Memory to Peripheral Transfer */
113#define AT_XDMAC_CC_MBSIZE_MASK (0x3 << 1)
114#define AT_XDMAC_CC_MBSIZE_SINGLE (0x0 << 1)
115#define AT_XDMAC_CC_MBSIZE_FOUR (0x1 << 1)
116#define AT_XDMAC_CC_MBSIZE_EIGHT (0x2 << 1)
117#define AT_XDMAC_CC_MBSIZE_SIXTEEN (0x3 << 1)
118#define AT_XDMAC_CC_DSYNC (0x1 << 4) /* Channel Synchronization */
119#define AT_XDMAC_CC_DSYNC_PER2MEM (0x0 << 4)
120#define AT_XDMAC_CC_DSYNC_MEM2PER (0x1 << 4)
121#define AT_XDMAC_CC_PROT (0x1 << 5) /* Channel Protection */
122#define AT_XDMAC_CC_PROT_SEC (0x0 << 5)
123#define AT_XDMAC_CC_PROT_UNSEC (0x1 << 5)
124#define AT_XDMAC_CC_SWREQ (0x1 << 6) /* Channel Software Request Trigger */
125#define AT_XDMAC_CC_SWREQ_HWR_CONNECTED (0x0 << 6)
126#define AT_XDMAC_CC_SWREQ_SWR_CONNECTED (0x1 << 6)
127#define AT_XDMAC_CC_MEMSET (0x1 << 7) /* Channel Fill Block of memory */
128#define AT_XDMAC_CC_MEMSET_NORMAL_MODE (0x0 << 7)
129#define AT_XDMAC_CC_MEMSET_HW_MODE (0x1 << 7)
130#define AT_XDMAC_CC_CSIZE(i) ((0x7 & (i)) << 8) /* Channel Chunk Size */
131#define AT_XDMAC_CC_DWIDTH_OFFSET 11
132#define AT_XDMAC_CC_DWIDTH_MASK (0x3 << AT_XDMAC_CC_DWIDTH_OFFSET)
133#define AT_XDMAC_CC_DWIDTH(i) ((0x3 & (i)) << AT_XDMAC_CC_DWIDTH_OFFSET) /* Channel Data Width */
134#define AT_XDMAC_CC_DWIDTH_BYTE 0x0
135#define AT_XDMAC_CC_DWIDTH_HALFWORD 0x1
136#define AT_XDMAC_CC_DWIDTH_WORD 0x2
137#define AT_XDMAC_CC_DWIDTH_DWORD 0x3
138#define AT_XDMAC_CC_SIF(i) ((0x1 & (i)) << 13) /* Channel Source Interface Identifier */
139#define AT_XDMAC_CC_DIF(i) ((0x1 & (i)) << 14) /* Channel Destination Interface Identifier */
140#define AT_XDMAC_CC_SAM_MASK (0x3 << 16) /* Channel Source Addressing Mode */
141#define AT_XDMAC_CC_SAM_FIXED_AM (0x0 << 16)
142#define AT_XDMAC_CC_SAM_INCREMENTED_AM (0x1 << 16)
143#define AT_XDMAC_CC_SAM_UBS_AM (0x2 << 16)
144#define AT_XDMAC_CC_SAM_UBS_DS_AM (0x3 << 16)
145#define AT_XDMAC_CC_DAM_MASK (0x3 << 18) /* Channel Source Addressing Mode */
146#define AT_XDMAC_CC_DAM_FIXED_AM (0x0 << 18)
147#define AT_XDMAC_CC_DAM_INCREMENTED_AM (0x1 << 18)
148#define AT_XDMAC_CC_DAM_UBS_AM (0x2 << 18)
149#define AT_XDMAC_CC_DAM_UBS_DS_AM (0x3 << 18)
150#define AT_XDMAC_CC_INITD (0x1 << 21) /* Channel Initialization Terminated (read only) */
151#define AT_XDMAC_CC_INITD_TERMINATED (0x0 << 21)
152#define AT_XDMAC_CC_INITD_IN_PROGRESS (0x1 << 21)
153#define AT_XDMAC_CC_RDIP (0x1 << 22) /* Read in Progress (read only) */
154#define AT_XDMAC_CC_RDIP_DONE (0x0 << 22)
155#define AT_XDMAC_CC_RDIP_IN_PROGRESS (0x1 << 22)
156#define AT_XDMAC_CC_WRIP (0x1 << 23) /* Write in Progress (read only) */
157#define AT_XDMAC_CC_WRIP_DONE (0x0 << 23)
158#define AT_XDMAC_CC_WRIP_IN_PROGRESS (0x1 << 23)
159#define AT_XDMAC_CC_PERID(i) (0x7f & (h) << 24) /* Channel Peripheral Identifier */
160#define AT_XDMAC_CDS_MSP 0x2C /* Channel Data Stride Memory Set Pattern */
161#define AT_XDMAC_CSUS 0x30 /* Channel Source Microblock Stride */
162#define AT_XDMAC_CDUS 0x34 /* Channel Destination Microblock Stride */
163
164#define AT_XDMAC_CHAN_REG_BASE 0x50 /* Channel registers base address */
165
166/* Microblock control members */
167#define AT_XDMAC_MBR_UBC_UBLEN_MAX 0xFFFFFFUL /* Maximum Microblock Length */
168#define AT_XDMAC_MBR_UBC_NDE (0x1 << 24) /* Next Descriptor Enable */
169#define AT_XDMAC_MBR_UBC_NSEN (0x1 << 25) /* Next Descriptor Source Update */
170#define AT_XDMAC_MBR_UBC_NDEN (0x1 << 26) /* Next Descriptor Destination Update */
171#define AT_XDMAC_MBR_UBC_NDV0 (0x0 << 27) /* Next Descriptor View 0 */
172#define AT_XDMAC_MBR_UBC_NDV1 (0x1 << 27) /* Next Descriptor View 1 */
173#define AT_XDMAC_MBR_UBC_NDV2 (0x2 << 27) /* Next Descriptor View 2 */
174#define AT_XDMAC_MBR_UBC_NDV3 (0x3 << 27) /* Next Descriptor View 3 */
175
176#define AT_XDMAC_MAX_CHAN 0x20
Ludovic Desroches765c37d2015-06-08 10:33:15 +0200177#define AT_XDMAC_MAX_CSIZE 16 /* 16 data */
178#define AT_XDMAC_MAX_DWIDTH 8 /* 64 bits */
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200179
Ludovic Desroches8ac82f82014-11-17 14:42:44 +0100180#define AT_XDMAC_DMA_BUSWIDTHS\
181 (BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) |\
182 BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |\
183 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |\
184 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) |\
185 BIT(DMA_SLAVE_BUSWIDTH_8_BYTES))
186
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200187enum atc_status {
188 AT_XDMAC_CHAN_IS_CYCLIC = 0,
189 AT_XDMAC_CHAN_IS_PAUSED,
190};
191
192/* ----- Channels ----- */
193struct at_xdmac_chan {
194 struct dma_chan chan;
195 void __iomem *ch_regs;
196 u32 mask; /* Channel Mask */
Ludovic Desroches765c37d2015-06-08 10:33:15 +0200197 u32 cfg; /* Channel Configuration Register */
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200198 u8 perid; /* Peripheral ID */
199 u8 perif; /* Peripheral Interface */
200 u8 memif; /* Memory Interface */
Ludovic Desroches734bb9a2015-01-27 16:30:30 +0100201 u32 save_cc;
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200202 u32 save_cim;
203 u32 save_cnda;
204 u32 save_cndc;
205 unsigned long status;
206 struct tasklet_struct tasklet;
Ludovic Desroches765c37d2015-06-08 10:33:15 +0200207 struct dma_slave_config sconfig;
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200208
209 spinlock_t lock;
210
211 struct list_head xfers_list;
212 struct list_head free_descs_list;
213};
214
215
216/* ----- Controller ----- */
217struct at_xdmac {
218 struct dma_device dma;
219 void __iomem *regs;
220 int irq;
221 struct clk *clk;
222 u32 save_gim;
223 u32 save_gs;
224 struct dma_pool *at_xdmac_desc_pool;
225 struct at_xdmac_chan chan[0];
226};
227
228
229/* ----- Descriptors ----- */
230
231/* Linked List Descriptor */
232struct at_xdmac_lld {
233 dma_addr_t mbr_nda; /* Next Descriptor Member */
234 u32 mbr_ubc; /* Microblock Control Member */
235 dma_addr_t mbr_sa; /* Source Address Member */
236 dma_addr_t mbr_da; /* Destination Address Member */
237 u32 mbr_cfg; /* Configuration Register */
Maxime Ripardee0fe352015-05-07 17:38:08 +0200238 u32 mbr_bc; /* Block Control Register */
239 u32 mbr_ds; /* Data Stride Register */
240 u32 mbr_sus; /* Source Microblock Stride Register */
241 u32 mbr_dus; /* Destination Microblock Stride Register */
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200242};
243
244
245struct at_xdmac_desc {
246 struct at_xdmac_lld lld;
247 enum dma_transfer_direction direction;
248 struct dma_async_tx_descriptor tx_dma_desc;
249 struct list_head desc_node;
250 /* Following members are only used by the first descriptor */
251 bool active_xfer;
252 unsigned int xfer_size;
253 struct list_head descs_list;
254 struct list_head xfer_node;
255};
256
257static inline void __iomem *at_xdmac_chan_reg_base(struct at_xdmac *atxdmac, unsigned int chan_nb)
258{
259 return atxdmac->regs + (AT_XDMAC_CHAN_REG_BASE + chan_nb * 0x40);
260}
261
Ludovic Desroches6e5ae292014-11-13 11:52:39 +0100262#define at_xdmac_read(atxdmac, reg) readl_relaxed((atxdmac)->regs + (reg))
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200263#define at_xdmac_write(atxdmac, reg, value) \
Ludovic Desroches6e5ae292014-11-13 11:52:39 +0100264 writel_relaxed((value), (atxdmac)->regs + (reg))
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200265
Ludovic Desroches6e5ae292014-11-13 11:52:39 +0100266#define at_xdmac_chan_read(atchan, reg) readl_relaxed((atchan)->ch_regs + (reg))
267#define at_xdmac_chan_write(atchan, reg, value) writel_relaxed((value), (atchan)->ch_regs + (reg))
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200268
269static inline struct at_xdmac_chan *to_at_xdmac_chan(struct dma_chan *dchan)
270{
271 return container_of(dchan, struct at_xdmac_chan, chan);
272}
273
274static struct device *chan2dev(struct dma_chan *chan)
275{
276 return &chan->dev->device;
277}
278
279static inline struct at_xdmac *to_at_xdmac(struct dma_device *ddev)
280{
281 return container_of(ddev, struct at_xdmac, dma);
282}
283
284static inline struct at_xdmac_desc *txd_to_at_desc(struct dma_async_tx_descriptor *txd)
285{
286 return container_of(txd, struct at_xdmac_desc, tx_dma_desc);
287}
288
289static inline int at_xdmac_chan_is_cyclic(struct at_xdmac_chan *atchan)
290{
291 return test_bit(AT_XDMAC_CHAN_IS_CYCLIC, &atchan->status);
292}
293
294static inline int at_xdmac_chan_is_paused(struct at_xdmac_chan *atchan)
295{
296 return test_bit(AT_XDMAC_CHAN_IS_PAUSED, &atchan->status);
297}
298
299static inline int at_xdmac_csize(u32 maxburst)
300{
301 int csize;
302
303 csize = ffs(maxburst) - 1;
304 if (csize > 4)
305 csize = -EINVAL;
306
307 return csize;
308};
309
310static inline u8 at_xdmac_get_dwidth(u32 cfg)
311{
312 return (cfg & AT_XDMAC_CC_DWIDTH_MASK) >> AT_XDMAC_CC_DWIDTH_OFFSET;
313};
314
315static unsigned int init_nr_desc_per_channel = 64;
316module_param(init_nr_desc_per_channel, uint, 0644);
317MODULE_PARM_DESC(init_nr_desc_per_channel,
318 "initial descriptors per channel (default: 64)");
319
320
321static bool at_xdmac_chan_is_enabled(struct at_xdmac_chan *atchan)
322{
323 return at_xdmac_chan_read(atchan, AT_XDMAC_GS) & atchan->mask;
324}
325
326static void at_xdmac_off(struct at_xdmac *atxdmac)
327{
328 at_xdmac_write(atxdmac, AT_XDMAC_GD, -1L);
329
330 /* Wait that all chans are disabled. */
331 while (at_xdmac_read(atxdmac, AT_XDMAC_GS))
332 cpu_relax();
333
334 at_xdmac_write(atxdmac, AT_XDMAC_GID, -1L);
335}
336
337/* Call with lock hold. */
338static void at_xdmac_start_xfer(struct at_xdmac_chan *atchan,
339 struct at_xdmac_desc *first)
340{
341 struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device);
342 u32 reg;
343
344 dev_vdbg(chan2dev(&atchan->chan), "%s: desc 0x%p\n", __func__, first);
345
346 if (at_xdmac_chan_is_enabled(atchan))
347 return;
348
349 /* Set transfer as active to not try to start it again. */
350 first->active_xfer = true;
351
352 /* Tell xdmac where to get the first descriptor. */
353 reg = AT_XDMAC_CNDA_NDA(first->tx_dma_desc.phys)
354 | AT_XDMAC_CNDA_NDAIF(atchan->memif);
355 at_xdmac_chan_write(atchan, AT_XDMAC_CNDA, reg);
356
357 /*
Ludovic Desroches6d3a7d92015-01-27 16:30:32 +0100358 * When doing non cyclic transfer we need to use the next
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200359 * descriptor view 2 since some fields of the configuration register
360 * depend on transfer size and src/dest addresses.
361 */
Ludovic Desroches6d3a7d92015-01-27 16:30:32 +0100362 if (at_xdmac_chan_is_cyclic(atchan)) {
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200363 reg = AT_XDMAC_CNDC_NDVIEW_NDV1;
Ludovic Desrochesbe835072015-01-27 16:30:31 +0100364 at_xdmac_chan_write(atchan, AT_XDMAC_CC, first->lld.mbr_cfg);
Maxime Ripardee0fe352015-05-07 17:38:08 +0200365 } else if (first->lld.mbr_ubc & AT_XDMAC_MBR_UBC_NDV3) {
366 reg = AT_XDMAC_CNDC_NDVIEW_NDV3;
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200367 } else {
368 /*
369 * No need to write AT_XDMAC_CC reg, it will be done when the
370 * descriptor is fecthed.
371 */
372 reg = AT_XDMAC_CNDC_NDVIEW_NDV2;
373 }
374
375 reg |= AT_XDMAC_CNDC_NDDUP
376 | AT_XDMAC_CNDC_NDSUP
377 | AT_XDMAC_CNDC_NDE;
378 at_xdmac_chan_write(atchan, AT_XDMAC_CNDC, reg);
379
380 dev_vdbg(chan2dev(&atchan->chan),
381 "%s: CC=0x%08x CNDA=0x%08x, CNDC=0x%08x, CSA=0x%08x, CDA=0x%08x, CUBC=0x%08x\n",
382 __func__, at_xdmac_chan_read(atchan, AT_XDMAC_CC),
383 at_xdmac_chan_read(atchan, AT_XDMAC_CNDA),
384 at_xdmac_chan_read(atchan, AT_XDMAC_CNDC),
385 at_xdmac_chan_read(atchan, AT_XDMAC_CSA),
386 at_xdmac_chan_read(atchan, AT_XDMAC_CDA),
387 at_xdmac_chan_read(atchan, AT_XDMAC_CUBC));
388
389 at_xdmac_chan_write(atchan, AT_XDMAC_CID, 0xffffffff);
390 reg = AT_XDMAC_CIE_RBEIE | AT_XDMAC_CIE_WBEIE | AT_XDMAC_CIE_ROIE;
391 /*
392 * There is no end of list when doing cyclic dma, we need to get
393 * an interrupt after each periods.
394 */
395 if (at_xdmac_chan_is_cyclic(atchan))
396 at_xdmac_chan_write(atchan, AT_XDMAC_CIE,
397 reg | AT_XDMAC_CIE_BIE);
398 else
399 at_xdmac_chan_write(atchan, AT_XDMAC_CIE,
400 reg | AT_XDMAC_CIE_LIE);
401 at_xdmac_write(atxdmac, AT_XDMAC_GIE, atchan->mask);
402 dev_vdbg(chan2dev(&atchan->chan),
403 "%s: enable channel (0x%08x)\n", __func__, atchan->mask);
404 wmb();
405 at_xdmac_write(atxdmac, AT_XDMAC_GE, atchan->mask);
406
407 dev_vdbg(chan2dev(&atchan->chan),
408 "%s: CC=0x%08x CNDA=0x%08x, CNDC=0x%08x, CSA=0x%08x, CDA=0x%08x, CUBC=0x%08x\n",
409 __func__, at_xdmac_chan_read(atchan, AT_XDMAC_CC),
410 at_xdmac_chan_read(atchan, AT_XDMAC_CNDA),
411 at_xdmac_chan_read(atchan, AT_XDMAC_CNDC),
412 at_xdmac_chan_read(atchan, AT_XDMAC_CSA),
413 at_xdmac_chan_read(atchan, AT_XDMAC_CDA),
414 at_xdmac_chan_read(atchan, AT_XDMAC_CUBC));
415
416}
417
418static dma_cookie_t at_xdmac_tx_submit(struct dma_async_tx_descriptor *tx)
419{
420 struct at_xdmac_desc *desc = txd_to_at_desc(tx);
421 struct at_xdmac_chan *atchan = to_at_xdmac_chan(tx->chan);
422 dma_cookie_t cookie;
Ludovic Desroches4c374fc2015-06-08 10:33:14 +0200423 unsigned long irqflags;
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200424
Ludovic Desroches4c374fc2015-06-08 10:33:14 +0200425 spin_lock_irqsave(&atchan->lock, irqflags);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200426 cookie = dma_cookie_assign(tx);
427
428 dev_vdbg(chan2dev(tx->chan), "%s: atchan 0x%p, add desc 0x%p to xfers_list\n",
429 __func__, atchan, desc);
430 list_add_tail(&desc->xfer_node, &atchan->xfers_list);
431 if (list_is_singular(&atchan->xfers_list))
432 at_xdmac_start_xfer(atchan, desc);
433
Ludovic Desroches4c374fc2015-06-08 10:33:14 +0200434 spin_unlock_irqrestore(&atchan->lock, irqflags);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200435 return cookie;
436}
437
438static struct at_xdmac_desc *at_xdmac_alloc_desc(struct dma_chan *chan,
439 gfp_t gfp_flags)
440{
441 struct at_xdmac_desc *desc;
442 struct at_xdmac *atxdmac = to_at_xdmac(chan->device);
443 dma_addr_t phys;
444
445 desc = dma_pool_alloc(atxdmac->at_xdmac_desc_pool, gfp_flags, &phys);
446 if (desc) {
447 memset(desc, 0, sizeof(*desc));
448 INIT_LIST_HEAD(&desc->descs_list);
449 dma_async_tx_descriptor_init(&desc->tx_dma_desc, chan);
450 desc->tx_dma_desc.tx_submit = at_xdmac_tx_submit;
451 desc->tx_dma_desc.phys = phys;
452 }
453
454 return desc;
455}
456
457/* Call must be protected by lock. */
458static struct at_xdmac_desc *at_xdmac_get_desc(struct at_xdmac_chan *atchan)
459{
460 struct at_xdmac_desc *desc;
461
462 if (list_empty(&atchan->free_descs_list)) {
463 desc = at_xdmac_alloc_desc(&atchan->chan, GFP_NOWAIT);
464 } else {
465 desc = list_first_entry(&atchan->free_descs_list,
466 struct at_xdmac_desc, desc_node);
467 list_del(&desc->desc_node);
468 desc->active_xfer = false;
469 }
470
471 return desc;
472}
473
Maxime Ripard0d0ee752015-05-07 17:38:10 +0200474static void at_xdmac_queue_desc(struct dma_chan *chan,
475 struct at_xdmac_desc *prev,
476 struct at_xdmac_desc *desc)
477{
478 if (!prev || !desc)
479 return;
480
481 prev->lld.mbr_nda = desc->tx_dma_desc.phys;
482 prev->lld.mbr_ubc |= AT_XDMAC_MBR_UBC_NDE;
483
484 dev_dbg(chan2dev(chan), "%s: chain lld: prev=0x%p, mbr_nda=%pad\n",
485 __func__, prev, &prev->lld.mbr_nda);
486}
487
Maxime Ripard6007ccb2015-05-07 17:38:11 +0200488static inline void at_xdmac_increment_block_count(struct dma_chan *chan,
489 struct at_xdmac_desc *desc)
490{
491 if (!desc)
492 return;
493
494 desc->lld.mbr_bc++;
495
496 dev_dbg(chan2dev(chan),
497 "%s: incrementing the block count of the desc 0x%p\n",
498 __func__, desc);
499}
500
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200501static struct dma_chan *at_xdmac_xlate(struct of_phandle_args *dma_spec,
502 struct of_dma *of_dma)
503{
504 struct at_xdmac *atxdmac = of_dma->of_dma_data;
505 struct at_xdmac_chan *atchan;
506 struct dma_chan *chan;
507 struct device *dev = atxdmac->dma.dev;
508
509 if (dma_spec->args_count != 1) {
510 dev_err(dev, "dma phandler args: bad number of args\n");
511 return NULL;
512 }
513
514 chan = dma_get_any_slave_channel(&atxdmac->dma);
515 if (!chan) {
516 dev_err(dev, "can't get a dma channel\n");
517 return NULL;
518 }
519
520 atchan = to_at_xdmac_chan(chan);
521 atchan->memif = AT91_XDMAC_DT_GET_MEM_IF(dma_spec->args[0]);
522 atchan->perif = AT91_XDMAC_DT_GET_PER_IF(dma_spec->args[0]);
523 atchan->perid = AT91_XDMAC_DT_GET_PERID(dma_spec->args[0]);
524 dev_dbg(dev, "chan dt cfg: memif=%u perif=%u perid=%u\n",
525 atchan->memif, atchan->perif, atchan->perid);
526
527 return chan;
528}
529
Ludovic Desroches765c37d2015-06-08 10:33:15 +0200530static int at_xdmac_compute_chan_conf(struct dma_chan *chan,
531 enum dma_transfer_direction direction)
532{
533 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
534 int csize, dwidth;
535
536 if (direction == DMA_DEV_TO_MEM) {
537 atchan->cfg =
538 AT91_XDMAC_DT_PERID(atchan->perid)
539 | AT_XDMAC_CC_DAM_INCREMENTED_AM
540 | AT_XDMAC_CC_SAM_FIXED_AM
541 | AT_XDMAC_CC_DIF(atchan->memif)
542 | AT_XDMAC_CC_SIF(atchan->perif)
543 | AT_XDMAC_CC_SWREQ_HWR_CONNECTED
544 | AT_XDMAC_CC_DSYNC_PER2MEM
545 | AT_XDMAC_CC_MBSIZE_SIXTEEN
546 | AT_XDMAC_CC_TYPE_PER_TRAN;
547 csize = ffs(atchan->sconfig.src_maxburst) - 1;
548 if (csize < 0) {
549 dev_err(chan2dev(chan), "invalid src maxburst value\n");
550 return -EINVAL;
551 }
552 atchan->cfg |= AT_XDMAC_CC_CSIZE(csize);
553 dwidth = ffs(atchan->sconfig.src_addr_width) - 1;
554 if (dwidth < 0) {
555 dev_err(chan2dev(chan), "invalid src addr width value\n");
556 return -EINVAL;
557 }
558 atchan->cfg |= AT_XDMAC_CC_DWIDTH(dwidth);
559 } else if (direction == DMA_MEM_TO_DEV) {
560 atchan->cfg =
561 AT91_XDMAC_DT_PERID(atchan->perid)
562 | AT_XDMAC_CC_DAM_FIXED_AM
563 | AT_XDMAC_CC_SAM_INCREMENTED_AM
564 | AT_XDMAC_CC_DIF(atchan->perif)
565 | AT_XDMAC_CC_SIF(atchan->memif)
566 | AT_XDMAC_CC_SWREQ_HWR_CONNECTED
567 | AT_XDMAC_CC_DSYNC_MEM2PER
568 | AT_XDMAC_CC_MBSIZE_SIXTEEN
569 | AT_XDMAC_CC_TYPE_PER_TRAN;
570 csize = ffs(atchan->sconfig.dst_maxburst) - 1;
571 if (csize < 0) {
572 dev_err(chan2dev(chan), "invalid src maxburst value\n");
573 return -EINVAL;
574 }
575 atchan->cfg |= AT_XDMAC_CC_CSIZE(csize);
576 dwidth = ffs(atchan->sconfig.dst_addr_width) - 1;
577 if (dwidth < 0) {
578 dev_err(chan2dev(chan), "invalid dst addr width value\n");
579 return -EINVAL;
580 }
581 atchan->cfg |= AT_XDMAC_CC_DWIDTH(dwidth);
582 }
583
584 dev_dbg(chan2dev(chan), "%s: cfg=0x%08x\n", __func__, atchan->cfg);
585
586 return 0;
587}
588
589/*
590 * Only check that maxburst and addr width values are supported by the
591 * the controller but not that the configuration is good to perform the
592 * transfer since we don't know the direction at this stage.
593 */
594static int at_xdmac_check_slave_config(struct dma_slave_config *sconfig)
595{
596 if ((sconfig->src_maxburst > AT_XDMAC_MAX_CSIZE)
597 || (sconfig->dst_maxburst > AT_XDMAC_MAX_CSIZE))
598 return -EINVAL;
599
600 if ((sconfig->src_addr_width > AT_XDMAC_MAX_DWIDTH)
601 || (sconfig->dst_addr_width > AT_XDMAC_MAX_DWIDTH))
602 return -EINVAL;
603
604 return 0;
605}
606
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200607static int at_xdmac_set_slave_config(struct dma_chan *chan,
608 struct dma_slave_config *sconfig)
609{
610 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200611
Ludovic Desroches765c37d2015-06-08 10:33:15 +0200612 if (at_xdmac_check_slave_config(sconfig)) {
613 dev_err(chan2dev(chan), "invalid slave configuration\n");
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200614 return -EINVAL;
615 }
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200616
Ludovic Desroches765c37d2015-06-08 10:33:15 +0200617 memcpy(&atchan->sconfig, sconfig, sizeof(atchan->sconfig));
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200618
619 return 0;
620}
621
622static struct dma_async_tx_descriptor *
623at_xdmac_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
624 unsigned int sg_len, enum dma_transfer_direction direction,
625 unsigned long flags, void *context)
626{
627 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
628 struct at_xdmac_desc *first = NULL, *prev = NULL;
629 struct scatterlist *sg;
630 int i;
Cyrille Pitchen57819272014-11-13 11:52:42 +0100631 unsigned int xfer_size = 0;
Ludovic Desroches4c374fc2015-06-08 10:33:14 +0200632 unsigned long irqflags;
633 struct dma_async_tx_descriptor *ret = NULL;
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200634
635 if (!sgl)
636 return NULL;
637
638 if (!is_slave_direction(direction)) {
639 dev_err(chan2dev(chan), "invalid DMA direction\n");
640 return NULL;
641 }
642
643 dev_dbg(chan2dev(chan), "%s: sg_len=%d, dir=%s, flags=0x%lx\n",
644 __func__, sg_len,
645 direction == DMA_MEM_TO_DEV ? "to device" : "from device",
646 flags);
647
648 /* Protect dma_sconfig field that can be modified by set_slave_conf. */
Ludovic Desroches4c374fc2015-06-08 10:33:14 +0200649 spin_lock_irqsave(&atchan->lock, irqflags);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200650
Ludovic Desroches765c37d2015-06-08 10:33:15 +0200651 if (at_xdmac_compute_chan_conf(chan, direction))
652 goto spin_unlock;
653
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200654 /* Prepare descriptors. */
655 for_each_sg(sgl, sg, sg_len, i) {
656 struct at_xdmac_desc *desc = NULL;
Ludovic Desroches6d3a7d92015-01-27 16:30:32 +0100657 u32 len, mem, dwidth, fixed_dwidth;
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200658
659 len = sg_dma_len(sg);
660 mem = sg_dma_address(sg);
661 if (unlikely(!len)) {
662 dev_err(chan2dev(chan), "sg data length is zero\n");
Ludovic Desroches4c374fc2015-06-08 10:33:14 +0200663 goto spin_unlock;
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200664 }
665 dev_dbg(chan2dev(chan), "%s: * sg%d len=%u, mem=0x%08x\n",
666 __func__, i, len, mem);
667
668 desc = at_xdmac_get_desc(atchan);
669 if (!desc) {
670 dev_err(chan2dev(chan), "can't get descriptor\n");
671 if (first)
672 list_splice_init(&first->descs_list, &atchan->free_descs_list);
Ludovic Desroches4c374fc2015-06-08 10:33:14 +0200673 goto spin_unlock;
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200674 }
675
676 /* Linked list descriptor setup. */
677 if (direction == DMA_DEV_TO_MEM) {
Ludovic Desroches765c37d2015-06-08 10:33:15 +0200678 desc->lld.mbr_sa = atchan->sconfig.src_addr;
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200679 desc->lld.mbr_da = mem;
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200680 } else {
681 desc->lld.mbr_sa = mem;
Ludovic Desroches765c37d2015-06-08 10:33:15 +0200682 desc->lld.mbr_da = atchan->sconfig.dst_addr;
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200683 }
Ludovic Desroches765c37d2015-06-08 10:33:15 +0200684 desc->lld.mbr_cfg = atchan->cfg;
Ludovic Desroches6d3a7d92015-01-27 16:30:32 +0100685 dwidth = at_xdmac_get_dwidth(desc->lld.mbr_cfg);
686 fixed_dwidth = IS_ALIGNED(len, 1 << dwidth)
687 ? at_xdmac_get_dwidth(desc->lld.mbr_cfg)
688 : AT_XDMAC_CC_DWIDTH_BYTE;
689 desc->lld.mbr_ubc = AT_XDMAC_MBR_UBC_NDV2 /* next descriptor view */
Ludovic Desrochesbe835072015-01-27 16:30:31 +0100690 | AT_XDMAC_MBR_UBC_NDEN /* next descriptor dst parameter update */
691 | AT_XDMAC_MBR_UBC_NSEN /* next descriptor src parameter update */
Ludovic Desroches6d3a7d92015-01-27 16:30:32 +0100692 | (len >> fixed_dwidth); /* microblock length */
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200693 dev_dbg(chan2dev(chan),
Vinod Koul82e24242014-11-06 18:02:52 +0530694 "%s: lld: mbr_sa=%pad, mbr_da=%pad, mbr_ubc=0x%08x\n",
695 __func__, &desc->lld.mbr_sa, &desc->lld.mbr_da, desc->lld.mbr_ubc);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200696
697 /* Chain lld. */
Maxime Ripard0d0ee752015-05-07 17:38:10 +0200698 if (prev)
699 at_xdmac_queue_desc(chan, prev, desc);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200700
701 prev = desc;
702 if (!first)
703 first = desc;
704
705 dev_dbg(chan2dev(chan), "%s: add desc 0x%p to descs_list 0x%p\n",
706 __func__, desc, first);
707 list_add_tail(&desc->desc_node, &first->descs_list);
Cyrille Pitchen57819272014-11-13 11:52:42 +0100708 xfer_size += len;
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200709 }
710
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200711
712 first->tx_dma_desc.flags = flags;
Cyrille Pitchen57819272014-11-13 11:52:42 +0100713 first->xfer_size = xfer_size;
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200714 first->direction = direction;
Ludovic Desroches4c374fc2015-06-08 10:33:14 +0200715 ret = &first->tx_dma_desc;
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200716
Ludovic Desroches4c374fc2015-06-08 10:33:14 +0200717spin_unlock:
718 spin_unlock_irqrestore(&atchan->lock, irqflags);
719 return ret;
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200720}
721
722static struct dma_async_tx_descriptor *
723at_xdmac_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr,
724 size_t buf_len, size_t period_len,
725 enum dma_transfer_direction direction,
726 unsigned long flags)
727{
728 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
729 struct at_xdmac_desc *first = NULL, *prev = NULL;
730 unsigned int periods = buf_len / period_len;
731 int i;
Ludovic Desroches4c374fc2015-06-08 10:33:14 +0200732 unsigned long irqflags;
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200733
Vinod Koul82e24242014-11-06 18:02:52 +0530734 dev_dbg(chan2dev(chan), "%s: buf_addr=%pad, buf_len=%zd, period_len=%zd, dir=%s, flags=0x%lx\n",
735 __func__, &buf_addr, buf_len, period_len,
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200736 direction == DMA_MEM_TO_DEV ? "mem2per" : "per2mem", flags);
737
738 if (!is_slave_direction(direction)) {
739 dev_err(chan2dev(chan), "invalid DMA direction\n");
740 return NULL;
741 }
742
743 if (test_and_set_bit(AT_XDMAC_CHAN_IS_CYCLIC, &atchan->status)) {
744 dev_err(chan2dev(chan), "channel currently used\n");
745 return NULL;
746 }
747
Ludovic Desroches765c37d2015-06-08 10:33:15 +0200748 if (at_xdmac_compute_chan_conf(chan, direction))
749 return NULL;
750
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200751 for (i = 0; i < periods; i++) {
752 struct at_xdmac_desc *desc = NULL;
753
Ludovic Desroches4c374fc2015-06-08 10:33:14 +0200754 spin_lock_irqsave(&atchan->lock, irqflags);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200755 desc = at_xdmac_get_desc(atchan);
756 if (!desc) {
757 dev_err(chan2dev(chan), "can't get descriptor\n");
758 if (first)
759 list_splice_init(&first->descs_list, &atchan->free_descs_list);
Ludovic Desroches4c374fc2015-06-08 10:33:14 +0200760 spin_unlock_irqrestore(&atchan->lock, irqflags);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200761 return NULL;
762 }
Ludovic Desroches4c374fc2015-06-08 10:33:14 +0200763 spin_unlock_irqrestore(&atchan->lock, irqflags);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200764 dev_dbg(chan2dev(chan),
Vinod Koul82e24242014-11-06 18:02:52 +0530765 "%s: desc=0x%p, tx_dma_desc.phys=%pad\n",
766 __func__, desc, &desc->tx_dma_desc.phys);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200767
768 if (direction == DMA_DEV_TO_MEM) {
Ludovic Desroches765c37d2015-06-08 10:33:15 +0200769 desc->lld.mbr_sa = atchan->sconfig.src_addr;
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200770 desc->lld.mbr_da = buf_addr + i * period_len;
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200771 } else {
772 desc->lld.mbr_sa = buf_addr + i * period_len;
Ludovic Desroches765c37d2015-06-08 10:33:15 +0200773 desc->lld.mbr_da = atchan->sconfig.dst_addr;
kbuild test robot5ac7d582014-11-06 17:28:08 +0800774 }
Ludovic Desroches765c37d2015-06-08 10:33:15 +0200775 desc->lld.mbr_cfg = atchan->cfg;
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200776 desc->lld.mbr_ubc = AT_XDMAC_MBR_UBC_NDV1
777 | AT_XDMAC_MBR_UBC_NDEN
778 | AT_XDMAC_MBR_UBC_NSEN
Ludovic Desroches6eb9d3c2015-02-12 16:30:30 +0100779 | period_len >> at_xdmac_get_dwidth(desc->lld.mbr_cfg);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200780
781 dev_dbg(chan2dev(chan),
Vinod Koul82e24242014-11-06 18:02:52 +0530782 "%s: lld: mbr_sa=%pad, mbr_da=%pad, mbr_ubc=0x%08x\n",
783 __func__, &desc->lld.mbr_sa, &desc->lld.mbr_da, desc->lld.mbr_ubc);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200784
785 /* Chain lld. */
Maxime Ripard0d0ee752015-05-07 17:38:10 +0200786 if (prev)
787 at_xdmac_queue_desc(chan, prev, desc);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200788
789 prev = desc;
790 if (!first)
791 first = desc;
792
793 dev_dbg(chan2dev(chan), "%s: add desc 0x%p to descs_list 0x%p\n",
794 __func__, desc, first);
795 list_add_tail(&desc->desc_node, &first->descs_list);
796 }
797
798 prev->lld.mbr_nda = first->tx_dma_desc.phys;
799 dev_dbg(chan2dev(chan),
Vinod Koul82e24242014-11-06 18:02:52 +0530800 "%s: chain lld: prev=0x%p, mbr_nda=%pad\n",
801 __func__, prev, &prev->lld.mbr_nda);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +0200802 first->tx_dma_desc.flags = flags;
803 first->xfer_size = buf_len;
804 first->direction = direction;
805
806 return &first->tx_dma_desc;
807}
808
Maxime Ripardf0816a32015-05-07 17:38:09 +0200809static inline u32 at_xdmac_align_width(struct dma_chan *chan, dma_addr_t addr)
810{
811 u32 width;
812
813 /*
814 * Check address alignment to select the greater data width we
815 * can use.
816 *
817 * Some XDMAC implementations don't provide dword transfer, in
818 * this case selecting dword has the same behavior as
819 * selecting word transfers.
820 */
821 if (!(addr & 7)) {
822 width = AT_XDMAC_CC_DWIDTH_DWORD;
823 dev_dbg(chan2dev(chan), "%s: dwidth: double word\n", __func__);
824 } else if (!(addr & 3)) {
825 width = AT_XDMAC_CC_DWIDTH_WORD;
826 dev_dbg(chan2dev(chan), "%s: dwidth: word\n", __func__);
827 } else if (!(addr & 1)) {
828 width = AT_XDMAC_CC_DWIDTH_HALFWORD;
829 dev_dbg(chan2dev(chan), "%s: dwidth: half word\n", __func__);
830 } else {
831 width = AT_XDMAC_CC_DWIDTH_BYTE;
832 dev_dbg(chan2dev(chan), "%s: dwidth: byte\n", __func__);
833 }
834
835 return width;
836}
837
Maxime Ripard6007ccb2015-05-07 17:38:11 +0200838static struct at_xdmac_desc *
839at_xdmac_interleaved_queue_desc(struct dma_chan *chan,
840 struct at_xdmac_chan *atchan,
841 struct at_xdmac_desc *prev,
842 dma_addr_t src, dma_addr_t dst,
843 struct dma_interleaved_template *xt,
844 struct data_chunk *chunk)
845{
846 struct at_xdmac_desc *desc;
847 u32 dwidth;
848 unsigned long flags;
849 size_t ublen;
850 /*
851 * WARNING: The channel configuration is set here since there is no
852 * dmaengine_slave_config call in this case. Moreover we don't know the
853 * direction, it involves we can't dynamically set the source and dest
854 * interface so we have to use the same one. Only interface 0 allows EBI
855 * access. Hopefully we can access DDR through both ports (at least on
856 * SAMA5D4x), so we can use the same interface for source and dest,
857 * that solves the fact we don't know the direction.
858 */
859 u32 chan_cc = AT_XDMAC_CC_DIF(0)
860 | AT_XDMAC_CC_SIF(0)
861 | AT_XDMAC_CC_MBSIZE_SIXTEEN
862 | AT_XDMAC_CC_TYPE_MEM_TRAN;
863
864 dwidth = at_xdmac_align_width(chan, src | dst | chunk->size);
865 if (chunk->size >= (AT_XDMAC_MBR_UBC_UBLEN_MAX << dwidth)) {
866 dev_dbg(chan2dev(chan),
867 "%s: chunk too big (%d, max size %lu)...\n",
868 __func__, chunk->size,
869 AT_XDMAC_MBR_UBC_UBLEN_MAX << dwidth);
870 return NULL;
871 }
872
873 if (prev)
874 dev_dbg(chan2dev(chan),
875 "Adding items at the end of desc 0x%p\n", prev);
876
877 if (xt->src_inc) {
878 if (xt->src_sgl)
879 chan_cc |= AT_XDMAC_CC_SAM_UBS_DS_AM;
880 else
881 chan_cc |= AT_XDMAC_CC_SAM_INCREMENTED_AM;
882 }
883
884 if (xt->dst_inc) {
885 if (xt->dst_sgl)
886 chan_cc |= AT_XDMAC_CC_DAM_UBS_DS_AM;
887 else
888 chan_cc |= AT_XDMAC_CC_DAM_INCREMENTED_AM;
889 }
890
891 spin_lock_irqsave(&atchan->lock, flags);
892 desc = at_xdmac_get_desc(atchan);
893 spin_unlock_irqrestore(&atchan->lock, flags);
894 if (!desc) {
895 dev_err(chan2dev(chan), "can't get descriptor\n");
896 return NULL;
897 }
898
899 chan_cc |= AT_XDMAC_CC_DWIDTH(dwidth);
900
901 ublen = chunk->size >> dwidth;
902
903 desc->lld.mbr_sa = src;
904 desc->lld.mbr_da = dst;
Maxime Ripard87d001e2015-05-27 16:01:52 +0200905 desc->lld.mbr_sus = dmaengine_get_src_icg(xt, chunk);
906 desc->lld.mbr_dus = dmaengine_get_dst_icg(xt, chunk);
Maxime Ripard6007ccb2015-05-07 17:38:11 +0200907
908 desc->lld.mbr_ubc = AT_XDMAC_MBR_UBC_NDV3
909 | AT_XDMAC_MBR_UBC_NDEN
910 | AT_XDMAC_MBR_UBC_NSEN
911 | ublen;
912 desc->lld.mbr_cfg = chan_cc;
913
914 dev_dbg(chan2dev(chan),
915 "%s: lld: mbr_sa=0x%08x, mbr_da=0x%08x, mbr_ubc=0x%08x, mbr_cfg=0x%08x\n",
916 __func__, desc->lld.mbr_sa, desc->lld.mbr_da,
917 desc->lld.mbr_ubc, desc->lld.mbr_cfg);
918
919 /* Chain lld. */
920 if (prev)
921 at_xdmac_queue_desc(chan, prev, desc);
922
923 return desc;
924}
925
Maxime Ripard6007ccb2015-05-07 17:38:11 +0200926static struct dma_async_tx_descriptor *
927at_xdmac_prep_interleaved(struct dma_chan *chan,
928 struct dma_interleaved_template *xt,
929 unsigned long flags)
930{
931 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
932 struct at_xdmac_desc *prev = NULL, *first = NULL;
933 struct data_chunk *chunk, *prev_chunk = NULL;
934 dma_addr_t dst_addr, src_addr;
935 size_t dst_skip, src_skip, len = 0;
936 size_t prev_dst_icg = 0, prev_src_icg = 0;
937 int i;
938
939 if (!xt || (xt->numf != 1) || (xt->dir != DMA_MEM_TO_MEM))
940 return NULL;
941
942 dev_dbg(chan2dev(chan), "%s: src=0x%08x, dest=0x%08x, numf=%d, frame_size=%d, flags=0x%lx\n",
943 __func__, xt->src_start, xt->dst_start, xt->numf,
944 xt->frame_size, flags);
945
946 src_addr = xt->src_start;
947 dst_addr = xt->dst_start;
948
949 for (i = 0; i < xt->frame_size; i++) {
950 struct at_xdmac_desc *desc;
951 size_t src_icg, dst_icg;
952
953 chunk = xt->sgl + i;
954
Maxime Ripard87d001e2015-05-27 16:01:52 +0200955 dst_icg = dmaengine_get_dst_icg(xt, chunk);
956 src_icg = dmaengine_get_src_icg(xt, chunk);
Maxime Ripard6007ccb2015-05-07 17:38:11 +0200957
958 src_skip = chunk->size + src_icg;
959 dst_skip = chunk->size + dst_icg;
960
961 dev_dbg(chan2dev(chan),
962 "%s: chunk size=%d, src icg=%d, dst icg=%d\n",
963 __func__, chunk->size, src_icg, dst_icg);
964
965 /*
966 * Handle the case where we just have the same
967 * transfer to setup, we can just increase the
968 * block number and reuse the same descriptor.
969 */
970 if (prev_chunk && prev &&
971 (prev_chunk->size == chunk->size) &&
972 (prev_src_icg == src_icg) &&
973 (prev_dst_icg == dst_icg)) {
974 dev_dbg(chan2dev(chan),
975 "%s: same configuration that the previous chunk, merging the descriptors...\n",
976 __func__);
977 at_xdmac_increment_block_count(chan, prev);
978 continue;
979 }
980
981 desc = at_xdmac_interleaved_queue_desc(chan, atchan,
982 prev,
983 src_addr, dst_addr,
984 xt, chunk);
985 if (!desc) {
986 list_splice_init(&first->descs_list,
987 &atchan->free_descs_list);
988 return NULL;
989 }
990
991 if (!first)
992 first = desc;
993
994 dev_dbg(chan2dev(chan), "%s: add desc 0x%p to descs_list 0x%p\n",
995 __func__, desc, first);
996 list_add_tail(&desc->desc_node, &first->descs_list);
997
998 if (xt->src_sgl)
999 src_addr += src_skip;
1000
1001 if (xt->dst_sgl)
1002 dst_addr += dst_skip;
1003
1004 len += chunk->size;
1005 prev_chunk = chunk;
1006 prev_dst_icg = dst_icg;
1007 prev_src_icg = src_icg;
1008 prev = desc;
1009 }
1010
1011 first->tx_dma_desc.cookie = -EBUSY;
1012 first->tx_dma_desc.flags = flags;
1013 first->xfer_size = len;
1014
1015 return &first->tx_dma_desc;
1016}
1017
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001018static struct dma_async_tx_descriptor *
1019at_xdmac_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
1020 size_t len, unsigned long flags)
1021{
1022 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1023 struct at_xdmac_desc *first = NULL, *prev = NULL;
1024 size_t remaining_size = len, xfer_size = 0, ublen;
1025 dma_addr_t src_addr = src, dst_addr = dest;
1026 u32 dwidth;
1027 /*
1028 * WARNING: We don't know the direction, it involves we can't
1029 * dynamically set the source and dest interface so we have to use the
1030 * same one. Only interface 0 allows EBI access. Hopefully we can
1031 * access DDR through both ports (at least on SAMA5D4x), so we can use
1032 * the same interface for source and dest, that solves the fact we
1033 * don't know the direction.
1034 */
1035 u32 chan_cc = AT_XDMAC_CC_DAM_INCREMENTED_AM
1036 | AT_XDMAC_CC_SAM_INCREMENTED_AM
1037 | AT_XDMAC_CC_DIF(0)
1038 | AT_XDMAC_CC_SIF(0)
1039 | AT_XDMAC_CC_MBSIZE_SIXTEEN
1040 | AT_XDMAC_CC_TYPE_MEM_TRAN;
Ludovic Desroches4c374fc2015-06-08 10:33:14 +02001041 unsigned long irqflags;
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001042
Vinod Koul82e24242014-11-06 18:02:52 +05301043 dev_dbg(chan2dev(chan), "%s: src=%pad, dest=%pad, len=%zd, flags=0x%lx\n",
1044 __func__, &src, &dest, len, flags);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001045
1046 if (unlikely(!len))
1047 return NULL;
1048
Maxime Ripardf0816a32015-05-07 17:38:09 +02001049 dwidth = at_xdmac_align_width(chan, src_addr | dst_addr);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001050
1051 /* Prepare descriptors. */
1052 while (remaining_size) {
1053 struct at_xdmac_desc *desc = NULL;
1054
Vinod Koulc66ec042014-11-06 17:37:48 +05301055 dev_dbg(chan2dev(chan), "%s: remaining_size=%zu\n", __func__, remaining_size);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001056
Ludovic Desroches4c374fc2015-06-08 10:33:14 +02001057 spin_lock_irqsave(&atchan->lock, irqflags);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001058 desc = at_xdmac_get_desc(atchan);
Ludovic Desroches4c374fc2015-06-08 10:33:14 +02001059 spin_unlock_irqrestore(&atchan->lock, irqflags);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001060 if (!desc) {
1061 dev_err(chan2dev(chan), "can't get descriptor\n");
1062 if (first)
1063 list_splice_init(&first->descs_list, &atchan->free_descs_list);
1064 return NULL;
1065 }
1066
1067 /* Update src and dest addresses. */
1068 src_addr += xfer_size;
1069 dst_addr += xfer_size;
1070
1071 if (remaining_size >= AT_XDMAC_MBR_UBC_UBLEN_MAX << dwidth)
1072 xfer_size = AT_XDMAC_MBR_UBC_UBLEN_MAX << dwidth;
1073 else
1074 xfer_size = remaining_size;
1075
Vinod Koulc66ec042014-11-06 17:37:48 +05301076 dev_dbg(chan2dev(chan), "%s: xfer_size=%zu\n", __func__, xfer_size);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001077
1078 /* Check remaining length and change data width if needed. */
Maxime Ripardf0816a32015-05-07 17:38:09 +02001079 dwidth = at_xdmac_align_width(chan,
1080 src_addr | dst_addr | xfer_size);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001081 chan_cc |= AT_XDMAC_CC_DWIDTH(dwidth);
1082
1083 ublen = xfer_size >> dwidth;
1084 remaining_size -= xfer_size;
1085
1086 desc->lld.mbr_sa = src_addr;
1087 desc->lld.mbr_da = dst_addr;
1088 desc->lld.mbr_ubc = AT_XDMAC_MBR_UBC_NDV2
1089 | AT_XDMAC_MBR_UBC_NDEN
1090 | AT_XDMAC_MBR_UBC_NSEN
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001091 | ublen;
1092 desc->lld.mbr_cfg = chan_cc;
1093
1094 dev_dbg(chan2dev(chan),
Vinod Koul82e24242014-11-06 18:02:52 +05301095 "%s: lld: mbr_sa=%pad, mbr_da=%pad, mbr_ubc=0x%08x, mbr_cfg=0x%08x\n",
1096 __func__, &desc->lld.mbr_sa, &desc->lld.mbr_da, desc->lld.mbr_ubc, desc->lld.mbr_cfg);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001097
1098 /* Chain lld. */
Maxime Ripard0d0ee752015-05-07 17:38:10 +02001099 if (prev)
1100 at_xdmac_queue_desc(chan, prev, desc);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001101
1102 prev = desc;
1103 if (!first)
1104 first = desc;
1105
1106 dev_dbg(chan2dev(chan), "%s: add desc 0x%p to descs_list 0x%p\n",
1107 __func__, desc, first);
1108 list_add_tail(&desc->desc_node, &first->descs_list);
1109 }
1110
1111 first->tx_dma_desc.flags = flags;
1112 first->xfer_size = len;
1113
1114 return &first->tx_dma_desc;
1115}
1116
Maxime Ripardb206d9a2015-05-18 13:46:16 +02001117static struct at_xdmac_desc *at_xdmac_memset_create_desc(struct dma_chan *chan,
1118 struct at_xdmac_chan *atchan,
1119 dma_addr_t dst_addr,
1120 size_t len,
1121 int value)
1122{
1123 struct at_xdmac_desc *desc;
1124 unsigned long flags;
1125 size_t ublen;
1126 u32 dwidth;
1127 /*
1128 * WARNING: The channel configuration is set here since there is no
1129 * dmaengine_slave_config call in this case. Moreover we don't know the
1130 * direction, it involves we can't dynamically set the source and dest
1131 * interface so we have to use the same one. Only interface 0 allows EBI
1132 * access. Hopefully we can access DDR through both ports (at least on
1133 * SAMA5D4x), so we can use the same interface for source and dest,
1134 * that solves the fact we don't know the direction.
1135 */
1136 u32 chan_cc = AT_XDMAC_CC_DAM_INCREMENTED_AM
1137 | AT_XDMAC_CC_SAM_INCREMENTED_AM
1138 | AT_XDMAC_CC_DIF(0)
1139 | AT_XDMAC_CC_SIF(0)
1140 | AT_XDMAC_CC_MBSIZE_SIXTEEN
1141 | AT_XDMAC_CC_MEMSET_HW_MODE
1142 | AT_XDMAC_CC_TYPE_MEM_TRAN;
1143
1144 dwidth = at_xdmac_align_width(chan, dst_addr);
1145
1146 if (len >= (AT_XDMAC_MBR_UBC_UBLEN_MAX << dwidth)) {
1147 dev_err(chan2dev(chan),
1148 "%s: Transfer too large, aborting...\n",
1149 __func__);
1150 return NULL;
1151 }
1152
1153 spin_lock_irqsave(&atchan->lock, flags);
1154 desc = at_xdmac_get_desc(atchan);
1155 spin_unlock_irqrestore(&atchan->lock, flags);
1156 if (!desc) {
1157 dev_err(chan2dev(chan), "can't get descriptor\n");
1158 return NULL;
1159 }
1160
1161 chan_cc |= AT_XDMAC_CC_DWIDTH(dwidth);
1162
1163 ublen = len >> dwidth;
1164
1165 desc->lld.mbr_da = dst_addr;
1166 desc->lld.mbr_ds = value;
1167 desc->lld.mbr_ubc = AT_XDMAC_MBR_UBC_NDV3
1168 | AT_XDMAC_MBR_UBC_NDEN
1169 | AT_XDMAC_MBR_UBC_NSEN
1170 | ublen;
1171 desc->lld.mbr_cfg = chan_cc;
1172
1173 dev_dbg(chan2dev(chan),
1174 "%s: lld: mbr_da=0x%08x, mbr_ds=0x%08x, mbr_ubc=0x%08x, mbr_cfg=0x%08x\n",
1175 __func__, desc->lld.mbr_da, desc->lld.mbr_ds, desc->lld.mbr_ubc,
1176 desc->lld.mbr_cfg);
1177
1178 return desc;
1179}
1180
1181struct dma_async_tx_descriptor *
1182at_xdmac_prep_dma_memset(struct dma_chan *chan, dma_addr_t dest, int value,
1183 size_t len, unsigned long flags)
1184{
1185 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1186 struct at_xdmac_desc *desc;
1187
1188 dev_dbg(chan2dev(chan), "%s: dest=0x%08x, len=%d, pattern=0x%x, flags=0x%lx\n",
1189 __func__, dest, len, value, flags);
1190
1191 if (unlikely(!len))
1192 return NULL;
1193
1194 desc = at_xdmac_memset_create_desc(chan, atchan, dest, len, value);
1195 list_add_tail(&desc->desc_node, &desc->descs_list);
1196
1197 desc->tx_dma_desc.cookie = -EBUSY;
1198 desc->tx_dma_desc.flags = flags;
1199 desc->xfer_size = len;
1200
1201 return &desc->tx_dma_desc;
1202}
1203
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001204static enum dma_status
1205at_xdmac_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
1206 struct dma_tx_state *txstate)
1207{
1208 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1209 struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device);
1210 struct at_xdmac_desc *desc, *_desc;
1211 struct list_head *descs_list;
1212 enum dma_status ret;
1213 int residue;
Cyrille Pitchen4e097822014-11-13 11:52:41 +01001214 u32 cur_nda, mask, value;
Ludovic Desrochesbe835072015-01-27 16:30:31 +01001215 u8 dwidth = 0;
Ludovic Desroches4c374fc2015-06-08 10:33:14 +02001216 unsigned long flags;
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001217
1218 ret = dma_cookie_status(chan, cookie, txstate);
1219 if (ret == DMA_COMPLETE)
1220 return ret;
1221
1222 if (!txstate)
1223 return ret;
1224
Ludovic Desroches4c374fc2015-06-08 10:33:14 +02001225 spin_lock_irqsave(&atchan->lock, flags);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001226
1227 desc = list_first_entry(&atchan->xfers_list, struct at_xdmac_desc, xfer_node);
1228
1229 /*
1230 * If the transfer has not been started yet, don't need to compute the
1231 * residue, it's the transfer length.
1232 */
1233 if (!desc->active_xfer) {
1234 dma_set_residue(txstate, desc->xfer_size);
Ludovic Desroches4c374fc2015-06-08 10:33:14 +02001235 goto spin_unlock;
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001236 }
1237
1238 residue = desc->xfer_size;
Cyrille Pitchen4e097822014-11-13 11:52:41 +01001239 /*
1240 * Flush FIFO: only relevant when the transfer is source peripheral
1241 * synchronized.
1242 */
1243 mask = AT_XDMAC_CC_TYPE | AT_XDMAC_CC_DSYNC;
1244 value = AT_XDMAC_CC_TYPE_PER_TRAN | AT_XDMAC_CC_DSYNC_PER2MEM;
Ludovic Desrochesbe835072015-01-27 16:30:31 +01001245 if ((desc->lld.mbr_cfg & mask) == value) {
Cyrille Pitchen4e097822014-11-13 11:52:41 +01001246 at_xdmac_write(atxdmac, AT_XDMAC_GSWF, atchan->mask);
1247 while (!(at_xdmac_chan_read(atchan, AT_XDMAC_CIS) & AT_XDMAC_CIS_FIS))
1248 cpu_relax();
1249 }
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001250
1251 cur_nda = at_xdmac_chan_read(atchan, AT_XDMAC_CNDA) & 0xfffffffc;
1252 /*
1253 * Remove size of all microblocks already transferred and the current
1254 * one. Then add the remaining size to transfer of the current
1255 * microblock.
1256 */
1257 descs_list = &desc->descs_list;
1258 list_for_each_entry_safe(desc, _desc, descs_list, desc_node) {
Ludovic Desrochesbe835072015-01-27 16:30:31 +01001259 dwidth = at_xdmac_get_dwidth(desc->lld.mbr_cfg);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001260 residue -= (desc->lld.mbr_ubc & 0xffffff) << dwidth;
1261 if ((desc->lld.mbr_nda & 0xfffffffc) == cur_nda)
1262 break;
1263 }
1264 residue += at_xdmac_chan_read(atchan, AT_XDMAC_CUBC) << dwidth;
1265
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001266 dma_set_residue(txstate, residue);
1267
1268 dev_dbg(chan2dev(chan),
Vinod Koul82e24242014-11-06 18:02:52 +05301269 "%s: desc=0x%p, tx_dma_desc.phys=%pad, tx_status=%d, cookie=%d, residue=%d\n",
1270 __func__, desc, &desc->tx_dma_desc.phys, ret, cookie, residue);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001271
Ludovic Desroches4c374fc2015-06-08 10:33:14 +02001272spin_unlock:
1273 spin_unlock_irqrestore(&atchan->lock, flags);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001274 return ret;
1275}
1276
1277/* Call must be protected by lock. */
1278static void at_xdmac_remove_xfer(struct at_xdmac_chan *atchan,
1279 struct at_xdmac_desc *desc)
1280{
1281 dev_dbg(chan2dev(&atchan->chan), "%s: desc 0x%p\n", __func__, desc);
1282
1283 /*
1284 * Remove the transfer from the transfer list then move the transfer
1285 * descriptors into the free descriptors list.
1286 */
1287 list_del(&desc->xfer_node);
1288 list_splice_init(&desc->descs_list, &atchan->free_descs_list);
1289}
1290
1291static void at_xdmac_advance_work(struct at_xdmac_chan *atchan)
1292{
1293 struct at_xdmac_desc *desc;
Ludovic Desroches4c374fc2015-06-08 10:33:14 +02001294 unsigned long flags;
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001295
Ludovic Desroches4c374fc2015-06-08 10:33:14 +02001296 spin_lock_irqsave(&atchan->lock, flags);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001297
1298 /*
1299 * If channel is enabled, do nothing, advance_work will be triggered
1300 * after the interruption.
1301 */
1302 if (!at_xdmac_chan_is_enabled(atchan) && !list_empty(&atchan->xfers_list)) {
1303 desc = list_first_entry(&atchan->xfers_list,
1304 struct at_xdmac_desc,
1305 xfer_node);
1306 dev_vdbg(chan2dev(&atchan->chan), "%s: desc 0x%p\n", __func__, desc);
1307 if (!desc->active_xfer)
1308 at_xdmac_start_xfer(atchan, desc);
1309 }
1310
Ludovic Desroches4c374fc2015-06-08 10:33:14 +02001311 spin_unlock_irqrestore(&atchan->lock, flags);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001312}
1313
1314static void at_xdmac_handle_cyclic(struct at_xdmac_chan *atchan)
1315{
1316 struct at_xdmac_desc *desc;
1317 struct dma_async_tx_descriptor *txd;
1318
1319 desc = list_first_entry(&atchan->xfers_list, struct at_xdmac_desc, xfer_node);
1320 txd = &desc->tx_dma_desc;
1321
1322 if (txd->callback && (txd->flags & DMA_PREP_INTERRUPT))
1323 txd->callback(txd->callback_param);
1324}
1325
1326static void at_xdmac_tasklet(unsigned long data)
1327{
1328 struct at_xdmac_chan *atchan = (struct at_xdmac_chan *)data;
1329 struct at_xdmac_desc *desc;
1330 u32 error_mask;
1331
1332 dev_dbg(chan2dev(&atchan->chan), "%s: status=0x%08lx\n",
1333 __func__, atchan->status);
1334
1335 error_mask = AT_XDMAC_CIS_RBEIS
1336 | AT_XDMAC_CIS_WBEIS
1337 | AT_XDMAC_CIS_ROIS;
1338
1339 if (at_xdmac_chan_is_cyclic(atchan)) {
1340 at_xdmac_handle_cyclic(atchan);
1341 } else if ((atchan->status & AT_XDMAC_CIS_LIS)
1342 || (atchan->status & error_mask)) {
1343 struct dma_async_tx_descriptor *txd;
1344
1345 if (atchan->status & AT_XDMAC_CIS_RBEIS)
1346 dev_err(chan2dev(&atchan->chan), "read bus error!!!");
1347 if (atchan->status & AT_XDMAC_CIS_WBEIS)
1348 dev_err(chan2dev(&atchan->chan), "write bus error!!!");
1349 if (atchan->status & AT_XDMAC_CIS_ROIS)
1350 dev_err(chan2dev(&atchan->chan), "request overflow error!!!");
1351
1352 spin_lock_bh(&atchan->lock);
1353 desc = list_first_entry(&atchan->xfers_list,
1354 struct at_xdmac_desc,
1355 xfer_node);
1356 dev_vdbg(chan2dev(&atchan->chan), "%s: desc 0x%p\n", __func__, desc);
1357 BUG_ON(!desc->active_xfer);
1358
1359 txd = &desc->tx_dma_desc;
1360
1361 at_xdmac_remove_xfer(atchan, desc);
1362 spin_unlock_bh(&atchan->lock);
1363
1364 if (!at_xdmac_chan_is_cyclic(atchan)) {
1365 dma_cookie_complete(txd);
1366 if (txd->callback && (txd->flags & DMA_PREP_INTERRUPT))
1367 txd->callback(txd->callback_param);
1368 }
1369
1370 dma_run_dependencies(txd);
1371
1372 at_xdmac_advance_work(atchan);
1373 }
1374}
1375
1376static irqreturn_t at_xdmac_interrupt(int irq, void *dev_id)
1377{
1378 struct at_xdmac *atxdmac = (struct at_xdmac *)dev_id;
1379 struct at_xdmac_chan *atchan;
1380 u32 imr, status, pending;
1381 u32 chan_imr, chan_status;
1382 int i, ret = IRQ_NONE;
1383
1384 do {
1385 imr = at_xdmac_read(atxdmac, AT_XDMAC_GIM);
1386 status = at_xdmac_read(atxdmac, AT_XDMAC_GIS);
1387 pending = status & imr;
1388
1389 dev_vdbg(atxdmac->dma.dev,
1390 "%s: status=0x%08x, imr=0x%08x, pending=0x%08x\n",
1391 __func__, status, imr, pending);
1392
1393 if (!pending)
1394 break;
1395
1396 /* We have to find which channel has generated the interrupt. */
1397 for (i = 0; i < atxdmac->dma.chancnt; i++) {
1398 if (!((1 << i) & pending))
1399 continue;
1400
1401 atchan = &atxdmac->chan[i];
1402 chan_imr = at_xdmac_chan_read(atchan, AT_XDMAC_CIM);
1403 chan_status = at_xdmac_chan_read(atchan, AT_XDMAC_CIS);
1404 atchan->status = chan_status & chan_imr;
1405 dev_vdbg(atxdmac->dma.dev,
1406 "%s: chan%d: imr=0x%x, status=0x%x\n",
1407 __func__, i, chan_imr, chan_status);
1408 dev_vdbg(chan2dev(&atchan->chan),
1409 "%s: CC=0x%08x CNDA=0x%08x, CNDC=0x%08x, CSA=0x%08x, CDA=0x%08x, CUBC=0x%08x\n",
1410 __func__,
1411 at_xdmac_chan_read(atchan, AT_XDMAC_CC),
1412 at_xdmac_chan_read(atchan, AT_XDMAC_CNDA),
1413 at_xdmac_chan_read(atchan, AT_XDMAC_CNDC),
1414 at_xdmac_chan_read(atchan, AT_XDMAC_CSA),
1415 at_xdmac_chan_read(atchan, AT_XDMAC_CDA),
1416 at_xdmac_chan_read(atchan, AT_XDMAC_CUBC));
1417
1418 if (atchan->status & (AT_XDMAC_CIS_RBEIS | AT_XDMAC_CIS_WBEIS))
1419 at_xdmac_write(atxdmac, AT_XDMAC_GD, atchan->mask);
1420
1421 tasklet_schedule(&atchan->tasklet);
1422 ret = IRQ_HANDLED;
1423 }
1424
1425 } while (pending);
1426
1427 return ret;
1428}
1429
1430static void at_xdmac_issue_pending(struct dma_chan *chan)
1431{
1432 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1433
1434 dev_dbg(chan2dev(&atchan->chan), "%s\n", __func__);
1435
1436 if (!at_xdmac_chan_is_cyclic(atchan))
1437 at_xdmac_advance_work(atchan);
1438
1439 return;
1440}
1441
Ludovic Desroches3d138872014-11-17 14:42:07 +01001442static int at_xdmac_device_config(struct dma_chan *chan,
1443 struct dma_slave_config *config)
1444{
1445 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1446 int ret;
Ludovic Desroches4c374fc2015-06-08 10:33:14 +02001447 unsigned long flags;
Ludovic Desroches3d138872014-11-17 14:42:07 +01001448
1449 dev_dbg(chan2dev(chan), "%s\n", __func__);
1450
Ludovic Desroches4c374fc2015-06-08 10:33:14 +02001451 spin_lock_irqsave(&atchan->lock, flags);
Ludovic Desroches3d138872014-11-17 14:42:07 +01001452 ret = at_xdmac_set_slave_config(chan, config);
Ludovic Desroches4c374fc2015-06-08 10:33:14 +02001453 spin_unlock_irqrestore(&atchan->lock, flags);
Ludovic Desroches3d138872014-11-17 14:42:07 +01001454
1455 return ret;
1456}
1457
1458static int at_xdmac_device_pause(struct dma_chan *chan)
1459{
1460 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1461 struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device);
Ludovic Desroches4c374fc2015-06-08 10:33:14 +02001462 unsigned long flags;
Ludovic Desroches3d138872014-11-17 14:42:07 +01001463
1464 dev_dbg(chan2dev(chan), "%s\n", __func__);
1465
Cyrille Pitchencbb85e62015-01-27 16:30:29 +01001466 if (test_and_set_bit(AT_XDMAC_CHAN_IS_PAUSED, &atchan->status))
1467 return 0;
1468
Ludovic Desroches4c374fc2015-06-08 10:33:14 +02001469 spin_lock_irqsave(&atchan->lock, flags);
Ludovic Desroches3d138872014-11-17 14:42:07 +01001470 at_xdmac_write(atxdmac, AT_XDMAC_GRWS, atchan->mask);
Cyrille Pitchencbb85e62015-01-27 16:30:29 +01001471 while (at_xdmac_chan_read(atchan, AT_XDMAC_CC)
1472 & (AT_XDMAC_CC_WRIP | AT_XDMAC_CC_RDIP))
1473 cpu_relax();
Ludovic Desroches4c374fc2015-06-08 10:33:14 +02001474 spin_unlock_irqrestore(&atchan->lock, flags);
Ludovic Desroches3d138872014-11-17 14:42:07 +01001475
1476 return 0;
1477}
1478
1479static int at_xdmac_device_resume(struct dma_chan *chan)
1480{
1481 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1482 struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device);
Ludovic Desroches4c374fc2015-06-08 10:33:14 +02001483 unsigned long flags;
Ludovic Desroches3d138872014-11-17 14:42:07 +01001484
1485 dev_dbg(chan2dev(chan), "%s\n", __func__);
1486
Ludovic Desroches4c374fc2015-06-08 10:33:14 +02001487 spin_lock_irqsave(&atchan->lock, flags);
Niklas Cassel0434a232015-04-07 16:42:45 +02001488 if (!at_xdmac_chan_is_paused(atchan)) {
Ludovic Desroches4c374fc2015-06-08 10:33:14 +02001489 spin_unlock_irqrestore(&atchan->lock, flags);
Ludovic Desroches3d138872014-11-17 14:42:07 +01001490 return 0;
Niklas Cassel0434a232015-04-07 16:42:45 +02001491 }
Ludovic Desroches3d138872014-11-17 14:42:07 +01001492
1493 at_xdmac_write(atxdmac, AT_XDMAC_GRWR, atchan->mask);
1494 clear_bit(AT_XDMAC_CHAN_IS_PAUSED, &atchan->status);
Ludovic Desroches4c374fc2015-06-08 10:33:14 +02001495 spin_unlock_irqrestore(&atchan->lock, flags);
Ludovic Desroches3d138872014-11-17 14:42:07 +01001496
1497 return 0;
1498}
1499
1500static int at_xdmac_device_terminate_all(struct dma_chan *chan)
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001501{
1502 struct at_xdmac_desc *desc, *_desc;
1503 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1504 struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device);
Ludovic Desroches4c374fc2015-06-08 10:33:14 +02001505 unsigned long flags;
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001506
Ludovic Desroches3d138872014-11-17 14:42:07 +01001507 dev_dbg(chan2dev(chan), "%s\n", __func__);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001508
Ludovic Desroches4c374fc2015-06-08 10:33:14 +02001509 spin_lock_irqsave(&atchan->lock, flags);
Ludovic Desroches3d138872014-11-17 14:42:07 +01001510 at_xdmac_write(atxdmac, AT_XDMAC_GD, atchan->mask);
1511 while (at_xdmac_read(atxdmac, AT_XDMAC_GS) & atchan->mask)
1512 cpu_relax();
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001513
Ludovic Desroches3d138872014-11-17 14:42:07 +01001514 /* Cancel all pending transfers. */
1515 list_for_each_entry_safe(desc, _desc, &atchan->xfers_list, xfer_node)
1516 at_xdmac_remove_xfer(atchan, desc);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001517
Ludovic Desroches3d138872014-11-17 14:42:07 +01001518 clear_bit(AT_XDMAC_CHAN_IS_CYCLIC, &atchan->status);
Ludovic Desroches4c374fc2015-06-08 10:33:14 +02001519 spin_unlock_irqrestore(&atchan->lock, flags);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001520
Ludovic Desroches3d138872014-11-17 14:42:07 +01001521 return 0;
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001522}
1523
1524static int at_xdmac_alloc_chan_resources(struct dma_chan *chan)
1525{
1526 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1527 struct at_xdmac_desc *desc;
1528 int i;
Ludovic Desroches4c374fc2015-06-08 10:33:14 +02001529 unsigned long flags;
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001530
Ludovic Desroches4c374fc2015-06-08 10:33:14 +02001531 spin_lock_irqsave(&atchan->lock, flags);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001532
1533 if (at_xdmac_chan_is_enabled(atchan)) {
1534 dev_err(chan2dev(chan),
1535 "can't allocate channel resources (channel enabled)\n");
1536 i = -EIO;
1537 goto spin_unlock;
1538 }
1539
1540 if (!list_empty(&atchan->free_descs_list)) {
1541 dev_err(chan2dev(chan),
1542 "can't allocate channel resources (channel not free from a previous use)\n");
1543 i = -EIO;
1544 goto spin_unlock;
1545 }
1546
1547 for (i = 0; i < init_nr_desc_per_channel; i++) {
1548 desc = at_xdmac_alloc_desc(chan, GFP_ATOMIC);
1549 if (!desc) {
1550 dev_warn(chan2dev(chan),
1551 "only %d descriptors have been allocated\n", i);
1552 break;
1553 }
1554 list_add_tail(&desc->desc_node, &atchan->free_descs_list);
1555 }
1556
1557 dma_cookie_init(chan);
1558
1559 dev_dbg(chan2dev(chan), "%s: allocated %d descriptors\n", __func__, i);
1560
1561spin_unlock:
Ludovic Desroches4c374fc2015-06-08 10:33:14 +02001562 spin_unlock_irqrestore(&atchan->lock, flags);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001563 return i;
1564}
1565
1566static void at_xdmac_free_chan_resources(struct dma_chan *chan)
1567{
1568 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1569 struct at_xdmac *atxdmac = to_at_xdmac(chan->device);
1570 struct at_xdmac_desc *desc, *_desc;
1571
1572 list_for_each_entry_safe(desc, _desc, &atchan->free_descs_list, desc_node) {
1573 dev_dbg(chan2dev(chan), "%s: freeing descriptor %p\n", __func__, desc);
1574 list_del(&desc->desc_node);
1575 dma_pool_free(atxdmac->at_xdmac_desc_pool, desc, desc->tx_dma_desc.phys);
1576 }
1577
1578 return;
1579}
1580
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001581#ifdef CONFIG_PM
1582static int atmel_xdmac_prepare(struct device *dev)
1583{
1584 struct platform_device *pdev = to_platform_device(dev);
1585 struct at_xdmac *atxdmac = platform_get_drvdata(pdev);
1586 struct dma_chan *chan, *_chan;
1587
1588 list_for_each_entry_safe(chan, _chan, &atxdmac->dma.channels, device_node) {
1589 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1590
1591 /* Wait for transfer completion, except in cyclic case. */
1592 if (at_xdmac_chan_is_enabled(atchan) && !at_xdmac_chan_is_cyclic(atchan))
1593 return -EAGAIN;
1594 }
1595 return 0;
1596}
1597#else
1598# define atmel_xdmac_prepare NULL
1599#endif
1600
1601#ifdef CONFIG_PM_SLEEP
1602static int atmel_xdmac_suspend(struct device *dev)
1603{
1604 struct platform_device *pdev = to_platform_device(dev);
1605 struct at_xdmac *atxdmac = platform_get_drvdata(pdev);
1606 struct dma_chan *chan, *_chan;
1607
1608 list_for_each_entry_safe(chan, _chan, &atxdmac->dma.channels, device_node) {
1609 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1610
Ludovic Desroches734bb9a2015-01-27 16:30:30 +01001611 atchan->save_cc = at_xdmac_chan_read(atchan, AT_XDMAC_CC);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001612 if (at_xdmac_chan_is_cyclic(atchan)) {
1613 if (!at_xdmac_chan_is_paused(atchan))
Ludovic Desroches3d138872014-11-17 14:42:07 +01001614 at_xdmac_device_pause(chan);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001615 atchan->save_cim = at_xdmac_chan_read(atchan, AT_XDMAC_CIM);
1616 atchan->save_cnda = at_xdmac_chan_read(atchan, AT_XDMAC_CNDA);
1617 atchan->save_cndc = at_xdmac_chan_read(atchan, AT_XDMAC_CNDC);
1618 }
1619 }
1620 atxdmac->save_gim = at_xdmac_read(atxdmac, AT_XDMAC_GIM);
1621
1622 at_xdmac_off(atxdmac);
1623 clk_disable_unprepare(atxdmac->clk);
1624 return 0;
1625}
1626
1627static int atmel_xdmac_resume(struct device *dev)
1628{
1629 struct platform_device *pdev = to_platform_device(dev);
1630 struct at_xdmac *atxdmac = platform_get_drvdata(pdev);
1631 struct at_xdmac_chan *atchan;
1632 struct dma_chan *chan, *_chan;
1633 int i;
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001634
1635 clk_prepare_enable(atxdmac->clk);
1636
1637 /* Clear pending interrupts. */
1638 for (i = 0; i < atxdmac->dma.chancnt; i++) {
1639 atchan = &atxdmac->chan[i];
1640 while (at_xdmac_chan_read(atchan, AT_XDMAC_CIS))
1641 cpu_relax();
1642 }
1643
1644 at_xdmac_write(atxdmac, AT_XDMAC_GIE, atxdmac->save_gim);
1645 at_xdmac_write(atxdmac, AT_XDMAC_GE, atxdmac->save_gs);
1646 list_for_each_entry_safe(chan, _chan, &atxdmac->dma.channels, device_node) {
1647 atchan = to_at_xdmac_chan(chan);
Ludovic Desroches734bb9a2015-01-27 16:30:30 +01001648 at_xdmac_chan_write(atchan, AT_XDMAC_CC, atchan->save_cc);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001649 if (at_xdmac_chan_is_cyclic(atchan)) {
1650 at_xdmac_chan_write(atchan, AT_XDMAC_CNDA, atchan->save_cnda);
1651 at_xdmac_chan_write(atchan, AT_XDMAC_CNDC, atchan->save_cndc);
1652 at_xdmac_chan_write(atchan, AT_XDMAC_CIE, atchan->save_cim);
1653 wmb();
1654 at_xdmac_write(atxdmac, AT_XDMAC_GE, atchan->mask);
1655 }
1656 }
1657 return 0;
1658}
1659#endif /* CONFIG_PM_SLEEP */
1660
1661static int at_xdmac_probe(struct platform_device *pdev)
1662{
1663 struct resource *res;
1664 struct at_xdmac *atxdmac;
1665 int irq, size, nr_channels, i, ret;
1666 void __iomem *base;
1667 u32 reg;
1668
1669 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1670 if (!res)
1671 return -EINVAL;
1672
1673 irq = platform_get_irq(pdev, 0);
1674 if (irq < 0)
1675 return irq;
1676
1677 base = devm_ioremap_resource(&pdev->dev, res);
1678 if (IS_ERR(base))
1679 return PTR_ERR(base);
1680
1681 /*
1682 * Read number of xdmac channels, read helper function can't be used
1683 * since atxdmac is not yet allocated and we need to know the number
1684 * of channels to do the allocation.
1685 */
1686 reg = readl_relaxed(base + AT_XDMAC_GTYPE);
1687 nr_channels = AT_XDMAC_NB_CH(reg);
1688 if (nr_channels > AT_XDMAC_MAX_CHAN) {
1689 dev_err(&pdev->dev, "invalid number of channels (%u)\n",
1690 nr_channels);
1691 return -EINVAL;
1692 }
1693
1694 size = sizeof(*atxdmac);
1695 size += nr_channels * sizeof(struct at_xdmac_chan);
1696 atxdmac = devm_kzalloc(&pdev->dev, size, GFP_KERNEL);
1697 if (!atxdmac) {
1698 dev_err(&pdev->dev, "can't allocate at_xdmac structure\n");
1699 return -ENOMEM;
1700 }
1701
1702 atxdmac->regs = base;
1703 atxdmac->irq = irq;
1704
1705 atxdmac->clk = devm_clk_get(&pdev->dev, "dma_clk");
1706 if (IS_ERR(atxdmac->clk)) {
1707 dev_err(&pdev->dev, "can't get dma_clk\n");
1708 return PTR_ERR(atxdmac->clk);
1709 }
1710
1711 /* Do not use dev res to prevent races with tasklet */
1712 ret = request_irq(atxdmac->irq, at_xdmac_interrupt, 0, "at_xdmac", atxdmac);
1713 if (ret) {
1714 dev_err(&pdev->dev, "can't request irq\n");
1715 return ret;
1716 }
1717
1718 ret = clk_prepare_enable(atxdmac->clk);
1719 if (ret) {
1720 dev_err(&pdev->dev, "can't prepare or enable clock\n");
1721 goto err_free_irq;
1722 }
1723
1724 atxdmac->at_xdmac_desc_pool =
1725 dmam_pool_create(dev_name(&pdev->dev), &pdev->dev,
1726 sizeof(struct at_xdmac_desc), 4, 0);
1727 if (!atxdmac->at_xdmac_desc_pool) {
1728 dev_err(&pdev->dev, "no memory for descriptors dma pool\n");
1729 ret = -ENOMEM;
1730 goto err_clk_disable;
1731 }
1732
1733 dma_cap_set(DMA_CYCLIC, atxdmac->dma.cap_mask);
Maxime Ripard6007ccb2015-05-07 17:38:11 +02001734 dma_cap_set(DMA_INTERLEAVE, atxdmac->dma.cap_mask);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001735 dma_cap_set(DMA_MEMCPY, atxdmac->dma.cap_mask);
Maxime Ripardb206d9a2015-05-18 13:46:16 +02001736 dma_cap_set(DMA_MEMSET, atxdmac->dma.cap_mask);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001737 dma_cap_set(DMA_SLAVE, atxdmac->dma.cap_mask);
Ludovic Desrochesfef4cbf2014-11-13 11:52:45 +01001738 /*
1739 * Without DMA_PRIVATE the driver is not able to allocate more than
1740 * one channel, second allocation fails in private_candidate.
1741 */
1742 dma_cap_set(DMA_PRIVATE, atxdmac->dma.cap_mask);
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001743 atxdmac->dma.dev = &pdev->dev;
1744 atxdmac->dma.device_alloc_chan_resources = at_xdmac_alloc_chan_resources;
1745 atxdmac->dma.device_free_chan_resources = at_xdmac_free_chan_resources;
1746 atxdmac->dma.device_tx_status = at_xdmac_tx_status;
1747 atxdmac->dma.device_issue_pending = at_xdmac_issue_pending;
1748 atxdmac->dma.device_prep_dma_cyclic = at_xdmac_prep_dma_cyclic;
Maxime Ripard6007ccb2015-05-07 17:38:11 +02001749 atxdmac->dma.device_prep_interleaved_dma = at_xdmac_prep_interleaved;
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001750 atxdmac->dma.device_prep_dma_memcpy = at_xdmac_prep_dma_memcpy;
Maxime Ripardb206d9a2015-05-18 13:46:16 +02001751 atxdmac->dma.device_prep_dma_memset = at_xdmac_prep_dma_memset;
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001752 atxdmac->dma.device_prep_slave_sg = at_xdmac_prep_slave_sg;
Ludovic Desroches3d138872014-11-17 14:42:07 +01001753 atxdmac->dma.device_config = at_xdmac_device_config;
1754 atxdmac->dma.device_pause = at_xdmac_device_pause;
1755 atxdmac->dma.device_resume = at_xdmac_device_resume;
1756 atxdmac->dma.device_terminate_all = at_xdmac_device_terminate_all;
Ludovic Desroches8ac82f82014-11-17 14:42:44 +01001757 atxdmac->dma.src_addr_widths = AT_XDMAC_DMA_BUSWIDTHS;
1758 atxdmac->dma.dst_addr_widths = AT_XDMAC_DMA_BUSWIDTHS;
1759 atxdmac->dma.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
1760 atxdmac->dma.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001761
1762 /* Disable all chans and interrupts. */
1763 at_xdmac_off(atxdmac);
1764
1765 /* Init channels. */
1766 INIT_LIST_HEAD(&atxdmac->dma.channels);
1767 for (i = 0; i < nr_channels; i++) {
1768 struct at_xdmac_chan *atchan = &atxdmac->chan[i];
1769
1770 atchan->chan.device = &atxdmac->dma;
1771 list_add_tail(&atchan->chan.device_node,
1772 &atxdmac->dma.channels);
1773
1774 atchan->ch_regs = at_xdmac_chan_reg_base(atxdmac, i);
1775 atchan->mask = 1 << i;
1776
1777 spin_lock_init(&atchan->lock);
1778 INIT_LIST_HEAD(&atchan->xfers_list);
1779 INIT_LIST_HEAD(&atchan->free_descs_list);
1780 tasklet_init(&atchan->tasklet, at_xdmac_tasklet,
1781 (unsigned long)atchan);
1782
1783 /* Clear pending interrupts. */
1784 while (at_xdmac_chan_read(atchan, AT_XDMAC_CIS))
1785 cpu_relax();
1786 }
1787 platform_set_drvdata(pdev, atxdmac);
1788
1789 ret = dma_async_device_register(&atxdmac->dma);
1790 if (ret) {
1791 dev_err(&pdev->dev, "fail to register DMA engine device\n");
1792 goto err_clk_disable;
1793 }
1794
1795 ret = of_dma_controller_register(pdev->dev.of_node,
1796 at_xdmac_xlate, atxdmac);
1797 if (ret) {
1798 dev_err(&pdev->dev, "could not register of dma controller\n");
1799 goto err_dma_unregister;
1800 }
1801
1802 dev_info(&pdev->dev, "%d channels, mapped at 0x%p\n",
1803 nr_channels, atxdmac->regs);
1804
1805 return 0;
1806
1807err_dma_unregister:
1808 dma_async_device_unregister(&atxdmac->dma);
1809err_clk_disable:
1810 clk_disable_unprepare(atxdmac->clk);
1811err_free_irq:
1812 free_irq(atxdmac->irq, atxdmac->dma.dev);
1813 return ret;
1814}
1815
1816static int at_xdmac_remove(struct platform_device *pdev)
1817{
1818 struct at_xdmac *atxdmac = (struct at_xdmac *)platform_get_drvdata(pdev);
1819 int i;
1820
1821 at_xdmac_off(atxdmac);
1822 of_dma_controller_free(pdev->dev.of_node);
1823 dma_async_device_unregister(&atxdmac->dma);
1824 clk_disable_unprepare(atxdmac->clk);
1825
1826 synchronize_irq(atxdmac->irq);
1827
1828 free_irq(atxdmac->irq, atxdmac->dma.dev);
1829
1830 for (i = 0; i < atxdmac->dma.chancnt; i++) {
1831 struct at_xdmac_chan *atchan = &atxdmac->chan[i];
1832
1833 tasklet_kill(&atchan->tasklet);
1834 at_xdmac_free_chan_resources(&atchan->chan);
1835 }
1836
1837 return 0;
1838}
1839
1840static const struct dev_pm_ops atmel_xdmac_dev_pm_ops = {
1841 .prepare = atmel_xdmac_prepare,
1842 SET_LATE_SYSTEM_SLEEP_PM_OPS(atmel_xdmac_suspend, atmel_xdmac_resume)
1843};
1844
1845static const struct of_device_id atmel_xdmac_dt_ids[] = {
1846 {
1847 .compatible = "atmel,sama5d4-dma",
1848 }, {
1849 /* sentinel */
1850 }
1851};
1852MODULE_DEVICE_TABLE(of, atmel_xdmac_dt_ids);
1853
1854static struct platform_driver at_xdmac_driver = {
1855 .probe = at_xdmac_probe,
1856 .remove = at_xdmac_remove,
1857 .driver = {
1858 .name = "at_xdmac",
Ludovic Desrochese1f7c9e2014-10-22 17:22:18 +02001859 .of_match_table = of_match_ptr(atmel_xdmac_dt_ids),
1860 .pm = &atmel_xdmac_dev_pm_ops,
1861 }
1862};
1863
1864static int __init at_xdmac_init(void)
1865{
1866 return platform_driver_probe(&at_xdmac_driver, at_xdmac_probe);
1867}
1868subsys_initcall(at_xdmac_init);
1869
1870MODULE_DESCRIPTION("Atmel Extended DMA Controller driver");
1871MODULE_AUTHOR("Ludovic Desroches <ludovic.desroches@atmel.com>");
1872MODULE_LICENSE("GPL");