blob: 2dbd3785ee6f0d00b4c3d88bada28d83c0203b2a [file] [log] [blame]
Kevin Hilman8bd22942009-05-28 10:56:16 -07001/*
2 * OMAP3 Power Management Routines
3 *
4 * Copyright (C) 2006-2008 Nokia Corporation
5 * Tony Lindgren <tony@atomide.com>
6 * Jouni Hogander
7 *
Rajendra Nayak2f5939c2008-09-26 17:50:07 +05308 * Copyright (C) 2007 Texas Instruments, Inc.
9 * Rajendra Nayak <rnayak@ti.com>
10 *
Kevin Hilman8bd22942009-05-28 10:56:16 -070011 * Copyright (C) 2005 Texas Instruments, Inc.
12 * Richard Woodruff <r-woodruff2@ti.com>
13 *
14 * Based on pm.c for omap1
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
19 */
20
21#include <linux/pm.h>
22#include <linux/suspend.h>
23#include <linux/interrupt.h>
24#include <linux/module.h>
25#include <linux/list.h>
26#include <linux/err.h>
27#include <linux/gpio.h>
Kevin Hilmanc40552b2009-10-06 14:25:09 -070028#include <linux/clk.h>
Tero Kristodccaad82009-11-17 18:34:53 +020029#include <linux/delay.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090030#include <linux/slab.h>
Tony Lindgren45c3eb72012-11-30 08:41:50 -080031#include <linux/omap-dma.h>
Tony Lindgrene639cd52014-11-20 12:11:25 -080032#include <linux/omap-gpmc.h>
Tony Lindgren4b254082012-08-30 15:37:24 -070033#include <linux/platform_data/gpio-omap.h>
34
Jean Pihet5e7c58d2011-03-03 11:25:43 +010035#include <trace/events/power.h>
Kevin Hilman8bd22942009-05-28 10:56:16 -070036
Tony Lindgrenbf027ca2012-10-29 13:54:06 -070037#include <asm/fncpy.h>
Russell King2c74a0c2011-06-22 17:41:48 +010038#include <asm/suspend.h>
David Howells9f97da72012-03-28 18:30:01 +010039#include <asm/system_misc.h>
Russell King2c74a0c2011-06-22 17:41:48 +010040
Paul Walmsley1540f2142010-12-21 21:05:15 -070041#include "clockdomain.h"
Paul Walmsley72e06d02010-12-21 21:05:16 -070042#include "powerdomain.h"
Tony Lindgrene4c060d2012-10-05 13:25:59 -070043#include "soc.h"
Tony Lindgren4e653312011-11-10 22:45:17 +010044#include "common.h"
Paul Walmsleyff4ae5d2012-10-21 01:01:11 -060045#include "cm3xxx.h"
Kevin Hilman8bd22942009-05-28 10:56:16 -070046#include "cm-regbits-34xx.h"
47#include "prm-regbits-34xx.h"
Paul Walmsley139563a2012-10-21 01:01:10 -060048#include "prm3xxx.h"
Kevin Hilman8bd22942009-05-28 10:56:16 -070049#include "pm.h"
Tero Kristo13a6fe0f2008-10-13 13:17:06 +030050#include "sdrc.h"
Tony Lindgrenbf027ca2012-10-29 13:54:06 -070051#include "sram.h"
Paul Walmsley4814ced2010-10-08 11:40:20 -060052#include "control.h"
Tony Lindgren3b8c4eb2014-05-05 17:27:35 -070053#include "vc.h"
Tero Kristo13a6fe0f2008-10-13 13:17:06 +030054
Nishanth Menon8cdfd832010-12-20 14:05:05 -060055/* pm34xx errata defined in pm.h */
56u16 pm34xx_errata;
57
Kevin Hilman8bd22942009-05-28 10:56:16 -070058struct power_state {
59 struct powerdomain *pwrdm;
60 u32 next_state;
Kevin Hilman10f90ed2009-06-24 11:39:18 -070061#ifdef CONFIG_SUSPEND
Kevin Hilman8bd22942009-05-28 10:56:16 -070062 u32 saved_state;
Kevin Hilman10f90ed2009-06-24 11:39:18 -070063#endif
Kevin Hilman8bd22942009-05-28 10:56:16 -070064 struct list_head node;
65};
66
67static LIST_HEAD(pwrst_list);
68
Tero Kristo27d59a42008-10-13 13:15:00 +030069static int (*_omap_save_secure_sram)(u32 *addr);
Jean Pihet46e130d2011-06-29 18:40:23 +020070void (*omap3_do_wfi_sram)(void);
Tero Kristo27d59a42008-10-13 13:15:00 +030071
Rajendra Nayakfa3c2a42008-09-26 17:49:22 +053072static struct powerdomain *mpu_pwrdm, *neon_pwrdm;
73static struct powerdomain *core_pwrdm, *per_pwrdm;
Kalle Jokiniemi3a7ec262009-03-26 15:59:01 +020074
Rajendra Nayak2f5939c2008-09-26 17:50:07 +053075static void omap3_core_save_context(void)
76{
Paul Walmsley596efe42010-12-21 21:05:16 -070077 omap3_ctrl_save_padconf();
Tero Kristodccaad82009-11-17 18:34:53 +020078
79 /*
80 * Force write last pad into memory, as this can fail in some
Jean Pihet83521292010-12-18 16:44:46 +010081 * cases according to errata 1.157, 1.185
Tero Kristodccaad82009-11-17 18:34:53 +020082 */
83 omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14),
84 OMAP343X_CONTROL_MEM_WKUP + 0x2a0);
85
Rajendra Nayak2f5939c2008-09-26 17:50:07 +053086 /* Save the Interrupt controller context */
87 omap_intc_save_context();
88 /* Save the GPMC context */
89 omap3_gpmc_save_context();
90 /* Save the system control module context, padconf already save above*/
91 omap3_control_save_context();
Tero Kristof2d11852008-08-28 13:13:31 +000092 omap_dma_global_context_save();
Rajendra Nayak2f5939c2008-09-26 17:50:07 +053093}
94
95static void omap3_core_restore_context(void)
96{
97 /* Restore the control module context, padconf restored by h/w */
98 omap3_control_restore_context();
99 /* Restore the GPMC context */
100 omap3_gpmc_restore_context();
101 /* Restore the interrupt controller context */
102 omap_intc_restore_context();
Tero Kristof2d11852008-08-28 13:13:31 +0000103 omap_dma_global_context_restore();
Rajendra Nayak2f5939c2008-09-26 17:50:07 +0530104}
105
Tero Kristo9d971402008-12-12 11:20:05 +0200106/*
107 * FIXME: This function should be called before entering off-mode after
108 * OMAP3 secure services have been accessed. Currently it is only called
109 * once during boot sequence, but this works as we are not using secure
110 * services.
111 */
Kevin Hilman617fcc92011-01-25 16:40:01 -0800112static void omap3_save_secure_ram_context(void)
Tero Kristo27d59a42008-10-13 13:15:00 +0300113{
114 u32 ret;
Kevin Hilman617fcc92011-01-25 16:40:01 -0800115 int mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
Tero Kristo27d59a42008-10-13 13:15:00 +0300116
117 if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
Tero Kristo27d59a42008-10-13 13:15:00 +0300118 /*
119 * MPU next state must be set to POWER_ON temporarily,
120 * otherwise the WFI executed inside the ROM code
121 * will hang the system.
122 */
123 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
Olof Johansson6dd1e352013-11-12 22:51:28 -0800124 ret = _omap_save_secure_sram((u32 *)(unsigned long)
Tero Kristo27d59a42008-10-13 13:15:00 +0300125 __pa(omap3_secure_ram_storage));
Kevin Hilman617fcc92011-01-25 16:40:01 -0800126 pwrdm_set_next_pwrst(mpu_pwrdm, mpu_next_state);
Tero Kristo27d59a42008-10-13 13:15:00 +0300127 /* Following is for error tracking, it should not happen */
128 if (ret) {
Mark A. Greer98179852012-03-17 18:22:48 -0700129 pr_err("save_secure_sram() returns %08x\n", ret);
Tero Kristo27d59a42008-10-13 13:15:00 +0300130 while (1)
131 ;
132 }
133 }
134}
135
Tero Kristo22f51372011-12-16 14:36:59 -0700136static irqreturn_t _prcm_int_handle_io(int irq, void *unused)
Paul Walmsley8cb0ac92009-07-22 10:29:02 -0700137{
138 int c;
139
Tero Kristo9cb6d362014-04-04 12:31:51 +0300140 c = omap_prm_clear_mod_irqs(WKUP_MOD, 1, OMAP3430_ST_IO_MASK |
141 OMAP3430_ST_IO_CHAIN_MASK);
Paul Walmsley8cb0ac92009-07-22 10:29:02 -0700142
Tero Kristo22f51372011-12-16 14:36:59 -0700143 return c ? IRQ_HANDLED : IRQ_NONE;
Jon Hunter77da2d92009-06-27 00:07:25 -0500144}
145
Tero Kristo22f51372011-12-16 14:36:59 -0700146static irqreturn_t _prcm_int_handle_wakeup(int irq, void *unused)
Kevin Hilman8bd22942009-05-28 10:56:16 -0700147{
Tero Kristo22f51372011-12-16 14:36:59 -0700148 int c;
Kevin Hilman8bd22942009-05-28 10:56:16 -0700149
Tero Kristo22f51372011-12-16 14:36:59 -0700150 /*
151 * Clear all except ST_IO and ST_IO_CHAIN for wkup module,
152 * these are handled in a separate handler to avoid acking
153 * IO events before parsing in mux code
154 */
Tero Kristo9cb6d362014-04-04 12:31:51 +0300155 c = omap_prm_clear_mod_irqs(WKUP_MOD, 1, ~(OMAP3430_ST_IO_MASK |
156 OMAP3430_ST_IO_CHAIN_MASK));
157 c += omap_prm_clear_mod_irqs(CORE_MOD, 1, ~0);
158 c += omap_prm_clear_mod_irqs(OMAP3430_PER_MOD, 1, ~0);
Tero Kristo22f51372011-12-16 14:36:59 -0700159 if (omap_rev() > OMAP3430_REV_ES1_0) {
Tero Kristo9cb6d362014-04-04 12:31:51 +0300160 c += omap_prm_clear_mod_irqs(CORE_MOD, 3, ~0);
161 c += omap_prm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1, ~0);
Tero Kristo22f51372011-12-16 14:36:59 -0700162 }
Paul Walmsley8cb0ac92009-07-22 10:29:02 -0700163
Tero Kristo22f51372011-12-16 14:36:59 -0700164 return c ? IRQ_HANDLED : IRQ_NONE;
Kevin Hilman8bd22942009-05-28 10:56:16 -0700165}
166
Russell Kingcbe26342011-06-30 08:45:49 +0100167static void omap34xx_save_context(u32 *save)
168{
169 u32 val;
170
171 /* Read Auxiliary Control Register */
172 asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (val));
173 *save++ = 1;
174 *save++ = val;
175
176 /* Read L2 AUX ctrl register */
177 asm("mrc p15, 1, %0, c9, c0, 2" : "=r" (val));
178 *save++ = 1;
179 *save++ = val;
180}
181
Russell King29cb3cd2011-07-02 09:54:01 +0100182static int omap34xx_do_sram_idle(unsigned long save_state)
Rajendra Nayak57f277b2008-09-26 17:49:34 +0530183{
Russell Kingcbe26342011-06-30 08:45:49 +0100184 omap34xx_cpu_suspend(save_state);
Russell King29cb3cd2011-07-02 09:54:01 +0100185 return 0;
Rajendra Nayak57f277b2008-09-26 17:49:34 +0530186}
187
Rajendra Nayak99e6a4d2008-10-08 17:30:58 +0530188void omap_sram_idle(void)
Kevin Hilman8bd22942009-05-28 10:56:16 -0700189{
190 /* Variable to tell what needs to be saved and restored
191 * in omap_sram_idle*/
192 /* save_state = 0 => Nothing to save and restored */
193 /* save_state = 1 => Only L1 and logic lost */
194 /* save_state = 2 => Only L2 lost */
195 /* save_state = 3 => L1, L2 and logic lost */
Rajendra Nayakfa3c2a42008-09-26 17:49:22 +0530196 int save_state = 0;
197 int mpu_next_state = PWRDM_POWER_ON;
198 int per_next_state = PWRDM_POWER_ON;
199 int core_next_state = PWRDM_POWER_ON;
Paul Walmsley72e06d02010-12-21 21:05:16 -0700200 int per_going_off;
Paul Walmsleyeeb37112012-04-13 06:34:32 -0600201 int core_prev_state;
Tero Kristo13a6fe0f2008-10-13 13:17:06 +0300202 u32 sdrc_pwr = 0;
Kevin Hilman8bd22942009-05-28 10:56:16 -0700203
Kevin Hilman8bd22942009-05-28 10:56:16 -0700204 mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
205 switch (mpu_next_state) {
Rajendra Nayakfa3c2a42008-09-26 17:49:22 +0530206 case PWRDM_POWER_ON:
Kevin Hilman8bd22942009-05-28 10:56:16 -0700207 case PWRDM_POWER_RET:
208 /* No need to save context */
209 save_state = 0;
210 break;
Rajendra Nayak61255ab2008-09-26 17:49:56 +0530211 case PWRDM_POWER_OFF:
212 save_state = 3;
213 break;
Kevin Hilman8bd22942009-05-28 10:56:16 -0700214 default:
215 /* Invalid state */
Mark A. Greer98179852012-03-17 18:22:48 -0700216 pr_err("Invalid mpu state in sram_idle\n");
Kevin Hilman8bd22942009-05-28 10:56:16 -0700217 return;
218 }
Peter 'p2' De Schrijverfe617af2008-10-15 17:48:44 +0300219
Rajendra Nayakfa3c2a42008-09-26 17:49:22 +0530220 /* NEON control */
221 if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON)
Jouni Hogander71391782008-10-28 10:59:05 +0200222 pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state);
Rajendra Nayakfa3c2a42008-09-26 17:49:22 +0530223
Mike Chan40742fa2010-05-03 16:04:06 -0700224 /* Enable IO-PAD and IO-CHAIN wakeups */
Kevin Hilman658ce972008-11-04 20:50:52 -0800225 per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
Tero Kristoecf157d2008-12-01 13:17:29 +0200226 core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
Mike Chan40742fa2010-05-03 16:04:06 -0700227
Kevin Hilmane0e29fd2012-08-07 11:28:06 -0700228 pwrdm_pre_transition(NULL);
Charulatha Vff2f8e52011-09-13 18:32:37 +0530229
Mike Chan40742fa2010-05-03 16:04:06 -0700230 /* PER */
Kevin Hilman658ce972008-11-04 20:50:52 -0800231 if (per_next_state < PWRDM_POWER_ON) {
Paul Walmsley72e06d02010-12-21 21:05:16 -0700232 per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0;
Paul Walmsley72e06d02010-12-21 21:05:16 -0700233 omap2_gpio_prepare_for_idle(per_going_off);
Kevin Hilman658ce972008-11-04 20:50:52 -0800234 }
235
236 /* CORE */
Rajendra Nayakfa3c2a42008-09-26 17:49:22 +0530237 if (core_next_state < PWRDM_POWER_ON) {
Rajendra Nayak2f5939c2008-09-26 17:50:07 +0530238 if (core_next_state == PWRDM_POWER_OFF) {
239 omap3_core_save_context();
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700240 omap3_cm_save_context();
Rajendra Nayak2f5939c2008-09-26 17:50:07 +0530241 }
Rajendra Nayakfa3c2a42008-09-26 17:49:22 +0530242 }
Mike Chan40742fa2010-05-03 16:04:06 -0700243
Tony Lindgren3b8c4eb2014-05-05 17:27:35 -0700244 /* Configure PMIC signaling for I2C4 or sys_off_mode */
245 omap3_vc_set_pmic_signaling(core_next_state);
246
Tero Kristof18cc2f2009-10-23 19:03:50 +0300247 omap3_intc_prepare_idle();
Kevin Hilman8bd22942009-05-28 10:56:16 -0700248
Rajendra Nayak61255ab2008-09-26 17:49:56 +0530249 /*
Paul Walmsley30474542011-10-06 13:43:23 -0600250 * On EMU/HS devices ROM code restores a SRDC value
251 * from scratchpad which has automatic self refresh on timeout
252 * of AUTO_CNT = 1 enabled. This takes care of erratum ID i443.
253 * Hence store/restore the SDRC_POWER register here.
254 */
255 if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 &&
256 (omap_type() == OMAP2_DEVICE_TYPE_EMU ||
257 omap_type() == OMAP2_DEVICE_TYPE_SEC) &&
Rajendra Nayakf265dc42009-06-09 22:30:41 +0530258 core_next_state == PWRDM_POWER_OFF)
Tero Kristo13a6fe0f2008-10-13 13:17:06 +0300259 sdrc_pwr = sdrc_read_reg(SDRC_POWER);
Tero Kristo13a6fe0f2008-10-13 13:17:06 +0300260
261 /*
Russell King076f2cc2011-06-22 15:42:54 +0100262 * omap3_arm_context is the location where some ARM context
263 * get saved. The rest is placed on the stack, and restored
264 * from there before resuming.
Rajendra Nayak61255ab2008-09-26 17:49:56 +0530265 */
Russell Kingcbe26342011-06-30 08:45:49 +0100266 if (save_state)
267 omap34xx_save_context(omap3_arm_context);
Russell King076f2cc2011-06-22 15:42:54 +0100268 if (save_state == 1 || save_state == 3)
Russell King2c74a0c2011-06-22 17:41:48 +0100269 cpu_suspend(save_state, omap34xx_do_sram_idle);
Russell King076f2cc2011-06-22 15:42:54 +0100270 else
271 omap34xx_do_sram_idle(save_state);
Kevin Hilman8bd22942009-05-28 10:56:16 -0700272
Rajendra Nayakf265dc42009-06-09 22:30:41 +0530273 /* Restore normal SDRC POWER settings */
Paul Walmsley30474542011-10-06 13:43:23 -0600274 if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 &&
275 (omap_type() == OMAP2_DEVICE_TYPE_EMU ||
276 omap_type() == OMAP2_DEVICE_TYPE_SEC) &&
Tero Kristo13a6fe0f2008-10-13 13:17:06 +0300277 core_next_state == PWRDM_POWER_OFF)
278 sdrc_write_reg(sdrc_pwr, SDRC_POWER);
279
Kevin Hilman658ce972008-11-04 20:50:52 -0800280 /* CORE */
Rajendra Nayakfa3c2a42008-09-26 17:49:22 +0530281 if (core_next_state < PWRDM_POWER_ON) {
Rajendra Nayak2f5939c2008-09-26 17:50:07 +0530282 core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm);
283 if (core_prev_state == PWRDM_POWER_OFF) {
284 omap3_core_restore_context();
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700285 omap3_cm_restore_context();
Rajendra Nayak2f5939c2008-09-26 17:50:07 +0530286 omap3_sram_restore_context();
Kalle Jokiniemi8a917d22009-05-13 13:32:11 +0300287 omap2_sms_restore_context();
Rajendra Nayak2f5939c2008-09-26 17:50:07 +0530288 }
Kevin Hilman658ce972008-11-04 20:50:52 -0800289 }
Tero Kristof18cc2f2009-10-23 19:03:50 +0300290 omap3_intc_resume_idle();
Kevin Hilman658ce972008-11-04 20:50:52 -0800291
Kevin Hilmane0e29fd2012-08-07 11:28:06 -0700292 pwrdm_post_transition(NULL);
Kevin Hilman658ce972008-11-04 20:50:52 -0800293
Kevin Hilmane0e29fd2012-08-07 11:28:06 -0700294 /* PER */
295 if (per_next_state < PWRDM_POWER_ON)
296 omap2_gpio_resume_after_idle();
Kevin Hilman8bd22942009-05-28 10:56:16 -0700297}
298
Kevin Hilman8bd22942009-05-28 10:56:16 -0700299static void omap3_pm_idle(void)
300{
Nicolas Pitre0bcd24b2012-01-04 16:27:48 -0500301 if (omap_irq_pending())
Santosh Shilimkar6b856382013-02-11 19:29:45 +0530302 return;
Kevin Hilman8bd22942009-05-28 10:56:16 -0700303
Jisheng Zhang6ca22702015-09-18 13:41:21 +0800304 trace_cpu_idle_rcuidle(1, smp_processor_id());
Jean Pihet5e7c58d2011-03-03 11:25:43 +0100305
Kevin Hilman8bd22942009-05-28 10:56:16 -0700306 omap_sram_idle();
307
Jisheng Zhang6ca22702015-09-18 13:41:21 +0800308 trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
Kevin Hilman8bd22942009-05-28 10:56:16 -0700309}
310
Kevin Hilman10f90ed2009-06-24 11:39:18 -0700311#ifdef CONFIG_SUSPEND
Kevin Hilman8bd22942009-05-28 10:56:16 -0700312static int omap3_pm_suspend(void)
313{
314 struct power_state *pwrst;
315 int state, ret = 0;
316
317 /* Read current next_pwrsts */
318 list_for_each_entry(pwrst, &pwrst_list, node)
319 pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
320 /* Set ones wanted by suspend */
321 list_for_each_entry(pwrst, &pwrst_list, node) {
Santosh Shilimkareb6a2c72010-09-15 01:04:01 +0530322 if (omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state))
Kevin Hilman8bd22942009-05-28 10:56:16 -0700323 goto restore;
324 if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm))
325 goto restore;
326 }
327
Tero Kristo2bbe3af2009-10-23 19:03:48 +0300328 omap3_intc_suspend();
329
Kevin Hilman8bd22942009-05-28 10:56:16 -0700330 omap_sram_idle();
331
332restore:
333 /* Restore next_pwrsts */
334 list_for_each_entry(pwrst, &pwrst_list, node) {
Kevin Hilman8bd22942009-05-28 10:56:16 -0700335 state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
336 if (state > pwrst->next_state) {
Paul Walmsley7852ec02012-07-26 00:54:26 -0600337 pr_info("Powerdomain (%s) didn't enter target state %d\n",
338 pwrst->pwrdm->name, pwrst->next_state);
Kevin Hilman8bd22942009-05-28 10:56:16 -0700339 ret = -1;
340 }
Santosh Shilimkareb6a2c72010-09-15 01:04:01 +0530341 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
Kevin Hilman8bd22942009-05-28 10:56:16 -0700342 }
343 if (ret)
Mark A. Greer98179852012-03-17 18:22:48 -0700344 pr_err("Could not enter target state in pm_suspend\n");
Kevin Hilman8bd22942009-05-28 10:56:16 -0700345 else
Mark A. Greer98179852012-03-17 18:22:48 -0700346 pr_info("Successfully put all powerdomains to target state\n");
Kevin Hilman8bd22942009-05-28 10:56:16 -0700347
348 return ret;
349}
Dave Gerlach2e4b62d2014-05-12 13:33:21 -0500350#else
351#define omap3_pm_suspend NULL
Kevin Hilman10f90ed2009-06-24 11:39:18 -0700352#endif /* CONFIG_SUSPEND */
Kevin Hilman8bd22942009-05-28 10:56:16 -0700353
Kevin Hilman8111b222009-04-28 15:27:44 -0700354static void __init prcm_setup_regs(void)
355{
Tero Kristoba12c242014-03-04 17:43:04 +0200356 omap3_ctrl_init();
Tero Kristob296c812009-10-23 19:03:49 +0300357
Tero Kristoc5180a22014-02-26 17:30:43 +0200358 omap3_prm_init_pm(cpu_is_omap3630(), omap3_has_iva());
Kevin Hilman8bd22942009-05-28 10:56:16 -0700359}
360
Kevin Hilmanc40552b2009-10-06 14:25:09 -0700361void omap3_pm_off_mode_enable(int enable)
362{
363 struct power_state *pwrst;
364 u32 state;
365
366 if (enable)
367 state = PWRDM_POWER_OFF;
368 else
369 state = PWRDM_POWER_RET;
370
371 list_for_each_entry(pwrst, &pwrst_list, node) {
Eduardo Valentincc1b6022010-12-20 14:05:09 -0600372 if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583) &&
373 pwrst->pwrdm == core_pwrdm &&
374 state == PWRDM_POWER_OFF) {
375 pwrst->next_state = PWRDM_POWER_RET;
Ricardo Salveti de Araujoe16b41b2011-01-31 11:35:25 -0200376 pr_warn("%s: Core OFF disabled due to errata i583\n",
Eduardo Valentincc1b6022010-12-20 14:05:09 -0600377 __func__);
378 } else {
379 pwrst->next_state = state;
380 }
381 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
Kevin Hilmanc40552b2009-10-06 14:25:09 -0700382 }
383}
384
Tero Kristo68d47782008-11-26 12:26:24 +0200385int omap3_pm_get_suspend_state(struct powerdomain *pwrdm)
386{
387 struct power_state *pwrst;
388
389 list_for_each_entry(pwrst, &pwrst_list, node) {
390 if (pwrst->pwrdm == pwrdm)
391 return pwrst->next_state;
392 }
393 return -EINVAL;
394}
395
396int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state)
397{
398 struct power_state *pwrst;
399
400 list_for_each_entry(pwrst, &pwrst_list, node) {
401 if (pwrst->pwrdm == pwrdm) {
402 pwrst->next_state = state;
403 return 0;
404 }
405 }
406 return -EINVAL;
407}
408
Peter 'p2' De Schrijvera23456e2008-10-15 18:13:47 +0300409static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
Kevin Hilman8bd22942009-05-28 10:56:16 -0700410{
411 struct power_state *pwrst;
412
413 if (!pwrdm->pwrsts)
414 return 0;
415
Ming Leid3d381c2009-08-22 21:20:26 +0800416 pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
Kevin Hilman8bd22942009-05-28 10:56:16 -0700417 if (!pwrst)
418 return -ENOMEM;
419 pwrst->pwrdm = pwrdm;
420 pwrst->next_state = PWRDM_POWER_RET;
421 list_add(&pwrst->node, &pwrst_list);
422
423 if (pwrdm_has_hdwr_sar(pwrdm))
424 pwrdm_enable_hdwr_sar(pwrdm);
425
Santosh Shilimkareb6a2c72010-09-15 01:04:01 +0530426 return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
Kevin Hilman8bd22942009-05-28 10:56:16 -0700427}
428
429/*
Jean Pihet46e130d2011-06-29 18:40:23 +0200430 * Push functions to SRAM
431 *
432 * The minimum set of functions is pushed to SRAM for execution:
433 * - omap3_do_wfi for erratum i581 WA,
434 * - save_secure_ram_context for security extensions.
435 */
Rajendra Nayak3231fc82008-09-26 17:49:14 +0530436void omap_push_sram_idle(void)
437{
Jean Pihet46e130d2011-06-29 18:40:23 +0200438 omap3_do_wfi_sram = omap_sram_push(omap3_do_wfi, omap3_do_wfi_sz);
439
Tero Kristo27d59a42008-10-13 13:15:00 +0300440 if (omap_type() != OMAP2_DEVICE_TYPE_GP)
441 _omap_save_secure_sram = omap_sram_push(save_secure_ram_context,
442 save_secure_ram_context_sz);
Rajendra Nayak3231fc82008-09-26 17:49:14 +0530443}
444
Nishanth Menon8cdfd832010-12-20 14:05:05 -0600445static void __init pm_errata_configure(void)
446{
Peter 'p2' De Schrijverc4236d22010-12-20 14:05:07 -0600447 if (cpu_is_omap3630()) {
Nishanth Menon458e9992010-12-20 14:05:06 -0600448 pm34xx_errata |= PM_RTA_ERRATUM_i608;
Peter 'p2' De Schrijverc4236d22010-12-20 14:05:07 -0600449 /* Enable the l2 cache toggling in sleep logic */
450 enable_omap3630_toggle_l2_on_restore();
Eduardo Valentincc1b6022010-12-20 14:05:09 -0600451 if (omap_rev() < OMAP3630_REV_ES1_2)
Paul Walmsley856c3c52012-10-16 00:08:53 -0600452 pm34xx_errata |= (PM_SDRC_WAKEUP_ERRATUM_i583 |
453 PM_PER_MEMORIES_ERRATUM_i582);
454 } else if (cpu_is_omap34xx()) {
455 pm34xx_errata |= PM_PER_MEMORIES_ERRATUM_i582;
Peter 'p2' De Schrijverc4236d22010-12-20 14:05:07 -0600456 }
Nishanth Menon8cdfd832010-12-20 14:05:05 -0600457}
458
Shawn Guobbd707a2012-04-26 16:06:50 +0800459int __init omap3_pm_init(void)
Kevin Hilman8bd22942009-05-28 10:56:16 -0700460{
461 struct power_state *pwrst, *tmp;
Paul Walmsley856c3c52012-10-16 00:08:53 -0600462 struct clockdomain *neon_clkdm, *mpu_clkdm, *per_clkdm, *wkup_clkdm;
Kevin Hilman8bd22942009-05-28 10:56:16 -0700463 int ret;
464
Paul Walmsleyb02b9172011-10-06 17:18:45 -0600465 if (!omap3_has_io_chain_ctrl())
Joe Perches3d0cb732014-09-13 11:31:16 -0700466 pr_warn("PM: no software I/O chain control; some wakeups may be lost\n");
Paul Walmsleyb02b9172011-10-06 17:18:45 -0600467
Nishanth Menon8cdfd832010-12-20 14:05:05 -0600468 pm_errata_configure();
469
Kevin Hilman8bd22942009-05-28 10:56:16 -0700470 /* XXX prcm_setup_regs needs to be before enabling hw
471 * supervised mode for powerdomains */
472 prcm_setup_regs();
473
Tero Kristo22f51372011-12-16 14:36:59 -0700474 ret = request_irq(omap_prcm_event_to_irq("wkup"),
475 _prcm_int_handle_wakeup, IRQF_NO_SUSPEND, "pm_wkup", NULL);
476
Kevin Hilman8bd22942009-05-28 10:56:16 -0700477 if (ret) {
Tero Kristo22f51372011-12-16 14:36:59 -0700478 pr_err("pm: Failed to request pm_wkup irq\n");
479 goto err1;
480 }
481
482 /* IO interrupt is shared with mux code */
483 ret = request_irq(omap_prcm_event_to_irq("io"),
484 _prcm_int_handle_io, IRQF_SHARED | IRQF_NO_SUSPEND, "pm_io",
485 omap3_pm_init);
Kevin Hilman99b59df2012-04-27 16:05:51 -0700486 enable_irq(omap_prcm_event_to_irq("io"));
Tero Kristo22f51372011-12-16 14:36:59 -0700487
488 if (ret) {
489 pr_err("pm: Failed to request pm_io irq\n");
Mark A. Greerce229c52012-03-17 18:22:47 -0700490 goto err2;
Kevin Hilman8bd22942009-05-28 10:56:16 -0700491 }
492
Peter 'p2' De Schrijvera23456e2008-10-15 18:13:47 +0300493 ret = pwrdm_for_each(pwrdms_setup, NULL);
Kevin Hilman8bd22942009-05-28 10:56:16 -0700494 if (ret) {
Mark A. Greer98179852012-03-17 18:22:48 -0700495 pr_err("Failed to setup powerdomains\n");
Mark A. Greerce229c52012-03-17 18:22:47 -0700496 goto err3;
Kevin Hilman8bd22942009-05-28 10:56:16 -0700497 }
498
Paul Walmsley92206fd2012-02-02 02:38:50 -0700499 (void) clkdm_for_each(omap_pm_clkdms_setup, NULL);
Kevin Hilman8bd22942009-05-28 10:56:16 -0700500
501 mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
502 if (mpu_pwrdm == NULL) {
Mark A. Greer98179852012-03-17 18:22:48 -0700503 pr_err("Failed to get mpu_pwrdm\n");
Mark A. Greerce229c52012-03-17 18:22:47 -0700504 ret = -EINVAL;
505 goto err3;
Kevin Hilman8bd22942009-05-28 10:56:16 -0700506 }
507
Rajendra Nayakfa3c2a42008-09-26 17:49:22 +0530508 neon_pwrdm = pwrdm_lookup("neon_pwrdm");
509 per_pwrdm = pwrdm_lookup("per_pwrdm");
510 core_pwrdm = pwrdm_lookup("core_pwrdm");
511
Paul Walmsley55ed9692010-01-26 20:12:59 -0700512 neon_clkdm = clkdm_lookup("neon_clkdm");
513 mpu_clkdm = clkdm_lookup("mpu_clkdm");
Paul Walmsley856c3c52012-10-16 00:08:53 -0600514 per_clkdm = clkdm_lookup("per_clkdm");
515 wkup_clkdm = clkdm_lookup("wkup_clkdm");
Paul Walmsley55ed9692010-01-26 20:12:59 -0700516
Dave Gerlach2e4b62d2014-05-12 13:33:21 -0500517 omap_common_suspend_init(omap3_pm_suspend);
Kevin Hilman8bd22942009-05-28 10:56:16 -0700518
Nicolas Pitre0bcd24b2012-01-04 16:27:48 -0500519 arm_pm_idle = omap3_pm_idle;
Kalle Jokiniemi03433712008-09-26 11:04:20 +0300520 omap3_idle_init();
Kevin Hilman8bd22942009-05-28 10:56:16 -0700521
Nishanth Menon458e9992010-12-20 14:05:06 -0600522 /*
523 * RTA is disabled during initialization as per erratum i608
524 * it is safer to disable RTA by the bootloader, but we would like
525 * to be doubly sure here and prevent any mishaps.
526 */
527 if (IS_PM34XX_ERRATUM(PM_RTA_ERRATUM_i608))
528 omap3630_ctrl_disable_rta();
529
Paul Walmsley856c3c52012-10-16 00:08:53 -0600530 /*
531 * The UART3/4 FIFO and the sidetone memory in McBSP2/3 are
532 * not correctly reset when the PER powerdomain comes back
533 * from OFF or OSWR when the CORE powerdomain is kept active.
534 * See OMAP36xx Erratum i582 "PER Domain reset issue after
535 * Domain-OFF/OSWR Wakeup". This wakeup dependency is not a
536 * complete workaround. The kernel must also prevent the PER
537 * powerdomain from going to OSWR/OFF while the CORE
538 * powerdomain is not going to OSWR/OFF. And if PER last
539 * power state was off while CORE last power state was ON, the
540 * UART3/4 and McBSP2/3 SIDETONE devices need to run a
541 * self-test using their loopback tests; if that fails, those
542 * devices are unusable until the PER/CORE can complete a transition
543 * from ON to OSWR/OFF and then back to ON.
544 *
545 * XXX Technically this workaround is only needed if off-mode
546 * or OSWR is enabled.
547 */
548 if (IS_PM34XX_ERRATUM(PM_PER_MEMORIES_ERRATUM_i582))
549 clkdm_add_wkdep(per_clkdm, wkup_clkdm);
550
Paul Walmsley55ed9692010-01-26 20:12:59 -0700551 clkdm_add_wkdep(neon_clkdm, mpu_clkdm);
Tero Kristo27d59a42008-10-13 13:15:00 +0300552 if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
553 omap3_secure_ram_storage =
554 kmalloc(0x803F, GFP_KERNEL);
555 if (!omap3_secure_ram_storage)
Paul Walmsley7852ec02012-07-26 00:54:26 -0600556 pr_err("Memory allocation failed when allocating for secure sram context\n");
Tero Kristo27d59a42008-10-13 13:15:00 +0300557
Tero Kristo9d971402008-12-12 11:20:05 +0200558 local_irq_disable();
Tero Kristo9d971402008-12-12 11:20:05 +0200559
560 omap_dma_global_context_save();
Kevin Hilman617fcc92011-01-25 16:40:01 -0800561 omap3_save_secure_ram_context();
Tero Kristo9d971402008-12-12 11:20:05 +0200562 omap_dma_global_context_restore();
563
564 local_irq_enable();
Tero Kristo9d971402008-12-12 11:20:05 +0200565 }
566
567 omap3_save_scratchpad_contents();
Kevin Hilman8bd22942009-05-28 10:56:16 -0700568 return ret;
Mark A. Greerce229c52012-03-17 18:22:47 -0700569
570err3:
Kevin Hilman8bd22942009-05-28 10:56:16 -0700571 list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) {
572 list_del(&pwrst->node);
573 kfree(pwrst);
574 }
Mark A. Greerce229c52012-03-17 18:22:47 -0700575 free_irq(omap_prcm_event_to_irq("io"), omap3_pm_init);
576err2:
577 free_irq(omap_prcm_event_to_irq("wkup"), NULL);
578err1:
Kevin Hilman8bd22942009-05-28 10:56:16 -0700579 return ret;
580}