Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2006 Dave Airlie <airlied@linux.ie> |
| 3 | * Copyright © 2006-2007 Intel Corporation |
| 4 | * Jesse Barnes <jesse.barnes@intel.com> |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the "Software"), |
| 8 | * to deal in the Software without restriction, including without limitation |
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
| 11 | * Software is furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice (including the next |
| 14 | * paragraph) shall be included in all copies or substantial portions of the |
| 15 | * Software. |
| 16 | * |
| 17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 22 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
| 23 | * DEALINGS IN THE SOFTWARE. |
| 24 | * |
| 25 | * Authors: |
| 26 | * Eric Anholt <eric@anholt.net> |
| 27 | */ |
| 28 | #include <linux/i2c.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 29 | #include <linux/slab.h> |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 30 | #include <linux/delay.h> |
Paul Gortmaker | 2d1a8a4 | 2011-08-30 18:16:33 -0400 | [diff] [blame] | 31 | #include <linux/export.h> |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 32 | #include "drmP.h" |
| 33 | #include "drm.h" |
| 34 | #include "drm_crtc.h" |
ling.ma@intel.com | 2b8d33f7 | 2009-07-29 11:31:18 +0800 | [diff] [blame] | 35 | #include "drm_edid.h" |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 36 | #include "intel_drv.h" |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 37 | #include "i915_drm.h" |
| 38 | #include "i915_drv.h" |
| 39 | #include "intel_sdvo_regs.h" |
| 40 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 41 | #define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1) |
| 42 | #define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1) |
| 43 | #define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1) |
| 44 | #define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0) |
| 45 | |
| 46 | #define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 47 | SDVO_TV_MASK) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 48 | |
| 49 | #define IS_TV(c) (c->output_flag & SDVO_TV_MASK) |
Chris Wilson | 13946743 | 2011-02-09 20:01:16 +0000 | [diff] [blame] | 50 | #define IS_TMDS(c) (c->output_flag & SDVO_TMDS_MASK) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 51 | #define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK) |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 52 | #define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK)) |
Chris Wilson | 5222008 | 2011-06-20 14:45:50 +0100 | [diff] [blame^] | 53 | #define IS_DIGITAL(c) (c->output_flag & (SDVO_TMDS_MASK | SDVO_LVDS_MASK)) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 54 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 55 | |
Chris Wilson | 2e88e40 | 2010-08-07 11:01:27 +0100 | [diff] [blame] | 56 | static const char *tv_format_names[] = { |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 57 | "NTSC_M" , "NTSC_J" , "NTSC_443", |
| 58 | "PAL_B" , "PAL_D" , "PAL_G" , |
| 59 | "PAL_H" , "PAL_I" , "PAL_M" , |
| 60 | "PAL_N" , "PAL_NC" , "PAL_60" , |
| 61 | "SECAM_B" , "SECAM_D" , "SECAM_G" , |
| 62 | "SECAM_K" , "SECAM_K1", "SECAM_L" , |
| 63 | "SECAM_60" |
| 64 | }; |
| 65 | |
| 66 | #define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names)) |
| 67 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 68 | struct intel_sdvo { |
| 69 | struct intel_encoder base; |
| 70 | |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 71 | struct i2c_adapter *i2c; |
Keith Packard | f9c10a9 | 2009-05-30 12:16:25 -0700 | [diff] [blame] | 72 | u8 slave_addr; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 73 | |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 74 | struct i2c_adapter ddc; |
| 75 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 76 | /* Register for the SDVO device: SDVOB or SDVOC */ |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 77 | int sdvo_reg; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 78 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 79 | /* Active outputs controlled by this SDVO output */ |
| 80 | uint16_t controlled_output; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 81 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 82 | /* |
| 83 | * Capabilities of the SDVO device returned by |
| 84 | * i830_sdvo_get_capabilities() |
| 85 | */ |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 86 | struct intel_sdvo_caps caps; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 87 | |
| 88 | /* Pixel clock limitations reported by the SDVO device, in kHz */ |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 89 | int pixel_clock_min, pixel_clock_max; |
| 90 | |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 91 | /* |
| 92 | * For multiple function SDVO device, |
| 93 | * this is for current attached outputs. |
| 94 | */ |
| 95 | uint16_t attached_output; |
| 96 | |
Simon Farnsworth | cc68c81 | 2011-09-21 17:13:30 +0100 | [diff] [blame] | 97 | /* |
| 98 | * Hotplug activation bits for this device |
| 99 | */ |
| 100 | uint8_t hotplug_active[2]; |
| 101 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 102 | /** |
Chris Wilson | e953fd7 | 2011-02-21 22:23:52 +0000 | [diff] [blame] | 103 | * This is used to select the color range of RBG outputs in HDMI mode. |
| 104 | * It is only valid when using TMDS encoding and 8 bit per color mode. |
| 105 | */ |
| 106 | uint32_t color_range; |
| 107 | |
| 108 | /** |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 109 | * This is set if we're going to treat the device as TV-out. |
| 110 | * |
| 111 | * While we have these nice friendly flags for output types that ought |
| 112 | * to decide this for us, the S-Video output on our HDMI+S-Video card |
| 113 | * shows up as RGB1 (VGA). |
| 114 | */ |
| 115 | bool is_tv; |
| 116 | |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 117 | /* This is for current tv format name */ |
Chris Wilson | 4003975 | 2010-08-04 13:50:26 +0100 | [diff] [blame] | 118 | int tv_format_index; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 119 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 120 | /** |
| 121 | * This is set if we treat the device as HDMI, instead of DVI. |
| 122 | */ |
| 123 | bool is_hdmi; |
Chris Wilson | da79de9 | 2010-11-22 11:12:46 +0000 | [diff] [blame] | 124 | bool has_hdmi_monitor; |
| 125 | bool has_hdmi_audio; |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 126 | |
Ma Ling | 7086c87 | 2009-05-13 11:20:06 +0800 | [diff] [blame] | 127 | /** |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 128 | * This is set if we detect output of sdvo device as LVDS and |
| 129 | * have a valid fixed mode to use with the panel. |
Ma Ling | 7086c87 | 2009-05-13 11:20:06 +0800 | [diff] [blame] | 130 | */ |
| 131 | bool is_lvds; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 132 | |
| 133 | /** |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 134 | * This is sdvo fixed pannel mode pointer |
| 135 | */ |
| 136 | struct drm_display_mode *sdvo_lvds_fixed_mode; |
| 137 | |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 138 | /* DDC bus used by this SDVO encoder */ |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 139 | uint8_t ddc_bus; |
| 140 | |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 141 | /* Input timings for adjusted_mode */ |
| 142 | struct intel_sdvo_dtd input_dtd; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 143 | }; |
| 144 | |
| 145 | struct intel_sdvo_connector { |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 146 | struct intel_connector base; |
| 147 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 148 | /* Mark the type of connector */ |
| 149 | uint16_t output_flag; |
| 150 | |
Chris Wilson | 7f36e7e | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 151 | int force_audio; |
| 152 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 153 | /* This contains all current supported TV format */ |
Chris Wilson | 4003975 | 2010-08-04 13:50:26 +0100 | [diff] [blame] | 154 | u8 tv_format_supported[TV_FORMAT_NUM]; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 155 | int format_supported_num; |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 156 | struct drm_property *tv_format; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 157 | |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 158 | /* add the property for the SDVO-TV */ |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 159 | struct drm_property *left; |
| 160 | struct drm_property *right; |
| 161 | struct drm_property *top; |
| 162 | struct drm_property *bottom; |
| 163 | struct drm_property *hpos; |
| 164 | struct drm_property *vpos; |
| 165 | struct drm_property *contrast; |
| 166 | struct drm_property *saturation; |
| 167 | struct drm_property *hue; |
| 168 | struct drm_property *sharpness; |
| 169 | struct drm_property *flicker_filter; |
| 170 | struct drm_property *flicker_filter_adaptive; |
| 171 | struct drm_property *flicker_filter_2d; |
| 172 | struct drm_property *tv_chroma_filter; |
| 173 | struct drm_property *tv_luma_filter; |
Chris Wilson | e044218 | 2010-08-04 13:50:29 +0100 | [diff] [blame] | 174 | struct drm_property *dot_crawl; |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 175 | |
| 176 | /* add the property for the SDVO-TV/LVDS */ |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 177 | struct drm_property *brightness; |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 178 | |
| 179 | /* Add variable to record current setting for the above property */ |
| 180 | u32 left_margin, right_margin, top_margin, bottom_margin; |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 181 | |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 182 | /* this is to get the range of margin.*/ |
| 183 | u32 max_hscan, max_vscan; |
| 184 | u32 max_hpos, cur_hpos; |
| 185 | u32 max_vpos, cur_vpos; |
| 186 | u32 cur_brightness, max_brightness; |
| 187 | u32 cur_contrast, max_contrast; |
| 188 | u32 cur_saturation, max_saturation; |
| 189 | u32 cur_hue, max_hue; |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 190 | u32 cur_sharpness, max_sharpness; |
| 191 | u32 cur_flicker_filter, max_flicker_filter; |
| 192 | u32 cur_flicker_filter_adaptive, max_flicker_filter_adaptive; |
| 193 | u32 cur_flicker_filter_2d, max_flicker_filter_2d; |
| 194 | u32 cur_tv_chroma_filter, max_tv_chroma_filter; |
| 195 | u32 cur_tv_luma_filter, max_tv_luma_filter; |
Chris Wilson | e044218 | 2010-08-04 13:50:29 +0100 | [diff] [blame] | 196 | u32 cur_dot_crawl, max_dot_crawl; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 197 | }; |
| 198 | |
Chris Wilson | 890f335 | 2010-09-14 16:46:59 +0100 | [diff] [blame] | 199 | static struct intel_sdvo *to_intel_sdvo(struct drm_encoder *encoder) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 200 | { |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 201 | return container_of(encoder, struct intel_sdvo, base.base); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 202 | } |
| 203 | |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 204 | static struct intel_sdvo *intel_attached_sdvo(struct drm_connector *connector) |
| 205 | { |
| 206 | return container_of(intel_attached_encoder(connector), |
| 207 | struct intel_sdvo, base); |
| 208 | } |
| 209 | |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 210 | static struct intel_sdvo_connector *to_intel_sdvo_connector(struct drm_connector *connector) |
| 211 | { |
| 212 | return container_of(to_intel_connector(connector), struct intel_sdvo_connector, base); |
| 213 | } |
| 214 | |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 215 | static bool |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 216 | intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags); |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 217 | static bool |
| 218 | intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo, |
| 219 | struct intel_sdvo_connector *intel_sdvo_connector, |
| 220 | int type); |
| 221 | static bool |
| 222 | intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo, |
| 223 | struct intel_sdvo_connector *intel_sdvo_connector); |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 224 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 225 | /** |
| 226 | * Writes the SDVOB or SDVOC with the given value, but always writes both |
| 227 | * SDVOB and SDVOC to work around apparent hardware issues (according to |
| 228 | * comments in the BIOS). |
| 229 | */ |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 230 | static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 231 | { |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 232 | struct drm_device *dev = intel_sdvo->base.base.dev; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 233 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 234 | u32 bval = val, cval = val; |
| 235 | int i; |
| 236 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 237 | if (intel_sdvo->sdvo_reg == PCH_SDVOB) { |
| 238 | I915_WRITE(intel_sdvo->sdvo_reg, val); |
| 239 | I915_READ(intel_sdvo->sdvo_reg); |
Zhao Yakui | 461ed3c | 2010-03-30 15:11:33 +0800 | [diff] [blame] | 240 | return; |
| 241 | } |
| 242 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 243 | if (intel_sdvo->sdvo_reg == SDVOB) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 244 | cval = I915_READ(SDVOC); |
| 245 | } else { |
| 246 | bval = I915_READ(SDVOB); |
| 247 | } |
| 248 | /* |
| 249 | * Write the registers twice for luck. Sometimes, |
| 250 | * writing them only once doesn't appear to 'stick'. |
| 251 | * The BIOS does this too. Yay, magic |
| 252 | */ |
| 253 | for (i = 0; i < 2; i++) |
| 254 | { |
| 255 | I915_WRITE(SDVOB, bval); |
| 256 | I915_READ(SDVOB); |
| 257 | I915_WRITE(SDVOC, cval); |
| 258 | I915_READ(SDVOC); |
| 259 | } |
| 260 | } |
| 261 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 262 | static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 263 | { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 264 | struct i2c_msg msgs[] = { |
| 265 | { |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 266 | .addr = intel_sdvo->slave_addr, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 267 | .flags = 0, |
| 268 | .len = 1, |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 269 | .buf = &addr, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 270 | }, |
| 271 | { |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 272 | .addr = intel_sdvo->slave_addr, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 273 | .flags = I2C_M_RD, |
| 274 | .len = 1, |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 275 | .buf = ch, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 276 | } |
| 277 | }; |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 278 | int ret; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 279 | |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 280 | if ((ret = i2c_transfer(intel_sdvo->i2c, msgs, 2)) == 2) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 281 | return true; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 282 | |
Zhao Yakui | 8a4c47f | 2009-07-20 13:48:04 +0800 | [diff] [blame] | 283 | DRM_DEBUG_KMS("i2c transfer returned %d\n", ret); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 284 | return false; |
| 285 | } |
| 286 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 287 | #define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd} |
| 288 | /** Mapping of command numbers to names, for debug output */ |
Tobias Klauser | 005568b | 2009-02-09 22:02:42 +0100 | [diff] [blame] | 289 | static const struct _sdvo_cmd_name { |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 290 | u8 cmd; |
Chris Wilson | 2e88e40 | 2010-08-07 11:01:27 +0100 | [diff] [blame] | 291 | const char *name; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 292 | } sdvo_cmd_names[] = { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 293 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET), |
| 294 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS), |
| 295 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV), |
| 296 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS), |
| 297 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS), |
| 298 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS), |
| 299 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP), |
| 300 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP), |
| 301 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS), |
| 302 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT), |
| 303 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG), |
| 304 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG), |
| 305 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE), |
| 306 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT), |
| 307 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT), |
| 308 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1), |
| 309 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2), |
| 310 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1), |
| 311 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2), |
| 312 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1), |
| 313 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1), |
| 314 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2), |
| 315 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1), |
| 316 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2), |
| 317 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING), |
| 318 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1), |
| 319 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2), |
| 320 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE), |
| 321 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE), |
| 322 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS), |
| 323 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT), |
| 324 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT), |
| 325 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS), |
| 326 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT), |
| 327 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT), |
| 328 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES), |
| 329 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE), |
| 330 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE), |
| 331 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE), |
| 332 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH), |
| 333 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT), |
| 334 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT), |
| 335 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS), |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 336 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 337 | /* Add the op code for SDVO enhancements */ |
| 338 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS), |
| 339 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS), |
| 340 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS), |
| 341 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS), |
| 342 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS), |
| 343 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS), |
| 344 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION), |
| 345 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION), |
| 346 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION), |
| 347 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE), |
| 348 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE), |
| 349 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE), |
| 350 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST), |
| 351 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST), |
| 352 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST), |
| 353 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS), |
| 354 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS), |
| 355 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS), |
| 356 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H), |
| 357 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H), |
| 358 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H), |
| 359 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V), |
| 360 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V), |
| 361 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V), |
| 362 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER), |
| 363 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER), |
| 364 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER), |
| 365 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE), |
| 366 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE), |
| 367 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE), |
| 368 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D), |
| 369 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D), |
| 370 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D), |
| 371 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS), |
| 372 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS), |
| 373 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS), |
| 374 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL), |
| 375 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL), |
| 376 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER), |
| 377 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER), |
| 378 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER), |
| 379 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER), |
| 380 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER), |
| 381 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER), |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 382 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 383 | /* HDMI op code */ |
| 384 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE), |
| 385 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE), |
| 386 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE), |
| 387 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI), |
| 388 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI), |
| 389 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP), |
| 390 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY), |
| 391 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY), |
| 392 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER), |
| 393 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT), |
| 394 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT), |
| 395 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX), |
| 396 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX), |
| 397 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO), |
| 398 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT), |
| 399 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT), |
| 400 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE), |
| 401 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE), |
| 402 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA), |
| 403 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA), |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 404 | }; |
| 405 | |
Zhao Yakui | 461ed3c | 2010-03-30 15:11:33 +0800 | [diff] [blame] | 406 | #define IS_SDVOB(reg) (reg == SDVOB || reg == PCH_SDVOB) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 407 | #define SDVO_NAME(svdo) (IS_SDVOB((svdo)->sdvo_reg) ? "SDVOB" : "SDVOC") |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 408 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 409 | static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd, |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 410 | const void *args, int args_len) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 411 | { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 412 | int i; |
| 413 | |
Zhao Yakui | 8a4c47f | 2009-07-20 13:48:04 +0800 | [diff] [blame] | 414 | DRM_DEBUG_KMS("%s: W: %02X ", |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 415 | SDVO_NAME(intel_sdvo), cmd); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 416 | for (i = 0; i < args_len; i++) |
yakui_zhao | 342dc38 | 2009-06-02 14:12:00 +0800 | [diff] [blame] | 417 | DRM_LOG_KMS("%02X ", ((u8 *)args)[i]); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 418 | for (; i < 8; i++) |
yakui_zhao | 342dc38 | 2009-06-02 14:12:00 +0800 | [diff] [blame] | 419 | DRM_LOG_KMS(" "); |
Kulikov Vasiliy | 04ad327 | 2010-06-28 15:54:56 +0400 | [diff] [blame] | 420 | for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 421 | if (cmd == sdvo_cmd_names[i].cmd) { |
yakui_zhao | 342dc38 | 2009-06-02 14:12:00 +0800 | [diff] [blame] | 422 | DRM_LOG_KMS("(%s)", sdvo_cmd_names[i].name); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 423 | break; |
| 424 | } |
| 425 | } |
Kulikov Vasiliy | 04ad327 | 2010-06-28 15:54:56 +0400 | [diff] [blame] | 426 | if (i == ARRAY_SIZE(sdvo_cmd_names)) |
yakui_zhao | 342dc38 | 2009-06-02 14:12:00 +0800 | [diff] [blame] | 427 | DRM_LOG_KMS("(%02X)", cmd); |
| 428 | DRM_LOG_KMS("\n"); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 429 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 430 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 431 | static const char *cmd_status_names[] = { |
| 432 | "Power on", |
| 433 | "Success", |
| 434 | "Not supported", |
| 435 | "Invalid arg", |
| 436 | "Pending", |
| 437 | "Target not specified", |
| 438 | "Scaling not supported" |
| 439 | }; |
| 440 | |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 441 | static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd, |
| 442 | const void *args, int args_len) |
| 443 | { |
| 444 | u8 buf[args_len*2 + 2], status; |
| 445 | struct i2c_msg msgs[args_len + 3]; |
| 446 | int i, ret; |
| 447 | |
| 448 | intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len); |
| 449 | |
| 450 | for (i = 0; i < args_len; i++) { |
| 451 | msgs[i].addr = intel_sdvo->slave_addr; |
| 452 | msgs[i].flags = 0; |
| 453 | msgs[i].len = 2; |
| 454 | msgs[i].buf = buf + 2 *i; |
| 455 | buf[2*i + 0] = SDVO_I2C_ARG_0 - i; |
| 456 | buf[2*i + 1] = ((u8*)args)[i]; |
| 457 | } |
| 458 | msgs[i].addr = intel_sdvo->slave_addr; |
| 459 | msgs[i].flags = 0; |
| 460 | msgs[i].len = 2; |
| 461 | msgs[i].buf = buf + 2*i; |
| 462 | buf[2*i + 0] = SDVO_I2C_OPCODE; |
| 463 | buf[2*i + 1] = cmd; |
| 464 | |
| 465 | /* the following two are to read the response */ |
| 466 | status = SDVO_I2C_CMD_STATUS; |
| 467 | msgs[i+1].addr = intel_sdvo->slave_addr; |
| 468 | msgs[i+1].flags = 0; |
| 469 | msgs[i+1].len = 1; |
| 470 | msgs[i+1].buf = &status; |
| 471 | |
| 472 | msgs[i+2].addr = intel_sdvo->slave_addr; |
| 473 | msgs[i+2].flags = I2C_M_RD; |
| 474 | msgs[i+2].len = 1; |
| 475 | msgs[i+2].buf = &status; |
| 476 | |
| 477 | ret = i2c_transfer(intel_sdvo->i2c, msgs, i+3); |
| 478 | if (ret < 0) { |
| 479 | DRM_DEBUG_KMS("I2c transfer returned %d\n", ret); |
| 480 | return false; |
| 481 | } |
| 482 | if (ret != i+3) { |
| 483 | /* failure in I2C transfer */ |
| 484 | DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3); |
| 485 | return false; |
| 486 | } |
| 487 | |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 488 | return true; |
| 489 | } |
| 490 | |
Chris Wilson | b5c616a | 2010-09-09 19:06:13 +0100 | [diff] [blame] | 491 | static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo, |
| 492 | void *response, int response_len) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 493 | { |
Chris Wilson | b5c616a | 2010-09-09 19:06:13 +0100 | [diff] [blame] | 494 | u8 retry = 5; |
| 495 | u8 status; |
Zhenyu Wang | 33b5296 | 2009-03-24 14:02:40 +0800 | [diff] [blame] | 496 | int i; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 497 | |
Chris Wilson | d121a5d | 2011-01-25 15:00:01 +0000 | [diff] [blame] | 498 | DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(intel_sdvo)); |
| 499 | |
Chris Wilson | b5c616a | 2010-09-09 19:06:13 +0100 | [diff] [blame] | 500 | /* |
| 501 | * The documentation states that all commands will be |
| 502 | * processed within 15µs, and that we need only poll |
| 503 | * the status byte a maximum of 3 times in order for the |
| 504 | * command to be complete. |
| 505 | * |
| 506 | * Check 5 times in case the hardware failed to read the docs. |
| 507 | */ |
Chris Wilson | d121a5d | 2011-01-25 15:00:01 +0000 | [diff] [blame] | 508 | if (!intel_sdvo_read_byte(intel_sdvo, |
| 509 | SDVO_I2C_CMD_STATUS, |
| 510 | &status)) |
| 511 | goto log_fail; |
| 512 | |
| 513 | while (status == SDVO_CMD_STATUS_PENDING && retry--) { |
| 514 | udelay(15); |
Chris Wilson | b5c616a | 2010-09-09 19:06:13 +0100 | [diff] [blame] | 515 | if (!intel_sdvo_read_byte(intel_sdvo, |
| 516 | SDVO_I2C_CMD_STATUS, |
| 517 | &status)) |
Chris Wilson | d121a5d | 2011-01-25 15:00:01 +0000 | [diff] [blame] | 518 | goto log_fail; |
| 519 | } |
Chris Wilson | b5c616a | 2010-09-09 19:06:13 +0100 | [diff] [blame] | 520 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 521 | if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP) |
yakui_zhao | 342dc38 | 2009-06-02 14:12:00 +0800 | [diff] [blame] | 522 | DRM_LOG_KMS("(%s)", cmd_status_names[status]); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 523 | else |
yakui_zhao | 342dc38 | 2009-06-02 14:12:00 +0800 | [diff] [blame] | 524 | DRM_LOG_KMS("(??? %d)", status); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 525 | |
Chris Wilson | b5c616a | 2010-09-09 19:06:13 +0100 | [diff] [blame] | 526 | if (status != SDVO_CMD_STATUS_SUCCESS) |
| 527 | goto log_fail; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 528 | |
Chris Wilson | b5c616a | 2010-09-09 19:06:13 +0100 | [diff] [blame] | 529 | /* Read the command response */ |
| 530 | for (i = 0; i < response_len; i++) { |
| 531 | if (!intel_sdvo_read_byte(intel_sdvo, |
| 532 | SDVO_I2C_RETURN_0 + i, |
| 533 | &((u8 *)response)[i])) |
| 534 | goto log_fail; |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 535 | DRM_LOG_KMS(" %02X", ((u8 *)response)[i]); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 536 | } |
Chris Wilson | b5c616a | 2010-09-09 19:06:13 +0100 | [diff] [blame] | 537 | DRM_LOG_KMS("\n"); |
Chris Wilson | b5c616a | 2010-09-09 19:06:13 +0100 | [diff] [blame] | 538 | return true; |
| 539 | |
| 540 | log_fail: |
Chris Wilson | d121a5d | 2011-01-25 15:00:01 +0000 | [diff] [blame] | 541 | DRM_LOG_KMS("... failed\n"); |
Chris Wilson | b5c616a | 2010-09-09 19:06:13 +0100 | [diff] [blame] | 542 | return false; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 543 | } |
| 544 | |
Hannes Eder | b358d0a | 2008-12-18 21:18:47 +0100 | [diff] [blame] | 545 | static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 546 | { |
| 547 | if (mode->clock >= 100000) |
| 548 | return 1; |
| 549 | else if (mode->clock >= 50000) |
| 550 | return 2; |
| 551 | else |
| 552 | return 4; |
| 553 | } |
| 554 | |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 555 | static bool intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo, |
| 556 | u8 ddc_bus) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 557 | { |
Chris Wilson | d121a5d | 2011-01-25 15:00:01 +0000 | [diff] [blame] | 558 | /* This must be the immediately preceding write before the i2c xfer */ |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 559 | return intel_sdvo_write_cmd(intel_sdvo, |
| 560 | SDVO_CMD_SET_CONTROL_BUS_SWITCH, |
| 561 | &ddc_bus, 1); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 562 | } |
| 563 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 564 | static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len) |
| 565 | { |
Chris Wilson | d121a5d | 2011-01-25 15:00:01 +0000 | [diff] [blame] | 566 | if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len)) |
| 567 | return false; |
| 568 | |
| 569 | return intel_sdvo_read_response(intel_sdvo, NULL, 0); |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 570 | } |
| 571 | |
| 572 | static bool |
| 573 | intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len) |
| 574 | { |
| 575 | if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0)) |
| 576 | return false; |
| 577 | |
| 578 | return intel_sdvo_read_response(intel_sdvo, value, len); |
| 579 | } |
| 580 | |
| 581 | static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 582 | { |
| 583 | struct intel_sdvo_set_target_input_args targets = {0}; |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 584 | return intel_sdvo_set_value(intel_sdvo, |
| 585 | SDVO_CMD_SET_TARGET_INPUT, |
| 586 | &targets, sizeof(targets)); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 587 | } |
| 588 | |
| 589 | /** |
| 590 | * Return whether each input is trained. |
| 591 | * |
| 592 | * This function is making an assumption about the layout of the response, |
| 593 | * which should be checked against the docs. |
| 594 | */ |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 595 | static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 596 | { |
| 597 | struct intel_sdvo_get_trained_inputs_response response; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 598 | |
Chris Wilson | 1a3665c | 2011-01-25 13:59:37 +0000 | [diff] [blame] | 599 | BUILD_BUG_ON(sizeof(response) != 1); |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 600 | if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS, |
| 601 | &response, sizeof(response))) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 602 | return false; |
| 603 | |
| 604 | *input_1 = response.input0_trained; |
| 605 | *input_2 = response.input1_trained; |
| 606 | return true; |
| 607 | } |
| 608 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 609 | static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 610 | u16 outputs) |
| 611 | { |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 612 | return intel_sdvo_set_value(intel_sdvo, |
| 613 | SDVO_CMD_SET_ACTIVE_OUTPUTS, |
| 614 | &outputs, sizeof(outputs)); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 615 | } |
| 616 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 617 | static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 618 | int mode) |
| 619 | { |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 620 | u8 state = SDVO_ENCODER_STATE_ON; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 621 | |
| 622 | switch (mode) { |
| 623 | case DRM_MODE_DPMS_ON: |
| 624 | state = SDVO_ENCODER_STATE_ON; |
| 625 | break; |
| 626 | case DRM_MODE_DPMS_STANDBY: |
| 627 | state = SDVO_ENCODER_STATE_STANDBY; |
| 628 | break; |
| 629 | case DRM_MODE_DPMS_SUSPEND: |
| 630 | state = SDVO_ENCODER_STATE_SUSPEND; |
| 631 | break; |
| 632 | case DRM_MODE_DPMS_OFF: |
| 633 | state = SDVO_ENCODER_STATE_OFF; |
| 634 | break; |
| 635 | } |
| 636 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 637 | return intel_sdvo_set_value(intel_sdvo, |
| 638 | SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state)); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 639 | } |
| 640 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 641 | static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 642 | int *clock_min, |
| 643 | int *clock_max) |
| 644 | { |
| 645 | struct intel_sdvo_pixel_clock_range clocks; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 646 | |
Chris Wilson | 1a3665c | 2011-01-25 13:59:37 +0000 | [diff] [blame] | 647 | BUILD_BUG_ON(sizeof(clocks) != 4); |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 648 | if (!intel_sdvo_get_value(intel_sdvo, |
| 649 | SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE, |
| 650 | &clocks, sizeof(clocks))) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 651 | return false; |
| 652 | |
| 653 | /* Convert the values from units of 10 kHz to kHz. */ |
| 654 | *clock_min = clocks.min * 10; |
| 655 | *clock_max = clocks.max * 10; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 656 | return true; |
| 657 | } |
| 658 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 659 | static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 660 | u16 outputs) |
| 661 | { |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 662 | return intel_sdvo_set_value(intel_sdvo, |
| 663 | SDVO_CMD_SET_TARGET_OUTPUT, |
| 664 | &outputs, sizeof(outputs)); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 665 | } |
| 666 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 667 | static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 668 | struct intel_sdvo_dtd *dtd) |
| 669 | { |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 670 | return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) && |
| 671 | intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2)); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 672 | } |
| 673 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 674 | static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 675 | struct intel_sdvo_dtd *dtd) |
| 676 | { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 677 | return intel_sdvo_set_timing(intel_sdvo, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 678 | SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd); |
| 679 | } |
| 680 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 681 | static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 682 | struct intel_sdvo_dtd *dtd) |
| 683 | { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 684 | return intel_sdvo_set_timing(intel_sdvo, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 685 | SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd); |
| 686 | } |
| 687 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 688 | static bool |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 689 | intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 690 | uint16_t clock, |
| 691 | uint16_t width, |
| 692 | uint16_t height) |
| 693 | { |
| 694 | struct intel_sdvo_preferred_input_timing_args args; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 695 | |
Zhenyu Wang | e642c6f | 2009-03-24 14:02:42 +0800 | [diff] [blame] | 696 | memset(&args, 0, sizeof(args)); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 697 | args.clock = clock; |
| 698 | args.width = width; |
| 699 | args.height = height; |
Zhenyu Wang | e642c6f | 2009-03-24 14:02:42 +0800 | [diff] [blame] | 700 | args.interlace = 0; |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 701 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 702 | if (intel_sdvo->is_lvds && |
| 703 | (intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width || |
| 704 | intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height)) |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 705 | args.scaled = 1; |
| 706 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 707 | return intel_sdvo_set_value(intel_sdvo, |
| 708 | SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING, |
| 709 | &args, sizeof(args)); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 710 | } |
| 711 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 712 | static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 713 | struct intel_sdvo_dtd *dtd) |
| 714 | { |
Chris Wilson | 1a3665c | 2011-01-25 13:59:37 +0000 | [diff] [blame] | 715 | BUILD_BUG_ON(sizeof(dtd->part1) != 8); |
| 716 | BUILD_BUG_ON(sizeof(dtd->part2) != 8); |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 717 | return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1, |
| 718 | &dtd->part1, sizeof(dtd->part1)) && |
| 719 | intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2, |
| 720 | &dtd->part2, sizeof(dtd->part2)); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 721 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 722 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 723 | static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 724 | { |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 725 | return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 726 | } |
| 727 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 728 | static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd, |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 729 | const struct drm_display_mode *mode) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 730 | { |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 731 | uint16_t width, height; |
| 732 | uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len; |
| 733 | uint16_t h_sync_offset, v_sync_offset; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 734 | |
| 735 | width = mode->crtc_hdisplay; |
| 736 | height = mode->crtc_vdisplay; |
| 737 | |
| 738 | /* do some mode translations */ |
| 739 | h_blank_len = mode->crtc_hblank_end - mode->crtc_hblank_start; |
| 740 | h_sync_len = mode->crtc_hsync_end - mode->crtc_hsync_start; |
| 741 | |
| 742 | v_blank_len = mode->crtc_vblank_end - mode->crtc_vblank_start; |
| 743 | v_sync_len = mode->crtc_vsync_end - mode->crtc_vsync_start; |
| 744 | |
| 745 | h_sync_offset = mode->crtc_hsync_start - mode->crtc_hblank_start; |
| 746 | v_sync_offset = mode->crtc_vsync_start - mode->crtc_vblank_start; |
| 747 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 748 | dtd->part1.clock = mode->clock / 10; |
| 749 | dtd->part1.h_active = width & 0xff; |
| 750 | dtd->part1.h_blank = h_blank_len & 0xff; |
| 751 | dtd->part1.h_high = (((width >> 8) & 0xf) << 4) | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 752 | ((h_blank_len >> 8) & 0xf); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 753 | dtd->part1.v_active = height & 0xff; |
| 754 | dtd->part1.v_blank = v_blank_len & 0xff; |
| 755 | dtd->part1.v_high = (((height >> 8) & 0xf) << 4) | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 756 | ((v_blank_len >> 8) & 0xf); |
| 757 | |
Zhenyu Wang | 171a9e9 | 2009-03-24 14:02:41 +0800 | [diff] [blame] | 758 | dtd->part2.h_sync_off = h_sync_offset & 0xff; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 759 | dtd->part2.h_sync_width = h_sync_len & 0xff; |
| 760 | dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 761 | (v_sync_len & 0xf); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 762 | dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 763 | ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) | |
| 764 | ((v_sync_len & 0x30) >> 4); |
| 765 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 766 | dtd->part2.dtd_flags = 0x18; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 767 | if (mode->flags & DRM_MODE_FLAG_PHSYNC) |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 768 | dtd->part2.dtd_flags |= 0x2; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 769 | if (mode->flags & DRM_MODE_FLAG_PVSYNC) |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 770 | dtd->part2.dtd_flags |= 0x4; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 771 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 772 | dtd->part2.sdvo_flags = 0; |
| 773 | dtd->part2.v_sync_off_high = v_sync_offset & 0xc0; |
| 774 | dtd->part2.reserved = 0; |
| 775 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 776 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 777 | static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode, |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 778 | const struct intel_sdvo_dtd *dtd) |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 779 | { |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 780 | mode->hdisplay = dtd->part1.h_active; |
| 781 | mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8; |
| 782 | mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off; |
Zhenyu Wang | 171a9e9 | 2009-03-24 14:02:41 +0800 | [diff] [blame] | 783 | mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 784 | mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width; |
| 785 | mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4; |
| 786 | mode->htotal = mode->hdisplay + dtd->part1.h_blank; |
| 787 | mode->htotal += (dtd->part1.h_high & 0xf) << 8; |
| 788 | |
| 789 | mode->vdisplay = dtd->part1.v_active; |
| 790 | mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8; |
| 791 | mode->vsync_start = mode->vdisplay; |
| 792 | mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf; |
Zhenyu Wang | 171a9e9 | 2009-03-24 14:02:41 +0800 | [diff] [blame] | 793 | mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 794 | mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0; |
| 795 | mode->vsync_end = mode->vsync_start + |
| 796 | (dtd->part2.v_sync_off_width & 0xf); |
| 797 | mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4; |
| 798 | mode->vtotal = mode->vdisplay + dtd->part1.v_blank; |
| 799 | mode->vtotal += (dtd->part1.v_high & 0xf) << 8; |
| 800 | |
| 801 | mode->clock = dtd->part1.clock * 10; |
| 802 | |
Zhenyu Wang | 171a9e9 | 2009-03-24 14:02:41 +0800 | [diff] [blame] | 803 | mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 804 | if (dtd->part2.dtd_flags & 0x2) |
| 805 | mode->flags |= DRM_MODE_FLAG_PHSYNC; |
| 806 | if (dtd->part2.dtd_flags & 0x4) |
| 807 | mode->flags |= DRM_MODE_FLAG_PVSYNC; |
| 808 | } |
| 809 | |
Chris Wilson | e27d853 | 2010-10-22 09:15:22 +0100 | [diff] [blame] | 810 | static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo) |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 811 | { |
Chris Wilson | e27d853 | 2010-10-22 09:15:22 +0100 | [diff] [blame] | 812 | struct intel_sdvo_encode encode; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 813 | |
Chris Wilson | 1a3665c | 2011-01-25 13:59:37 +0000 | [diff] [blame] | 814 | BUILD_BUG_ON(sizeof(encode) != 2); |
Chris Wilson | e27d853 | 2010-10-22 09:15:22 +0100 | [diff] [blame] | 815 | return intel_sdvo_get_value(intel_sdvo, |
| 816 | SDVO_CMD_GET_SUPP_ENCODE, |
| 817 | &encode, sizeof(encode)); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 818 | } |
| 819 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 820 | static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo, |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 821 | uint8_t mode) |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 822 | { |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 823 | return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 824 | } |
| 825 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 826 | static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 827 | uint8_t mode) |
| 828 | { |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 829 | return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 830 | } |
| 831 | |
| 832 | #if 0 |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 833 | static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo) |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 834 | { |
| 835 | int i, j; |
| 836 | uint8_t set_buf_index[2]; |
| 837 | uint8_t av_split; |
| 838 | uint8_t buf_size; |
| 839 | uint8_t buf[48]; |
| 840 | uint8_t *pos; |
| 841 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 842 | intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 843 | |
| 844 | for (i = 0; i <= av_split; i++) { |
| 845 | set_buf_index[0] = i; set_buf_index[1] = 0; |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 846 | intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 847 | set_buf_index, 2); |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 848 | intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0); |
| 849 | intel_sdvo_read_response(encoder, &buf_size, 1); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 850 | |
| 851 | pos = buf; |
| 852 | for (j = 0; j <= buf_size; j += 8) { |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 853 | intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 854 | NULL, 0); |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 855 | intel_sdvo_read_response(encoder, pos, 8); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 856 | pos += 8; |
| 857 | } |
| 858 | } |
| 859 | } |
| 860 | #endif |
| 861 | |
David Härdeman | 3c17fe4 | 2010-09-24 21:44:32 +0200 | [diff] [blame] | 862 | static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo) |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 863 | { |
| 864 | struct dip_infoframe avi_if = { |
| 865 | .type = DIP_TYPE_AVI, |
David Härdeman | 3c17fe4 | 2010-09-24 21:44:32 +0200 | [diff] [blame] | 866 | .ver = DIP_VERSION_AVI, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 867 | .len = DIP_LEN_AVI, |
| 868 | }; |
David Härdeman | 3c17fe4 | 2010-09-24 21:44:32 +0200 | [diff] [blame] | 869 | uint8_t tx_rate = SDVO_HBUF_TX_VSYNC; |
| 870 | uint8_t set_buf_index[2] = { 1, 0 }; |
| 871 | uint64_t *data = (uint64_t *)&avi_if; |
| 872 | unsigned i; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 873 | |
David Härdeman | 3c17fe4 | 2010-09-24 21:44:32 +0200 | [diff] [blame] | 874 | intel_dip_infoframe_csum(&avi_if); |
| 875 | |
Chris Wilson | d121a5d | 2011-01-25 15:00:01 +0000 | [diff] [blame] | 876 | if (!intel_sdvo_set_value(intel_sdvo, |
| 877 | SDVO_CMD_SET_HBUF_INDEX, |
David Härdeman | 3c17fe4 | 2010-09-24 21:44:32 +0200 | [diff] [blame] | 878 | set_buf_index, 2)) |
| 879 | return false; |
| 880 | |
| 881 | for (i = 0; i < sizeof(avi_if); i += 8) { |
Chris Wilson | d121a5d | 2011-01-25 15:00:01 +0000 | [diff] [blame] | 882 | if (!intel_sdvo_set_value(intel_sdvo, |
| 883 | SDVO_CMD_SET_HBUF_DATA, |
David Härdeman | 3c17fe4 | 2010-09-24 21:44:32 +0200 | [diff] [blame] | 884 | data, 8)) |
| 885 | return false; |
| 886 | data++; |
| 887 | } |
| 888 | |
Chris Wilson | d121a5d | 2011-01-25 15:00:01 +0000 | [diff] [blame] | 889 | return intel_sdvo_set_value(intel_sdvo, |
| 890 | SDVO_CMD_SET_HBUF_TXRATE, |
David Härdeman | 3c17fe4 | 2010-09-24 21:44:32 +0200 | [diff] [blame] | 891 | &tx_rate, 1); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 892 | } |
| 893 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 894 | static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo) |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 895 | { |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 896 | struct intel_sdvo_tv_format format; |
Chris Wilson | 4003975 | 2010-08-04 13:50:26 +0100 | [diff] [blame] | 897 | uint32_t format_map; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 898 | |
Chris Wilson | 4003975 | 2010-08-04 13:50:26 +0100 | [diff] [blame] | 899 | format_map = 1 << intel_sdvo->tv_format_index; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 900 | memset(&format, 0, sizeof(format)); |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 901 | memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map))); |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 902 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 903 | BUILD_BUG_ON(sizeof(format) != 6); |
| 904 | return intel_sdvo_set_value(intel_sdvo, |
| 905 | SDVO_CMD_SET_TV_FORMAT, |
| 906 | &format, sizeof(format)); |
| 907 | } |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 908 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 909 | static bool |
| 910 | intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo, |
| 911 | struct drm_display_mode *mode) |
| 912 | { |
| 913 | struct intel_sdvo_dtd output_dtd; |
| 914 | |
| 915 | if (!intel_sdvo_set_target_output(intel_sdvo, |
| 916 | intel_sdvo->attached_output)) |
| 917 | return false; |
| 918 | |
| 919 | intel_sdvo_get_dtd_from_mode(&output_dtd, mode); |
| 920 | if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd)) |
| 921 | return false; |
| 922 | |
| 923 | return true; |
| 924 | } |
| 925 | |
| 926 | static bool |
| 927 | intel_sdvo_set_input_timings_for_mode(struct intel_sdvo *intel_sdvo, |
| 928 | struct drm_display_mode *mode, |
| 929 | struct drm_display_mode *adjusted_mode) |
| 930 | { |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 931 | /* Reset the input timing to the screen. Assume always input 0. */ |
| 932 | if (!intel_sdvo_set_target_input(intel_sdvo)) |
| 933 | return false; |
| 934 | |
| 935 | if (!intel_sdvo_create_preferred_input_timing(intel_sdvo, |
| 936 | mode->clock / 10, |
| 937 | mode->hdisplay, |
| 938 | mode->vdisplay)) |
| 939 | return false; |
| 940 | |
| 941 | if (!intel_sdvo_get_preferred_input_timing(intel_sdvo, |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 942 | &intel_sdvo->input_dtd)) |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 943 | return false; |
| 944 | |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 945 | intel_sdvo_get_mode_from_dtd(adjusted_mode, &intel_sdvo->input_dtd); |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 946 | |
| 947 | drm_mode_set_crtcinfo(adjusted_mode, 0); |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 948 | return true; |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 949 | } |
| 950 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 951 | static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder, |
| 952 | struct drm_display_mode *mode, |
| 953 | struct drm_display_mode *adjusted_mode) |
| 954 | { |
Chris Wilson | 890f335 | 2010-09-14 16:46:59 +0100 | [diff] [blame] | 955 | struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder); |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 956 | int multiplier; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 957 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 958 | /* We need to construct preferred input timings based on our |
| 959 | * output timings. To do that, we have to set the output |
| 960 | * timings, even though this isn't really the right place in |
| 961 | * the sequence to do it. Oh well. |
| 962 | */ |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 963 | if (intel_sdvo->is_tv) { |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 964 | if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode)) |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 965 | return false; |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 966 | |
Pavel Roskin | c74696b | 2010-09-02 14:46:34 -0400 | [diff] [blame] | 967 | (void) intel_sdvo_set_input_timings_for_mode(intel_sdvo, |
| 968 | mode, |
| 969 | adjusted_mode); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 970 | } else if (intel_sdvo->is_lvds) { |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 971 | if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 972 | intel_sdvo->sdvo_lvds_fixed_mode)) |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 973 | return false; |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 974 | |
Pavel Roskin | c74696b | 2010-09-02 14:46:34 -0400 | [diff] [blame] | 975 | (void) intel_sdvo_set_input_timings_for_mode(intel_sdvo, |
| 976 | mode, |
| 977 | adjusted_mode); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 978 | } |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 979 | |
| 980 | /* Make the CRTC code factor in the SDVO pixel multiplier. The |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 981 | * SDVO device will factor out the multiplier during mode_set. |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 982 | */ |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 983 | multiplier = intel_sdvo_get_pixel_multiplier(adjusted_mode); |
| 984 | intel_mode_set_pixel_multiplier(adjusted_mode, multiplier); |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 985 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 986 | return true; |
| 987 | } |
| 988 | |
| 989 | static void intel_sdvo_mode_set(struct drm_encoder *encoder, |
| 990 | struct drm_display_mode *mode, |
| 991 | struct drm_display_mode *adjusted_mode) |
| 992 | { |
| 993 | struct drm_device *dev = encoder->dev; |
| 994 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 995 | struct drm_crtc *crtc = encoder->crtc; |
| 996 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Chris Wilson | 890f335 | 2010-09-14 16:46:59 +0100 | [diff] [blame] | 997 | struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder); |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 998 | u32 sdvox; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 999 | struct intel_sdvo_in_out_map in_out; |
| 1000 | struct intel_sdvo_dtd input_dtd; |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 1001 | int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode); |
| 1002 | int rate; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1003 | |
| 1004 | if (!mode) |
| 1005 | return; |
| 1006 | |
| 1007 | /* First, set the input mapping for the first input to our controlled |
| 1008 | * output. This is only correct if we're a single-input device, in |
| 1009 | * which case the first input is the output from the appropriate SDVO |
| 1010 | * channel on the motherboard. In a two-input device, the first input |
| 1011 | * will be SDVOB and the second SDVOC. |
| 1012 | */ |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1013 | in_out.in0 = intel_sdvo->attached_output; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1014 | in_out.in1 = 0; |
| 1015 | |
Pavel Roskin | c74696b | 2010-09-02 14:46:34 -0400 | [diff] [blame] | 1016 | intel_sdvo_set_value(intel_sdvo, |
| 1017 | SDVO_CMD_SET_IN_OUT_MAP, |
| 1018 | &in_out, sizeof(in_out)); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1019 | |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 1020 | /* Set the output timings to the screen */ |
| 1021 | if (!intel_sdvo_set_target_output(intel_sdvo, |
| 1022 | intel_sdvo->attached_output)) |
| 1023 | return; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1024 | |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1025 | /* We have tried to get input timing in mode_fixup, and filled into |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 1026 | * adjusted_mode. |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1027 | */ |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 1028 | if (intel_sdvo->is_tv || intel_sdvo->is_lvds) { |
| 1029 | input_dtd = intel_sdvo->input_dtd; |
| 1030 | } else { |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1031 | /* Set the output timing to the screen */ |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1032 | if (!intel_sdvo_set_target_output(intel_sdvo, |
| 1033 | intel_sdvo->attached_output)) |
| 1034 | return; |
| 1035 | |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 1036 | intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode); |
Pavel Roskin | c74696b | 2010-09-02 14:46:34 -0400 | [diff] [blame] | 1037 | (void) intel_sdvo_set_output_timing(intel_sdvo, &input_dtd); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1038 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1039 | |
| 1040 | /* Set the input timing to the screen. Assume always input 0. */ |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1041 | if (!intel_sdvo_set_target_input(intel_sdvo)) |
| 1042 | return; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1043 | |
Chris Wilson | 97aaf91 | 2011-01-04 20:10:52 +0000 | [diff] [blame] | 1044 | if (intel_sdvo->has_hdmi_monitor) { |
| 1045 | intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI); |
| 1046 | intel_sdvo_set_colorimetry(intel_sdvo, |
| 1047 | SDVO_COLORIMETRY_RGB256); |
| 1048 | intel_sdvo_set_avi_infoframe(intel_sdvo); |
| 1049 | } else |
| 1050 | intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_DVI); |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1051 | |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 1052 | if (intel_sdvo->is_tv && |
| 1053 | !intel_sdvo_set_tv_format(intel_sdvo)) |
| 1054 | return; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1055 | |
Pavel Roskin | c74696b | 2010-09-02 14:46:34 -0400 | [diff] [blame] | 1056 | (void) intel_sdvo_set_input_timing(intel_sdvo, &input_dtd); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1057 | |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 1058 | switch (pixel_multiplier) { |
| 1059 | default: |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1060 | case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break; |
| 1061 | case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break; |
| 1062 | case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1063 | } |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1064 | if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate)) |
| 1065 | return; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1066 | |
| 1067 | /* Set the SDVO control regs. */ |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 1068 | if (INTEL_INFO(dev)->gen >= 4) { |
Chris Wilson | 6714afb | 2010-12-17 04:10:51 +0000 | [diff] [blame] | 1069 | sdvox = 0; |
Chris Wilson | e953fd7 | 2011-02-21 22:23:52 +0000 | [diff] [blame] | 1070 | if (intel_sdvo->is_hdmi) |
| 1071 | sdvox |= intel_sdvo->color_range; |
Chris Wilson | 6714afb | 2010-12-17 04:10:51 +0000 | [diff] [blame] | 1072 | if (INTEL_INFO(dev)->gen < 5) |
| 1073 | sdvox |= SDVO_BORDER_ENABLE; |
Adam Jackson | 81a14b4 | 2010-07-16 14:46:32 -0400 | [diff] [blame] | 1074 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
| 1075 | sdvox |= SDVO_VSYNC_ACTIVE_HIGH; |
| 1076 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
| 1077 | sdvox |= SDVO_HSYNC_ACTIVE_HIGH; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1078 | } else { |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 1079 | sdvox = I915_READ(intel_sdvo->sdvo_reg); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1080 | switch (intel_sdvo->sdvo_reg) { |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1081 | case SDVOB: |
| 1082 | sdvox &= SDVOB_PRESERVE_MASK; |
| 1083 | break; |
| 1084 | case SDVOC: |
| 1085 | sdvox &= SDVOC_PRESERVE_MASK; |
| 1086 | break; |
| 1087 | } |
| 1088 | sdvox |= (9 << 19) | SDVO_BORDER_ENABLE; |
| 1089 | } |
Paulo Zanoni | 3573c41 | 2011-10-14 18:16:22 -0300 | [diff] [blame] | 1090 | |
| 1091 | if (INTEL_PCH_TYPE(dev) >= PCH_CPT) |
| 1092 | sdvox |= TRANSCODER_CPT(intel_crtc->pipe); |
| 1093 | else |
| 1094 | sdvox |= TRANSCODER(intel_crtc->pipe); |
| 1095 | |
Chris Wilson | da79de9 | 2010-11-22 11:12:46 +0000 | [diff] [blame] | 1096 | if (intel_sdvo->has_hdmi_audio) |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 1097 | sdvox |= SDVO_AUDIO_ENABLE; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1098 | |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 1099 | if (INTEL_INFO(dev)->gen >= 4) { |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1100 | /* done in crtc_mode_set as the dpll_md reg must be written early */ |
| 1101 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
| 1102 | /* done in crtc_mode_set as it lives inside the dpll register */ |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1103 | } else { |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 1104 | sdvox |= (pixel_multiplier - 1) << SDVO_PORT_MULTIPLY_SHIFT; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1105 | } |
| 1106 | |
Chris Wilson | 6714afb | 2010-12-17 04:10:51 +0000 | [diff] [blame] | 1107 | if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL && |
| 1108 | INTEL_INFO(dev)->gen < 5) |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 1109 | sdvox |= SDVO_STALL_SELECT; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1110 | intel_sdvo_write_sdvox(intel_sdvo, sdvox); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1111 | } |
| 1112 | |
| 1113 | static void intel_sdvo_dpms(struct drm_encoder *encoder, int mode) |
| 1114 | { |
| 1115 | struct drm_device *dev = encoder->dev; |
| 1116 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 890f335 | 2010-09-14 16:46:59 +0100 | [diff] [blame] | 1117 | struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder); |
Jesse Barnes | 9d0498a | 2010-08-18 13:20:54 -0700 | [diff] [blame] | 1118 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1119 | u32 temp; |
| 1120 | |
| 1121 | if (mode != DRM_MODE_DPMS_ON) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1122 | intel_sdvo_set_active_outputs(intel_sdvo, 0); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1123 | if (0) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1124 | intel_sdvo_set_encoder_power_state(intel_sdvo, mode); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1125 | |
| 1126 | if (mode == DRM_MODE_DPMS_OFF) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1127 | temp = I915_READ(intel_sdvo->sdvo_reg); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1128 | if ((temp & SDVO_ENABLE) != 0) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1129 | intel_sdvo_write_sdvox(intel_sdvo, temp & ~SDVO_ENABLE); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1130 | } |
| 1131 | } |
| 1132 | } else { |
| 1133 | bool input1, input2; |
| 1134 | int i; |
| 1135 | u8 status; |
| 1136 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1137 | temp = I915_READ(intel_sdvo->sdvo_reg); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1138 | if ((temp & SDVO_ENABLE) == 0) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1139 | intel_sdvo_write_sdvox(intel_sdvo, temp | SDVO_ENABLE); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1140 | for (i = 0; i < 2; i++) |
Jesse Barnes | 9d0498a | 2010-08-18 13:20:54 -0700 | [diff] [blame] | 1141 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1142 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1143 | status = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1144 | /* Warn if the device reported failure to sync. |
| 1145 | * A lot of SDVO devices fail to notify of sync, but it's |
| 1146 | * a given it the status is a success, we succeeded. |
| 1147 | */ |
| 1148 | if (status == SDVO_CMD_STATUS_SUCCESS && !input1) { |
Zhao Yakui | 8a4c47f | 2009-07-20 13:48:04 +0800 | [diff] [blame] | 1149 | DRM_DEBUG_KMS("First %s output reported failure to " |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1150 | "sync\n", SDVO_NAME(intel_sdvo)); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1151 | } |
| 1152 | |
| 1153 | if (0) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1154 | intel_sdvo_set_encoder_power_state(intel_sdvo, mode); |
| 1155 | intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1156 | } |
| 1157 | return; |
| 1158 | } |
| 1159 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1160 | static int intel_sdvo_mode_valid(struct drm_connector *connector, |
| 1161 | struct drm_display_mode *mode) |
| 1162 | { |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 1163 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1164 | |
| 1165 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) |
| 1166 | return MODE_NO_DBLESCAN; |
| 1167 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1168 | if (intel_sdvo->pixel_clock_min > mode->clock) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1169 | return MODE_CLOCK_LOW; |
| 1170 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1171 | if (intel_sdvo->pixel_clock_max < mode->clock) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1172 | return MODE_CLOCK_HIGH; |
| 1173 | |
Chris Wilson | 8545423 | 2010-08-08 14:28:23 +0100 | [diff] [blame] | 1174 | if (intel_sdvo->is_lvds) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1175 | if (mode->hdisplay > intel_sdvo->sdvo_lvds_fixed_mode->hdisplay) |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 1176 | return MODE_PANEL; |
| 1177 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1178 | if (mode->vdisplay > intel_sdvo->sdvo_lvds_fixed_mode->vdisplay) |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 1179 | return MODE_PANEL; |
| 1180 | } |
| 1181 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1182 | return MODE_OK; |
| 1183 | } |
| 1184 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1185 | static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1186 | { |
Chris Wilson | 1a3665c | 2011-01-25 13:59:37 +0000 | [diff] [blame] | 1187 | BUILD_BUG_ON(sizeof(*caps) != 8); |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 1188 | if (!intel_sdvo_get_value(intel_sdvo, |
| 1189 | SDVO_CMD_GET_DEVICE_CAPS, |
| 1190 | caps, sizeof(*caps))) |
| 1191 | return false; |
| 1192 | |
| 1193 | DRM_DEBUG_KMS("SDVO capabilities:\n" |
| 1194 | " vendor_id: %d\n" |
| 1195 | " device_id: %d\n" |
| 1196 | " device_rev_id: %d\n" |
| 1197 | " sdvo_version_major: %d\n" |
| 1198 | " sdvo_version_minor: %d\n" |
| 1199 | " sdvo_inputs_mask: %d\n" |
| 1200 | " smooth_scaling: %d\n" |
| 1201 | " sharp_scaling: %d\n" |
| 1202 | " up_scaling: %d\n" |
| 1203 | " down_scaling: %d\n" |
| 1204 | " stall_support: %d\n" |
| 1205 | " output_flags: %d\n", |
| 1206 | caps->vendor_id, |
| 1207 | caps->device_id, |
| 1208 | caps->device_rev_id, |
| 1209 | caps->sdvo_version_major, |
| 1210 | caps->sdvo_version_minor, |
| 1211 | caps->sdvo_inputs_mask, |
| 1212 | caps->smooth_scaling, |
| 1213 | caps->sharp_scaling, |
| 1214 | caps->up_scaling, |
| 1215 | caps->down_scaling, |
| 1216 | caps->stall_support, |
| 1217 | caps->output_flags); |
| 1218 | |
| 1219 | return true; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1220 | } |
| 1221 | |
Simon Farnsworth | cc68c81 | 2011-09-21 17:13:30 +0100 | [diff] [blame] | 1222 | static int intel_sdvo_supports_hotplug(struct intel_sdvo *intel_sdvo) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1223 | { |
| 1224 | u8 response[2]; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1225 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1226 | return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT, |
| 1227 | &response, 2) && response[0]; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1228 | } |
| 1229 | |
Simon Farnsworth | cc68c81 | 2011-09-21 17:13:30 +0100 | [diff] [blame] | 1230 | static void intel_sdvo_enable_hotplug(struct intel_encoder *encoder) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1231 | { |
Simon Farnsworth | cc68c81 | 2011-09-21 17:13:30 +0100 | [diff] [blame] | 1232 | struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1233 | |
Simon Farnsworth | cc68c81 | 2011-09-21 17:13:30 +0100 | [diff] [blame] | 1234 | intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &intel_sdvo->hotplug_active, 2); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1235 | } |
| 1236 | |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 1237 | static bool |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1238 | intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo) |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 1239 | { |
Chris Wilson | bc65212 | 2011-01-25 13:28:29 +0000 | [diff] [blame] | 1240 | /* Is there more than one type of output? */ |
Adam Jackson | 2294488 | 2011-06-16 16:36:24 -0400 | [diff] [blame] | 1241 | return hweight16(intel_sdvo->caps.output_flags) > 1; |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 1242 | } |
| 1243 | |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 1244 | static struct edid * |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 1245 | intel_sdvo_get_edid(struct drm_connector *connector) |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 1246 | { |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 1247 | struct intel_sdvo *sdvo = intel_attached_sdvo(connector); |
| 1248 | return drm_get_edid(connector, &sdvo->ddc); |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 1249 | } |
| 1250 | |
Chris Wilson | ff482d8 | 2010-09-15 10:40:38 +0100 | [diff] [blame] | 1251 | /* Mac mini hack -- use the same DDC as the analog connector */ |
| 1252 | static struct edid * |
| 1253 | intel_sdvo_get_analog_edid(struct drm_connector *connector) |
| 1254 | { |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 1255 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
Chris Wilson | ff482d8 | 2010-09-15 10:40:38 +0100 | [diff] [blame] | 1256 | |
Chris Wilson | 0c1dab8 | 2010-11-23 22:37:01 +0000 | [diff] [blame] | 1257 | return drm_get_edid(connector, |
| 1258 | &dev_priv->gmbus[dev_priv->crt_ddc_pin].adapter); |
Chris Wilson | ff482d8 | 2010-09-15 10:40:38 +0100 | [diff] [blame] | 1259 | } |
| 1260 | |
ling.ma@intel.com | 2b8d33f7 | 2009-07-29 11:31:18 +0800 | [diff] [blame] | 1261 | enum drm_connector_status |
Adam Jackson | 8bf3848 | 2011-06-16 16:36:25 -0400 | [diff] [blame] | 1262 | intel_sdvo_tmds_sink_detect(struct drm_connector *connector) |
Ma Ling | 9dff6af | 2009-04-02 13:13:26 +0800 | [diff] [blame] | 1263 | { |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 1264 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); |
Chris Wilson | 9d1a903 | 2010-09-14 17:58:19 +0100 | [diff] [blame] | 1265 | enum drm_connector_status status; |
| 1266 | struct edid *edid; |
Ma Ling | 9dff6af | 2009-04-02 13:13:26 +0800 | [diff] [blame] | 1267 | |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 1268 | edid = intel_sdvo_get_edid(connector); |
Keith Packard | 57cdaf9 | 2009-09-04 13:07:54 +0800 | [diff] [blame] | 1269 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1270 | if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) { |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 1271 | u8 ddc, saved_ddc = intel_sdvo->ddc_bus; |
Chris Wilson | 9d1a903 | 2010-09-14 17:58:19 +0100 | [diff] [blame] | 1272 | |
Zhao Yakui | 7c3f0a2 | 2010-01-08 10:58:20 +0800 | [diff] [blame] | 1273 | /* |
| 1274 | * Don't use the 1 as the argument of DDC bus switch to get |
| 1275 | * the EDID. It is used for SDVO SPD ROM. |
| 1276 | */ |
Chris Wilson | 9d1a903 | 2010-09-14 17:58:19 +0100 | [diff] [blame] | 1277 | for (ddc = intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) { |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 1278 | intel_sdvo->ddc_bus = ddc; |
| 1279 | edid = intel_sdvo_get_edid(connector); |
| 1280 | if (edid) |
Zhao Yakui | 7c3f0a2 | 2010-01-08 10:58:20 +0800 | [diff] [blame] | 1281 | break; |
Zhao Yakui | 7c3f0a2 | 2010-01-08 10:58:20 +0800 | [diff] [blame] | 1282 | } |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 1283 | /* |
| 1284 | * If we found the EDID on the other bus, |
| 1285 | * assume that is the correct DDC bus. |
| 1286 | */ |
| 1287 | if (edid == NULL) |
| 1288 | intel_sdvo->ddc_bus = saved_ddc; |
Zhao Yakui | 7c3f0a2 | 2010-01-08 10:58:20 +0800 | [diff] [blame] | 1289 | } |
Chris Wilson | 9d1a903 | 2010-09-14 17:58:19 +0100 | [diff] [blame] | 1290 | |
| 1291 | /* |
| 1292 | * When there is no edid and no monitor is connected with VGA |
| 1293 | * port, try to use the CRT ddc to read the EDID for DVI-connector. |
Keith Packard | 57cdaf9 | 2009-09-04 13:07:54 +0800 | [diff] [blame] | 1294 | */ |
Chris Wilson | ff482d8 | 2010-09-15 10:40:38 +0100 | [diff] [blame] | 1295 | if (edid == NULL) |
| 1296 | edid = intel_sdvo_get_analog_edid(connector); |
Adam Jackson | 149c36a | 2010-04-29 14:05:18 -0400 | [diff] [blame] | 1297 | |
Chris Wilson | 2f551c8 | 2010-09-15 10:42:50 +0100 | [diff] [blame] | 1298 | status = connector_status_unknown; |
Ma Ling | 9dff6af | 2009-04-02 13:13:26 +0800 | [diff] [blame] | 1299 | if (edid != NULL) { |
Adam Jackson | 149c36a | 2010-04-29 14:05:18 -0400 | [diff] [blame] | 1300 | /* DDC bus is shared, match EDID to connector type */ |
Chris Wilson | 9d1a903 | 2010-09-14 17:58:19 +0100 | [diff] [blame] | 1301 | if (edid->input & DRM_EDID_INPUT_DIGITAL) { |
| 1302 | status = connector_status_connected; |
Chris Wilson | da79de9 | 2010-11-22 11:12:46 +0000 | [diff] [blame] | 1303 | if (intel_sdvo->is_hdmi) { |
| 1304 | intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid); |
| 1305 | intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid); |
| 1306 | } |
Chris Wilson | 13946743 | 2011-02-09 20:01:16 +0000 | [diff] [blame] | 1307 | } else |
| 1308 | status = connector_status_disconnected; |
Zhenyu Wang | d2a82a6 | 2010-03-29 21:22:55 +0800 | [diff] [blame] | 1309 | connector->display_info.raw_edid = NULL; |
Chris Wilson | 9d1a903 | 2010-09-14 17:58:19 +0100 | [diff] [blame] | 1310 | kfree(edid); |
| 1311 | } |
Chris Wilson | 7f36e7e | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 1312 | |
| 1313 | if (status == connector_status_connected) { |
| 1314 | struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); |
| 1315 | if (intel_sdvo_connector->force_audio) |
Chris Wilson | da79de9 | 2010-11-22 11:12:46 +0000 | [diff] [blame] | 1316 | intel_sdvo->has_hdmi_audio = intel_sdvo_connector->force_audio > 0; |
Chris Wilson | 7f36e7e | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 1317 | } |
| 1318 | |
ling.ma@intel.com | 2b8d33f7 | 2009-07-29 11:31:18 +0800 | [diff] [blame] | 1319 | return status; |
Ma Ling | 9dff6af | 2009-04-02 13:13:26 +0800 | [diff] [blame] | 1320 | } |
| 1321 | |
Chris Wilson | 5222008 | 2011-06-20 14:45:50 +0100 | [diff] [blame^] | 1322 | static bool |
| 1323 | intel_sdvo_connector_matches_edid(struct intel_sdvo_connector *sdvo, |
| 1324 | struct edid *edid) |
| 1325 | { |
| 1326 | bool monitor_is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL); |
| 1327 | bool connector_is_digital = !!IS_DIGITAL(sdvo); |
| 1328 | |
| 1329 | DRM_DEBUG_KMS("connector_is_digital? %d, monitor_is_digital? %d\n", |
| 1330 | connector_is_digital, monitor_is_digital); |
| 1331 | return connector_is_digital == monitor_is_digital; |
| 1332 | } |
| 1333 | |
Chris Wilson | 7b334fc | 2010-09-09 23:51:02 +0100 | [diff] [blame] | 1334 | static enum drm_connector_status |
Chris Wilson | 930a9e2 | 2010-09-14 11:07:23 +0100 | [diff] [blame] | 1335 | intel_sdvo_detect(struct drm_connector *connector, bool force) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1336 | { |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 1337 | uint16_t response; |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 1338 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 1339 | struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1340 | enum drm_connector_status ret; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1341 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1342 | if (!intel_sdvo_write_cmd(intel_sdvo, |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 1343 | SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0)) |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1344 | return connector_status_unknown; |
Chris Wilson | ba84cd1 | 2010-11-24 17:37:17 +0000 | [diff] [blame] | 1345 | |
| 1346 | /* add 30ms delay when the output type might be TV */ |
| 1347 | if (intel_sdvo->caps.output_flags & |
| 1348 | (SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_CVBS0)) |
Zhao Yakui | d09c23d | 2009-11-06 15:39:56 +0800 | [diff] [blame] | 1349 | mdelay(30); |
Chris Wilson | ba84cd1 | 2010-11-24 17:37:17 +0000 | [diff] [blame] | 1350 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1351 | if (!intel_sdvo_read_response(intel_sdvo, &response, 2)) |
| 1352 | return connector_status_unknown; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1353 | |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 1354 | DRM_DEBUG_KMS("SDVO response %d %d [%x]\n", |
| 1355 | response & 0xff, response >> 8, |
| 1356 | intel_sdvo_connector->output_flag); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1357 | |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 1358 | if (response == 0) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1359 | return connector_status_disconnected; |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 1360 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1361 | intel_sdvo->attached_output = response; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1362 | |
Chris Wilson | 97aaf91 | 2011-01-04 20:10:52 +0000 | [diff] [blame] | 1363 | intel_sdvo->has_hdmi_monitor = false; |
| 1364 | intel_sdvo->has_hdmi_audio = false; |
| 1365 | |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 1366 | if ((intel_sdvo_connector->output_flag & response) == 0) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1367 | ret = connector_status_disconnected; |
Chris Wilson | 13946743 | 2011-02-09 20:01:16 +0000 | [diff] [blame] | 1368 | else if (IS_TMDS(intel_sdvo_connector)) |
Adam Jackson | 8bf3848 | 2011-06-16 16:36:25 -0400 | [diff] [blame] | 1369 | ret = intel_sdvo_tmds_sink_detect(connector); |
Chris Wilson | 13946743 | 2011-02-09 20:01:16 +0000 | [diff] [blame] | 1370 | else { |
| 1371 | struct edid *edid; |
| 1372 | |
| 1373 | /* if we have an edid check it matches the connection */ |
| 1374 | edid = intel_sdvo_get_edid(connector); |
| 1375 | if (edid == NULL) |
| 1376 | edid = intel_sdvo_get_analog_edid(connector); |
| 1377 | if (edid != NULL) { |
Chris Wilson | 5222008 | 2011-06-20 14:45:50 +0100 | [diff] [blame^] | 1378 | if (intel_sdvo_connector_matches_edid(intel_sdvo_connector, |
| 1379 | edid)) |
Chris Wilson | 13946743 | 2011-02-09 20:01:16 +0000 | [diff] [blame] | 1380 | ret = connector_status_connected; |
Chris Wilson | 5222008 | 2011-06-20 14:45:50 +0100 | [diff] [blame^] | 1381 | else |
| 1382 | ret = connector_status_disconnected; |
| 1383 | |
Chris Wilson | 13946743 | 2011-02-09 20:01:16 +0000 | [diff] [blame] | 1384 | connector->display_info.raw_edid = NULL; |
| 1385 | kfree(edid); |
| 1386 | } else |
| 1387 | ret = connector_status_connected; |
| 1388 | } |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1389 | |
| 1390 | /* May update encoder flag for like clock for SDVO TV, etc.*/ |
| 1391 | if (ret == connector_status_connected) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1392 | intel_sdvo->is_tv = false; |
| 1393 | intel_sdvo->is_lvds = false; |
| 1394 | intel_sdvo->base.needs_tv_clock = false; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1395 | |
| 1396 | if (response & SDVO_TV_MASK) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1397 | intel_sdvo->is_tv = true; |
| 1398 | intel_sdvo->base.needs_tv_clock = true; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1399 | } |
| 1400 | if (response & SDVO_LVDS_MASK) |
Chris Wilson | 8545423 | 2010-08-08 14:28:23 +0100 | [diff] [blame] | 1401 | intel_sdvo->is_lvds = intel_sdvo->sdvo_lvds_fixed_mode != NULL; |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 1402 | } |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1403 | |
| 1404 | return ret; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1405 | } |
| 1406 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1407 | static void intel_sdvo_get_ddc_modes(struct drm_connector *connector) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1408 | { |
Chris Wilson | ff482d8 | 2010-09-15 10:40:38 +0100 | [diff] [blame] | 1409 | struct edid *edid; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1410 | |
| 1411 | /* set the bus switch and get the modes */ |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 1412 | edid = intel_sdvo_get_edid(connector); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1413 | |
Keith Packard | 57cdaf9 | 2009-09-04 13:07:54 +0800 | [diff] [blame] | 1414 | /* |
| 1415 | * Mac mini hack. On this device, the DVI-I connector shares one DDC |
| 1416 | * link between analog and digital outputs. So, if the regular SDVO |
| 1417 | * DDC fails, check to see if the analog output is disconnected, in |
| 1418 | * which case we'll look there for the digital DDC data. |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1419 | */ |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 1420 | if (edid == NULL) |
| 1421 | edid = intel_sdvo_get_analog_edid(connector); |
| 1422 | |
Chris Wilson | ff482d8 | 2010-09-15 10:40:38 +0100 | [diff] [blame] | 1423 | if (edid != NULL) { |
Chris Wilson | 5222008 | 2011-06-20 14:45:50 +0100 | [diff] [blame^] | 1424 | if (intel_sdvo_connector_matches_edid(to_intel_sdvo_connector(connector), |
| 1425 | edid)) { |
Chris Wilson | 0c1dab8 | 2010-11-23 22:37:01 +0000 | [diff] [blame] | 1426 | drm_mode_connector_update_edid_property(connector, edid); |
| 1427 | drm_add_edid_modes(connector, edid); |
| 1428 | } |
Chris Wilson | 13946743 | 2011-02-09 20:01:16 +0000 | [diff] [blame] | 1429 | |
Chris Wilson | ff482d8 | 2010-09-15 10:40:38 +0100 | [diff] [blame] | 1430 | connector->display_info.raw_edid = NULL; |
| 1431 | kfree(edid); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1432 | } |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1433 | } |
| 1434 | |
| 1435 | /* |
| 1436 | * Set of SDVO TV modes. |
| 1437 | * Note! This is in reply order (see loop in get_tv_modes). |
| 1438 | * XXX: all 60Hz refresh? |
| 1439 | */ |
Chris Wilson | b1f559e | 2011-01-26 09:49:47 +0000 | [diff] [blame] | 1440 | static const struct drm_display_mode sdvo_tv_modes[] = { |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1441 | { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384, |
| 1442 | 416, 0, 200, 201, 232, 233, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1443 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1444 | { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384, |
| 1445 | 416, 0, 240, 241, 272, 273, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1446 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1447 | { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464, |
| 1448 | 496, 0, 300, 301, 332, 333, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1449 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1450 | { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704, |
| 1451 | 736, 0, 350, 351, 382, 383, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1452 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1453 | { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704, |
| 1454 | 736, 0, 400, 401, 432, 433, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1455 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1456 | { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704, |
| 1457 | 736, 0, 480, 481, 512, 513, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1458 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1459 | { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768, |
| 1460 | 800, 0, 480, 481, 512, 513, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1461 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1462 | { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768, |
| 1463 | 800, 0, 576, 577, 608, 609, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1464 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1465 | { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784, |
| 1466 | 816, 0, 350, 351, 382, 383, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1467 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1468 | { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784, |
| 1469 | 816, 0, 400, 401, 432, 433, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1470 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1471 | { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784, |
| 1472 | 816, 0, 480, 481, 512, 513, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1473 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1474 | { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784, |
| 1475 | 816, 0, 540, 541, 572, 573, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1476 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1477 | { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784, |
| 1478 | 816, 0, 576, 577, 608, 609, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1479 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1480 | { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832, |
| 1481 | 864, 0, 576, 577, 608, 609, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1482 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1483 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864, |
| 1484 | 896, 0, 600, 601, 632, 633, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1485 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1486 | { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896, |
| 1487 | 928, 0, 624, 625, 656, 657, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1488 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1489 | { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984, |
| 1490 | 1016, 0, 766, 767, 798, 799, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1491 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1492 | { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088, |
| 1493 | 1120, 0, 768, 769, 800, 801, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1494 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1495 | { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344, |
| 1496 | 1376, 0, 1024, 1025, 1056, 1057, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1497 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
| 1498 | }; |
| 1499 | |
| 1500 | static void intel_sdvo_get_tv_modes(struct drm_connector *connector) |
| 1501 | { |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 1502 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1503 | struct intel_sdvo_sdtv_resolution_request tv_res; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1504 | uint32_t reply = 0, format_map = 0; |
| 1505 | int i; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1506 | |
| 1507 | /* Read the list of supported input resolutions for the selected TV |
| 1508 | * format. |
| 1509 | */ |
Chris Wilson | 4003975 | 2010-08-04 13:50:26 +0100 | [diff] [blame] | 1510 | format_map = 1 << intel_sdvo->tv_format_index; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1511 | memcpy(&tv_res, &format_map, |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1512 | min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request))); |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1513 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1514 | if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output)) |
| 1515 | return; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1516 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1517 | BUILD_BUG_ON(sizeof(tv_res) != 3); |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 1518 | if (!intel_sdvo_write_cmd(intel_sdvo, |
| 1519 | SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT, |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1520 | &tv_res, sizeof(tv_res))) |
| 1521 | return; |
| 1522 | if (!intel_sdvo_read_response(intel_sdvo, &reply, 3)) |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1523 | return; |
| 1524 | |
| 1525 | for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++) |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1526 | if (reply & (1 << i)) { |
| 1527 | struct drm_display_mode *nmode; |
| 1528 | nmode = drm_mode_duplicate(connector->dev, |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1529 | &sdvo_tv_modes[i]); |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1530 | if (nmode) |
| 1531 | drm_mode_probed_add(connector, nmode); |
| 1532 | } |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1533 | } |
| 1534 | |
Ma Ling | 7086c87 | 2009-05-13 11:20:06 +0800 | [diff] [blame] | 1535 | static void intel_sdvo_get_lvds_modes(struct drm_connector *connector) |
| 1536 | { |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 1537 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); |
Ma Ling | 7086c87 | 2009-05-13 11:20:06 +0800 | [diff] [blame] | 1538 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 1539 | struct drm_display_mode *newmode; |
Ma Ling | 7086c87 | 2009-05-13 11:20:06 +0800 | [diff] [blame] | 1540 | |
| 1541 | /* |
| 1542 | * Attempt to get the mode list from DDC. |
| 1543 | * Assume that the preferred modes are |
| 1544 | * arranged in priority order. |
| 1545 | */ |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 1546 | intel_ddc_get_modes(connector, intel_sdvo->i2c); |
Ma Ling | 7086c87 | 2009-05-13 11:20:06 +0800 | [diff] [blame] | 1547 | if (list_empty(&connector->probed_modes) == false) |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 1548 | goto end; |
Ma Ling | 7086c87 | 2009-05-13 11:20:06 +0800 | [diff] [blame] | 1549 | |
| 1550 | /* Fetch modes from VBT */ |
| 1551 | if (dev_priv->sdvo_lvds_vbt_mode != NULL) { |
Ma Ling | 7086c87 | 2009-05-13 11:20:06 +0800 | [diff] [blame] | 1552 | newmode = drm_mode_duplicate(connector->dev, |
| 1553 | dev_priv->sdvo_lvds_vbt_mode); |
| 1554 | if (newmode != NULL) { |
| 1555 | /* Guarantee the mode is preferred */ |
| 1556 | newmode->type = (DRM_MODE_TYPE_PREFERRED | |
| 1557 | DRM_MODE_TYPE_DRIVER); |
| 1558 | drm_mode_probed_add(connector, newmode); |
| 1559 | } |
| 1560 | } |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 1561 | |
| 1562 | end: |
| 1563 | list_for_each_entry(newmode, &connector->probed_modes, head) { |
| 1564 | if (newmode->type & DRM_MODE_TYPE_PREFERRED) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1565 | intel_sdvo->sdvo_lvds_fixed_mode = |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 1566 | drm_mode_duplicate(connector->dev, newmode); |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 1567 | |
| 1568 | drm_mode_set_crtcinfo(intel_sdvo->sdvo_lvds_fixed_mode, |
| 1569 | 0); |
| 1570 | |
Chris Wilson | 8545423 | 2010-08-08 14:28:23 +0100 | [diff] [blame] | 1571 | intel_sdvo->is_lvds = true; |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 1572 | break; |
| 1573 | } |
| 1574 | } |
| 1575 | |
Ma Ling | 7086c87 | 2009-05-13 11:20:06 +0800 | [diff] [blame] | 1576 | } |
| 1577 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1578 | static int intel_sdvo_get_modes(struct drm_connector *connector) |
| 1579 | { |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 1580 | struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1581 | |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 1582 | if (IS_TV(intel_sdvo_connector)) |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1583 | intel_sdvo_get_tv_modes(connector); |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 1584 | else if (IS_LVDS(intel_sdvo_connector)) |
Ma Ling | 7086c87 | 2009-05-13 11:20:06 +0800 | [diff] [blame] | 1585 | intel_sdvo_get_lvds_modes(connector); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1586 | else |
| 1587 | intel_sdvo_get_ddc_modes(connector); |
| 1588 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1589 | return !list_empty(&connector->probed_modes); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1590 | } |
| 1591 | |
Chris Wilson | fcc8d67 | 2010-08-04 13:50:27 +0100 | [diff] [blame] | 1592 | static void |
| 1593 | intel_sdvo_destroy_enhance_property(struct drm_connector *connector) |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1594 | { |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 1595 | struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1596 | struct drm_device *dev = connector->dev; |
| 1597 | |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 1598 | if (intel_sdvo_connector->left) |
| 1599 | drm_property_destroy(dev, intel_sdvo_connector->left); |
| 1600 | if (intel_sdvo_connector->right) |
| 1601 | drm_property_destroy(dev, intel_sdvo_connector->right); |
| 1602 | if (intel_sdvo_connector->top) |
| 1603 | drm_property_destroy(dev, intel_sdvo_connector->top); |
| 1604 | if (intel_sdvo_connector->bottom) |
| 1605 | drm_property_destroy(dev, intel_sdvo_connector->bottom); |
| 1606 | if (intel_sdvo_connector->hpos) |
| 1607 | drm_property_destroy(dev, intel_sdvo_connector->hpos); |
| 1608 | if (intel_sdvo_connector->vpos) |
| 1609 | drm_property_destroy(dev, intel_sdvo_connector->vpos); |
| 1610 | if (intel_sdvo_connector->saturation) |
| 1611 | drm_property_destroy(dev, intel_sdvo_connector->saturation); |
| 1612 | if (intel_sdvo_connector->contrast) |
| 1613 | drm_property_destroy(dev, intel_sdvo_connector->contrast); |
| 1614 | if (intel_sdvo_connector->hue) |
| 1615 | drm_property_destroy(dev, intel_sdvo_connector->hue); |
| 1616 | if (intel_sdvo_connector->sharpness) |
| 1617 | drm_property_destroy(dev, intel_sdvo_connector->sharpness); |
| 1618 | if (intel_sdvo_connector->flicker_filter) |
| 1619 | drm_property_destroy(dev, intel_sdvo_connector->flicker_filter); |
| 1620 | if (intel_sdvo_connector->flicker_filter_2d) |
| 1621 | drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_2d); |
| 1622 | if (intel_sdvo_connector->flicker_filter_adaptive) |
| 1623 | drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_adaptive); |
| 1624 | if (intel_sdvo_connector->tv_luma_filter) |
| 1625 | drm_property_destroy(dev, intel_sdvo_connector->tv_luma_filter); |
| 1626 | if (intel_sdvo_connector->tv_chroma_filter) |
| 1627 | drm_property_destroy(dev, intel_sdvo_connector->tv_chroma_filter); |
Chris Wilson | e044218 | 2010-08-04 13:50:29 +0100 | [diff] [blame] | 1628 | if (intel_sdvo_connector->dot_crawl) |
| 1629 | drm_property_destroy(dev, intel_sdvo_connector->dot_crawl); |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 1630 | if (intel_sdvo_connector->brightness) |
| 1631 | drm_property_destroy(dev, intel_sdvo_connector->brightness); |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1632 | } |
| 1633 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1634 | static void intel_sdvo_destroy(struct drm_connector *connector) |
| 1635 | { |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 1636 | struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1637 | |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 1638 | if (intel_sdvo_connector->tv_format) |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1639 | drm_property_destroy(connector->dev, |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 1640 | intel_sdvo_connector->tv_format); |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1641 | |
Zhenyu Wang | d2a82a6 | 2010-03-29 21:22:55 +0800 | [diff] [blame] | 1642 | intel_sdvo_destroy_enhance_property(connector); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1643 | drm_sysfs_connector_remove(connector); |
| 1644 | drm_connector_cleanup(connector); |
Zhenyu Wang | d2a82a6 | 2010-03-29 21:22:55 +0800 | [diff] [blame] | 1645 | kfree(connector); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1646 | } |
| 1647 | |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 1648 | static bool intel_sdvo_detect_hdmi_audio(struct drm_connector *connector) |
| 1649 | { |
| 1650 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); |
| 1651 | struct edid *edid; |
| 1652 | bool has_audio = false; |
| 1653 | |
| 1654 | if (!intel_sdvo->is_hdmi) |
| 1655 | return false; |
| 1656 | |
| 1657 | edid = intel_sdvo_get_edid(connector); |
| 1658 | if (edid != NULL && edid->input & DRM_EDID_INPUT_DIGITAL) |
| 1659 | has_audio = drm_detect_monitor_audio(edid); |
| 1660 | |
| 1661 | return has_audio; |
| 1662 | } |
| 1663 | |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1664 | static int |
| 1665 | intel_sdvo_set_property(struct drm_connector *connector, |
| 1666 | struct drm_property *property, |
| 1667 | uint64_t val) |
| 1668 | { |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 1669 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 1670 | struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); |
Chris Wilson | e953fd7 | 2011-02-21 22:23:52 +0000 | [diff] [blame] | 1671 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1672 | uint16_t temp_value; |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1673 | uint8_t cmd; |
| 1674 | int ret; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1675 | |
| 1676 | ret = drm_connector_property_set_value(connector, property, val); |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1677 | if (ret) |
| 1678 | return ret; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1679 | |
Chris Wilson | 3f43c48 | 2011-05-12 22:17:24 +0100 | [diff] [blame] | 1680 | if (property == dev_priv->force_audio_property) { |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 1681 | int i = val; |
| 1682 | bool has_audio; |
| 1683 | |
| 1684 | if (i == intel_sdvo_connector->force_audio) |
Chris Wilson | 7f36e7e | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 1685 | return 0; |
| 1686 | |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 1687 | intel_sdvo_connector->force_audio = i; |
Chris Wilson | 7f36e7e | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 1688 | |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 1689 | if (i == 0) |
| 1690 | has_audio = intel_sdvo_detect_hdmi_audio(connector); |
| 1691 | else |
| 1692 | has_audio = i > 0; |
| 1693 | |
| 1694 | if (has_audio == intel_sdvo->has_hdmi_audio) |
Chris Wilson | 7f36e7e | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 1695 | return 0; |
| 1696 | |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 1697 | intel_sdvo->has_hdmi_audio = has_audio; |
Chris Wilson | 7f36e7e | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 1698 | goto done; |
| 1699 | } |
| 1700 | |
Chris Wilson | e953fd7 | 2011-02-21 22:23:52 +0000 | [diff] [blame] | 1701 | if (property == dev_priv->broadcast_rgb_property) { |
| 1702 | if (val == !!intel_sdvo->color_range) |
| 1703 | return 0; |
| 1704 | |
| 1705 | intel_sdvo->color_range = val ? SDVO_COLOR_RANGE_16_235 : 0; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1706 | goto done; |
| 1707 | } |
| 1708 | |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 1709 | #define CHECK_PROPERTY(name, NAME) \ |
| 1710 | if (intel_sdvo_connector->name == property) { \ |
| 1711 | if (intel_sdvo_connector->cur_##name == temp_value) return 0; \ |
| 1712 | if (intel_sdvo_connector->max_##name < temp_value) return -EINVAL; \ |
| 1713 | cmd = SDVO_CMD_SET_##NAME; \ |
| 1714 | intel_sdvo_connector->cur_##name = temp_value; \ |
| 1715 | goto set_value; \ |
| 1716 | } |
| 1717 | |
| 1718 | if (property == intel_sdvo_connector->tv_format) { |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1719 | if (val >= TV_FORMAT_NUM) |
| 1720 | return -EINVAL; |
| 1721 | |
Chris Wilson | 4003975 | 2010-08-04 13:50:26 +0100 | [diff] [blame] | 1722 | if (intel_sdvo->tv_format_index == |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 1723 | intel_sdvo_connector->tv_format_supported[val]) |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1724 | return 0; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1725 | |
Chris Wilson | 4003975 | 2010-08-04 13:50:26 +0100 | [diff] [blame] | 1726 | intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[val]; |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 1727 | goto done; |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1728 | } else if (IS_TV_OR_LVDS(intel_sdvo_connector)) { |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1729 | temp_value = val; |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 1730 | if (intel_sdvo_connector->left == property) { |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1731 | drm_connector_property_set_value(connector, |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 1732 | intel_sdvo_connector->right, val); |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 1733 | if (intel_sdvo_connector->left_margin == temp_value) |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1734 | return 0; |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1735 | |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 1736 | intel_sdvo_connector->left_margin = temp_value; |
| 1737 | intel_sdvo_connector->right_margin = temp_value; |
| 1738 | temp_value = intel_sdvo_connector->max_hscan - |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 1739 | intel_sdvo_connector->left_margin; |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1740 | cmd = SDVO_CMD_SET_OVERSCAN_H; |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 1741 | goto set_value; |
| 1742 | } else if (intel_sdvo_connector->right == property) { |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1743 | drm_connector_property_set_value(connector, |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 1744 | intel_sdvo_connector->left, val); |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 1745 | if (intel_sdvo_connector->right_margin == temp_value) |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1746 | return 0; |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1747 | |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 1748 | intel_sdvo_connector->left_margin = temp_value; |
| 1749 | intel_sdvo_connector->right_margin = temp_value; |
| 1750 | temp_value = intel_sdvo_connector->max_hscan - |
| 1751 | intel_sdvo_connector->left_margin; |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1752 | cmd = SDVO_CMD_SET_OVERSCAN_H; |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 1753 | goto set_value; |
| 1754 | } else if (intel_sdvo_connector->top == property) { |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1755 | drm_connector_property_set_value(connector, |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 1756 | intel_sdvo_connector->bottom, val); |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 1757 | if (intel_sdvo_connector->top_margin == temp_value) |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1758 | return 0; |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1759 | |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 1760 | intel_sdvo_connector->top_margin = temp_value; |
| 1761 | intel_sdvo_connector->bottom_margin = temp_value; |
| 1762 | temp_value = intel_sdvo_connector->max_vscan - |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 1763 | intel_sdvo_connector->top_margin; |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1764 | cmd = SDVO_CMD_SET_OVERSCAN_V; |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 1765 | goto set_value; |
| 1766 | } else if (intel_sdvo_connector->bottom == property) { |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1767 | drm_connector_property_set_value(connector, |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 1768 | intel_sdvo_connector->top, val); |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 1769 | if (intel_sdvo_connector->bottom_margin == temp_value) |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1770 | return 0; |
| 1771 | |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 1772 | intel_sdvo_connector->top_margin = temp_value; |
| 1773 | intel_sdvo_connector->bottom_margin = temp_value; |
| 1774 | temp_value = intel_sdvo_connector->max_vscan - |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 1775 | intel_sdvo_connector->top_margin; |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1776 | cmd = SDVO_CMD_SET_OVERSCAN_V; |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 1777 | goto set_value; |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1778 | } |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 1779 | CHECK_PROPERTY(hpos, HPOS) |
| 1780 | CHECK_PROPERTY(vpos, VPOS) |
| 1781 | CHECK_PROPERTY(saturation, SATURATION) |
| 1782 | CHECK_PROPERTY(contrast, CONTRAST) |
| 1783 | CHECK_PROPERTY(hue, HUE) |
| 1784 | CHECK_PROPERTY(brightness, BRIGHTNESS) |
| 1785 | CHECK_PROPERTY(sharpness, SHARPNESS) |
| 1786 | CHECK_PROPERTY(flicker_filter, FLICKER_FILTER) |
| 1787 | CHECK_PROPERTY(flicker_filter_2d, FLICKER_FILTER_2D) |
| 1788 | CHECK_PROPERTY(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE) |
| 1789 | CHECK_PROPERTY(tv_chroma_filter, TV_CHROMA_FILTER) |
| 1790 | CHECK_PROPERTY(tv_luma_filter, TV_LUMA_FILTER) |
Chris Wilson | e044218 | 2010-08-04 13:50:29 +0100 | [diff] [blame] | 1791 | CHECK_PROPERTY(dot_crawl, DOT_CRAWL) |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1792 | } |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 1793 | |
| 1794 | return -EINVAL; /* unknown property */ |
| 1795 | |
| 1796 | set_value: |
| 1797 | if (!intel_sdvo_set_value(intel_sdvo, cmd, &temp_value, 2)) |
| 1798 | return -EIO; |
| 1799 | |
| 1800 | |
| 1801 | done: |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 1802 | if (intel_sdvo->base.base.crtc) { |
| 1803 | struct drm_crtc *crtc = intel_sdvo->base.base.crtc; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1804 | drm_crtc_helper_set_mode(crtc, &crtc->mode, crtc->x, |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 1805 | crtc->y, crtc->fb); |
| 1806 | } |
| 1807 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1808 | return 0; |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 1809 | #undef CHECK_PROPERTY |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1810 | } |
| 1811 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1812 | static const struct drm_encoder_helper_funcs intel_sdvo_helper_funcs = { |
| 1813 | .dpms = intel_sdvo_dpms, |
| 1814 | .mode_fixup = intel_sdvo_mode_fixup, |
| 1815 | .prepare = intel_encoder_prepare, |
| 1816 | .mode_set = intel_sdvo_mode_set, |
| 1817 | .commit = intel_encoder_commit, |
| 1818 | }; |
| 1819 | |
| 1820 | static const struct drm_connector_funcs intel_sdvo_connector_funcs = { |
Keith Packard | c9fb15f | 2009-05-30 20:42:28 -0700 | [diff] [blame] | 1821 | .dpms = drm_helper_connector_dpms, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1822 | .detect = intel_sdvo_detect, |
| 1823 | .fill_modes = drm_helper_probe_single_connector_modes, |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1824 | .set_property = intel_sdvo_set_property, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1825 | .destroy = intel_sdvo_destroy, |
| 1826 | }; |
| 1827 | |
| 1828 | static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = { |
| 1829 | .get_modes = intel_sdvo_get_modes, |
| 1830 | .mode_valid = intel_sdvo_mode_valid, |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 1831 | .best_encoder = intel_best_encoder, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1832 | }; |
| 1833 | |
Hannes Eder | b358d0a | 2008-12-18 21:18:47 +0100 | [diff] [blame] | 1834 | static void intel_sdvo_enc_destroy(struct drm_encoder *encoder) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1835 | { |
Chris Wilson | 890f335 | 2010-09-14 16:46:59 +0100 | [diff] [blame] | 1836 | struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder); |
Zhenyu Wang | d2a82a6 | 2010-03-29 21:22:55 +0800 | [diff] [blame] | 1837 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1838 | if (intel_sdvo->sdvo_lvds_fixed_mode != NULL) |
Zhenyu Wang | d2a82a6 | 2010-03-29 21:22:55 +0800 | [diff] [blame] | 1839 | drm_mode_destroy(encoder->dev, |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1840 | intel_sdvo->sdvo_lvds_fixed_mode); |
Zhenyu Wang | d2a82a6 | 2010-03-29 21:22:55 +0800 | [diff] [blame] | 1841 | |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 1842 | i2c_del_adapter(&intel_sdvo->ddc); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1843 | intel_encoder_destroy(encoder); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1844 | } |
| 1845 | |
| 1846 | static const struct drm_encoder_funcs intel_sdvo_enc_funcs = { |
| 1847 | .destroy = intel_sdvo_enc_destroy, |
| 1848 | }; |
| 1849 | |
Chris Wilson | b66d842 | 2010-08-12 15:26:41 +0100 | [diff] [blame] | 1850 | static void |
| 1851 | intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo) |
| 1852 | { |
| 1853 | uint16_t mask = 0; |
| 1854 | unsigned int num_bits; |
| 1855 | |
| 1856 | /* Make a mask of outputs less than or equal to our own priority in the |
| 1857 | * list. |
| 1858 | */ |
| 1859 | switch (sdvo->controlled_output) { |
| 1860 | case SDVO_OUTPUT_LVDS1: |
| 1861 | mask |= SDVO_OUTPUT_LVDS1; |
| 1862 | case SDVO_OUTPUT_LVDS0: |
| 1863 | mask |= SDVO_OUTPUT_LVDS0; |
| 1864 | case SDVO_OUTPUT_TMDS1: |
| 1865 | mask |= SDVO_OUTPUT_TMDS1; |
| 1866 | case SDVO_OUTPUT_TMDS0: |
| 1867 | mask |= SDVO_OUTPUT_TMDS0; |
| 1868 | case SDVO_OUTPUT_RGB1: |
| 1869 | mask |= SDVO_OUTPUT_RGB1; |
| 1870 | case SDVO_OUTPUT_RGB0: |
| 1871 | mask |= SDVO_OUTPUT_RGB0; |
| 1872 | break; |
| 1873 | } |
| 1874 | |
| 1875 | /* Count bits to find what number we are in the priority list. */ |
| 1876 | mask &= sdvo->caps.output_flags; |
| 1877 | num_bits = hweight16(mask); |
| 1878 | /* If more than 3 outputs, default to DDC bus 3 for now. */ |
| 1879 | if (num_bits > 3) |
| 1880 | num_bits = 3; |
| 1881 | |
| 1882 | /* Corresponds to SDVO_CONTROL_BUS_DDCx */ |
| 1883 | sdvo->ddc_bus = 1 << num_bits; |
| 1884 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1885 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1886 | /** |
| 1887 | * Choose the appropriate DDC bus for control bus switch command for this |
| 1888 | * SDVO output based on the controlled output. |
| 1889 | * |
| 1890 | * DDC bus number assignment is in a priority order of RGB outputs, then TMDS |
| 1891 | * outputs, then LVDS outputs. |
| 1892 | */ |
| 1893 | static void |
Adam Jackson | b108333 | 2010-04-23 16:07:40 -0400 | [diff] [blame] | 1894 | intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv, |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1895 | struct intel_sdvo *sdvo, u32 reg) |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1896 | { |
Adam Jackson | b108333 | 2010-04-23 16:07:40 -0400 | [diff] [blame] | 1897 | struct sdvo_device_mapping *mapping; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1898 | |
Adam Jackson | b108333 | 2010-04-23 16:07:40 -0400 | [diff] [blame] | 1899 | if (IS_SDVOB(reg)) |
| 1900 | mapping = &(dev_priv->sdvo_mappings[0]); |
| 1901 | else |
| 1902 | mapping = &(dev_priv->sdvo_mappings[1]); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1903 | |
Chris Wilson | b66d842 | 2010-08-12 15:26:41 +0100 | [diff] [blame] | 1904 | if (mapping->initialized) |
| 1905 | sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4); |
| 1906 | else |
| 1907 | intel_sdvo_guess_ddc_bus(sdvo); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1908 | } |
| 1909 | |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 1910 | static void |
| 1911 | intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv, |
| 1912 | struct intel_sdvo *sdvo, u32 reg) |
| 1913 | { |
| 1914 | struct sdvo_device_mapping *mapping; |
Adam Jackson | 46eb303 | 2011-06-16 16:36:23 -0400 | [diff] [blame] | 1915 | u8 pin; |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 1916 | |
| 1917 | if (IS_SDVOB(reg)) |
| 1918 | mapping = &dev_priv->sdvo_mappings[0]; |
| 1919 | else |
| 1920 | mapping = &dev_priv->sdvo_mappings[1]; |
| 1921 | |
| 1922 | pin = GMBUS_PORT_DPB; |
Adam Jackson | 46eb303 | 2011-06-16 16:36:23 -0400 | [diff] [blame] | 1923 | if (mapping->initialized) |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 1924 | pin = mapping->i2c_pin; |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 1925 | |
Chris Wilson | 63abf3e | 2010-12-08 16:48:21 +0000 | [diff] [blame] | 1926 | if (pin < GMBUS_NUM_PORTS) { |
| 1927 | sdvo->i2c = &dev_priv->gmbus[pin].adapter; |
Adam Jackson | d5090b9 | 2011-06-16 16:36:28 -0400 | [diff] [blame] | 1928 | intel_gmbus_set_speed(sdvo->i2c, GMBUS_RATE_1MHZ); |
Chris Wilson | 63abf3e | 2010-12-08 16:48:21 +0000 | [diff] [blame] | 1929 | intel_gmbus_force_bit(sdvo->i2c, true); |
Adam Jackson | 46eb303 | 2011-06-16 16:36:23 -0400 | [diff] [blame] | 1930 | } else { |
Chris Wilson | 63abf3e | 2010-12-08 16:48:21 +0000 | [diff] [blame] | 1931 | sdvo->i2c = &dev_priv->gmbus[GMBUS_PORT_DPB].adapter; |
Adam Jackson | 46eb303 | 2011-06-16 16:36:23 -0400 | [diff] [blame] | 1932 | } |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 1933 | } |
| 1934 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1935 | static bool |
Chris Wilson | e27d853 | 2010-10-22 09:15:22 +0100 | [diff] [blame] | 1936 | intel_sdvo_is_hdmi_connector(struct intel_sdvo *intel_sdvo, int device) |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1937 | { |
Chris Wilson | 97aaf91 | 2011-01-04 20:10:52 +0000 | [diff] [blame] | 1938 | return intel_sdvo_check_supp_encode(intel_sdvo); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1939 | } |
| 1940 | |
yakui_zhao | 714605e | 2009-05-31 17:18:07 +0800 | [diff] [blame] | 1941 | static u8 |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 1942 | intel_sdvo_get_slave_addr(struct drm_device *dev, int sdvo_reg) |
yakui_zhao | 714605e | 2009-05-31 17:18:07 +0800 | [diff] [blame] | 1943 | { |
| 1944 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1945 | struct sdvo_device_mapping *my_mapping, *other_mapping; |
| 1946 | |
Zhao Yakui | 461ed3c | 2010-03-30 15:11:33 +0800 | [diff] [blame] | 1947 | if (IS_SDVOB(sdvo_reg)) { |
yakui_zhao | 714605e | 2009-05-31 17:18:07 +0800 | [diff] [blame] | 1948 | my_mapping = &dev_priv->sdvo_mappings[0]; |
| 1949 | other_mapping = &dev_priv->sdvo_mappings[1]; |
| 1950 | } else { |
| 1951 | my_mapping = &dev_priv->sdvo_mappings[1]; |
| 1952 | other_mapping = &dev_priv->sdvo_mappings[0]; |
| 1953 | } |
| 1954 | |
| 1955 | /* If the BIOS described our SDVO device, take advantage of it. */ |
| 1956 | if (my_mapping->slave_addr) |
| 1957 | return my_mapping->slave_addr; |
| 1958 | |
| 1959 | /* If the BIOS only described a different SDVO device, use the |
| 1960 | * address that it isn't using. |
| 1961 | */ |
| 1962 | if (other_mapping->slave_addr) { |
| 1963 | if (other_mapping->slave_addr == 0x70) |
| 1964 | return 0x72; |
| 1965 | else |
| 1966 | return 0x70; |
| 1967 | } |
| 1968 | |
| 1969 | /* No SDVO device info is found for another DVO port, |
| 1970 | * so use mapping assumption we had before BIOS parsing. |
| 1971 | */ |
Zhao Yakui | 461ed3c | 2010-03-30 15:11:33 +0800 | [diff] [blame] | 1972 | if (IS_SDVOB(sdvo_reg)) |
yakui_zhao | 714605e | 2009-05-31 17:18:07 +0800 | [diff] [blame] | 1973 | return 0x70; |
| 1974 | else |
| 1975 | return 0x72; |
| 1976 | } |
| 1977 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1978 | static void |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 1979 | intel_sdvo_connector_init(struct intel_sdvo_connector *connector, |
| 1980 | struct intel_sdvo *encoder) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1981 | { |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 1982 | drm_connector_init(encoder->base.base.dev, |
| 1983 | &connector->base.base, |
| 1984 | &intel_sdvo_connector_funcs, |
| 1985 | connector->base.base.connector_type); |
Zhao Yakui | 6070a4a | 2010-02-08 21:35:12 +0800 | [diff] [blame] | 1986 | |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 1987 | drm_connector_helper_add(&connector->base.base, |
| 1988 | &intel_sdvo_connector_helper_funcs); |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1989 | |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 1990 | connector->base.base.interlace_allowed = 0; |
| 1991 | connector->base.base.doublescan_allowed = 0; |
| 1992 | connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1993 | |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 1994 | intel_connector_attach_encoder(&connector->base, &encoder->base); |
| 1995 | drm_sysfs_connector_add(&connector->base.base); |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1996 | } |
| 1997 | |
Chris Wilson | 7f36e7e | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 1998 | static void |
| 1999 | intel_sdvo_add_hdmi_properties(struct intel_sdvo_connector *connector) |
| 2000 | { |
| 2001 | struct drm_device *dev = connector->base.base.dev; |
| 2002 | |
Chris Wilson | 3f43c48 | 2011-05-12 22:17:24 +0100 | [diff] [blame] | 2003 | intel_attach_force_audio_property(&connector->base.base); |
Chris Wilson | e953fd7 | 2011-02-21 22:23:52 +0000 | [diff] [blame] | 2004 | if (INTEL_INFO(dev)->gen >= 4 && IS_MOBILE(dev)) |
| 2005 | intel_attach_broadcast_rgb_property(&connector->base.base); |
Chris Wilson | 7f36e7e | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 2006 | } |
| 2007 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2008 | static bool |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2009 | intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2010 | { |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2011 | struct drm_encoder *encoder = &intel_sdvo->base.base; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2012 | struct drm_connector *connector; |
Simon Farnsworth | cc68c81 | 2011-09-21 17:13:30 +0100 | [diff] [blame] | 2013 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2014 | struct intel_connector *intel_connector; |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 2015 | struct intel_sdvo_connector *intel_sdvo_connector; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2016 | |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 2017 | intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL); |
| 2018 | if (!intel_sdvo_connector) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2019 | return false; |
| 2020 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2021 | if (device == 0) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2022 | intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0; |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 2023 | intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2024 | } else if (device == 1) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2025 | intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1; |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 2026 | intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2027 | } |
| 2028 | |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 2029 | intel_connector = &intel_sdvo_connector->base; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2030 | connector = &intel_connector->base; |
Simon Farnsworth | cc68c81 | 2011-09-21 17:13:30 +0100 | [diff] [blame] | 2031 | if (intel_sdvo_supports_hotplug(intel_sdvo) & (1 << device)) { |
| 2032 | connector->polled = DRM_CONNECTOR_POLL_HPD; |
| 2033 | intel_sdvo->hotplug_active[0] |= 1 << device; |
| 2034 | /* Some SDVO devices have one-shot hotplug interrupts. |
| 2035 | * Ensure that they get re-enabled when an interrupt happens. |
| 2036 | */ |
| 2037 | intel_encoder->hot_plug = intel_sdvo_enable_hotplug; |
| 2038 | intel_sdvo_enable_hotplug(intel_encoder); |
| 2039 | } |
| 2040 | else |
| 2041 | connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2042 | encoder->encoder_type = DRM_MODE_ENCODER_TMDS; |
| 2043 | connector->connector_type = DRM_MODE_CONNECTOR_DVID; |
| 2044 | |
Chris Wilson | e27d853 | 2010-10-22 09:15:22 +0100 | [diff] [blame] | 2045 | if (intel_sdvo_is_hdmi_connector(intel_sdvo, device)) { |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2046 | connector->connector_type = DRM_MODE_CONNECTOR_HDMIA; |
Chris Wilson | e27d853 | 2010-10-22 09:15:22 +0100 | [diff] [blame] | 2047 | intel_sdvo->is_hdmi = true; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2048 | } |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2049 | intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) | |
| 2050 | (1 << INTEL_ANALOG_CLONE_BIT)); |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2051 | |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 2052 | intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo); |
Chris Wilson | f797d22 | 2010-12-23 09:43:48 +0000 | [diff] [blame] | 2053 | if (intel_sdvo->is_hdmi) |
| 2054 | intel_sdvo_add_hdmi_properties(intel_sdvo_connector); |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2055 | |
| 2056 | return true; |
| 2057 | } |
| 2058 | |
| 2059 | static bool |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2060 | intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2061 | { |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2062 | struct drm_encoder *encoder = &intel_sdvo->base.base; |
| 2063 | struct drm_connector *connector; |
| 2064 | struct intel_connector *intel_connector; |
| 2065 | struct intel_sdvo_connector *intel_sdvo_connector; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2066 | |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 2067 | intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL); |
| 2068 | if (!intel_sdvo_connector) |
| 2069 | return false; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2070 | |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 2071 | intel_connector = &intel_sdvo_connector->base; |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2072 | connector = &intel_connector->base; |
| 2073 | encoder->encoder_type = DRM_MODE_ENCODER_TVDAC; |
| 2074 | connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2075 | |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2076 | intel_sdvo->controlled_output |= type; |
| 2077 | intel_sdvo_connector->output_flag = type; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2078 | |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2079 | intel_sdvo->is_tv = true; |
| 2080 | intel_sdvo->base.needs_tv_clock = true; |
| 2081 | intel_sdvo->base.clone_mask = 1 << INTEL_SDVO_TV_CLONE_BIT; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2082 | |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 2083 | intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo); |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2084 | |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2085 | if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type)) |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2086 | goto err; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2087 | |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2088 | if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector)) |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2089 | goto err; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2090 | |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2091 | return true; |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2092 | |
| 2093 | err: |
Chris Wilson | 123d5c0 | 2010-09-23 16:15:21 +0100 | [diff] [blame] | 2094 | intel_sdvo_destroy(connector); |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2095 | return false; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2096 | } |
| 2097 | |
| 2098 | static bool |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2099 | intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2100 | { |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2101 | struct drm_encoder *encoder = &intel_sdvo->base.base; |
| 2102 | struct drm_connector *connector; |
| 2103 | struct intel_connector *intel_connector; |
| 2104 | struct intel_sdvo_connector *intel_sdvo_connector; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2105 | |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 2106 | intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL); |
| 2107 | if (!intel_sdvo_connector) |
| 2108 | return false; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2109 | |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 2110 | intel_connector = &intel_sdvo_connector->base; |
| 2111 | connector = &intel_connector->base; |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2112 | connector->polled = DRM_CONNECTOR_POLL_CONNECT; |
| 2113 | encoder->encoder_type = DRM_MODE_ENCODER_DAC; |
| 2114 | connector->connector_type = DRM_MODE_CONNECTOR_VGA; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2115 | |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2116 | if (device == 0) { |
| 2117 | intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0; |
| 2118 | intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0; |
| 2119 | } else if (device == 1) { |
| 2120 | intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1; |
| 2121 | intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1; |
| 2122 | } |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2123 | |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2124 | intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) | |
| 2125 | (1 << INTEL_ANALOG_CLONE_BIT)); |
| 2126 | |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 2127 | intel_sdvo_connector_init(intel_sdvo_connector, |
| 2128 | intel_sdvo); |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2129 | return true; |
| 2130 | } |
| 2131 | |
| 2132 | static bool |
| 2133 | intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device) |
| 2134 | { |
| 2135 | struct drm_encoder *encoder = &intel_sdvo->base.base; |
| 2136 | struct drm_connector *connector; |
| 2137 | struct intel_connector *intel_connector; |
| 2138 | struct intel_sdvo_connector *intel_sdvo_connector; |
| 2139 | |
| 2140 | intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL); |
| 2141 | if (!intel_sdvo_connector) |
| 2142 | return false; |
| 2143 | |
| 2144 | intel_connector = &intel_sdvo_connector->base; |
| 2145 | connector = &intel_connector->base; |
| 2146 | encoder->encoder_type = DRM_MODE_ENCODER_LVDS; |
| 2147 | connector->connector_type = DRM_MODE_CONNECTOR_LVDS; |
| 2148 | |
| 2149 | if (device == 0) { |
| 2150 | intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0; |
| 2151 | intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0; |
| 2152 | } else if (device == 1) { |
| 2153 | intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1; |
| 2154 | intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1; |
| 2155 | } |
| 2156 | |
| 2157 | intel_sdvo->base.clone_mask = ((1 << INTEL_ANALOG_CLONE_BIT) | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2158 | (1 << INTEL_SDVO_LVDS_CLONE_BIT)); |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2159 | |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 2160 | intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo); |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2161 | if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector)) |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2162 | goto err; |
| 2163 | |
| 2164 | return true; |
| 2165 | |
| 2166 | err: |
Chris Wilson | 123d5c0 | 2010-09-23 16:15:21 +0100 | [diff] [blame] | 2167 | intel_sdvo_destroy(connector); |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2168 | return false; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2169 | } |
Zhao Yakui | 6070a4a | 2010-02-08 21:35:12 +0800 | [diff] [blame] | 2170 | |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2171 | static bool |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2172 | intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags) |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2173 | { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2174 | intel_sdvo->is_tv = false; |
| 2175 | intel_sdvo->base.needs_tv_clock = false; |
| 2176 | intel_sdvo->is_lvds = false; |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2177 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2178 | /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/ |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2179 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2180 | if (flags & SDVO_OUTPUT_TMDS0) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2181 | if (!intel_sdvo_dvi_init(intel_sdvo, 0)) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2182 | return false; |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2183 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2184 | if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2185 | if (!intel_sdvo_dvi_init(intel_sdvo, 1)) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2186 | return false; |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2187 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2188 | /* TV has no XXX1 function block */ |
Zhenyu Wang | a1f4b7ff | 2010-03-29 23:16:13 +0800 | [diff] [blame] | 2189 | if (flags & SDVO_OUTPUT_SVID0) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2190 | if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0)) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2191 | return false; |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2192 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2193 | if (flags & SDVO_OUTPUT_CVBS0) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2194 | if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0)) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2195 | return false; |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2196 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2197 | if (flags & SDVO_OUTPUT_RGB0) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2198 | if (!intel_sdvo_analog_init(intel_sdvo, 0)) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2199 | return false; |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2200 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2201 | if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2202 | if (!intel_sdvo_analog_init(intel_sdvo, 1)) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2203 | return false; |
Zhao Yakui | 2dd8738 | 2010-01-27 16:32:46 +0800 | [diff] [blame] | 2204 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2205 | if (flags & SDVO_OUTPUT_LVDS0) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2206 | if (!intel_sdvo_lvds_init(intel_sdvo, 0)) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2207 | return false; |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2208 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2209 | if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2210 | if (!intel_sdvo_lvds_init(intel_sdvo, 1)) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2211 | return false; |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2212 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2213 | if ((flags & SDVO_OUTPUT_MASK) == 0) { |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2214 | unsigned char bytes[2]; |
| 2215 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2216 | intel_sdvo->controlled_output = 0; |
| 2217 | memcpy(bytes, &intel_sdvo->caps.output_flags, 2); |
Dave Airlie | 51c8b40 | 2009-08-20 13:38:04 +1000 | [diff] [blame] | 2218 | DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n", |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2219 | SDVO_NAME(intel_sdvo), |
Dave Airlie | 51c8b40 | 2009-08-20 13:38:04 +1000 | [diff] [blame] | 2220 | bytes[0], bytes[1]); |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2221 | return false; |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2222 | } |
Jesse Barnes | 27f8227 | 2011-09-02 12:54:37 -0700 | [diff] [blame] | 2223 | intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2224 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2225 | return true; |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2226 | } |
| 2227 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2228 | static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo, |
| 2229 | struct intel_sdvo_connector *intel_sdvo_connector, |
| 2230 | int type) |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2231 | { |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2232 | struct drm_device *dev = intel_sdvo->base.base.dev; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2233 | struct intel_sdvo_tv_format format; |
| 2234 | uint32_t format_map, i; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2235 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2236 | if (!intel_sdvo_set_target_output(intel_sdvo, type)) |
| 2237 | return false; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2238 | |
Chris Wilson | 1a3665c | 2011-01-25 13:59:37 +0000 | [diff] [blame] | 2239 | BUILD_BUG_ON(sizeof(format) != 6); |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2240 | if (!intel_sdvo_get_value(intel_sdvo, |
| 2241 | SDVO_CMD_GET_SUPPORTED_TV_FORMATS, |
| 2242 | &format, sizeof(format))) |
| 2243 | return false; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2244 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2245 | memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format))); |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2246 | |
| 2247 | if (format_map == 0) |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2248 | return false; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2249 | |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 2250 | intel_sdvo_connector->format_supported_num = 0; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2251 | for (i = 0 ; i < TV_FORMAT_NUM; i++) |
Chris Wilson | 4003975 | 2010-08-04 13:50:26 +0100 | [diff] [blame] | 2252 | if (format_map & (1 << i)) |
| 2253 | intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2254 | |
| 2255 | |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2256 | intel_sdvo_connector->tv_format = |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2257 | drm_property_create(dev, DRM_MODE_PROP_ENUM, |
| 2258 | "mode", intel_sdvo_connector->format_supported_num); |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2259 | if (!intel_sdvo_connector->tv_format) |
Chris Wilson | fcc8d67 | 2010-08-04 13:50:27 +0100 | [diff] [blame] | 2260 | return false; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2261 | |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 2262 | for (i = 0; i < intel_sdvo_connector->format_supported_num; i++) |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2263 | drm_property_add_enum( |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2264 | intel_sdvo_connector->tv_format, i, |
Chris Wilson | 4003975 | 2010-08-04 13:50:26 +0100 | [diff] [blame] | 2265 | i, tv_format_names[intel_sdvo_connector->tv_format_supported[i]]); |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2266 | |
Chris Wilson | 4003975 | 2010-08-04 13:50:26 +0100 | [diff] [blame] | 2267 | intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[0]; |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2268 | drm_connector_attach_property(&intel_sdvo_connector->base.base, |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2269 | intel_sdvo_connector->tv_format, 0); |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2270 | return true; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2271 | |
| 2272 | } |
| 2273 | |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2274 | #define ENHANCEMENT(name, NAME) do { \ |
| 2275 | if (enhancements.name) { \ |
| 2276 | if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \ |
| 2277 | !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \ |
| 2278 | return false; \ |
| 2279 | intel_sdvo_connector->max_##name = data_value[0]; \ |
| 2280 | intel_sdvo_connector->cur_##name = response; \ |
| 2281 | intel_sdvo_connector->name = \ |
| 2282 | drm_property_create(dev, DRM_MODE_PROP_RANGE, #name, 2); \ |
| 2283 | if (!intel_sdvo_connector->name) return false; \ |
| 2284 | intel_sdvo_connector->name->values[0] = 0; \ |
| 2285 | intel_sdvo_connector->name->values[1] = data_value[0]; \ |
| 2286 | drm_connector_attach_property(connector, \ |
| 2287 | intel_sdvo_connector->name, \ |
| 2288 | intel_sdvo_connector->cur_##name); \ |
| 2289 | DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \ |
| 2290 | data_value[0], data_value[1], response); \ |
| 2291 | } \ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 2292 | } while (0) |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2293 | |
| 2294 | static bool |
| 2295 | intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo, |
| 2296 | struct intel_sdvo_connector *intel_sdvo_connector, |
| 2297 | struct intel_sdvo_enhancements_reply enhancements) |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2298 | { |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2299 | struct drm_device *dev = intel_sdvo->base.base.dev; |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2300 | struct drm_connector *connector = &intel_sdvo_connector->base.base; |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2301 | uint16_t response, data_value[2]; |
| 2302 | |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2303 | /* when horizontal overscan is supported, Add the left/right property */ |
| 2304 | if (enhancements.overscan_h) { |
| 2305 | if (!intel_sdvo_get_value(intel_sdvo, |
| 2306 | SDVO_CMD_GET_MAX_OVERSCAN_H, |
| 2307 | &data_value, 4)) |
| 2308 | return false; |
| 2309 | |
| 2310 | if (!intel_sdvo_get_value(intel_sdvo, |
| 2311 | SDVO_CMD_GET_OVERSCAN_H, |
| 2312 | &response, 2)) |
| 2313 | return false; |
| 2314 | |
| 2315 | intel_sdvo_connector->max_hscan = data_value[0]; |
| 2316 | intel_sdvo_connector->left_margin = data_value[0] - response; |
| 2317 | intel_sdvo_connector->right_margin = intel_sdvo_connector->left_margin; |
| 2318 | intel_sdvo_connector->left = |
| 2319 | drm_property_create(dev, DRM_MODE_PROP_RANGE, |
| 2320 | "left_margin", 2); |
| 2321 | if (!intel_sdvo_connector->left) |
| 2322 | return false; |
| 2323 | |
| 2324 | intel_sdvo_connector->left->values[0] = 0; |
| 2325 | intel_sdvo_connector->left->values[1] = data_value[0]; |
| 2326 | drm_connector_attach_property(connector, |
| 2327 | intel_sdvo_connector->left, |
| 2328 | intel_sdvo_connector->left_margin); |
| 2329 | |
| 2330 | intel_sdvo_connector->right = |
| 2331 | drm_property_create(dev, DRM_MODE_PROP_RANGE, |
| 2332 | "right_margin", 2); |
| 2333 | if (!intel_sdvo_connector->right) |
| 2334 | return false; |
| 2335 | |
| 2336 | intel_sdvo_connector->right->values[0] = 0; |
| 2337 | intel_sdvo_connector->right->values[1] = data_value[0]; |
| 2338 | drm_connector_attach_property(connector, |
| 2339 | intel_sdvo_connector->right, |
| 2340 | intel_sdvo_connector->right_margin); |
| 2341 | DRM_DEBUG_KMS("h_overscan: max %d, " |
| 2342 | "default %d, current %d\n", |
| 2343 | data_value[0], data_value[1], response); |
| 2344 | } |
| 2345 | |
| 2346 | if (enhancements.overscan_v) { |
| 2347 | if (!intel_sdvo_get_value(intel_sdvo, |
| 2348 | SDVO_CMD_GET_MAX_OVERSCAN_V, |
| 2349 | &data_value, 4)) |
| 2350 | return false; |
| 2351 | |
| 2352 | if (!intel_sdvo_get_value(intel_sdvo, |
| 2353 | SDVO_CMD_GET_OVERSCAN_V, |
| 2354 | &response, 2)) |
| 2355 | return false; |
| 2356 | |
| 2357 | intel_sdvo_connector->max_vscan = data_value[0]; |
| 2358 | intel_sdvo_connector->top_margin = data_value[0] - response; |
| 2359 | intel_sdvo_connector->bottom_margin = intel_sdvo_connector->top_margin; |
| 2360 | intel_sdvo_connector->top = |
| 2361 | drm_property_create(dev, DRM_MODE_PROP_RANGE, |
| 2362 | "top_margin", 2); |
| 2363 | if (!intel_sdvo_connector->top) |
| 2364 | return false; |
| 2365 | |
| 2366 | intel_sdvo_connector->top->values[0] = 0; |
| 2367 | intel_sdvo_connector->top->values[1] = data_value[0]; |
| 2368 | drm_connector_attach_property(connector, |
| 2369 | intel_sdvo_connector->top, |
| 2370 | intel_sdvo_connector->top_margin); |
| 2371 | |
| 2372 | intel_sdvo_connector->bottom = |
| 2373 | drm_property_create(dev, DRM_MODE_PROP_RANGE, |
| 2374 | "bottom_margin", 2); |
| 2375 | if (!intel_sdvo_connector->bottom) |
| 2376 | return false; |
| 2377 | |
| 2378 | intel_sdvo_connector->bottom->values[0] = 0; |
| 2379 | intel_sdvo_connector->bottom->values[1] = data_value[0]; |
| 2380 | drm_connector_attach_property(connector, |
| 2381 | intel_sdvo_connector->bottom, |
| 2382 | intel_sdvo_connector->bottom_margin); |
| 2383 | DRM_DEBUG_KMS("v_overscan: max %d, " |
| 2384 | "default %d, current %d\n", |
| 2385 | data_value[0], data_value[1], response); |
| 2386 | } |
| 2387 | |
| 2388 | ENHANCEMENT(hpos, HPOS); |
| 2389 | ENHANCEMENT(vpos, VPOS); |
| 2390 | ENHANCEMENT(saturation, SATURATION); |
| 2391 | ENHANCEMENT(contrast, CONTRAST); |
| 2392 | ENHANCEMENT(hue, HUE); |
| 2393 | ENHANCEMENT(sharpness, SHARPNESS); |
| 2394 | ENHANCEMENT(brightness, BRIGHTNESS); |
| 2395 | ENHANCEMENT(flicker_filter, FLICKER_FILTER); |
| 2396 | ENHANCEMENT(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE); |
| 2397 | ENHANCEMENT(flicker_filter_2d, FLICKER_FILTER_2D); |
| 2398 | ENHANCEMENT(tv_chroma_filter, TV_CHROMA_FILTER); |
| 2399 | ENHANCEMENT(tv_luma_filter, TV_LUMA_FILTER); |
| 2400 | |
Chris Wilson | e044218 | 2010-08-04 13:50:29 +0100 | [diff] [blame] | 2401 | if (enhancements.dot_crawl) { |
| 2402 | if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2)) |
| 2403 | return false; |
| 2404 | |
| 2405 | intel_sdvo_connector->max_dot_crawl = 1; |
| 2406 | intel_sdvo_connector->cur_dot_crawl = response & 0x1; |
| 2407 | intel_sdvo_connector->dot_crawl = |
| 2408 | drm_property_create(dev, DRM_MODE_PROP_RANGE, "dot_crawl", 2); |
| 2409 | if (!intel_sdvo_connector->dot_crawl) |
| 2410 | return false; |
| 2411 | |
| 2412 | intel_sdvo_connector->dot_crawl->values[0] = 0; |
| 2413 | intel_sdvo_connector->dot_crawl->values[1] = 1; |
| 2414 | drm_connector_attach_property(connector, |
| 2415 | intel_sdvo_connector->dot_crawl, |
| 2416 | intel_sdvo_connector->cur_dot_crawl); |
| 2417 | DRM_DEBUG_KMS("dot crawl: current %d\n", response); |
| 2418 | } |
| 2419 | |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2420 | return true; |
| 2421 | } |
| 2422 | |
| 2423 | static bool |
| 2424 | intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo, |
| 2425 | struct intel_sdvo_connector *intel_sdvo_connector, |
| 2426 | struct intel_sdvo_enhancements_reply enhancements) |
| 2427 | { |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2428 | struct drm_device *dev = intel_sdvo->base.base.dev; |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2429 | struct drm_connector *connector = &intel_sdvo_connector->base.base; |
| 2430 | uint16_t response, data_value[2]; |
| 2431 | |
| 2432 | ENHANCEMENT(brightness, BRIGHTNESS); |
| 2433 | |
| 2434 | return true; |
| 2435 | } |
| 2436 | #undef ENHANCEMENT |
| 2437 | |
| 2438 | static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo, |
| 2439 | struct intel_sdvo_connector *intel_sdvo_connector) |
| 2440 | { |
| 2441 | union { |
| 2442 | struct intel_sdvo_enhancements_reply reply; |
| 2443 | uint16_t response; |
| 2444 | } enhancements; |
| 2445 | |
Chris Wilson | 1a3665c | 2011-01-25 13:59:37 +0000 | [diff] [blame] | 2446 | BUILD_BUG_ON(sizeof(enhancements) != 2); |
| 2447 | |
Chris Wilson | cf9a2f3 | 2010-09-23 16:17:33 +0100 | [diff] [blame] | 2448 | enhancements.response = 0; |
| 2449 | intel_sdvo_get_value(intel_sdvo, |
| 2450 | SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS, |
| 2451 | &enhancements, sizeof(enhancements)); |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2452 | if (enhancements.response == 0) { |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2453 | DRM_DEBUG_KMS("No enhancement is supported\n"); |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2454 | return true; |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2455 | } |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2456 | |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2457 | if (IS_TV(intel_sdvo_connector)) |
| 2458 | return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply); |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 2459 | else if (IS_LVDS(intel_sdvo_connector)) |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2460 | return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply); |
| 2461 | else |
| 2462 | return true; |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 2463 | } |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2464 | |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 2465 | static int intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter, |
| 2466 | struct i2c_msg *msgs, |
| 2467 | int num) |
| 2468 | { |
| 2469 | struct intel_sdvo *sdvo = adapter->algo_data; |
| 2470 | |
| 2471 | if (!intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus)) |
| 2472 | return -EIO; |
| 2473 | |
| 2474 | return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num); |
| 2475 | } |
| 2476 | |
| 2477 | static u32 intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter) |
| 2478 | { |
| 2479 | struct intel_sdvo *sdvo = adapter->algo_data; |
| 2480 | return sdvo->i2c->algo->functionality(sdvo->i2c); |
| 2481 | } |
| 2482 | |
| 2483 | static const struct i2c_algorithm intel_sdvo_ddc_proxy = { |
| 2484 | .master_xfer = intel_sdvo_ddc_proxy_xfer, |
| 2485 | .functionality = intel_sdvo_ddc_proxy_func |
| 2486 | }; |
| 2487 | |
| 2488 | static bool |
| 2489 | intel_sdvo_init_ddc_proxy(struct intel_sdvo *sdvo, |
| 2490 | struct drm_device *dev) |
| 2491 | { |
| 2492 | sdvo->ddc.owner = THIS_MODULE; |
| 2493 | sdvo->ddc.class = I2C_CLASS_DDC; |
| 2494 | snprintf(sdvo->ddc.name, I2C_NAME_SIZE, "SDVO DDC proxy"); |
| 2495 | sdvo->ddc.dev.parent = &dev->pdev->dev; |
| 2496 | sdvo->ddc.algo_data = sdvo; |
| 2497 | sdvo->ddc.algo = &intel_sdvo_ddc_proxy; |
| 2498 | |
| 2499 | return i2c_add_adapter(&sdvo->ddc) == 0; |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2500 | } |
| 2501 | |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 2502 | bool intel_sdvo_init(struct drm_device *dev, int sdvo_reg) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2503 | { |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 2504 | struct drm_i915_private *dev_priv = dev->dev_private; |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 2505 | struct intel_encoder *intel_encoder; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2506 | struct intel_sdvo *intel_sdvo; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2507 | int i; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2508 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2509 | intel_sdvo = kzalloc(sizeof(struct intel_sdvo), GFP_KERNEL); |
| 2510 | if (!intel_sdvo) |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 2511 | return false; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2512 | |
Chris Wilson | 56184e3 | 2011-05-17 14:03:50 +0100 | [diff] [blame] | 2513 | intel_sdvo->sdvo_reg = sdvo_reg; |
| 2514 | intel_sdvo->slave_addr = intel_sdvo_get_slave_addr(dev, sdvo_reg) >> 1; |
| 2515 | intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo, sdvo_reg); |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 2516 | if (!intel_sdvo_init_ddc_proxy(intel_sdvo, dev)) { |
| 2517 | kfree(intel_sdvo); |
| 2518 | return false; |
| 2519 | } |
| 2520 | |
Chris Wilson | 56184e3 | 2011-05-17 14:03:50 +0100 | [diff] [blame] | 2521 | /* encoder type will be decided later */ |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2522 | intel_encoder = &intel_sdvo->base; |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 2523 | intel_encoder->type = INTEL_OUTPUT_SDVO; |
Chris Wilson | 373a3cf | 2010-09-15 12:03:59 +0100 | [diff] [blame] | 2524 | drm_encoder_init(dev, &intel_encoder->base, &intel_sdvo_enc_funcs, 0); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2525 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2526 | /* Read the regs to test if we can talk to the device */ |
| 2527 | for (i = 0; i < 0x40; i++) { |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 2528 | u8 byte; |
| 2529 | |
| 2530 | if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) { |
Zhao Yakui | 8a4c47f | 2009-07-20 13:48:04 +0800 | [diff] [blame] | 2531 | DRM_DEBUG_KMS("No SDVO device found on SDVO%c\n", |
Zhao Yakui | 461ed3c | 2010-03-30 15:11:33 +0800 | [diff] [blame] | 2532 | IS_SDVOB(sdvo_reg) ? 'B' : 'C'); |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 2533 | goto err; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2534 | } |
| 2535 | } |
| 2536 | |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 2537 | if (IS_SDVOB(sdvo_reg)) |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 2538 | dev_priv->hotplug_supported_mask |= SDVOB_HOTPLUG_INT_STATUS; |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 2539 | else |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 2540 | dev_priv->hotplug_supported_mask |= SDVOC_HOTPLUG_INT_STATUS; |
Ma Ling | 619ac3b | 2009-05-18 16:12:46 +0800 | [diff] [blame] | 2541 | |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2542 | drm_encoder_helper_add(&intel_encoder->base, &intel_sdvo_helper_funcs); |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2543 | |
André Goddard Rosa | af901ca | 2009-11-14 13:09:05 -0200 | [diff] [blame] | 2544 | /* In default case sdvo lvds is false */ |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2545 | if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps)) |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 2546 | goto err; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2547 | |
Simon Farnsworth | cc68c81 | 2011-09-21 17:13:30 +0100 | [diff] [blame] | 2548 | /* Set up hotplug command - note paranoia about contents of reply. |
| 2549 | * We assume that the hardware is in a sane state, and only touch |
| 2550 | * the bits we think we understand. |
| 2551 | */ |
| 2552 | intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_ACTIVE_HOT_PLUG, |
| 2553 | &intel_sdvo->hotplug_active, 2); |
| 2554 | intel_sdvo->hotplug_active[0] &= ~0x3; |
| 2555 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2556 | if (intel_sdvo_output_setup(intel_sdvo, |
| 2557 | intel_sdvo->caps.output_flags) != true) { |
Dave Airlie | 51c8b40 | 2009-08-20 13:38:04 +1000 | [diff] [blame] | 2558 | DRM_DEBUG_KMS("SDVO output failed to setup on SDVO%c\n", |
Zhao Yakui | 461ed3c | 2010-03-30 15:11:33 +0800 | [diff] [blame] | 2559 | IS_SDVOB(sdvo_reg) ? 'B' : 'C'); |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 2560 | goto err; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2561 | } |
| 2562 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2563 | intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo, sdvo_reg); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 2564 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2565 | /* Set the input timing to the screen. Assume always input 0. */ |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2566 | if (!intel_sdvo_set_target_input(intel_sdvo)) |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 2567 | goto err; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2568 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2569 | if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo, |
| 2570 | &intel_sdvo->pixel_clock_min, |
| 2571 | &intel_sdvo->pixel_clock_max)) |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 2572 | goto err; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2573 | |
Zhao Yakui | 8a4c47f | 2009-07-20 13:48:04 +0800 | [diff] [blame] | 2574 | DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, " |
yakui_zhao | 342dc38 | 2009-06-02 14:12:00 +0800 | [diff] [blame] | 2575 | "clock range %dMHz - %dMHz, " |
| 2576 | "input 1: %c, input 2: %c, " |
| 2577 | "output 1: %c, output 2: %c\n", |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2578 | SDVO_NAME(intel_sdvo), |
| 2579 | intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id, |
| 2580 | intel_sdvo->caps.device_rev_id, |
| 2581 | intel_sdvo->pixel_clock_min / 1000, |
| 2582 | intel_sdvo->pixel_clock_max / 1000, |
| 2583 | (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N', |
| 2584 | (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N', |
yakui_zhao | 342dc38 | 2009-06-02 14:12:00 +0800 | [diff] [blame] | 2585 | /* check currently supported outputs */ |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2586 | intel_sdvo->caps.output_flags & |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2587 | (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N', |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2588 | intel_sdvo->caps.output_flags & |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2589 | (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N'); |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 2590 | return true; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2591 | |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 2592 | err: |
Chris Wilson | 373a3cf | 2010-09-15 12:03:59 +0100 | [diff] [blame] | 2593 | drm_encoder_cleanup(&intel_encoder->base); |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 2594 | i2c_del_adapter(&intel_sdvo->ddc); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2595 | kfree(intel_sdvo); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2596 | |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 2597 | return false; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2598 | } |