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gerrit-public.fairphone.software / kernel / msm-4.9 / 52a580f92b98ef21e50fb75ff33be090aeeb331a / . / arch / arm64 / boot / dts / qcom / sdm670-sde-display.dtsi
blob: 328df8f90b14f7e0894b2dc3816fb1389d108695 [file] [log] [blame]
Raviteja Tamatame97849a2017-09-12 20:25:50 +0530[diff] [blame]1/* Copyright (c) 2017, The Linux Foundation. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#include "dsi-panel-sim-video.dtsi"
14#include "dsi-panel-sim-cmd.dtsi"
15#include "dsi-panel-sim-dsc375-cmd.dtsi"
16#include "dsi-panel-sim-dualmipi-video.dtsi"
17#include "dsi-panel-sim-dualmipi-cmd.dtsi"
18#include "dsi-panel-sim-dualmipi-dsc375-cmd.dtsi"
19#include "dsi-panel-nt35597-truly-dualmipi-wqxga-video.dtsi"
20#include "dsi-panel-nt35597-truly-dualmipi-wqxga-cmd.dtsi"
21#include "dsi-panel-nt35597-truly-dsc-wqxga-cmd.dtsi"
22#include "dsi-panel-nt35597-truly-dsc-wqxga-video.dtsi"
Rashi Bindra5f52b4e2017-09-26 18:17:06 +0530[diff] [blame]23#include "dsi-panel-nt35597-dualmipi-wqxga-video.dtsi"
24#include "dsi-panel-nt35597-dualmipi-wqxga-cmd.dtsi"
25#include "dsi-panel-nt35695b-truly-fhd-video.dtsi"
26#include "dsi-panel-nt35695b-truly-fhd-cmd.dtsi"
27#include "dsi-panel-rm67195-amoled-fhd-cmd.dtsi"
Raviteja Tamatame97849a2017-09-12 20:25:50 +0530[diff] [blame]28#include <dt-bindings/clock/mdss-10nm-pll-clk.h>
29
30&soc {
31 dsi_panel_pwr_supply: dsi_panel_pwr_supply {
32 #address-cells = <1>;
33 #size-cells = <0>;
34
35 qcom,panel-supply-entry@0 {
36 reg = <0>;
37 qcom,supply-name = "vddio";
38 qcom,supply-min-voltage = <1800000>;
39 qcom,supply-max-voltage = <1800000>;
40 qcom,supply-enable-load = <62000>;
41 qcom,supply-disable-load = <80>;
42 qcom,supply-post-on-sleep = <20>;
43 };
44
45 qcom,panel-supply-entry@1 {
46 reg = <1>;
47 qcom,supply-name = "lab";
48 qcom,supply-min-voltage = <4600000>;
49 qcom,supply-max-voltage = <6000000>;
50 qcom,supply-enable-load = <100000>;
51 qcom,supply-disable-load = <100>;
52 };
53
54 qcom,panel-supply-entry@2 {
55 reg = <2>;
56 qcom,supply-name = "ibb";
57 qcom,supply-min-voltage = <4600000>;
58 qcom,supply-max-voltage = <6000000>;
59 qcom,supply-enable-load = <100000>;
60 qcom,supply-disable-load = <100>;
61 qcom,supply-post-on-sleep = <20>;
62 };
63 };
64
65 dsi_panel_pwr_supply_no_labibb: dsi_panel_pwr_supply_no_labibb {
66 #address-cells = <1>;
67 #size-cells = <0>;
68
69 qcom,panel-supply-entry@0 {
70 reg = <0>;
71 qcom,supply-name = "vddio";
72 qcom,supply-min-voltage = <1800000>;
73 qcom,supply-max-voltage = <1800000>;
74 qcom,supply-enable-load = <62000>;
75 qcom,supply-disable-load = <80>;
76 qcom,supply-post-on-sleep = <20>;
77 };
78 };
79
80 dsi_panel_pwr_supply_vdd_no_labibb: dsi_panel_pwr_supply_vdd_no_labibb {
81 #address-cells = <1>;
82 #size-cells = <0>;
83
84 qcom,panel-supply-entry@0 {
85 reg = <0>;
86 qcom,supply-name = "vddio";
87 qcom,supply-min-voltage = <1800000>;
88 qcom,supply-max-voltage = <1800000>;
89 qcom,supply-enable-load = <62000>;
90 qcom,supply-disable-load = <80>;
91 qcom,supply-post-on-sleep = <20>;
92 };
93
94 qcom,panel-supply-entry@1 {
95 reg = <1>;
96 qcom,supply-name = "vdd";
97 qcom,supply-min-voltage = <3000000>;
98 qcom,supply-max-voltage = <3000000>;
99 qcom,supply-enable-load = <857000>;
100 qcom,supply-disable-load = <0>;
101 qcom,supply-post-on-sleep = <0>;
102 };
103 };
104
Rashi Bindra5f52b4e2017-09-26 18:17:06 +0530[diff] [blame]105 dsi_panel_pwr_supply_labibb_amoled: dsi_panel_pwr_supply_labibb_amoled {
106 #address-cells = <1>;
107 #size-cells = <0>;
108
109 qcom,panel-supply-entry@0 {
110 reg = <0>;
111 qcom,supply-name = "wqhd-vddio";
112 qcom,supply-min-voltage = <1800000>;
113 qcom,supply-max-voltage = <1950000>;
114 qcom,supply-enable-load = <32000>;
115 qcom,supply-disable-load = <80>;
116 };
117
118 qcom,panel-supply-entry@1 {
119 reg = <1>;
120 qcom,supply-name = "vdda-3p3";
121 qcom,supply-min-voltage = <3300000>;
122 qcom,supply-max-voltage = <3300000>;
123 qcom,supply-enable-load = <13200>;
124 qcom,supply-disable-load = <80>;
125 };
126
127 qcom,panel-supply-entry@2 {
128 reg = <2>;
129 qcom,supply-name = "lab";
130 qcom,supply-min-voltage = <4600000>;
131 qcom,supply-max-voltage = <6100000>;
132 qcom,supply-enable-load = <100000>;
133 qcom,supply-disable-load = <100>;
134 };
135
136 qcom,panel-supply-entry@3 {
137 reg = <3>;
138 qcom,supply-name = "ibb";
139 qcom,supply-min-voltage = <4000000>;
140 qcom,supply-max-voltage = <6300000>;
141 qcom,supply-enable-load = <100000>;
142 qcom,supply-disable-load = <100>;
143 };
144
145 qcom,panel-supply-entry@4 {
146 reg = <4>;
147 qcom,supply-name = "oledb";
148 qcom,supply-min-voltage = <5000000>;
149 qcom,supply-max-voltage = <8100000>;
150 qcom,supply-enable-load = <100000>;
151 qcom,supply-disable-load = <100>;
152 };
153 };
154
Raviteja Tamatame97849a2017-09-12 20:25:50 +0530[diff] [blame]155 dsi_dual_nt35597_truly_video_display: qcom,dsi-display@0 {
156 compatible = "qcom,dsi-display";
157 label = "dsi_dual_nt35597_truly_video_display";
158 qcom,display-type = "primary";
159
160 qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
161 qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
162 clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
163 <&mdss_dsi0_pll PCLK_MUX_0_CLK>;
164 clock-names = "src_byte_clk", "src_pixel_clk";
165
166 pinctrl-names = "panel_active", "panel_suspend";
167 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
168 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
169 qcom,platform-reset-gpio = <&tlmm 75 0>;
170 qcom,panel-mode-gpio = <&tlmm 76 0>;
171
172 qcom,dsi-panel = <&dsi_dual_nt35597_truly_video>;
173 vddio-supply = <&pm660_l11>;
174 lab-supply = <&lcdb_ldo_vreg>;
175 ibb-supply = <&lcdb_ncp_vreg>;
176 };
177
178 dsi_dual_nt35597_truly_cmd_display: qcom,dsi-display@1 {
179 compatible = "qcom,dsi-display";
180 label = "dsi_dual_nt35597_truly_cmd_display";
181 qcom,display-type = "primary";
182
183 qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
184 qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
185 clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
186 <&mdss_dsi0_pll PCLK_MUX_0_CLK>;
187 clock-names = "src_byte_clk", "src_pixel_clk";
188
189 pinctrl-names = "panel_active", "panel_suspend";
190 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
191 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
192 qcom,platform-te-gpio = <&tlmm 10 0>;
193 qcom,platform-reset-gpio = <&tlmm 75 0>;
194 qcom,panel-mode-gpio = <&tlmm 76 0>;
195
196 qcom,dsi-panel = <&dsi_dual_nt35597_truly_cmd>;
197 vddio-supply = <&pm660_l11>;
198 lab-supply = <&lcdb_ldo_vreg>;
199 ibb-supply = <&lcdb_ncp_vreg>;
200 };
201
202 dsi_nt35597_truly_dsc_cmd_display: qcom,dsi-display@2 {
203 compatible = "qcom,dsi-display";
204 label = "dsi_nt35597_truly_dsc_cmd_display";
205 qcom,display-type = "primary";
206
207 qcom,dsi-ctrl = <&mdss_dsi1>;
208 qcom,dsi-phy = <&mdss_dsi_phy1>;
209 clocks = <&mdss_dsi1_pll BYTECLK_MUX_1_CLK>,
210 <&mdss_dsi1_pll PCLK_MUX_1_CLK>;
211 clock-names = "src_byte_clk", "src_pixel_clk";
212
213 pinctrl-names = "panel_active", "panel_suspend";
214 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
215 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
216 qcom,platform-te-gpio = <&tlmm 10 0>;
217 qcom,platform-reset-gpio = <&tlmm 75 0>;
218 qcom,panel-mode-gpio = <&tlmm 76 0>;
219
220 qcom,dsi-panel = <&dsi_nt35597_truly_dsc_cmd>;
221 vddio-supply = <&pm660_l11>;
222 lab-supply = <&lcdb_ldo_vreg>;
223 ibb-supply = <&lcdb_ncp_vreg>;
224 };
225
226 dsi_nt35597_truly_dsc_video_display: qcom,dsi-display@3 {
227 compatible = "qcom,dsi-display";
228 label = "dsi_nt35597_truly_dsc_video_display";
229 qcom,display-type = "primary";
230
231 qcom,dsi-ctrl = <&mdss_dsi1>;
232 qcom,dsi-phy = <&mdss_dsi_phy1>;
233 clocks = <&mdss_dsi1_pll BYTECLK_MUX_1_CLK>,
234 <&mdss_dsi1_pll PCLK_MUX_1_CLK>;
235 clock-names = "src_byte_clk", "src_pixel_clk";
236
237 pinctrl-names = "panel_active", "panel_suspend";
238 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
239 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
240 qcom,platform-te-gpio = <&tlmm 10 0>;
241 qcom,platform-reset-gpio = <&tlmm 75 0>;
242 qcom,panel-mode-gpio = <&tlmm 76 0>;
243
244 qcom,dsi-panel = <&dsi_nt35597_truly_dsc_video>;
245 vddio-supply = <&pm660_l11>;
246 lab-supply = <&lcdb_ldo_vreg>;
247 ibb-supply = <&lcdb_ncp_vreg>;
248 };
249
250 dsi_sim_vid_display: qcom,dsi-display@4 {
251 compatible = "qcom,dsi-display";
252 label = "dsi_sim_vid_display";
253 qcom,display-type = "primary";
254
255 qcom,dsi-ctrl = <&mdss_dsi0>;
256 qcom,dsi-phy = <&mdss_dsi_phy0>;
257 clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
258 <&mdss_dsi0_pll PCLK_MUX_0_CLK>;
259 clock-names = "src_byte_clk", "src_pixel_clk";
260
261 pinctrl-names = "panel_active", "panel_suspend";
262 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
263 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
264
265 qcom,dsi-panel = <&dsi_sim_vid>;
266 };
267
268 dsi_dual_sim_vid_display: qcom,dsi-display@5 {
269 compatible = "qcom,dsi-display";
270 label = "dsi_dual_sim_vid_display";
271 qcom,display-type = "primary";
272
273 qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
274 qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
275 clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
276 <&mdss_dsi0_pll PCLK_MUX_0_CLK>;
277 clock-names = "src_byte_clk", "src_pixel_clk";
278
279 pinctrl-names = "panel_active", "panel_suspend";
280 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
281 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
282
283 qcom,dsi-panel = <&dsi_dual_sim_vid>;
284 };
285
286 dsi_sim_cmd_display: qcom,dsi-display@6 {
287 compatible = "qcom,dsi-display";
288 label = "dsi_sim_cmd_display";
289 qcom,display-type = "primary";
290
291 qcom,dsi-ctrl = <&mdss_dsi0>;
292 qcom,dsi-phy = <&mdss_dsi_phy0>;
293 clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
294 <&mdss_dsi0_pll PCLK_MUX_0_CLK>;
295 clock-names = "src_byte_clk", "src_pixel_clk";
296
297 pinctrl-names = "panel_active", "panel_suspend";
298 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
299 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
300
301 qcom,dsi-panel = <&dsi_sim_cmd>;
302 };
303
304 dsi_dual_sim_cmd_display: qcom,dsi-display@7 {
305 compatible = "qcom,dsi-display";
306 label = "dsi_dual_sim_cmd_display";
307 qcom,display-type = "primary";
308
309 qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
310 qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
311 clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
312 <&mdss_dsi0_pll PCLK_MUX_0_CLK>;
313 clock-names = "src_byte_clk", "src_pixel_clk";
314
315 pinctrl-names = "panel_active", "panel_suspend";
316 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
317 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
318
319 qcom,dsi-panel = <&dsi_dual_sim_cmd>;
320 };
321
322 dsi_sim_dsc_375_cmd_display: qcom,dsi-display@8 {
323 compatible = "qcom,dsi-display";
324 label = "dsi_sim_dsc_375_cmd_display";
325 qcom,display-type = "primary";
326
327 qcom,dsi-ctrl = <&mdss_dsi0>;
328 qcom,dsi-phy = <&mdss_dsi_phy0>;
329 clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
330 <&mdss_dsi0_pll PCLK_MUX_0_CLK>;
331 clock-names = "src_byte_clk", "src_pixel_clk";
332
333 pinctrl-names = "panel_active", "panel_suspend";
334 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
335 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
336
337 qcom,dsi-panel = <&dsi_sim_dsc_375_cmd>;
338 };
339
340 dsi_dual_sim_dsc_375_cmd_display: qcom,dsi-display@9 {
341 compatible = "qcom,dsi-display";
342 label = "dsi_dual_sim_dsc_375_cmd_display";
343 qcom,display-type = "primary";
344
345 qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
346 qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
347 clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
348 <&mdss_dsi0_pll PCLK_MUX_0_CLK>;
349 clock-names = "src_byte_clk", "src_pixel_clk";
350
351 pinctrl-names = "panel_active", "panel_suspend";
352 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
353 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
354
355 qcom,dsi-panel = <&dsi_dual_sim_dsc_375_cmd>;
356 };
357
Rashi Bindra5f52b4e2017-09-26 18:17:06 +0530[diff] [blame]358 dsi_dual_nt35597_video_display: qcom,dsi-display@10 {
359 compatible = "qcom,dsi-display";
360 label = "dsi_dual_nt35597_video_display";
361 qcom,display-type = "primary";
362
363 qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
364 qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
365 clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
366 <&mdss_dsi0_pll PCLK_MUX_0_CLK>;
367 clock-names = "src_byte_clk", "src_pixel_clk";
368
369 pinctrl-names = "panel_active", "panel_suspend";
370 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
371 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
372 qcom,platform-reset-gpio = <&tlmm 75 0>;
373 qcom,panel-mode-gpio = <&tlmm 76 0>;
374
375 qcom,dsi-panel = <&dsi_dual_nt35597_video>;
376 vddio-supply = <&pm660_l11>;
377 lab-supply = <&lcdb_ldo_vreg>;
378 ibb-supply = <&lcdb_ncp_vreg>;
379 };
380
381 dsi_dual_nt35597_cmd_display: qcom,dsi-display@11 {
382 compatible = "qcom,dsi-display";
383 label = "dsi_dual_nt35597_cmd_display";
384 qcom,display-type = "primary";
385
386 qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
387 qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
388 clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
389 <&mdss_dsi0_pll PCLK_MUX_0_CLK>;
390 clock-names = "src_byte_clk", "src_pixel_clk";
391
392 pinctrl-names = "panel_active", "panel_suspend";
393 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
394 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
395 qcom,platform-reset-gpio = <&tlmm 75 0>;
396 qcom,panel-mode-gpio = <&tlmm 76 0>;
397
398 qcom,dsi-panel = <&dsi_dual_nt35597_cmd>;
399 vddio-supply = <&pm660_l11>;
400 lab-supply = <&lcdb_ldo_vreg>;
401 ibb-supply = <&lcdb_ncp_vreg>;
402 };
403
404 dsi_rm67195_amoled_fhd_cmd_display: qcom,dsi-display@12 {
405 compatible = "qcom,dsi-display";
406 label = "dsi_rm67195_amoled_fhd_cmd_display";
407 qcom,display-type = "primary";
408
409 qcom,dsi-ctrl = <&mdss_dsi0>;
410 qcom,dsi-phy = <&mdss_dsi_phy0>;
411 clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
412 <&mdss_dsi0_pll PCLK_MUX_0_CLK>;
413 clock-names = "src_byte_clk", "src_pixel_clk";
414
415 pinctrl-names = "panel_active", "panel_suspend";
416 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
417 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
418 qcom,platform-te-gpio = <&tlmm 10 0>;
419 qcom,platform-reset-gpio = <&tlmm 75 0>;
420
421 qcom,dsi-panel = <&dsi_rm67195_amoled_fhd_cmd>;
422 vddio-supply = <&pm660_l11>;
423 lab-supply = <&lcdb_ldo_vreg>;
424 ibb-supply = <&lcdb_ncp_vreg>;
425 };
426
427 dsi_nt35695b_truly_fhd_video_display: qcom,dsi-display@13 {
428 compatible = "qcom,dsi-display";
429 label = "dsi_nt35695b_truly_fhd_video_display";
430 qcom,display-type = "primary";
431
432 qcom,dsi-ctrl = <&mdss_dsi0>;
433 qcom,dsi-phy = <&mdss_dsi_phy0>;
434 clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
435 <&mdss_dsi0_pll PCLK_MUX_0_CLK>;
436 clock-names = "src_byte_clk", "src_pixel_clk";
437
438 pinctrl-names = "panel_active", "panel_suspend";
439 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
440 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
441 qcom,platform-reset-gpio = <&tlmm 75 0>;
442
443 qcom,dsi-panel = <&dsi_nt35695b_truly_fhd_video>;
444 vddio-supply = <&pm660_l11>;
445 lab-supply = <&lcdb_ldo_vreg>;
446 ibb-supply = <&lcdb_ncp_vreg>;
447 };
448
449 dsi_nt35695b_truly_fhd_cmd_display: qcom,dsi-display@14 {
450 compatible = "qcom,dsi-display";
451 label = "dsi_nt35695b_truly_fhd_cmd_display";
452 qcom,display-type = "primary";
453
454 qcom,dsi-ctrl = <&mdss_dsi0>;
455 qcom,dsi-phy = <&mdss_dsi_phy0>;
456 clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
457 <&mdss_dsi0_pll PCLK_MUX_0_CLK>;
458 clock-names = "src_byte_clk", "src_pixel_clk";
459
460 pinctrl-names = "panel_active", "panel_suspend";
461 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
462 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
463 qcom,platform-te-gpio = <&tlmm 10 0>;
464 qcom,platform-reset-gpio = <&tlmm 75 0>;
465
466 qcom,dsi-panel = <&dsi_nt35695b_truly_fhd_cmd>;
467 vddio-supply = <&pm660_l11>;
468 lab-supply = <&lcdb_ldo_vreg>;
469 ibb-supply = <&lcdb_ncp_vreg>;
470 };
471
Raviteja Tamatame97849a2017-09-12 20:25:50 +0530[diff] [blame]472 sde_wb: qcom,wb-display@0 {
473 compatible = "qcom,wb-display";
474 cell-index = <0>;
475 label = "wb_display";
476 };
477
478 ext_disp: qcom,msm-ext-disp {
479 compatible = "qcom,msm-ext-disp";
Raviteja Tamatame97849a2017-09-12 20:25:50 +0530[diff] [blame]480
481 ext_disp_audio_codec: qcom,msm-ext-disp-audio-codec-rx {
482 compatible = "qcom,msm-ext-disp-audio-codec-rx";
483 };
484 };
Raviteja Tamatame97849a2017-09-12 20:25:50 +0530[diff] [blame]485};
486
487&sde_dp {
Padmanabhan Komanduruf3838e42017-10-20 12:50:47 +0530[diff] [blame]488 qcom,dp-usbpd-detection = <&pm660_pdphy>;
489 qcom,ext-disp = <&ext_disp>;
490
Raviteja Tamatame97849a2017-09-12 20:25:50 +0530[diff] [blame]491 pinctrl-names = "mdss_dp_active", "mdss_dp_sleep";
492 pinctrl-0 = <&sde_dp_aux_active &sde_dp_usbplug_cc_active>;
493 pinctrl-1 = <&sde_dp_aux_suspend &sde_dp_usbplug_cc_suspend>;
494 qcom,aux-en-gpio = <&tlmm 50 0>;
495 qcom,aux-sel-gpio = <&tlmm 40 0>;
496 qcom,usbplug-cc-gpio = <&tlmm 38 0>;
497};
498
499&mdss_mdp {
Padmanabhan Komandurud03f38f2017-10-10 15:34:41 +0530[diff] [blame]500 connectors = <&sde_rscc &sde_wb &sde_dp>;
Raviteja Tamatame97849a2017-09-12 20:25:50 +0530[diff] [blame]501};
502
503&dsi_dual_nt35597_truly_video {
504 qcom,mdss-dsi-t-clk-post = <0x0D>;
505 qcom,mdss-dsi-t-clk-pre = <0x2D>;
Raviteja Tamatam52a580f2017-10-31 11:29:06 +0530[diff] [blame^]506 qcom,mdss-dsi-min-refresh-rate = <53>;
507 qcom,mdss-dsi-max-refresh-rate = <60>;
508 qcom,mdss-dsi-pan-enable-dynamic-fps;
509 qcom,mdss-dsi-pan-fps-update =
510 "dfps_immediate_porch_mode_vfp";
Raviteja Tamatame97849a2017-09-12 20:25:50 +0530[diff] [blame]511 qcom,mdss-dsi-display-timings {
512 timing@0{
513 qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 23 21 07
514 07 05 03 04 00];
515 qcom,display-topology = <2 0 2>,
516 <1 0 2>;
517 qcom,default-topology-index = <0>;
518 };
519 };
520};
521
522&dsi_dual_nt35597_truly_cmd {
523 qcom,mdss-dsi-t-clk-post = <0x0D>;
524 qcom,mdss-dsi-t-clk-pre = <0x2D>;
525 qcom,mdss-dsi-display-timings {
526 timing@0{
527 qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 23 21 07
528 07 05 03 04 00];
529 qcom,display-topology = <2 0 2>,
530 <1 0 2>;
531 qcom,default-topology-index = <0>;
532 };
533 };
534};
535
536&dsi_nt35597_truly_dsc_cmd {
537 qcom,mdss-dsi-t-clk-post = <0x0b>;
538 qcom,mdss-dsi-t-clk-pre = <0x23>;
539 qcom,mdss-dsi-display-timings {
540 timing@0{
541 qcom,mdss-dsi-panel-phy-timings = [00 15 05 05 20 1f 05
542 05 03 03 04 00];
543 qcom,display-topology = <1 1 1>,
544 <2 2 1>, /* dsc merge */
545 <2 1 1>; /* 3d mux */
546 qcom,default-topology-index = <1>;
547 };
548 };
549};
550
551&dsi_nt35597_truly_dsc_video {
552 qcom,mdss-dsi-t-clk-post = <0x0b>;
553 qcom,mdss-dsi-t-clk-pre = <0x23>;
Raviteja Tamatam52a580f2017-10-31 11:29:06 +0530[diff] [blame^]554 qcom,mdss-dsi-min-refresh-rate = <53>;
555 qcom,mdss-dsi-max-refresh-rate = <60>;
556 qcom,mdss-dsi-pan-enable-dynamic-fps;
557 qcom,mdss-dsi-pan-fps-update =
558 "dfps_immediate_porch_mode_vfp";
Raviteja Tamatame97849a2017-09-12 20:25:50 +0530[diff] [blame]559 qcom,mdss-dsi-display-timings {
560 timing@0{
561 qcom,mdss-dsi-panel-phy-timings = [00 15 05 05 20 1f 05
562 04 03 03 04 00];
563 qcom,display-topology = <1 1 1>,
564 <2 2 1>, /* dsc merge */
565 <2 1 1>; /* 3d mux */
566 qcom,default-topology-index = <1>;
567 };
568 };
569};
570
571&dsi_sim_vid {
572 qcom,mdss-dsi-t-clk-post = <0x0d>;
573 qcom,mdss-dsi-t-clk-pre = <0x2d>;
574 qcom,mdss-dsi-display-timings {
575 timing@0{
576 qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 23 21 07
577 07 05 03 04 00];
578 qcom,display-topology = <1 0 1>,
579 <2 0 1>;
580 qcom,default-topology-index = <0>;
581 };
582 };
583};
584
585&dsi_dual_sim_vid {
586 qcom,mdss-dsi-t-clk-post = <0x0d>;
587 qcom,mdss-dsi-t-clk-pre = <0x2d>;
588 qcom,mdss-dsi-display-timings {
589 timing@0{
590 qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 23 21 07
591 07 05 03 04 00];
592 qcom,display-topology = <2 0 2>,
593 <1 0 2>;
594 qcom,default-topology-index = <0>;
595 };
596 };
597};
598
599&dsi_sim_cmd {
600 qcom,mdss-dsi-t-clk-post = <0x0d>;
601 qcom,mdss-dsi-t-clk-pre = <0x2d>;
602 qcom,mdss-dsi-display-timings {
603 timing@0{
604 qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 23 21 07
605 07 05 03 04 00];
606 qcom,display-topology = <1 0 1>,
607 <2 0 1>;
608 qcom,default-topology-index = <0>;
609 };
610 };
611};
612
613&dsi_dual_sim_cmd {
614 qcom,mdss-dsi-t-clk-post = <0x0d>;
615 qcom,mdss-dsi-t-clk-pre = <0x2d>;
616 qcom,mdss-dsi-display-timings {
617 timing@0{
618 qcom,mdss-dsi-panel-phy-timings = [00 24 09 09 26 24 09
619 09 06 03 04 00];
620 qcom,display-topology = <2 0 2>;
621 qcom,default-topology-index = <0>;
622 };
623 timing@1{
624 qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 23 21 07
625 07 05 03 04 00];
626 qcom,display-topology = <2 0 2>,
627 <1 0 2>;
628 qcom,default-topology-index = <0>;
629 };
630 timing@2{
631 qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 21 20 06
632 06 04 03 04 00];
633 qcom,display-topology = <2 0 2>;
634 qcom,default-topology-index = <0>;
635 };
636 };
637};
638
639&dsi_sim_dsc_375_cmd {
640 qcom,mdss-dsi-t-clk-post = <0x0d>;
641 qcom,mdss-dsi-t-clk-pre = <0x2d>;
642 qcom,mdss-dsi-display-timings {
643 timing@0 { /* 1080p */
644 qcom,mdss-dsi-panel-phy-timings = [00 1A 06 06 22 20 07
645 07 04 03 04 00];
646 qcom,display-topology = <1 1 1>;
647 qcom,default-topology-index = <0>;
648 };
649 timing@1 { /* qhd */
650 qcom,mdss-dsi-panel-phy-timings = [00 15 05 05 20 1f 05
651 05 03 03 04 00];
652 qcom,display-topology = <1 1 1>,
653 <2 2 1>, /* dsc merge */
654 <2 1 1>; /* 3d mux */
655 qcom,default-topology-index = <0>;
656 };
657 };
658};
659
660&dsi_dual_sim_dsc_375_cmd {
661 qcom,mdss-dsi-t-clk-post = <0x0d>;
662 qcom,mdss-dsi-t-clk-pre = <0x2d>;
663 qcom,mdss-dsi-display-timings {
664 timing@0 { /* qhd */
665 qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 23 21 07
666 07 05 03 04 00];
667 qcom,display-topology = <2 2 2>;
668 qcom,default-topology-index = <0>;
669 };
670 timing@1 { /* 4k */
671 qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 21 20 06
672 06 04 03 04 00];
673 qcom,display-topology = <2 2 2>;
674 qcom,default-topology-index = <0>;
675 };
676 };
677};
Rashi Bindra5f52b4e2017-09-26 18:17:06 +0530[diff] [blame]678
679&dsi_dual_nt35597_video {
680 qcom,mdss-dsi-t-clk-post = <0x0d>;
681 qcom,mdss-dsi-t-clk-pre = <0x2d>;
682 qcom,mdss-dsi-display-timings {
683 timing@0 {
684 qcom,mdss-dsi-panel-timings = [00 1c 08 07 23 22 07 07
685 05 03 04 00];
686 qcom,display-topology = <2 0 2>,
687 <1 0 2>;
688 qcom,default-topology-index = <0>;
689 };
690 };
691};
692
693&dsi_dual_nt35597_cmd {
694 qcom,mdss-dsi-t-clk-post = <0x0d>;
695 qcom,mdss-dsi-t-clk-pre = <0x2d>;
696 qcom,mdss-dsi-display-timings {
697 timing@0 {
698 qcom,mdss-dsi-panel-timings = [00 1c 08 07 23 22 07 07
699 05 03 04 00];
700 qcom,display-topology = <2 0 2>,
701 <1 0 2>;
702 qcom,default-topology-index = <0>;
703 };
704 };
705};
706
707&dsi_rm67195_amoled_fhd_cmd {
708 qcom,mdss-dsi-t-clk-post = <0x07>;
709 qcom,mdss-dsi-t-clk-pre = <0x1c>;
710 qcom,mdss-dsi-display-timings {
711 timing@0 {
712 qcom,mdss-dsi-panel-phy-timings = [00 1c 05 06 0b 0c
713 05 07 05 03 04 00];
714 qcom,display-topology = <1 0 1>;
715 qcom,default-topology-index = <0>;
716 };
717 };
718};
719
720&dsi_nt35695b_truly_fhd_video {
721 qcom,mdss-dsi-t-clk-post = <0x07>;
722 qcom,mdss-dsi-t-clk-pre = <0x1c>;
723 qcom,mdss-dsi-display-timings {
724 timing@0 {
725 qcom,mdss-dsi-panel-phy-timings = [00 1c 05 06 0b 0c
726 05 07 05 03 04 00];
727 qcom,display-topology = <1 0 1>;
728 qcom,default-topology-index = <0>;
729 };
730 };
731};
732
733&dsi_nt35695b_truly_fhd_cmd {
734 qcom,mdss-dsi-t-clk-post = <0x07>;
735 qcom,mdss-dsi-t-clk-pre = <0x1c>;
736 qcom,mdss-dsi-display-timings {
737 timing@0 {
738 qcom,mdss-dsi-panel-phy-timings = [00 1c 05 06 0b 0c
739 05 07 05 03 04 00];
740 qcom,display-topology = <1 0 1>;
741 qcom,default-topology-index = <0>;
742 };
743 };
744};