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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * This program is free software; you can redistribute it and/or
3 * modify it under the terms of the GNU General Public License
4 * as published by the Free Software Foundation; either version
5 * 2 of the License, or (at your option) any later version.
6 *
7 * (c) Copyright 1998 Alan Cox <alan@lxorguk.ukuu.org.uk>
8 * (c) Copyright 2000, 2001 Red Hat Inc
9 *
10 * Development of this driver was funded by Equiinet Ltd
11 * http://www.equiinet.com
12 *
13 * ChangeLog:
14 *
15 * Asynchronous mode dropped for 2.2. For 2.5 we will attempt the
16 * unification of all the Z85x30 asynchronous drivers for real.
17 *
18 * DMA now uses get_free_page as kmalloc buffers may span a 64K
19 * boundary.
20 *
21 * Modified for SMP safety and SMP locking by Alan Cox <alan@redhat.com>
22 *
23 * Performance
24 *
25 * Z85230:
26 * Non DMA you want a 486DX50 or better to do 64Kbits. 9600 baud
27 * X.25 is not unrealistic on all machines. DMA mode can in theory
28 * handle T1/E1 quite nicely. In practice the limit seems to be about
29 * 512Kbit->1Mbit depending on motherboard.
30 *
31 * Z85C30:
32 * 64K will take DMA, 9600 baud X.25 should be ok.
33 *
34 * Z8530:
35 * Synchronous mode without DMA is unlikely to pass about 2400 baud.
36 */
37
38#include <linux/module.h>
39#include <linux/kernel.h>
40#include <linux/mm.h>
41#include <linux/net.h>
42#include <linux/skbuff.h>
43#include <linux/netdevice.h>
44#include <linux/if_arp.h>
45#include <linux/delay.h>
Krzysztof Hałasa52e8a6a2008-07-02 17:47:52 +020046#include <linux/hdlc.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070047#include <linux/ioport.h>
48#include <linux/init.h>
49#include <asm/dma.h>
50#include <asm/io.h>
51#define RT_LOCK
52#define RT_UNLOCK
53#include <linux/spinlock.h>
54
Linus Torvalds1da177e2005-04-16 15:20:36 -070055#include "z85230.h"
56
57
58/**
59 * z8530_read_port - Architecture specific interface function
60 * @p: port to read
61 *
62 * Provided port access methods. The Comtrol SV11 requires no delays
63 * between accesses and uses PC I/O. Some drivers may need a 5uS delay
64 *
65 * In the longer term this should become an architecture specific
66 * section so that this can become a generic driver interface for all
67 * platforms. For now we only handle PC I/O ports with or without the
68 * dread 5uS sanity delay.
69 *
70 * The caller must hold sufficient locks to avoid violating the horrible
71 * 5uS delay rule.
72 */
73
74static inline int z8530_read_port(unsigned long p)
75{
76 u8 r=inb(Z8530_PORT_OF(p));
77 if(p&Z8530_PORT_SLEEP) /* gcc should figure this out efficiently ! */
78 udelay(5);
79 return r;
80}
81
82/**
83 * z8530_write_port - Architecture specific interface function
84 * @p: port to write
85 * @d: value to write
86 *
87 * Write a value to a port with delays if need be. Note that the
88 * caller must hold locks to avoid read/writes from other contexts
89 * violating the 5uS rule
90 *
91 * In the longer term this should become an architecture specific
92 * section so that this can become a generic driver interface for all
93 * platforms. For now we only handle PC I/O ports with or without the
94 * dread 5uS sanity delay.
95 */
96
97
98static inline void z8530_write_port(unsigned long p, u8 d)
99{
100 outb(d,Z8530_PORT_OF(p));
101 if(p&Z8530_PORT_SLEEP)
102 udelay(5);
103}
104
105
106
107static void z8530_rx_done(struct z8530_channel *c);
108static void z8530_tx_done(struct z8530_channel *c);
109
110
111/**
112 * read_zsreg - Read a register from a Z85230
113 * @c: Z8530 channel to read from (2 per chip)
114 * @reg: Register to read
115 * FIXME: Use a spinlock.
116 *
117 * Most of the Z8530 registers are indexed off the control registers.
118 * A read is done by writing to the control register and reading the
119 * register back. The caller must hold the lock
120 */
121
122static inline u8 read_zsreg(struct z8530_channel *c, u8 reg)
123{
124 if(reg)
125 z8530_write_port(c->ctrlio, reg);
126 return z8530_read_port(c->ctrlio);
127}
128
129/**
130 * read_zsdata - Read the data port of a Z8530 channel
131 * @c: The Z8530 channel to read the data port from
132 *
133 * The data port provides fast access to some things. We still
134 * have all the 5uS delays to worry about.
135 */
136
137static inline u8 read_zsdata(struct z8530_channel *c)
138{
139 u8 r;
140 r=z8530_read_port(c->dataio);
141 return r;
142}
143
144/**
145 * write_zsreg - Write to a Z8530 channel register
146 * @c: The Z8530 channel
147 * @reg: Register number
148 * @val: Value to write
149 *
150 * Write a value to an indexed register. The caller must hold the lock
151 * to honour the irritating delay rules. We know about register 0
152 * being fast to access.
153 *
154 * Assumes c->lock is held.
155 */
156static inline void write_zsreg(struct z8530_channel *c, u8 reg, u8 val)
157{
158 if(reg)
159 z8530_write_port(c->ctrlio, reg);
160 z8530_write_port(c->ctrlio, val);
161
162}
163
164/**
165 * write_zsctrl - Write to a Z8530 control register
166 * @c: The Z8530 channel
167 * @val: Value to write
168 *
169 * Write directly to the control register on the Z8530
170 */
171
172static inline void write_zsctrl(struct z8530_channel *c, u8 val)
173{
174 z8530_write_port(c->ctrlio, val);
175}
176
177/**
178 * write_zsdata - Write to a Z8530 control register
179 * @c: The Z8530 channel
180 * @val: Value to write
181 *
182 * Write directly to the data register on the Z8530
183 */
184
185
186static inline void write_zsdata(struct z8530_channel *c, u8 val)
187{
188 z8530_write_port(c->dataio, val);
189}
190
191/*
192 * Register loading parameters for a dead port
193 */
194
195u8 z8530_dead_port[]=
196{
197 255
198};
199
200EXPORT_SYMBOL(z8530_dead_port);
201
202/*
203 * Register loading parameters for currently supported circuit types
204 */
205
206
207/*
208 * Data clocked by telco end. This is the correct data for the UK
209 * "kilostream" service, and most other similar services.
210 */
211
212u8 z8530_hdlc_kilostream[]=
213{
214 4, SYNC_ENAB|SDLC|X1CLK,
215 2, 0, /* No vector */
216 1, 0,
217 3, ENT_HM|RxCRC_ENAB|Rx8,
218 5, TxCRC_ENAB|RTS|TxENAB|Tx8|DTR,
219 9, 0, /* Disable interrupts */
220 6, 0xFF,
221 7, FLAG,
222 10, ABUNDER|NRZ|CRCPS,/*MARKIDLE ??*/
223 11, TCTRxCP,
224 14, DISDPLL,
225 15, DCDIE|SYNCIE|CTSIE|TxUIE|BRKIE,
226 1, EXT_INT_ENAB|TxINT_ENAB|INT_ALL_Rx,
227 9, NV|MIE|NORESET,
228 255
229};
230
231EXPORT_SYMBOL(z8530_hdlc_kilostream);
232
233/*
234 * As above but for enhanced chips.
235 */
236
237u8 z8530_hdlc_kilostream_85230[]=
238{
239 4, SYNC_ENAB|SDLC|X1CLK,
240 2, 0, /* No vector */
241 1, 0,
242 3, ENT_HM|RxCRC_ENAB|Rx8,
243 5, TxCRC_ENAB|RTS|TxENAB|Tx8|DTR,
244 9, 0, /* Disable interrupts */
245 6, 0xFF,
246 7, FLAG,
247 10, ABUNDER|NRZ|CRCPS, /* MARKIDLE?? */
248 11, TCTRxCP,
249 14, DISDPLL,
250 15, DCDIE|SYNCIE|CTSIE|TxUIE|BRKIE,
251 1, EXT_INT_ENAB|TxINT_ENAB|INT_ALL_Rx,
252 9, NV|MIE|NORESET,
253 23, 3, /* Extended mode AUTO TX and EOM*/
254
255 255
256};
257
258EXPORT_SYMBOL(z8530_hdlc_kilostream_85230);
259
260/**
261 * z8530_flush_fifo - Flush on chip RX FIFO
262 * @c: Channel to flush
263 *
264 * Flush the receive FIFO. There is no specific option for this, we
265 * blindly read bytes and discard them. Reading when there is no data
266 * is harmless. The 8530 has a 4 byte FIFO, the 85230 has 8 bytes.
267 *
268 * All locking is handled for the caller. On return data may still be
269 * present if it arrived during the flush.
270 */
271
272static void z8530_flush_fifo(struct z8530_channel *c)
273{
274 read_zsreg(c, R1);
275 read_zsreg(c, R1);
276 read_zsreg(c, R1);
277 read_zsreg(c, R1);
278 if(c->dev->type==Z85230)
279 {
280 read_zsreg(c, R1);
281 read_zsreg(c, R1);
282 read_zsreg(c, R1);
283 read_zsreg(c, R1);
284 }
285}
286
287/**
288 * z8530_rtsdtr - Control the outgoing DTS/RTS line
289 * @c: The Z8530 channel to control;
290 * @set: 1 to set, 0 to clear
291 *
292 * Sets or clears DTR/RTS on the requested line. All locking is handled
293 * by the caller. For now we assume all boards use the actual RTS/DTR
294 * on the chip. Apparently one or two don't. We'll scream about them
295 * later.
296 */
297
298static void z8530_rtsdtr(struct z8530_channel *c, int set)
299{
300 if (set)
301 c->regs[5] |= (RTS | DTR);
302 else
303 c->regs[5] &= ~(RTS | DTR);
304 write_zsreg(c, R5, c->regs[5]);
305}
306
307/**
308 * z8530_rx - Handle a PIO receive event
309 * @c: Z8530 channel to process
310 *
311 * Receive handler for receiving in PIO mode. This is much like the
312 * async one but not quite the same or as complex
313 *
314 * Note: Its intended that this handler can easily be separated from
315 * the main code to run realtime. That'll be needed for some machines
316 * (eg to ever clock 64kbits on a sparc ;)).
317 *
318 * The RT_LOCK macros don't do anything now. Keep the code covered
319 * by them as short as possible in all circumstances - clocks cost
320 * baud. The interrupt handler is assumed to be atomic w.r.t. to
321 * other code - this is true in the RT case too.
322 *
323 * We only cover the sync cases for this. If you want 2Mbit async
324 * do it yourself but consider medical assistance first. This non DMA
325 * synchronous mode is portable code. The DMA mode assumes PCI like
326 * ISA DMA
327 *
328 * Called with the device lock held
329 */
330
331static void z8530_rx(struct z8530_channel *c)
332{
333 u8 ch,stat;
Alan Cox45d3ac42007-02-05 16:31:03 -0800334
Linus Torvalds1da177e2005-04-16 15:20:36 -0700335 while(1)
336 {
337 /* FIFO empty ? */
338 if(!(read_zsreg(c, R0)&1))
339 break;
340 ch=read_zsdata(c);
341 stat=read_zsreg(c, R1);
342
343 /*
344 * Overrun ?
345 */
346 if(c->count < c->max)
347 {
348 *c->dptr++=ch;
349 c->count++;
350 }
351
352 if(stat&END_FR)
353 {
354
355 /*
356 * Error ?
357 */
358 if(stat&(Rx_OVR|CRC_ERR))
359 {
360 /* Rewind the buffer and return */
361 if(c->skb)
362 c->dptr=c->skb->data;
363 c->count=0;
364 if(stat&Rx_OVR)
365 {
366 printk(KERN_WARNING "%s: overrun\n", c->dev->name);
367 c->rx_overrun++;
368 }
369 if(stat&CRC_ERR)
370 {
371 c->rx_crc_err++;
372 /* printk("crc error\n"); */
373 }
374 /* Shove the frame upstream */
375 }
376 else
377 {
378 /*
379 * Drop the lock for RX processing, or
380 * there are deadlocks
381 */
382 z8530_rx_done(c);
383 write_zsctrl(c, RES_Rx_CRC);
384 }
385 }
386 }
387 /*
388 * Clear irq
389 */
390 write_zsctrl(c, ERR_RES);
391 write_zsctrl(c, RES_H_IUS);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700392}
393
394
395/**
396 * z8530_tx - Handle a PIO transmit event
397 * @c: Z8530 channel to process
398 *
399 * Z8530 transmit interrupt handler for the PIO mode. The basic
400 * idea is to attempt to keep the FIFO fed. We fill as many bytes
401 * in as possible, its quite possible that we won't keep up with the
402 * data rate otherwise.
403 */
404
405static void z8530_tx(struct z8530_channel *c)
406{
Linus Torvalds1da177e2005-04-16 15:20:36 -0700407 while(c->txcount) {
408 /* FIFO full ? */
409 if(!(read_zsreg(c, R0)&4))
Alan Coxfe797452007-03-07 16:37:38 +0000410 return;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700411 c->txcount--;
412 /*
413 * Shovel out the byte
414 */
415 write_zsreg(c, R8, *c->tx_ptr++);
416 write_zsctrl(c, RES_H_IUS);
417 /* We are about to underflow */
418 if(c->txcount==0)
419 {
420 write_zsctrl(c, RES_EOM_L);
421 write_zsreg(c, R10, c->regs[10]&~ABUNDER);
422 }
423 }
424
425
426 /*
427 * End of frame TX - fire another one
428 */
429
430 write_zsctrl(c, RES_Tx_P);
431
432 z8530_tx_done(c);
433 write_zsctrl(c, RES_H_IUS);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700434}
435
436/**
437 * z8530_status - Handle a PIO status exception
438 * @chan: Z8530 channel to process
439 *
440 * A status event occurred in PIO synchronous mode. There are several
441 * reasons the chip will bother us here. A transmit underrun means we
442 * failed to feed the chip fast enough and just broke a packet. A DCD
Krzysztof Hałasa52e8a6a2008-07-02 17:47:52 +0200443 * change is a line up or down.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700444 */
445
446static void z8530_status(struct z8530_channel *chan)
447{
448 u8 status, altered;
449
Krzysztof Hałasa52e8a6a2008-07-02 17:47:52 +0200450 status = read_zsreg(chan, R0);
451 altered = chan->status ^ status;
452
453 chan->status = status;
454
455 if (status & TxEOM) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700456/* printk("%s: Tx underrun.\n", chan->dev->name); */
Krzysztof Hałasa52e8a6a2008-07-02 17:47:52 +0200457 chan->netdevice->stats.tx_fifo_errors++;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700458 write_zsctrl(chan, ERR_RES);
459 z8530_tx_done(chan);
460 }
Krzysztof Hałasa52e8a6a2008-07-02 17:47:52 +0200461
462 if (altered & chan->dcdcheck)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700463 {
Krzysztof Hałasa52e8a6a2008-07-02 17:47:52 +0200464 if (status & chan->dcdcheck) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700465 printk(KERN_INFO "%s: DCD raised\n", chan->dev->name);
Krzysztof Hałasa52e8a6a2008-07-02 17:47:52 +0200466 write_zsreg(chan, R3, chan->regs[3] | RxENABLE);
467 if (chan->netdevice)
468 netif_carrier_on(chan->netdevice);
469 } else {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700470 printk(KERN_INFO "%s: DCD lost\n", chan->dev->name);
Krzysztof Hałasa52e8a6a2008-07-02 17:47:52 +0200471 write_zsreg(chan, R3, chan->regs[3] & ~RxENABLE);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700472 z8530_flush_fifo(chan);
Krzysztof Hałasa52e8a6a2008-07-02 17:47:52 +0200473 if (chan->netdevice)
474 netif_carrier_off(chan->netdevice);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700475 }
Krzysztof Hałasa52e8a6a2008-07-02 17:47:52 +0200476
477 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700478 write_zsctrl(chan, RES_EXT_INT);
479 write_zsctrl(chan, RES_H_IUS);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700480}
481
Krzysztof Hałasa52e8a6a2008-07-02 17:47:52 +0200482struct z8530_irqhandler z8530_sync =
Linus Torvalds1da177e2005-04-16 15:20:36 -0700483{
484 z8530_rx,
485 z8530_tx,
486 z8530_status
487};
488
489EXPORT_SYMBOL(z8530_sync);
490
491/**
492 * z8530_dma_rx - Handle a DMA RX event
493 * @chan: Channel to handle
494 *
495 * Non bus mastering DMA interfaces for the Z8x30 devices. This
496 * is really pretty PC specific. The DMA mode means that most receive
497 * events are handled by the DMA hardware. We get a kick here only if
498 * a frame ended.
499 */
500
501static void z8530_dma_rx(struct z8530_channel *chan)
502{
Linus Torvalds1da177e2005-04-16 15:20:36 -0700503 if(chan->rxdma_on)
504 {
505 /* Special condition check only */
506 u8 status;
507
508 read_zsreg(chan, R7);
509 read_zsreg(chan, R6);
510
511 status=read_zsreg(chan, R1);
512
513 if(status&END_FR)
514 {
515 z8530_rx_done(chan); /* Fire up the next one */
516 }
517 write_zsctrl(chan, ERR_RES);
518 write_zsctrl(chan, RES_H_IUS);
519 }
520 else
521 {
522 /* DMA is off right now, drain the slow way */
523 z8530_rx(chan);
524 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700525}
526
527/**
528 * z8530_dma_tx - Handle a DMA TX event
529 * @chan: The Z8530 channel to handle
530 *
531 * We have received an interrupt while doing DMA transmissions. It
532 * shouldn't happen. Scream loudly if it does.
533 */
534
535static void z8530_dma_tx(struct z8530_channel *chan)
536{
Linus Torvalds1da177e2005-04-16 15:20:36 -0700537 if(!chan->dma_tx)
538 {
539 printk(KERN_WARNING "Hey who turned the DMA off?\n");
540 z8530_tx(chan);
541 return;
542 }
543 /* This shouldnt occur in DMA mode */
544 printk(KERN_ERR "DMA tx - bogus event!\n");
545 z8530_tx(chan);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700546}
547
548/**
549 * z8530_dma_status - Handle a DMA status exception
550 * @chan: Z8530 channel to process
551 *
552 * A status event occurred on the Z8530. We receive these for two reasons
553 * when in DMA mode. Firstly if we finished a packet transfer we get one
Krzysztof Hałasa52e8a6a2008-07-02 17:47:52 +0200554 * and kick the next packet out. Secondly we may see a DCD change.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700555 *
556 */
557
558static void z8530_dma_status(struct z8530_channel *chan)
559{
560 u8 status, altered;
561
562 status=read_zsreg(chan, R0);
563 altered=chan->status^status;
564
565 chan->status=status;
566
567
568 if(chan->dma_tx)
569 {
570 if(status&TxEOM)
571 {
572 unsigned long flags;
573
574 flags=claim_dma_lock();
575 disable_dma(chan->txdma);
576 clear_dma_ff(chan->txdma);
577 chan->txdma_on=0;
578 release_dma_lock(flags);
579 z8530_tx_done(chan);
580 }
581 }
582
Krzysztof Hałasa52e8a6a2008-07-02 17:47:52 +0200583 if (altered & chan->dcdcheck)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700584 {
Krzysztof Hałasa52e8a6a2008-07-02 17:47:52 +0200585 if (status & chan->dcdcheck) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700586 printk(KERN_INFO "%s: DCD raised\n", chan->dev->name);
Krzysztof Hałasa52e8a6a2008-07-02 17:47:52 +0200587 write_zsreg(chan, R3, chan->regs[3] | RxENABLE);
588 if (chan->netdevice)
589 netif_carrier_on(chan->netdevice);
590 } else {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700591 printk(KERN_INFO "%s:DCD lost\n", chan->dev->name);
Krzysztof Hałasa52e8a6a2008-07-02 17:47:52 +0200592 write_zsreg(chan, R3, chan->regs[3] & ~RxENABLE);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700593 z8530_flush_fifo(chan);
Krzysztof Hałasa52e8a6a2008-07-02 17:47:52 +0200594 if (chan->netdevice)
595 netif_carrier_off(chan->netdevice);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700596 }
Krzysztof Hałasa52e8a6a2008-07-02 17:47:52 +0200597 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700598
599 write_zsctrl(chan, RES_EXT_INT);
600 write_zsctrl(chan, RES_H_IUS);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700601}
602
603struct z8530_irqhandler z8530_dma_sync=
604{
605 z8530_dma_rx,
606 z8530_dma_tx,
607 z8530_dma_status
608};
609
610EXPORT_SYMBOL(z8530_dma_sync);
611
612struct z8530_irqhandler z8530_txdma_sync=
613{
614 z8530_rx,
615 z8530_dma_tx,
616 z8530_dma_status
617};
618
619EXPORT_SYMBOL(z8530_txdma_sync);
620
621/**
622 * z8530_rx_clear - Handle RX events from a stopped chip
623 * @c: Z8530 channel to shut up
624 *
625 * Receive interrupt vectors for a Z8530 that is in 'parked' mode.
626 * For machines with PCI Z85x30 cards, or level triggered interrupts
627 * (eg the MacII) we must clear the interrupt cause or die.
628 */
629
630
631static void z8530_rx_clear(struct z8530_channel *c)
632{
633 /*
634 * Data and status bytes
635 */
636 u8 stat;
637
638 read_zsdata(c);
639 stat=read_zsreg(c, R1);
640
641 if(stat&END_FR)
642 write_zsctrl(c, RES_Rx_CRC);
643 /*
644 * Clear irq
645 */
646 write_zsctrl(c, ERR_RES);
647 write_zsctrl(c, RES_H_IUS);
648}
649
650/**
651 * z8530_tx_clear - Handle TX events from a stopped chip
652 * @c: Z8530 channel to shut up
653 *
654 * Transmit interrupt vectors for a Z8530 that is in 'parked' mode.
655 * For machines with PCI Z85x30 cards, or level triggered interrupts
656 * (eg the MacII) we must clear the interrupt cause or die.
657 */
658
659static void z8530_tx_clear(struct z8530_channel *c)
660{
661 write_zsctrl(c, RES_Tx_P);
662 write_zsctrl(c, RES_H_IUS);
663}
664
665/**
666 * z8530_status_clear - Handle status events from a stopped chip
667 * @chan: Z8530 channel to shut up
668 *
669 * Status interrupt vectors for a Z8530 that is in 'parked' mode.
670 * For machines with PCI Z85x30 cards, or level triggered interrupts
671 * (eg the MacII) we must clear the interrupt cause or die.
672 */
673
674static void z8530_status_clear(struct z8530_channel *chan)
675{
676 u8 status=read_zsreg(chan, R0);
677 if(status&TxEOM)
678 write_zsctrl(chan, ERR_RES);
679 write_zsctrl(chan, RES_EXT_INT);
680 write_zsctrl(chan, RES_H_IUS);
681}
682
683struct z8530_irqhandler z8530_nop=
684{
685 z8530_rx_clear,
686 z8530_tx_clear,
687 z8530_status_clear
688};
689
690
691EXPORT_SYMBOL(z8530_nop);
692
693/**
694 * z8530_interrupt - Handle an interrupt from a Z8530
695 * @irq: Interrupt number
696 * @dev_id: The Z8530 device that is interrupting.
697 * @regs: unused
698 *
699 * A Z85[2]30 device has stuck its hand in the air for attention.
700 * We scan both the channels on the chip for events and then call
701 * the channel specific call backs for each channel that has events.
702 * We have to use callback functions because the two channels can be
703 * in different modes.
704 *
705 * Locking is done for the handlers. Note that locking is done
706 * at the chip level (the 5uS delay issue is per chip not per
707 * channel). c->lock for both channels points to dev->lock
708 */
709
David Howells7d12e782006-10-05 14:55:46 +0100710irqreturn_t z8530_interrupt(int irq, void *dev_id)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700711{
712 struct z8530_dev *dev=dev_id;
713 u8 intr;
714 static volatile int locker=0;
715 int work=0;
716 struct z8530_irqhandler *irqs;
717
718 if(locker)
719 {
720 printk(KERN_ERR "IRQ re-enter\n");
721 return IRQ_NONE;
722 }
723 locker=1;
724
725 spin_lock(&dev->lock);
726
727 while(++work<5000)
728 {
729
730 intr = read_zsreg(&dev->chanA, R3);
731 if(!(intr & (CHARxIP|CHATxIP|CHAEXT|CHBRxIP|CHBTxIP|CHBEXT)))
732 break;
733
734 /* This holds the IRQ status. On the 8530 you must read it from chan
735 A even though it applies to the whole chip */
736
737 /* Now walk the chip and see what it is wanting - it may be
738 an IRQ for someone else remember */
739
740 irqs=dev->chanA.irqs;
741
742 if(intr & (CHARxIP|CHATxIP|CHAEXT))
743 {
744 if(intr&CHARxIP)
745 irqs->rx(&dev->chanA);
746 if(intr&CHATxIP)
747 irqs->tx(&dev->chanA);
748 if(intr&CHAEXT)
749 irqs->status(&dev->chanA);
750 }
751
752 irqs=dev->chanB.irqs;
753
754 if(intr & (CHBRxIP|CHBTxIP|CHBEXT))
755 {
756 if(intr&CHBRxIP)
757 irqs->rx(&dev->chanB);
758 if(intr&CHBTxIP)
759 irqs->tx(&dev->chanB);
760 if(intr&CHBEXT)
761 irqs->status(&dev->chanB);
762 }
763 }
764 spin_unlock(&dev->lock);
765 if(work==5000)
766 printk(KERN_ERR "%s: interrupt jammed - abort(0x%X)!\n", dev->name, intr);
767 /* Ok all done */
768 locker=0;
769 return IRQ_HANDLED;
770}
771
772EXPORT_SYMBOL(z8530_interrupt);
773
774static char reg_init[16]=
775{
776 0,0,0,0,
777 0,0,0,0,
778 0,0,0,0,
779 0x55,0,0,0
780};
781
782
783/**
784 * z8530_sync_open - Open a Z8530 channel for PIO
785 * @dev: The network interface we are using
786 * @c: The Z8530 channel to open in synchronous PIO mode
787 *
788 * Switch a Z8530 into synchronous mode without DMA assist. We
789 * raise the RTS/DTR and commence network operation.
790 */
791
792int z8530_sync_open(struct net_device *dev, struct z8530_channel *c)
793{
794 unsigned long flags;
795
796 spin_lock_irqsave(c->lock, flags);
797
798 c->sync = 1;
799 c->mtu = dev->mtu+64;
800 c->count = 0;
801 c->skb = NULL;
802 c->skb2 = NULL;
803 c->irqs = &z8530_sync;
804
805 /* This loads the double buffer up */
806 z8530_rx_done(c); /* Load the frame ring */
807 z8530_rx_done(c); /* Load the backup frame */
808 z8530_rtsdtr(c,1);
809 c->dma_tx = 0;
810 c->regs[R1]|=TxINT_ENAB;
811 write_zsreg(c, R1, c->regs[R1]);
812 write_zsreg(c, R3, c->regs[R3]|RxENABLE);
813
814 spin_unlock_irqrestore(c->lock, flags);
815 return 0;
816}
817
818
819EXPORT_SYMBOL(z8530_sync_open);
820
821/**
822 * z8530_sync_close - Close a PIO Z8530 channel
823 * @dev: Network device to close
824 * @c: Z8530 channel to disassociate and move to idle
825 *
826 * Close down a Z8530 interface and switch its interrupt handlers
827 * to discard future events.
828 */
829
830int z8530_sync_close(struct net_device *dev, struct z8530_channel *c)
831{
832 u8 chk;
833 unsigned long flags;
834
835 spin_lock_irqsave(c->lock, flags);
836 c->irqs = &z8530_nop;
837 c->max = 0;
838 c->sync = 0;
839
840 chk=read_zsreg(c,R0);
841 write_zsreg(c, R3, c->regs[R3]);
842 z8530_rtsdtr(c,0);
843
844 spin_unlock_irqrestore(c->lock, flags);
845 return 0;
846}
847
848EXPORT_SYMBOL(z8530_sync_close);
849
850/**
851 * z8530_sync_dma_open - Open a Z8530 for DMA I/O
852 * @dev: The network device to attach
853 * @c: The Z8530 channel to configure in sync DMA mode.
854 *
855 * Set up a Z85x30 device for synchronous DMA in both directions. Two
856 * ISA DMA channels must be available for this to work. We assume ISA
857 * DMA driven I/O and PC limits on access.
858 */
859
860int z8530_sync_dma_open(struct net_device *dev, struct z8530_channel *c)
861{
862 unsigned long cflags, dflags;
863
864 c->sync = 1;
865 c->mtu = dev->mtu+64;
866 c->count = 0;
867 c->skb = NULL;
868 c->skb2 = NULL;
869 /*
870 * Load the DMA interfaces up
871 */
872 c->rxdma_on = 0;
873 c->txdma_on = 0;
874
875 /*
876 * Allocate the DMA flip buffers. Limit by page size.
877 * Everyone runs 1500 mtu or less on wan links so this
878 * should be fine.
879 */
880
881 if(c->mtu > PAGE_SIZE/2)
882 return -EMSGSIZE;
883
884 c->rx_buf[0]=(void *)get_zeroed_page(GFP_KERNEL|GFP_DMA);
885 if(c->rx_buf[0]==NULL)
886 return -ENOBUFS;
887 c->rx_buf[1]=c->rx_buf[0]+PAGE_SIZE/2;
888
889 c->tx_dma_buf[0]=(void *)get_zeroed_page(GFP_KERNEL|GFP_DMA);
890 if(c->tx_dma_buf[0]==NULL)
891 {
892 free_page((unsigned long)c->rx_buf[0]);
893 c->rx_buf[0]=NULL;
894 return -ENOBUFS;
895 }
896 c->tx_dma_buf[1]=c->tx_dma_buf[0]+PAGE_SIZE/2;
897
898 c->tx_dma_used=0;
899 c->dma_tx = 1;
900 c->dma_num=0;
901 c->dma_ready=1;
902
903 /*
904 * Enable DMA control mode
905 */
906
907 spin_lock_irqsave(c->lock, cflags);
908
909 /*
910 * TX DMA via DIR/REQ
911 */
912
913 c->regs[R14]|= DTRREQ;
914 write_zsreg(c, R14, c->regs[R14]);
915
916 c->regs[R1]&= ~TxINT_ENAB;
917 write_zsreg(c, R1, c->regs[R1]);
918
919 /*
920 * RX DMA via W/Req
921 */
922
923 c->regs[R1]|= WT_FN_RDYFN;
924 c->regs[R1]|= WT_RDY_RT;
925 c->regs[R1]|= INT_ERR_Rx;
926 c->regs[R1]&= ~TxINT_ENAB;
927 write_zsreg(c, R1, c->regs[R1]);
928 c->regs[R1]|= WT_RDY_ENAB;
929 write_zsreg(c, R1, c->regs[R1]);
930
931 /*
932 * DMA interrupts
933 */
934
935 /*
936 * Set up the DMA configuration
937 */
938
939 dflags=claim_dma_lock();
940
941 disable_dma(c->rxdma);
942 clear_dma_ff(c->rxdma);
943 set_dma_mode(c->rxdma, DMA_MODE_READ|0x10);
944 set_dma_addr(c->rxdma, virt_to_bus(c->rx_buf[0]));
945 set_dma_count(c->rxdma, c->mtu);
946 enable_dma(c->rxdma);
947
948 disable_dma(c->txdma);
949 clear_dma_ff(c->txdma);
950 set_dma_mode(c->txdma, DMA_MODE_WRITE);
951 disable_dma(c->txdma);
952
953 release_dma_lock(dflags);
954
955 /*
956 * Select the DMA interrupt handlers
957 */
958
959 c->rxdma_on = 1;
960 c->txdma_on = 1;
961 c->tx_dma_used = 1;
962
963 c->irqs = &z8530_dma_sync;
964 z8530_rtsdtr(c,1);
965 write_zsreg(c, R3, c->regs[R3]|RxENABLE);
966
967 spin_unlock_irqrestore(c->lock, cflags);
968
969 return 0;
970}
971
972EXPORT_SYMBOL(z8530_sync_dma_open);
973
974/**
975 * z8530_sync_dma_close - Close down DMA I/O
976 * @dev: Network device to detach
977 * @c: Z8530 channel to move into discard mode
978 *
979 * Shut down a DMA mode synchronous interface. Halt the DMA, and
980 * free the buffers.
981 */
982
983int z8530_sync_dma_close(struct net_device *dev, struct z8530_channel *c)
984{
985 u8 chk;
986 unsigned long flags;
987
988 c->irqs = &z8530_nop;
989 c->max = 0;
990 c->sync = 0;
991
992 /*
993 * Disable the PC DMA channels
994 */
995
996 flags=claim_dma_lock();
997 disable_dma(c->rxdma);
998 clear_dma_ff(c->rxdma);
999
1000 c->rxdma_on = 0;
1001
1002 disable_dma(c->txdma);
1003 clear_dma_ff(c->txdma);
1004 release_dma_lock(flags);
1005
1006 c->txdma_on = 0;
1007 c->tx_dma_used = 0;
1008
1009 spin_lock_irqsave(c->lock, flags);
1010
1011 /*
1012 * Disable DMA control mode
1013 */
1014
1015 c->regs[R1]&= ~WT_RDY_ENAB;
1016 write_zsreg(c, R1, c->regs[R1]);
1017 c->regs[R1]&= ~(WT_RDY_RT|WT_FN_RDYFN|INT_ERR_Rx);
1018 c->regs[R1]|= INT_ALL_Rx;
1019 write_zsreg(c, R1, c->regs[R1]);
1020 c->regs[R14]&= ~DTRREQ;
1021 write_zsreg(c, R14, c->regs[R14]);
1022
1023 if(c->rx_buf[0])
1024 {
1025 free_page((unsigned long)c->rx_buf[0]);
1026 c->rx_buf[0]=NULL;
1027 }
1028 if(c->tx_dma_buf[0])
1029 {
1030 free_page((unsigned long)c->tx_dma_buf[0]);
1031 c->tx_dma_buf[0]=NULL;
1032 }
1033 chk=read_zsreg(c,R0);
1034 write_zsreg(c, R3, c->regs[R3]);
1035 z8530_rtsdtr(c,0);
1036
1037 spin_unlock_irqrestore(c->lock, flags);
1038
1039 return 0;
1040}
1041
1042EXPORT_SYMBOL(z8530_sync_dma_close);
1043
1044/**
1045 * z8530_sync_txdma_open - Open a Z8530 for TX driven DMA
1046 * @dev: The network device to attach
1047 * @c: The Z8530 channel to configure in sync DMA mode.
1048 *
1049 * Set up a Z85x30 device for synchronous DMA tranmission. One
1050 * ISA DMA channel must be available for this to work. The receive
1051 * side is run in PIO mode, but then it has the bigger FIFO.
1052 */
1053
1054int z8530_sync_txdma_open(struct net_device *dev, struct z8530_channel *c)
1055{
1056 unsigned long cflags, dflags;
1057
1058 printk("Opening sync interface for TX-DMA\n");
1059 c->sync = 1;
1060 c->mtu = dev->mtu+64;
1061 c->count = 0;
1062 c->skb = NULL;
1063 c->skb2 = NULL;
1064
1065 /*
1066 * Allocate the DMA flip buffers. Limit by page size.
1067 * Everyone runs 1500 mtu or less on wan links so this
1068 * should be fine.
1069 */
1070
1071 if(c->mtu > PAGE_SIZE/2)
1072 return -EMSGSIZE;
1073
1074 c->tx_dma_buf[0]=(void *)get_zeroed_page(GFP_KERNEL|GFP_DMA);
1075 if(c->tx_dma_buf[0]==NULL)
1076 return -ENOBUFS;
1077
1078 c->tx_dma_buf[1] = c->tx_dma_buf[0] + PAGE_SIZE/2;
1079
1080
1081 spin_lock_irqsave(c->lock, cflags);
1082
1083 /*
1084 * Load the PIO receive ring
1085 */
1086
1087 z8530_rx_done(c);
1088 z8530_rx_done(c);
1089
1090 /*
1091 * Load the DMA interfaces up
1092 */
1093
1094 c->rxdma_on = 0;
1095 c->txdma_on = 0;
1096
1097 c->tx_dma_used=0;
1098 c->dma_num=0;
1099 c->dma_ready=1;
1100 c->dma_tx = 1;
1101
1102 /*
1103 * Enable DMA control mode
1104 */
1105
1106 /*
1107 * TX DMA via DIR/REQ
1108 */
1109 c->regs[R14]|= DTRREQ;
1110 write_zsreg(c, R14, c->regs[R14]);
1111
1112 c->regs[R1]&= ~TxINT_ENAB;
1113 write_zsreg(c, R1, c->regs[R1]);
1114
1115 /*
1116 * Set up the DMA configuration
1117 */
1118
1119 dflags = claim_dma_lock();
1120
1121 disable_dma(c->txdma);
1122 clear_dma_ff(c->txdma);
1123 set_dma_mode(c->txdma, DMA_MODE_WRITE);
1124 disable_dma(c->txdma);
1125
1126 release_dma_lock(dflags);
1127
1128 /*
1129 * Select the DMA interrupt handlers
1130 */
1131
1132 c->rxdma_on = 0;
1133 c->txdma_on = 1;
1134 c->tx_dma_used = 1;
1135
1136 c->irqs = &z8530_txdma_sync;
1137 z8530_rtsdtr(c,1);
1138 write_zsreg(c, R3, c->regs[R3]|RxENABLE);
1139 spin_unlock_irqrestore(c->lock, cflags);
1140
1141 return 0;
1142}
1143
1144EXPORT_SYMBOL(z8530_sync_txdma_open);
1145
1146/**
1147 * z8530_sync_txdma_close - Close down a TX driven DMA channel
1148 * @dev: Network device to detach
1149 * @c: Z8530 channel to move into discard mode
1150 *
1151 * Shut down a DMA/PIO split mode synchronous interface. Halt the DMA,
1152 * and free the buffers.
1153 */
1154
1155int z8530_sync_txdma_close(struct net_device *dev, struct z8530_channel *c)
1156{
1157 unsigned long dflags, cflags;
1158 u8 chk;
1159
1160
1161 spin_lock_irqsave(c->lock, cflags);
1162
1163 c->irqs = &z8530_nop;
1164 c->max = 0;
1165 c->sync = 0;
1166
1167 /*
1168 * Disable the PC DMA channels
1169 */
1170
1171 dflags = claim_dma_lock();
1172
1173 disable_dma(c->txdma);
1174 clear_dma_ff(c->txdma);
1175 c->txdma_on = 0;
1176 c->tx_dma_used = 0;
1177
1178 release_dma_lock(dflags);
1179
1180 /*
1181 * Disable DMA control mode
1182 */
1183
1184 c->regs[R1]&= ~WT_RDY_ENAB;
1185 write_zsreg(c, R1, c->regs[R1]);
1186 c->regs[R1]&= ~(WT_RDY_RT|WT_FN_RDYFN|INT_ERR_Rx);
1187 c->regs[R1]|= INT_ALL_Rx;
1188 write_zsreg(c, R1, c->regs[R1]);
1189 c->regs[R14]&= ~DTRREQ;
1190 write_zsreg(c, R14, c->regs[R14]);
1191
1192 if(c->tx_dma_buf[0])
1193 {
1194 free_page((unsigned long)c->tx_dma_buf[0]);
1195 c->tx_dma_buf[0]=NULL;
1196 }
1197 chk=read_zsreg(c,R0);
1198 write_zsreg(c, R3, c->regs[R3]);
1199 z8530_rtsdtr(c,0);
1200
1201 spin_unlock_irqrestore(c->lock, cflags);
1202 return 0;
1203}
1204
1205
1206EXPORT_SYMBOL(z8530_sync_txdma_close);
1207
1208
1209/*
1210 * Name strings for Z8530 chips. SGI claim to have a 130, Zilog deny
1211 * it exists...
1212 */
1213
1214static char *z8530_type_name[]={
1215 "Z8530",
1216 "Z85C30",
1217 "Z85230"
1218};
1219
1220/**
1221 * z8530_describe - Uniformly describe a Z8530 port
1222 * @dev: Z8530 device to describe
1223 * @mapping: string holding mapping type (eg "I/O" or "Mem")
1224 * @io: the port value in question
1225 *
1226 * Describe a Z8530 in a standard format. We must pass the I/O as
1227 * the port offset isnt predictable. The main reason for this function
1228 * is to try and get a common format of report.
1229 */
1230
1231void z8530_describe(struct z8530_dev *dev, char *mapping, unsigned long io)
1232{
1233 printk(KERN_INFO "%s: %s found at %s 0x%lX, IRQ %d.\n",
1234 dev->name,
1235 z8530_type_name[dev->type],
1236 mapping,
1237 Z8530_PORT_OF(io),
1238 dev->irq);
1239}
1240
1241EXPORT_SYMBOL(z8530_describe);
1242
1243/*
1244 * Locked operation part of the z8530 init code
1245 */
1246
1247static inline int do_z8530_init(struct z8530_dev *dev)
1248{
1249 /* NOP the interrupt handlers first - we might get a
1250 floating IRQ transition when we reset the chip */
1251 dev->chanA.irqs=&z8530_nop;
1252 dev->chanB.irqs=&z8530_nop;
1253 dev->chanA.dcdcheck=DCD;
1254 dev->chanB.dcdcheck=DCD;
1255
1256 /* Reset the chip */
1257 write_zsreg(&dev->chanA, R9, 0xC0);
1258 udelay(200);
1259 /* Now check its valid */
1260 write_zsreg(&dev->chanA, R12, 0xAA);
1261 if(read_zsreg(&dev->chanA, R12)!=0xAA)
1262 return -ENODEV;
1263 write_zsreg(&dev->chanA, R12, 0x55);
1264 if(read_zsreg(&dev->chanA, R12)!=0x55)
1265 return -ENODEV;
1266
1267 dev->type=Z8530;
1268
1269 /*
1270 * See the application note.
1271 */
1272
1273 write_zsreg(&dev->chanA, R15, 0x01);
1274
1275 /*
1276 * If we can set the low bit of R15 then
1277 * the chip is enhanced.
1278 */
1279
1280 if(read_zsreg(&dev->chanA, R15)==0x01)
1281 {
1282 /* This C30 versus 230 detect is from Klaus Kudielka's dmascc */
1283 /* Put a char in the fifo */
1284 write_zsreg(&dev->chanA, R8, 0);
1285 if(read_zsreg(&dev->chanA, R0)&Tx_BUF_EMP)
1286 dev->type = Z85230; /* Has a FIFO */
1287 else
1288 dev->type = Z85C30; /* Z85C30, 1 byte FIFO */
1289 }
1290
1291 /*
1292 * The code assumes R7' and friends are
1293 * off. Use write_zsext() for these and keep
1294 * this bit clear.
1295 */
1296
1297 write_zsreg(&dev->chanA, R15, 0);
1298
1299 /*
1300 * At this point it looks like the chip is behaving
1301 */
1302
1303 memcpy(dev->chanA.regs, reg_init, 16);
1304 memcpy(dev->chanB.regs, reg_init ,16);
1305
1306 return 0;
1307}
1308
1309/**
1310 * z8530_init - Initialise a Z8530 device
1311 * @dev: Z8530 device to initialise.
1312 *
1313 * Configure up a Z8530/Z85C30 or Z85230 chip. We check the device
1314 * is present, identify the type and then program it to hopefully
1315 * keep quite and behave. This matters a lot, a Z8530 in the wrong
1316 * state will sometimes get into stupid modes generating 10Khz
1317 * interrupt streams and the like.
1318 *
1319 * We set the interrupt handler up to discard any events, in case
1320 * we get them during reset or setp.
1321 *
1322 * Return 0 for success, or a negative value indicating the problem
1323 * in errno form.
1324 */
1325
1326int z8530_init(struct z8530_dev *dev)
1327{
1328 unsigned long flags;
1329 int ret;
1330
1331 /* Set up the chip level lock */
1332 spin_lock_init(&dev->lock);
1333 dev->chanA.lock = &dev->lock;
1334 dev->chanB.lock = &dev->lock;
1335
1336 spin_lock_irqsave(&dev->lock, flags);
1337 ret = do_z8530_init(dev);
1338 spin_unlock_irqrestore(&dev->lock, flags);
1339
1340 return ret;
1341}
1342
1343
1344EXPORT_SYMBOL(z8530_init);
1345
1346/**
1347 * z8530_shutdown - Shutdown a Z8530 device
1348 * @dev: The Z8530 chip to shutdown
1349 *
1350 * We set the interrupt handlers to silence any interrupts. We then
1351 * reset the chip and wait 100uS to be sure the reset completed. Just
1352 * in case the caller then tries to do stuff.
1353 *
1354 * This is called without the lock held
1355 */
1356
1357int z8530_shutdown(struct z8530_dev *dev)
1358{
1359 unsigned long flags;
1360 /* Reset the chip */
1361
1362 spin_lock_irqsave(&dev->lock, flags);
1363 dev->chanA.irqs=&z8530_nop;
1364 dev->chanB.irqs=&z8530_nop;
1365 write_zsreg(&dev->chanA, R9, 0xC0);
1366 /* We must lock the udelay, the chip is offlimits here */
1367 udelay(100);
1368 spin_unlock_irqrestore(&dev->lock, flags);
1369 return 0;
1370}
1371
1372EXPORT_SYMBOL(z8530_shutdown);
1373
1374/**
1375 * z8530_channel_load - Load channel data
1376 * @c: Z8530 channel to configure
1377 * @rtable: table of register, value pairs
1378 * FIXME: ioctl to allow user uploaded tables
1379 *
1380 * Load a Z8530 channel up from the system data. We use +16 to
1381 * indicate the "prime" registers. The value 255 terminates the
1382 * table.
1383 */
1384
1385int z8530_channel_load(struct z8530_channel *c, u8 *rtable)
1386{
1387 unsigned long flags;
1388
1389 spin_lock_irqsave(c->lock, flags);
1390
1391 while(*rtable!=255)
1392 {
1393 int reg=*rtable++;
1394 if(reg>0x0F)
1395 write_zsreg(c, R15, c->regs[15]|1);
1396 write_zsreg(c, reg&0x0F, *rtable);
1397 if(reg>0x0F)
1398 write_zsreg(c, R15, c->regs[15]&~1);
1399 c->regs[reg]=*rtable++;
1400 }
1401 c->rx_function=z8530_null_rx;
1402 c->skb=NULL;
1403 c->tx_skb=NULL;
1404 c->tx_next_skb=NULL;
1405 c->mtu=1500;
1406 c->max=0;
1407 c->count=0;
1408 c->status=read_zsreg(c, R0);
1409 c->sync=1;
1410 write_zsreg(c, R3, c->regs[R3]|RxENABLE);
1411
1412 spin_unlock_irqrestore(c->lock, flags);
1413 return 0;
1414}
1415
1416EXPORT_SYMBOL(z8530_channel_load);
1417
1418
1419/**
1420 * z8530_tx_begin - Begin packet transmission
1421 * @c: The Z8530 channel to kick
1422 *
1423 * This is the speed sensitive side of transmission. If we are called
1424 * and no buffer is being transmitted we commence the next buffer. If
1425 * nothing is queued we idle the sync.
1426 *
1427 * Note: We are handling this code path in the interrupt path, keep it
1428 * fast or bad things will happen.
1429 *
1430 * Called with the lock held.
1431 */
1432
1433static void z8530_tx_begin(struct z8530_channel *c)
1434{
1435 unsigned long flags;
1436 if(c->tx_skb)
1437 return;
1438
1439 c->tx_skb=c->tx_next_skb;
1440 c->tx_next_skb=NULL;
1441 c->tx_ptr=c->tx_next_ptr;
1442
1443 if(c->tx_skb==NULL)
1444 {
1445 /* Idle on */
1446 if(c->dma_tx)
1447 {
1448 flags=claim_dma_lock();
1449 disable_dma(c->txdma);
1450 /*
1451 * Check if we crapped out.
1452 */
Krzysztof Hałasa52e8a6a2008-07-02 17:47:52 +02001453 if (get_dma_residue(c->txdma))
Linus Torvalds1da177e2005-04-16 15:20:36 -07001454 {
Krzysztof Hałasa52e8a6a2008-07-02 17:47:52 +02001455 c->netdevice->stats.tx_dropped++;
1456 c->netdevice->stats.tx_fifo_errors++;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001457 }
1458 release_dma_lock(flags);
1459 }
1460 c->txcount=0;
1461 }
1462 else
1463 {
1464 c->txcount=c->tx_skb->len;
1465
1466
1467 if(c->dma_tx)
1468 {
1469 /*
1470 * FIXME. DMA is broken for the original 8530,
1471 * on the older parts we need to set a flag and
1472 * wait for a further TX interrupt to fire this
1473 * stage off
1474 */
1475
1476 flags=claim_dma_lock();
1477 disable_dma(c->txdma);
1478
1479 /*
1480 * These two are needed by the 8530/85C30
1481 * and must be issued when idling.
1482 */
1483
1484 if(c->dev->type!=Z85230)
1485 {
1486 write_zsctrl(c, RES_Tx_CRC);
1487 write_zsctrl(c, RES_EOM_L);
1488 }
1489 write_zsreg(c, R10, c->regs[10]&~ABUNDER);
1490 clear_dma_ff(c->txdma);
1491 set_dma_addr(c->txdma, virt_to_bus(c->tx_ptr));
1492 set_dma_count(c->txdma, c->txcount);
1493 enable_dma(c->txdma);
1494 release_dma_lock(flags);
1495 write_zsctrl(c, RES_EOM_L);
1496 write_zsreg(c, R5, c->regs[R5]|TxENAB);
1497 }
1498 else
1499 {
1500
1501 /* ABUNDER off */
1502 write_zsreg(c, R10, c->regs[10]);
1503 write_zsctrl(c, RES_Tx_CRC);
1504
1505 while(c->txcount && (read_zsreg(c,R0)&Tx_BUF_EMP))
1506 {
1507 write_zsreg(c, R8, *c->tx_ptr++);
1508 c->txcount--;
1509 }
1510
1511 }
1512 }
1513 /*
1514 * Since we emptied tx_skb we can ask for more
1515 */
1516 netif_wake_queue(c->netdevice);
1517}
1518
1519/**
1520 * z8530_tx_done - TX complete callback
1521 * @c: The channel that completed a transmit.
1522 *
1523 * This is called when we complete a packet send. We wake the queue,
1524 * start the next packet going and then free the buffer of the existing
1525 * packet. This code is fairly timing sensitive.
1526 *
1527 * Called with the register lock held.
Krzysztof Hałasa52e8a6a2008-07-02 17:47:52 +02001528 */
1529
Linus Torvalds1da177e2005-04-16 15:20:36 -07001530static void z8530_tx_done(struct z8530_channel *c)
1531{
1532 struct sk_buff *skb;
1533
1534 /* Actually this can happen.*/
Krzysztof Hałasa52e8a6a2008-07-02 17:47:52 +02001535 if (c->tx_skb == NULL)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001536 return;
1537
Krzysztof Hałasa52e8a6a2008-07-02 17:47:52 +02001538 skb = c->tx_skb;
1539 c->tx_skb = NULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001540 z8530_tx_begin(c);
Krzysztof Hałasa52e8a6a2008-07-02 17:47:52 +02001541 c->netdevice->stats.tx_packets++;
1542 c->netdevice->stats.tx_bytes += skb->len;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001543 dev_kfree_skb_irq(skb);
1544}
1545
1546/**
1547 * z8530_null_rx - Discard a packet
1548 * @c: The channel the packet arrived on
1549 * @skb: The buffer
1550 *
1551 * We point the receive handler at this function when idle. Instead
Krzysztof Hałasa52e8a6a2008-07-02 17:47:52 +02001552 * of processing the frames we get to throw them away.
Linus Torvalds1da177e2005-04-16 15:20:36 -07001553 */
1554
1555void z8530_null_rx(struct z8530_channel *c, struct sk_buff *skb)
1556{
1557 dev_kfree_skb_any(skb);
1558}
1559
1560EXPORT_SYMBOL(z8530_null_rx);
1561
1562/**
1563 * z8530_rx_done - Receive completion callback
1564 * @c: The channel that completed a receive
1565 *
1566 * A new packet is complete. Our goal here is to get back into receive
1567 * mode as fast as possible. On the Z85230 we could change to using
1568 * ESCC mode, but on the older chips we have no choice. We flip to the
1569 * new buffer immediately in DMA mode so that the DMA of the next
1570 * frame can occur while we are copying the previous buffer to an sk_buff
1571 *
1572 * Called with the lock held
1573 */
1574
1575static void z8530_rx_done(struct z8530_channel *c)
1576{
1577 struct sk_buff *skb;
1578 int ct;
1579
1580 /*
1581 * Is our receive engine in DMA mode
1582 */
1583
1584 if(c->rxdma_on)
1585 {
1586 /*
1587 * Save the ready state and the buffer currently
1588 * being used as the DMA target
1589 */
1590
1591 int ready=c->dma_ready;
1592 unsigned char *rxb=c->rx_buf[c->dma_num];
1593 unsigned long flags;
1594
1595 /*
1596 * Complete this DMA. Neccessary to find the length
1597 */
1598
1599 flags=claim_dma_lock();
1600
1601 disable_dma(c->rxdma);
1602 clear_dma_ff(c->rxdma);
1603 c->rxdma_on=0;
1604 ct=c->mtu-get_dma_residue(c->rxdma);
1605 if(ct<0)
1606 ct=2; /* Shit happens.. */
1607 c->dma_ready=0;
1608
1609 /*
1610 * Normal case: the other slot is free, start the next DMA
1611 * into it immediately.
1612 */
1613
1614 if(ready)
1615 {
1616 c->dma_num^=1;
1617 set_dma_mode(c->rxdma, DMA_MODE_READ|0x10);
1618 set_dma_addr(c->rxdma, virt_to_bus(c->rx_buf[c->dma_num]));
1619 set_dma_count(c->rxdma, c->mtu);
1620 c->rxdma_on = 1;
1621 enable_dma(c->rxdma);
1622 /* Stop any frames that we missed the head of
1623 from passing */
1624 write_zsreg(c, R0, RES_Rx_CRC);
1625 }
1626 else
1627 /* Can't occur as we dont reenable the DMA irq until
1628 after the flip is done */
Krzysztof Hałasa52e8a6a2008-07-02 17:47:52 +02001629 printk(KERN_WARNING "%s: DMA flip overrun!\n",
1630 c->netdevice->name);
1631
Linus Torvalds1da177e2005-04-16 15:20:36 -07001632 release_dma_lock(flags);
Krzysztof Hałasa52e8a6a2008-07-02 17:47:52 +02001633
Linus Torvalds1da177e2005-04-16 15:20:36 -07001634 /*
1635 * Shove the old buffer into an sk_buff. We can't DMA
1636 * directly into one on a PC - it might be above the 16Mb
1637 * boundary. Optimisation - we could check to see if we
1638 * can avoid the copy. Optimisation 2 - make the memcpy
1639 * a copychecksum.
1640 */
Krzysztof Hałasa52e8a6a2008-07-02 17:47:52 +02001641
1642 skb = dev_alloc_skb(ct);
1643 if (skb == NULL) {
1644 c->netdevice->stats.rx_dropped++;
1645 printk(KERN_WARNING "%s: Memory squeeze.\n",
1646 c->netdevice->name);
1647 } else {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001648 skb_put(skb, ct);
Arnaldo Carvalho de Melo27d7ff42007-03-31 11:55:19 -03001649 skb_copy_to_linear_data(skb, rxb, ct);
Krzysztof Hałasa52e8a6a2008-07-02 17:47:52 +02001650 c->netdevice->stats.rx_packets++;
1651 c->netdevice->stats.rx_bytes += ct;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001652 }
Krzysztof Hałasa52e8a6a2008-07-02 17:47:52 +02001653 c->dma_ready = 1;
1654 } else {
1655 RT_LOCK;
1656 skb = c->skb;
1657
Linus Torvalds1da177e2005-04-16 15:20:36 -07001658 /*
1659 * The game we play for non DMA is similar. We want to
1660 * get the controller set up for the next packet as fast
1661 * as possible. We potentially only have one byte + the
1662 * fifo length for this. Thus we want to flip to the new
1663 * buffer and then mess around copying and allocating
1664 * things. For the current case it doesn't matter but
1665 * if you build a system where the sync irq isnt blocked
1666 * by the kernel IRQ disable then you need only block the
1667 * sync IRQ for the RT_LOCK area.
Krzysztof Hałasa52e8a6a2008-07-02 17:47:52 +02001668 *
Linus Torvalds1da177e2005-04-16 15:20:36 -07001669 */
1670 ct=c->count;
Krzysztof Hałasa52e8a6a2008-07-02 17:47:52 +02001671
Linus Torvalds1da177e2005-04-16 15:20:36 -07001672 c->skb = c->skb2;
1673 c->count = 0;
1674 c->max = c->mtu;
Krzysztof Hałasa52e8a6a2008-07-02 17:47:52 +02001675 if (c->skb) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001676 c->dptr = c->skb->data;
1677 c->max = c->mtu;
Krzysztof Hałasa52e8a6a2008-07-02 17:47:52 +02001678 } else {
1679 c->count = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001680 c->max = 0;
1681 }
1682 RT_UNLOCK;
1683
1684 c->skb2 = dev_alloc_skb(c->mtu);
Krzysztof Hałasa52e8a6a2008-07-02 17:47:52 +02001685 if (c->skb2 == NULL)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001686 printk(KERN_WARNING "%s: memory squeeze.\n",
Krzysztof Hałasa52e8a6a2008-07-02 17:47:52 +02001687 c->netdevice->name);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001688 else
Krzysztof Hałasa52e8a6a2008-07-02 17:47:52 +02001689 skb_put(c->skb2, c->mtu);
1690 c->netdevice->stats.rx_packets++;
1691 c->netdevice->stats.rx_bytes += ct;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001692 }
1693 /*
1694 * If we received a frame we must now process it.
1695 */
Krzysztof Hałasa52e8a6a2008-07-02 17:47:52 +02001696 if (skb) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001697 skb_trim(skb, ct);
Krzysztof Hałasa52e8a6a2008-07-02 17:47:52 +02001698 c->rx_function(c, skb);
1699 } else {
1700 c->netdevice->stats.rx_dropped++;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001701 printk(KERN_ERR "%s: Lost a frame\n", c->netdevice->name);
1702 }
1703}
1704
1705/**
1706 * spans_boundary - Check a packet can be ISA DMA'd
1707 * @skb: The buffer to check
1708 *
1709 * Returns true if the buffer cross a DMA boundary on a PC. The poor
1710 * thing can only DMA within a 64K block not across the edges of it.
1711 */
Krzysztof Hałasa52e8a6a2008-07-02 17:47:52 +02001712
Linus Torvalds1da177e2005-04-16 15:20:36 -07001713static inline int spans_boundary(struct sk_buff *skb)
1714{
1715 unsigned long a=(unsigned long)skb->data;
1716 a^=(a+skb->len);
1717 if(a&0x00010000) /* If the 64K bit is different.. */
1718 return 1;
1719 return 0;
1720}
1721
1722/**
1723 * z8530_queue_xmit - Queue a packet
1724 * @c: The channel to use
1725 * @skb: The packet to kick down the channel
1726 *
1727 * Queue a packet for transmission. Because we have rather
1728 * hard to hit interrupt latencies for the Z85230 per packet
1729 * even in DMA mode we do the flip to DMA buffer if needed here
1730 * not in the IRQ.
1731 *
1732 * Called from the network code. The lock is not held at this
1733 * point.
1734 */
1735
1736int z8530_queue_xmit(struct z8530_channel *c, struct sk_buff *skb)
1737{
1738 unsigned long flags;
1739
1740 netif_stop_queue(c->netdevice);
1741 if(c->tx_next_skb)
1742 {
1743 return 1;
1744 }
1745
1746 /* PC SPECIFIC - DMA limits */
1747
1748 /*
1749 * If we will DMA the transmit and its gone over the ISA bus
1750 * limit, then copy to the flip buffer
1751 */
1752
1753 if(c->dma_tx && ((unsigned long)(virt_to_bus(skb->data+skb->len))>=16*1024*1024 || spans_boundary(skb)))
1754 {
1755 /*
1756 * Send the flip buffer, and flip the flippy bit.
1757 * We don't care which is used when just so long as
1758 * we never use the same buffer twice in a row. Since
1759 * only one buffer can be going out at a time the other
1760 * has to be safe.
1761 */
1762 c->tx_next_ptr=c->tx_dma_buf[c->tx_dma_used];
1763 c->tx_dma_used^=1; /* Flip temp buffer */
Arnaldo Carvalho de Melod626f622007-03-27 18:55:52 -03001764 skb_copy_from_linear_data(skb, c->tx_next_ptr, skb->len);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001765 }
1766 else
1767 c->tx_next_ptr=skb->data;
1768 RT_LOCK;
1769 c->tx_next_skb=skb;
1770 RT_UNLOCK;
1771
1772 spin_lock_irqsave(c->lock, flags);
1773 z8530_tx_begin(c);
1774 spin_unlock_irqrestore(c->lock, flags);
1775
1776 return 0;
1777}
1778
1779EXPORT_SYMBOL(z8530_queue_xmit);
1780
Linus Torvalds1da177e2005-04-16 15:20:36 -07001781/*
1782 * Module support
1783 */
1784static char banner[] __initdata = KERN_INFO "Generic Z85C30/Z85230 interface driver v0.02\n";
1785
1786static int __init z85230_init_driver(void)
1787{
1788 printk(banner);
1789 return 0;
1790}
1791module_init(z85230_init_driver);
1792
1793static void __exit z85230_cleanup_driver(void)
1794{
1795}
1796module_exit(z85230_cleanup_driver);
1797
1798MODULE_AUTHOR("Red Hat Inc.");
1799MODULE_DESCRIPTION("Z85x30 synchronous driver core");
1800MODULE_LICENSE("GPL");