blob: 7f4bc8ae5462190f777951c1eec6cf1e35dbd679 [file] [log] [blame]
Andrew Victord4b77802006-03-24 11:50:17 +02001/*
2 * Ethernet driver for the Atmel AT91RM9200 (Thunder)
3 *
4 * Copyright (C) 2003 SAN People (Pty) Ltd
5 *
6 * Based on an earlier Atmel EMAC macrocell driver by Atmel and Lineo Inc.
7 * Initial version by Rick Bronson 01/11/2003
8 *
9 * Intel LXT971A PHY support by Christopher Bahns & David Knickerbocker
10 * (Polaroid Corporation)
11 *
12 * Realtek RTL8201(B)L PHY support by Roman Avramenko <roman@imsystems.ru>
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License
16 * as published by the Free Software Foundation; either version
17 * 2 of the License, or (at your option) any later version.
18 */
19
20#include <linux/module.h>
21#include <linux/init.h>
Andrew Victord4b77802006-03-24 11:50:17 +020022#include <linux/mii.h>
23#include <linux/netdevice.h>
24#include <linux/etherdevice.h>
25#include <linux/skbuff.h>
26#include <linux/dma-mapping.h>
27#include <linux/ethtool.h>
28#include <linux/platform_device.h>
29#include <linux/clk.h>
30
31#include <asm/io.h>
32#include <asm/uaccess.h>
33#include <asm/mach-types.h>
34
Russell Kinga09e64f2008-08-05 16:14:15 +010035#include <mach/at91rm9200_emac.h>
36#include <mach/gpio.h>
37#include <mach/board.h>
Andrew Victord4b77802006-03-24 11:50:17 +020038
39#include "at91_ether.h"
40
41#define DRV_NAME "at91_ether"
42#define DRV_VERSION "1.0"
43
Andrew Victor775637d2006-06-20 11:50:23 +020044#define LINK_POLL_INTERVAL (HZ)
45
Andrew Victord4b77802006-03-24 11:50:17 +020046/* ..................................................................... */
47
48/*
49 * Read from a EMAC register.
50 */
51static inline unsigned long at91_emac_read(unsigned int reg)
52{
53 void __iomem *emac_base = (void __iomem *)AT91_VA_BASE_EMAC;
54
55 return __raw_readl(emac_base + reg);
56}
57
58/*
59 * Write to a EMAC register.
60 */
61static inline void at91_emac_write(unsigned int reg, unsigned long value)
62{
63 void __iomem *emac_base = (void __iomem *)AT91_VA_BASE_EMAC;
64
65 __raw_writel(value, emac_base + reg);
66}
67
68/* ........................... PHY INTERFACE ........................... */
69
70/*
71 * Enable the MDIO bit in MAC control register
72 * When not called from an interrupt-handler, access to the PHY must be
73 * protected by a spinlock.
74 */
75static void enable_mdi(void)
76{
77 unsigned long ctl;
78
79 ctl = at91_emac_read(AT91_EMAC_CTL);
80 at91_emac_write(AT91_EMAC_CTL, ctl | AT91_EMAC_MPE); /* enable management port */
81}
82
83/*
84 * Disable the MDIO bit in the MAC control register
85 */
86static void disable_mdi(void)
87{
88 unsigned long ctl;
89
90 ctl = at91_emac_read(AT91_EMAC_CTL);
91 at91_emac_write(AT91_EMAC_CTL, ctl & ~AT91_EMAC_MPE); /* disable management port */
92}
93
94/*
95 * Wait until the PHY operation is complete.
96 */
97static inline void at91_phy_wait(void) {
98 unsigned long timeout = jiffies + 2;
99
100 while (!(at91_emac_read(AT91_EMAC_SR) & AT91_EMAC_SR_IDLE)) {
101 if (time_after(jiffies, timeout)) {
102 printk("at91_ether: MIO timeout\n");
103 break;
104 }
105 cpu_relax();
106 }
107}
108
109/*
110 * Write value to the a PHY register
111 * Note: MDI interface is assumed to already have been enabled.
112 */
113static void write_phy(unsigned char phy_addr, unsigned char address, unsigned int value)
114{
115 at91_emac_write(AT91_EMAC_MAN, AT91_EMAC_MAN_802_3 | AT91_EMAC_RW_W
116 | ((phy_addr & 0x1f) << 23) | (address << 18) | (value & AT91_EMAC_DATA));
117
118 /* Wait until IDLE bit in Network Status register is cleared */
119 at91_phy_wait();
120}
121
122/*
123 * Read value stored in a PHY register.
124 * Note: MDI interface is assumed to already have been enabled.
125 */
126static void read_phy(unsigned char phy_addr, unsigned char address, unsigned int *value)
127{
128 at91_emac_write(AT91_EMAC_MAN, AT91_EMAC_MAN_802_3 | AT91_EMAC_RW_R
129 | ((phy_addr & 0x1f) << 23) | (address << 18));
130
131 /* Wait until IDLE bit in Network Status register is cleared */
132 at91_phy_wait();
133
134 *value = at91_emac_read(AT91_EMAC_MAN) & AT91_EMAC_DATA;
135}
136
137/* ........................... PHY MANAGEMENT .......................... */
138
139/*
140 * Access the PHY to determine the current link speed and mode, and update the
141 * MAC accordingly.
142 * If no link or auto-negotiation is busy, then no changes are made.
143 */
Andrew Victor775637d2006-06-20 11:50:23 +0200144static void update_linkspeed(struct net_device *dev, int silent)
Andrew Victord4b77802006-03-24 11:50:17 +0200145{
Andrew Victorc57ee092006-12-05 15:09:16 +0200146 struct at91_private *lp = netdev_priv(dev);
Andrew Victord4b77802006-03-24 11:50:17 +0200147 unsigned int bmsr, bmcr, lpa, mac_cfg;
148 unsigned int speed, duplex;
149
150 if (!mii_link_ok(&lp->mii)) { /* no link */
151 netif_carrier_off(dev);
Andrew Victor775637d2006-06-20 11:50:23 +0200152 if (!silent)
153 printk(KERN_INFO "%s: Link down.\n", dev->name);
Andrew Victord4b77802006-03-24 11:50:17 +0200154 return;
155 }
156
157 /* Link up, or auto-negotiation still in progress */
158 read_phy(lp->phy_address, MII_BMSR, &bmsr);
159 read_phy(lp->phy_address, MII_BMCR, &bmcr);
160 if (bmcr & BMCR_ANENABLE) { /* AutoNegotiation is enabled */
161 if (!(bmsr & BMSR_ANEGCOMPLETE))
162 return; /* Do nothing - another interrupt generated when negotiation complete */
163
164 read_phy(lp->phy_address, MII_LPA, &lpa);
165 if ((lpa & LPA_100FULL) || (lpa & LPA_100HALF)) speed = SPEED_100;
166 else speed = SPEED_10;
167 if ((lpa & LPA_100FULL) || (lpa & LPA_10FULL)) duplex = DUPLEX_FULL;
168 else duplex = DUPLEX_HALF;
169 } else {
170 speed = (bmcr & BMCR_SPEED100) ? SPEED_100 : SPEED_10;
171 duplex = (bmcr & BMCR_FULLDPLX) ? DUPLEX_FULL : DUPLEX_HALF;
172 }
173
174 /* Update the MAC */
175 mac_cfg = at91_emac_read(AT91_EMAC_CFG) & ~(AT91_EMAC_SPD | AT91_EMAC_FD);
176 if (speed == SPEED_100) {
177 if (duplex == DUPLEX_FULL) /* 100 Full Duplex */
178 mac_cfg |= AT91_EMAC_SPD | AT91_EMAC_FD;
179 else /* 100 Half Duplex */
180 mac_cfg |= AT91_EMAC_SPD;
181 } else {
182 if (duplex == DUPLEX_FULL) /* 10 Full Duplex */
183 mac_cfg |= AT91_EMAC_FD;
184 else {} /* 10 Half Duplex */
185 }
186 at91_emac_write(AT91_EMAC_CFG, mac_cfg);
187
Andrew Victor775637d2006-06-20 11:50:23 +0200188 if (!silent)
189 printk(KERN_INFO "%s: Link now %i-%s\n", dev->name, speed, (duplex == DUPLEX_FULL) ? "FullDuplex" : "HalfDuplex");
Andrew Victord4b77802006-03-24 11:50:17 +0200190 netif_carrier_on(dev);
191}
192
193/*
194 * Handle interrupts from the PHY
195 */
David Howells7d12e782006-10-05 14:55:46 +0100196static irqreturn_t at91ether_phy_interrupt(int irq, void *dev_id)
Andrew Victord4b77802006-03-24 11:50:17 +0200197{
198 struct net_device *dev = (struct net_device *) dev_id;
Andrew Victorc57ee092006-12-05 15:09:16 +0200199 struct at91_private *lp = netdev_priv(dev);
Andrew Victord4b77802006-03-24 11:50:17 +0200200 unsigned int phy;
201
202 /*
203 * This hander is triggered on both edges, but the PHY chips expect
204 * level-triggering. We therefore have to check if the PHY actually has
205 * an IRQ pending.
206 */
207 enable_mdi();
208 if ((lp->phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) {
209 read_phy(lp->phy_address, MII_DSINTR_REG, &phy); /* ack interrupt in Davicom PHY */
210 if (!(phy & (1 << 0)))
211 goto done;
212 }
213 else if (lp->phy_type == MII_LXT971A_ID) {
214 read_phy(lp->phy_address, MII_ISINTS_REG, &phy); /* ack interrupt in Intel PHY */
215 if (!(phy & (1 << 2)))
216 goto done;
217 }
218 else if (lp->phy_type == MII_BCM5221_ID) {
219 read_phy(lp->phy_address, MII_BCMINTR_REG, &phy); /* ack interrupt in Broadcom PHY */
220 if (!(phy & (1 << 0)))
221 goto done;
222 }
223 else if (lp->phy_type == MII_KS8721_ID) {
224 read_phy(lp->phy_address, MII_TPISTATUS, &phy); /* ack interrupt in Micrel PHY */
225 if (!(phy & ((1 << 2) | 1)))
226 goto done;
227 }
Andrew Victor6b4aea72007-05-03 09:17:15 +0200228 else if (lp->phy_type == MII_T78Q21x3_ID) { /* ack interrupt in Teridian PHY */
229 read_phy(lp->phy_address, MII_T78Q21INT_REG, &phy);
230 if (!(phy & ((1 << 2) | 1)))
231 goto done;
232 }
233 else if (lp->phy_type == MII_DP83848_ID) {
234 read_phy(lp->phy_address, MII_DPPHYSTS_REG, &phy); /* ack interrupt in DP83848 PHY */
235 if (!(phy & (1 << 7)))
236 goto done;
237 }
Andrew Victord4b77802006-03-24 11:50:17 +0200238
Andrew Victor775637d2006-06-20 11:50:23 +0200239 update_linkspeed(dev, 0);
Andrew Victord4b77802006-03-24 11:50:17 +0200240
241done:
242 disable_mdi();
243
244 return IRQ_HANDLED;
245}
246
247/*
248 * Initialize and enable the PHY interrupt for link-state changes
249 */
250static void enable_phyirq(struct net_device *dev)
251{
Andrew Victorc57ee092006-12-05 15:09:16 +0200252 struct at91_private *lp = netdev_priv(dev);
Andrew Victord4b77802006-03-24 11:50:17 +0200253 unsigned int dsintr, irq_number;
254 int status;
255
Andrew Victord4b77802006-03-24 11:50:17 +0200256 irq_number = lp->board_data.phy_irq_pin;
Andrew Victor775637d2006-06-20 11:50:23 +0200257 if (!irq_number) {
258 /*
259 * PHY doesn't have an IRQ pin (RTL8201, DP83847, AC101L),
260 * or board does not have it connected.
261 */
Andrew Victorcf425532006-12-05 15:21:19 +0200262 mod_timer(&lp->check_timer, jiffies + LINK_POLL_INTERVAL);
Andrew Victor775637d2006-06-20 11:50:23 +0200263 return;
264 }
265
Andrew Victord4b77802006-03-24 11:50:17 +0200266 status = request_irq(irq_number, at91ether_phy_interrupt, 0, dev->name, dev);
267 if (status) {
268 printk(KERN_ERR "at91_ether: PHY IRQ %d request failed - status %d!\n", irq_number, status);
269 return;
270 }
271
272 spin_lock_irq(&lp->lock);
273 enable_mdi();
274
275 if ((lp->phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) { /* for Davicom PHY */
276 read_phy(lp->phy_address, MII_DSINTR_REG, &dsintr);
277 dsintr = dsintr & ~0xf00; /* clear bits 8..11 */
278 write_phy(lp->phy_address, MII_DSINTR_REG, dsintr);
279 }
280 else if (lp->phy_type == MII_LXT971A_ID) { /* for Intel PHY */
281 read_phy(lp->phy_address, MII_ISINTE_REG, &dsintr);
282 dsintr = dsintr | 0xf2; /* set bits 1, 4..7 */
283 write_phy(lp->phy_address, MII_ISINTE_REG, dsintr);
284 }
285 else if (lp->phy_type == MII_BCM5221_ID) { /* for Broadcom PHY */
286 dsintr = (1 << 15) | ( 1 << 14);
287 write_phy(lp->phy_address, MII_BCMINTR_REG, dsintr);
288 }
289 else if (lp->phy_type == MII_KS8721_ID) { /* for Micrel PHY */
290 dsintr = (1 << 10) | ( 1 << 8);
291 write_phy(lp->phy_address, MII_TPISTATUS, dsintr);
292 }
Andrew Victor6b4aea72007-05-03 09:17:15 +0200293 else if (lp->phy_type == MII_T78Q21x3_ID) { /* for Teridian PHY */
294 read_phy(lp->phy_address, MII_T78Q21INT_REG, &dsintr);
295 dsintr = dsintr | 0x500; /* set bits 8, 10 */
296 write_phy(lp->phy_address, MII_T78Q21INT_REG, dsintr);
297 }
298 else if (lp->phy_type == MII_DP83848_ID) { /* National Semiconductor DP83848 PHY */
299 read_phy(lp->phy_address, MII_DPMISR_REG, &dsintr);
300 dsintr = dsintr | 0x3c; /* set bits 2..5 */
301 write_phy(lp->phy_address, MII_DPMISR_REG, dsintr);
302 read_phy(lp->phy_address, MII_DPMICR_REG, &dsintr);
303 dsintr = dsintr | 0x3; /* set bits 0,1 */
304 write_phy(lp->phy_address, MII_DPMICR_REG, dsintr);
305 }
Andrew Victord4b77802006-03-24 11:50:17 +0200306
307 disable_mdi();
308 spin_unlock_irq(&lp->lock);
309}
310
311/*
312 * Disable the PHY interrupt
313 */
314static void disable_phyirq(struct net_device *dev)
315{
Andrew Victorc57ee092006-12-05 15:09:16 +0200316 struct at91_private *lp = netdev_priv(dev);
Andrew Victord4b77802006-03-24 11:50:17 +0200317 unsigned int dsintr;
318 unsigned int irq_number;
319
Andrew Victor775637d2006-06-20 11:50:23 +0200320 irq_number = lp->board_data.phy_irq_pin;
321 if (!irq_number) {
Andrew Victorcf425532006-12-05 15:21:19 +0200322 del_timer_sync(&lp->check_timer);
Andrew Victord4b77802006-03-24 11:50:17 +0200323 return;
Andrew Victor775637d2006-06-20 11:50:23 +0200324 }
Andrew Victord4b77802006-03-24 11:50:17 +0200325
326 spin_lock_irq(&lp->lock);
327 enable_mdi();
328
329 if ((lp->phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) { /* for Davicom PHY */
330 read_phy(lp->phy_address, MII_DSINTR_REG, &dsintr);
331 dsintr = dsintr | 0xf00; /* set bits 8..11 */
332 write_phy(lp->phy_address, MII_DSINTR_REG, dsintr);
333 }
334 else if (lp->phy_type == MII_LXT971A_ID) { /* for Intel PHY */
335 read_phy(lp->phy_address, MII_ISINTE_REG, &dsintr);
336 dsintr = dsintr & ~0xf2; /* clear bits 1, 4..7 */
337 write_phy(lp->phy_address, MII_ISINTE_REG, dsintr);
338 }
339 else if (lp->phy_type == MII_BCM5221_ID) { /* for Broadcom PHY */
340 read_phy(lp->phy_address, MII_BCMINTR_REG, &dsintr);
341 dsintr = ~(1 << 14);
342 write_phy(lp->phy_address, MII_BCMINTR_REG, dsintr);
343 }
344 else if (lp->phy_type == MII_KS8721_ID) { /* for Micrel PHY */
345 read_phy(lp->phy_address, MII_TPISTATUS, &dsintr);
346 dsintr = ~((1 << 10) | (1 << 8));
347 write_phy(lp->phy_address, MII_TPISTATUS, dsintr);
348 }
Andrew Victor6b4aea72007-05-03 09:17:15 +0200349 else if (lp->phy_type == MII_T78Q21x3_ID) { /* for Teridian PHY */
350 read_phy(lp->phy_address, MII_T78Q21INT_REG, &dsintr);
351 dsintr = dsintr & ~0x500; /* clear bits 8, 10 */
352 write_phy(lp->phy_address, MII_T78Q21INT_REG, dsintr);
353 }
354 else if (lp->phy_type == MII_DP83848_ID) { /* National Semiconductor DP83848 PHY */
355 read_phy(lp->phy_address, MII_DPMICR_REG, &dsintr);
356 dsintr = dsintr & ~0x3; /* clear bits 0, 1 */
357 write_phy(lp->phy_address, MII_DPMICR_REG, dsintr);
358 read_phy(lp->phy_address, MII_DPMISR_REG, &dsintr);
359 dsintr = dsintr & ~0x3c; /* clear bits 2..5 */
360 write_phy(lp->phy_address, MII_DPMISR_REG, dsintr);
361 }
Andrew Victord4b77802006-03-24 11:50:17 +0200362
363 disable_mdi();
364 spin_unlock_irq(&lp->lock);
365
Andrew Victord4b77802006-03-24 11:50:17 +0200366 free_irq(irq_number, dev); /* Free interrupt handler */
367}
368
369/*
370 * Perform a software reset of the PHY.
371 */
372#if 0
373static void reset_phy(struct net_device *dev)
374{
Andrew Victorc57ee092006-12-05 15:09:16 +0200375 struct at91_private *lp = netdev_priv(dev);
Andrew Victord4b77802006-03-24 11:50:17 +0200376 unsigned int bmcr;
377
378 spin_lock_irq(&lp->lock);
379 enable_mdi();
380
381 /* Perform PHY reset */
382 write_phy(lp->phy_address, MII_BMCR, BMCR_RESET);
383
384 /* Wait until PHY reset is complete */
385 do {
386 read_phy(lp->phy_address, MII_BMCR, &bmcr);
Roel Kluin10a5a802008-01-29 21:14:56 +0100387 } while (!(bmcr & BMCR_RESET));
Andrew Victord4b77802006-03-24 11:50:17 +0200388
389 disable_mdi();
390 spin_unlock_irq(&lp->lock);
391}
392#endif
393
Andrew Victor775637d2006-06-20 11:50:23 +0200394static void at91ether_check_link(unsigned long dev_id)
395{
396 struct net_device *dev = (struct net_device *) dev_id;
Andrew Victorcf425532006-12-05 15:21:19 +0200397 struct at91_private *lp = netdev_priv(dev);
Andrew Victor775637d2006-06-20 11:50:23 +0200398
399 enable_mdi();
400 update_linkspeed(dev, 1);
401 disable_mdi();
402
Andrew Victorcf425532006-12-05 15:21:19 +0200403 mod_timer(&lp->check_timer, jiffies + LINK_POLL_INTERVAL);
Andrew Victor775637d2006-06-20 11:50:23 +0200404}
405
Andrew Victord4b77802006-03-24 11:50:17 +0200406/* ......................... ADDRESS MANAGEMENT ........................ */
407
408/*
409 * NOTE: Your bootloader must always set the MAC address correctly before
410 * booting into Linux.
411 *
412 * - It must always set the MAC address after reset, even if it doesn't
413 * happen to access the Ethernet while it's booting. Some versions of
414 * U-Boot on the AT91RM9200-DK do not do this.
415 *
416 * - Likewise it must store the addresses in the correct byte order.
417 * MicroMonitor (uMon) on the CSB337 does this incorrectly (and
418 * continues to do so, for bug-compatibility).
419 */
420
421static short __init unpack_mac_address(struct net_device *dev, unsigned int hi, unsigned int lo)
422{
423 char addr[6];
424
425 if (machine_is_csb337()) {
426 addr[5] = (lo & 0xff); /* The CSB337 bootloader stores the MAC the wrong-way around */
427 addr[4] = (lo & 0xff00) >> 8;
428 addr[3] = (lo & 0xff0000) >> 16;
429 addr[2] = (lo & 0xff000000) >> 24;
430 addr[1] = (hi & 0xff);
431 addr[0] = (hi & 0xff00) >> 8;
432 }
433 else {
434 addr[0] = (lo & 0xff);
435 addr[1] = (lo & 0xff00) >> 8;
436 addr[2] = (lo & 0xff0000) >> 16;
437 addr[3] = (lo & 0xff000000) >> 24;
438 addr[4] = (hi & 0xff);
439 addr[5] = (hi & 0xff00) >> 8;
440 }
441
442 if (is_valid_ether_addr(addr)) {
443 memcpy(dev->dev_addr, &addr, 6);
444 return 1;
445 }
446 return 0;
447}
448
449/*
450 * Set the ethernet MAC address in dev->dev_addr
451 */
452static void __init get_mac_address(struct net_device *dev)
453{
454 /* Check Specific-Address 1 */
455 if (unpack_mac_address(dev, at91_emac_read(AT91_EMAC_SA1H), at91_emac_read(AT91_EMAC_SA1L)))
456 return;
457 /* Check Specific-Address 2 */
458 if (unpack_mac_address(dev, at91_emac_read(AT91_EMAC_SA2H), at91_emac_read(AT91_EMAC_SA2L)))
459 return;
460 /* Check Specific-Address 3 */
461 if (unpack_mac_address(dev, at91_emac_read(AT91_EMAC_SA3H), at91_emac_read(AT91_EMAC_SA3L)))
462 return;
463 /* Check Specific-Address 4 */
464 if (unpack_mac_address(dev, at91_emac_read(AT91_EMAC_SA4H), at91_emac_read(AT91_EMAC_SA4L)))
465 return;
466
467 printk(KERN_ERR "at91_ether: Your bootloader did not configure a MAC address.\n");
468}
469
470/*
471 * Program the hardware MAC address from dev->dev_addr.
472 */
473static void update_mac_address(struct net_device *dev)
474{
475 at91_emac_write(AT91_EMAC_SA1L, (dev->dev_addr[3] << 24) | (dev->dev_addr[2] << 16) | (dev->dev_addr[1] << 8) | (dev->dev_addr[0]));
476 at91_emac_write(AT91_EMAC_SA1H, (dev->dev_addr[5] << 8) | (dev->dev_addr[4]));
477
478 at91_emac_write(AT91_EMAC_SA2L, 0);
479 at91_emac_write(AT91_EMAC_SA2H, 0);
480}
481
482/*
483 * Store the new hardware address in dev->dev_addr, and update the MAC.
484 */
485static int set_mac_address(struct net_device *dev, void* addr)
486{
487 struct sockaddr *address = addr;
488
489 if (!is_valid_ether_addr(address->sa_data))
490 return -EADDRNOTAVAIL;
491
492 memcpy(dev->dev_addr, address->sa_data, dev->addr_len);
493 update_mac_address(dev);
494
Johannes Berge1749612008-10-27 15:59:26 -0700495 printk("%s: Setting MAC address to %pM\n", dev->name,
496 dev->dev_addr);
Andrew Victord4b77802006-03-24 11:50:17 +0200497
498 return 0;
499}
500
501static int inline hash_bit_value(int bitnr, __u8 *addr)
502{
503 if (addr[bitnr / 8] & (1 << (bitnr % 8)))
504 return 1;
505 return 0;
506}
507
508/*
509 * The hash address register is 64 bits long and takes up two locations in the memory map.
510 * The least significant bits are stored in EMAC_HSL and the most significant
511 * bits in EMAC_HSH.
512 *
513 * The unicast hash enable and the multicast hash enable bits in the network configuration
514 * register enable the reception of hash matched frames. The destination address is
515 * reduced to a 6 bit index into the 64 bit hash register using the following hash function.
516 * The hash function is an exclusive or of every sixth bit of the destination address.
517 * hash_index[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47]
518 * hash_index[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46]
519 * hash_index[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45]
520 * hash_index[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44]
521 * hash_index[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43]
522 * hash_index[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42]
523 * da[0] represents the least significant bit of the first byte received, that is, the multicast/
524 * unicast indicator, and da[47] represents the most significant bit of the last byte
525 * received.
526 * If the hash index points to a bit that is set in the hash register then the frame will be
527 * matched according to whether the frame is multicast or unicast.
528 * A multicast match will be signalled if the multicast hash enable bit is set, da[0] is 1 and
529 * the hash index points to a bit set in the hash register.
530 * A unicast match will be signalled if the unicast hash enable bit is set, da[0] is 0 and the
531 * hash index points to a bit set in the hash register.
532 * To receive all multicast frames, the hash register should be set with all ones and the
533 * multicast hash enable bit should be set in the network configuration register.
534 */
535
536/*
537 * Return the hash index value for the specified address.
538 */
539static int hash_get_index(__u8 *addr)
540{
541 int i, j, bitval;
542 int hash_index = 0;
543
544 for (j = 0; j < 6; j++) {
545 for (i = 0, bitval = 0; i < 8; i++)
546 bitval ^= hash_bit_value(i*6 + j, addr);
547
548 hash_index |= (bitval << j);
549 }
550
Andrew Victor427d2692006-06-20 12:10:57 +0200551 return hash_index;
Andrew Victord4b77802006-03-24 11:50:17 +0200552}
553
554/*
555 * Add multicast addresses to the internal multicast-hash table.
556 */
557static void at91ether_sethashtable(struct net_device *dev)
558{
559 struct dev_mc_list *curr;
560 unsigned long mc_filter[2];
561 unsigned int i, bitnr;
562
563 mc_filter[0] = mc_filter[1] = 0;
564
565 curr = dev->mc_list;
566 for (i = 0; i < dev->mc_count; i++, curr = curr->next) {
567 if (!curr) break; /* unexpected end of list */
568
569 bitnr = hash_get_index(curr->dmi_addr);
570 mc_filter[bitnr >> 5] |= 1 << (bitnr & 31);
571 }
572
Andrew Victor8bc35472007-05-02 12:11:38 +0200573 at91_emac_write(AT91_EMAC_HSL, mc_filter[0]);
574 at91_emac_write(AT91_EMAC_HSH, mc_filter[1]);
Andrew Victord4b77802006-03-24 11:50:17 +0200575}
576
577/*
578 * Enable/Disable promiscuous and multicast modes.
579 */
Alexander Beregalov531c6802009-04-09 17:27:00 +0000580static void at91ether_set_multicast_list(struct net_device *dev)
Andrew Victord4b77802006-03-24 11:50:17 +0200581{
582 unsigned long cfg;
583
584 cfg = at91_emac_read(AT91_EMAC_CFG);
585
586 if (dev->flags & IFF_PROMISC) /* Enable promiscuous mode */
587 cfg |= AT91_EMAC_CAF;
588 else if (dev->flags & (~IFF_PROMISC)) /* Disable promiscuous mode */
589 cfg &= ~AT91_EMAC_CAF;
590
591 if (dev->flags & IFF_ALLMULTI) { /* Enable all multicast mode */
592 at91_emac_write(AT91_EMAC_HSH, -1);
593 at91_emac_write(AT91_EMAC_HSL, -1);
594 cfg |= AT91_EMAC_MTI;
595 } else if (dev->mc_count > 0) { /* Enable specific multicasts */
596 at91ether_sethashtable(dev);
597 cfg |= AT91_EMAC_MTI;
598 } else if (dev->flags & (~IFF_ALLMULTI)) { /* Disable all multicast mode */
599 at91_emac_write(AT91_EMAC_HSH, 0);
600 at91_emac_write(AT91_EMAC_HSL, 0);
601 cfg &= ~AT91_EMAC_MTI;
602 }
603
604 at91_emac_write(AT91_EMAC_CFG, cfg);
605}
606
Andrew Victord4b77802006-03-24 11:50:17 +0200607/* ......................... ETHTOOL SUPPORT ........................... */
608
Andrew Victord4b77802006-03-24 11:50:17 +0200609static int mdio_read(struct net_device *dev, int phy_id, int location)
610{
611 unsigned int value;
612
613 read_phy(phy_id, location, &value);
614 return value;
615}
616
617static void mdio_write(struct net_device *dev, int phy_id, int location, int value)
618{
619 write_phy(phy_id, location, value);
620}
621
622static int at91ether_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
623{
Andrew Victorc57ee092006-12-05 15:09:16 +0200624 struct at91_private *lp = netdev_priv(dev);
Andrew Victord4b77802006-03-24 11:50:17 +0200625 int ret;
626
627 spin_lock_irq(&lp->lock);
628 enable_mdi();
629
630 ret = mii_ethtool_gset(&lp->mii, cmd);
631
632 disable_mdi();
633 spin_unlock_irq(&lp->lock);
634
635 if (lp->phy_media == PORT_FIBRE) { /* override media type since mii.c doesn't know */
636 cmd->supported = SUPPORTED_FIBRE;
637 cmd->port = PORT_FIBRE;
638 }
639
640 return ret;
641}
642
643static int at91ether_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
644{
Andrew Victorc57ee092006-12-05 15:09:16 +0200645 struct at91_private *lp = netdev_priv(dev);
Andrew Victord4b77802006-03-24 11:50:17 +0200646 int ret;
647
648 spin_lock_irq(&lp->lock);
649 enable_mdi();
650
651 ret = mii_ethtool_sset(&lp->mii, cmd);
652
653 disable_mdi();
654 spin_unlock_irq(&lp->lock);
655
656 return ret;
657}
658
659static int at91ether_nwayreset(struct net_device *dev)
660{
Andrew Victorc57ee092006-12-05 15:09:16 +0200661 struct at91_private *lp = netdev_priv(dev);
Andrew Victord4b77802006-03-24 11:50:17 +0200662 int ret;
663
664 spin_lock_irq(&lp->lock);
665 enable_mdi();
666
667 ret = mii_nway_restart(&lp->mii);
668
669 disable_mdi();
670 spin_unlock_irq(&lp->lock);
671
672 return ret;
673}
674
675static void at91ether_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
676{
677 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
678 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
Kay Sievers3f978702008-05-30 17:42:11 +0200679 strlcpy(info->bus_info, dev_name(dev->dev.parent), sizeof(info->bus_info));
Andrew Victord4b77802006-03-24 11:50:17 +0200680}
681
Jeff Garzik7282d492006-09-13 14:30:00 -0400682static const struct ethtool_ops at91ether_ethtool_ops = {
Andrew Victord4b77802006-03-24 11:50:17 +0200683 .get_settings = at91ether_get_settings,
684 .set_settings = at91ether_set_settings,
685 .get_drvinfo = at91ether_get_drvinfo,
686 .nway_reset = at91ether_nwayreset,
687 .get_link = ethtool_op_get_link,
688};
689
Andrew Victorca5585e2006-06-20 11:59:05 +0200690static int at91ether_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
691{
Andrew Victorc57ee092006-12-05 15:09:16 +0200692 struct at91_private *lp = netdev_priv(dev);
Andrew Victorca5585e2006-06-20 11:59:05 +0200693 int res;
694
695 if (!netif_running(dev))
696 return -EINVAL;
697
698 spin_lock_irq(&lp->lock);
699 enable_mdi();
700 res = generic_mii_ioctl(&lp->mii, if_mii(rq), cmd, NULL);
701 disable_mdi();
702 spin_unlock_irq(&lp->lock);
703
704 return res;
705}
Andrew Victord4b77802006-03-24 11:50:17 +0200706
707/* ................................ MAC ................................ */
708
709/*
710 * Initialize and start the Receiver and Transmit subsystems
711 */
712static void at91ether_start(struct net_device *dev)
713{
Andrew Victorc57ee092006-12-05 15:09:16 +0200714 struct at91_private *lp = netdev_priv(dev);
Andrew Victord4b77802006-03-24 11:50:17 +0200715 struct recv_desc_bufs *dlist, *dlist_phys;
716 int i;
717 unsigned long ctl;
718
719 dlist = lp->dlist;
720 dlist_phys = lp->dlist_phys;
721
722 for (i = 0; i < MAX_RX_DESCR; i++) {
723 dlist->descriptors[i].addr = (unsigned int) &dlist_phys->recv_buf[i][0];
724 dlist->descriptors[i].size = 0;
725 }
726
727 /* Set the Wrap bit on the last descriptor */
728 dlist->descriptors[i-1].addr |= EMAC_DESC_WRAP;
729
730 /* Reset buffer index */
731 lp->rxBuffIndex = 0;
732
733 /* Program address of descriptor list in Rx Buffer Queue register */
734 at91_emac_write(AT91_EMAC_RBQP, (unsigned long) dlist_phys);
735
736 /* Enable Receive and Transmit */
737 ctl = at91_emac_read(AT91_EMAC_CTL);
738 at91_emac_write(AT91_EMAC_CTL, ctl | AT91_EMAC_RE | AT91_EMAC_TE);
739}
740
741/*
742 * Open the ethernet interface
743 */
744static int at91ether_open(struct net_device *dev)
745{
Andrew Victorc57ee092006-12-05 15:09:16 +0200746 struct at91_private *lp = netdev_priv(dev);
Andrew Victord4b77802006-03-24 11:50:17 +0200747 unsigned long ctl;
748
Andrew Victor427d2692006-06-20 12:10:57 +0200749 if (!is_valid_ether_addr(dev->dev_addr))
750 return -EADDRNOTAVAIL;
Andrew Victord4b77802006-03-24 11:50:17 +0200751
Andrew Victor427d2692006-06-20 12:10:57 +0200752 clk_enable(lp->ether_clk); /* Re-enable Peripheral clock */
Andrew Victord4b77802006-03-24 11:50:17 +0200753
754 /* Clear internal statistics */
755 ctl = at91_emac_read(AT91_EMAC_CTL);
756 at91_emac_write(AT91_EMAC_CTL, ctl | AT91_EMAC_CSR);
757
758 /* Update the MAC address (incase user has changed it) */
759 update_mac_address(dev);
760
761 /* Enable PHY interrupt */
762 enable_phyirq(dev);
763
764 /* Enable MAC interrupts */
765 at91_emac_write(AT91_EMAC_IER, AT91_EMAC_RCOM | AT91_EMAC_RBNA
766 | AT91_EMAC_TUND | AT91_EMAC_RTRY | AT91_EMAC_TCOM
767 | AT91_EMAC_ROVR | AT91_EMAC_ABT);
768
769 /* Determine current link speed */
770 spin_lock_irq(&lp->lock);
771 enable_mdi();
Andrew Victor775637d2006-06-20 11:50:23 +0200772 update_linkspeed(dev, 0);
Andrew Victord4b77802006-03-24 11:50:17 +0200773 disable_mdi();
774 spin_unlock_irq(&lp->lock);
775
776 at91ether_start(dev);
777 netif_start_queue(dev);
778 return 0;
779}
780
781/*
782 * Close the interface
783 */
784static int at91ether_close(struct net_device *dev)
785{
Andrew Victorc57ee092006-12-05 15:09:16 +0200786 struct at91_private *lp = netdev_priv(dev);
Andrew Victord4b77802006-03-24 11:50:17 +0200787 unsigned long ctl;
788
789 /* Disable Receiver and Transmitter */
790 ctl = at91_emac_read(AT91_EMAC_CTL);
791 at91_emac_write(AT91_EMAC_CTL, ctl & ~(AT91_EMAC_TE | AT91_EMAC_RE));
792
793 /* Disable PHY interrupt */
794 disable_phyirq(dev);
795
796 /* Disable MAC interrupts */
797 at91_emac_write(AT91_EMAC_IDR, AT91_EMAC_RCOM | AT91_EMAC_RBNA
798 | AT91_EMAC_TUND | AT91_EMAC_RTRY | AT91_EMAC_TCOM
799 | AT91_EMAC_ROVR | AT91_EMAC_ABT);
800
801 netif_stop_queue(dev);
802
Andrew Victor427d2692006-06-20 12:10:57 +0200803 clk_disable(lp->ether_clk); /* Disable Peripheral clock */
Andrew Victord4b77802006-03-24 11:50:17 +0200804
805 return 0;
806}
807
808/*
809 * Transmit packet.
810 */
Alexander Beregalov531c6802009-04-09 17:27:00 +0000811static int at91ether_start_xmit(struct sk_buff *skb, struct net_device *dev)
Andrew Victord4b77802006-03-24 11:50:17 +0200812{
Andrew Victorc57ee092006-12-05 15:09:16 +0200813 struct at91_private *lp = netdev_priv(dev);
Andrew Victord4b77802006-03-24 11:50:17 +0200814
815 if (at91_emac_read(AT91_EMAC_TSR) & AT91_EMAC_TSR_BNQ) {
816 netif_stop_queue(dev);
817
818 /* Store packet information (to free when Tx completed) */
819 lp->skb = skb;
820 lp->skb_length = skb->len;
821 lp->skb_physaddr = dma_map_single(NULL, skb->data, skb->len, DMA_TO_DEVICE);
Paulius Zaleckas7a2f53e2008-07-17 11:01:26 +0300822 dev->stats.tx_bytes += skb->len;
Andrew Victord4b77802006-03-24 11:50:17 +0200823
824 /* Set address of the data in the Transmit Address register */
825 at91_emac_write(AT91_EMAC_TAR, lp->skb_physaddr);
826 /* Set length of the packet in the Transmit Control register */
827 at91_emac_write(AT91_EMAC_TCR, skb->len);
828
829 dev->trans_start = jiffies;
830 } else {
Alexander Beregalov531c6802009-04-09 17:27:00 +0000831 printk(KERN_ERR "at91_ether.c: at91ether_start_xmit() called, but device is busy!\n");
Andrew Victord4b77802006-03-24 11:50:17 +0200832 return 1; /* if we return anything but zero, dev.c:1055 calls kfree_skb(skb)
833 on this skb, he also reports -ENETDOWN and printk's, so either
834 we free and return(0) or don't free and return 1 */
835 }
836
837 return 0;
838}
839
840/*
841 * Update the current statistics from the internal statistics registers.
842 */
843static struct net_device_stats *at91ether_stats(struct net_device *dev)
844{
Andrew Victord4b77802006-03-24 11:50:17 +0200845 int ale, lenerr, seqe, lcol, ecol;
846
847 if (netif_running(dev)) {
Paulius Zaleckas7a2f53e2008-07-17 11:01:26 +0300848 dev->stats.rx_packets += at91_emac_read(AT91_EMAC_OK); /* Good frames received */
Andrew Victord4b77802006-03-24 11:50:17 +0200849 ale = at91_emac_read(AT91_EMAC_ALE);
Paulius Zaleckas7a2f53e2008-07-17 11:01:26 +0300850 dev->stats.rx_frame_errors += ale; /* Alignment errors */
Andrew Victord4b77802006-03-24 11:50:17 +0200851 lenerr = at91_emac_read(AT91_EMAC_ELR) + at91_emac_read(AT91_EMAC_USF);
Paulius Zaleckas7a2f53e2008-07-17 11:01:26 +0300852 dev->stats.rx_length_errors += lenerr; /* Excessive Length or Undersize Frame error */
Andrew Victord4b77802006-03-24 11:50:17 +0200853 seqe = at91_emac_read(AT91_EMAC_SEQE);
Paulius Zaleckas7a2f53e2008-07-17 11:01:26 +0300854 dev->stats.rx_crc_errors += seqe; /* CRC error */
855 dev->stats.rx_fifo_errors += at91_emac_read(AT91_EMAC_DRFC); /* Receive buffer not available */
856 dev->stats.rx_errors += (ale + lenerr + seqe
Andrew Victord4b77802006-03-24 11:50:17 +0200857 + at91_emac_read(AT91_EMAC_CDE) + at91_emac_read(AT91_EMAC_RJB));
858
Paulius Zaleckas7a2f53e2008-07-17 11:01:26 +0300859 dev->stats.tx_packets += at91_emac_read(AT91_EMAC_FRA); /* Frames successfully transmitted */
860 dev->stats.tx_fifo_errors += at91_emac_read(AT91_EMAC_TUE); /* Transmit FIFO underruns */
861 dev->stats.tx_carrier_errors += at91_emac_read(AT91_EMAC_CSE); /* Carrier Sense errors */
862 dev->stats.tx_heartbeat_errors += at91_emac_read(AT91_EMAC_SQEE);/* Heartbeat error */
Andrew Victord4b77802006-03-24 11:50:17 +0200863
864 lcol = at91_emac_read(AT91_EMAC_LCOL);
865 ecol = at91_emac_read(AT91_EMAC_ECOL);
Paulius Zaleckas7a2f53e2008-07-17 11:01:26 +0300866 dev->stats.tx_window_errors += lcol; /* Late collisions */
867 dev->stats.tx_aborted_errors += ecol; /* 16 collisions */
Andrew Victord4b77802006-03-24 11:50:17 +0200868
Paulius Zaleckas7a2f53e2008-07-17 11:01:26 +0300869 dev->stats.collisions += (at91_emac_read(AT91_EMAC_SCOL) + at91_emac_read(AT91_EMAC_MCOL) + lcol + ecol);
Andrew Victord4b77802006-03-24 11:50:17 +0200870 }
Paulius Zaleckas7a2f53e2008-07-17 11:01:26 +0300871 return &dev->stats;
Andrew Victord4b77802006-03-24 11:50:17 +0200872}
873
874/*
875 * Extract received frame from buffer descriptors and sent to upper layers.
876 * (Called from interrupt context)
877 */
878static void at91ether_rx(struct net_device *dev)
879{
Andrew Victorc57ee092006-12-05 15:09:16 +0200880 struct at91_private *lp = netdev_priv(dev);
Andrew Victord4b77802006-03-24 11:50:17 +0200881 struct recv_desc_bufs *dlist;
882 unsigned char *p_recv;
883 struct sk_buff *skb;
884 unsigned int pktlen;
885
886 dlist = lp->dlist;
887 while (dlist->descriptors[lp->rxBuffIndex].addr & EMAC_DESC_DONE) {
888 p_recv = dlist->recv_buf[lp->rxBuffIndex];
889 pktlen = dlist->descriptors[lp->rxBuffIndex].size & 0x7ff; /* Length of frame including FCS */
Andrew Victora3f63e42006-12-05 15:37:02 +0200890 skb = dev_alloc_skb(pktlen + 2);
Andrew Victord4b77802006-03-24 11:50:17 +0200891 if (skb != NULL) {
892 skb_reserve(skb, 2);
893 memcpy(skb_put(skb, pktlen), p_recv, pktlen);
894
Andrew Victord4b77802006-03-24 11:50:17 +0200895 skb->protocol = eth_type_trans(skb, dev);
Paulius Zaleckas7a2f53e2008-07-17 11:01:26 +0300896 dev->stats.rx_bytes += pktlen;
Andrew Victord4b77802006-03-24 11:50:17 +0200897 netif_rx(skb);
898 }
899 else {
Paulius Zaleckas7a2f53e2008-07-17 11:01:26 +0300900 dev->stats.rx_dropped += 1;
Andrew Victord4b77802006-03-24 11:50:17 +0200901 printk(KERN_NOTICE "%s: Memory squeeze, dropping packet.\n", dev->name);
902 }
903
904 if (dlist->descriptors[lp->rxBuffIndex].size & EMAC_MULTICAST)
Paulius Zaleckas7a2f53e2008-07-17 11:01:26 +0300905 dev->stats.multicast++;
Andrew Victord4b77802006-03-24 11:50:17 +0200906
907 dlist->descriptors[lp->rxBuffIndex].addr &= ~EMAC_DESC_DONE; /* reset ownership bit */
908 if (lp->rxBuffIndex == MAX_RX_DESCR-1) /* wrap after last buffer */
909 lp->rxBuffIndex = 0;
910 else
911 lp->rxBuffIndex++;
912 }
913}
914
915/*
916 * MAC interrupt handler
917 */
David Howells7d12e782006-10-05 14:55:46 +0100918static irqreturn_t at91ether_interrupt(int irq, void *dev_id)
Andrew Victord4b77802006-03-24 11:50:17 +0200919{
920 struct net_device *dev = (struct net_device *) dev_id;
Andrew Victorc57ee092006-12-05 15:09:16 +0200921 struct at91_private *lp = netdev_priv(dev);
Andrew Victord4b77802006-03-24 11:50:17 +0200922 unsigned long intstatus, ctl;
923
924 /* MAC Interrupt Status register indicates what interrupts are pending.
925 It is automatically cleared once read. */
926 intstatus = at91_emac_read(AT91_EMAC_ISR);
927
928 if (intstatus & AT91_EMAC_RCOM) /* Receive complete */
929 at91ether_rx(dev);
930
Andrew Victor427d2692006-06-20 12:10:57 +0200931 if (intstatus & AT91_EMAC_TCOM) { /* Transmit complete */
Andrew Victord4b77802006-03-24 11:50:17 +0200932 /* The TCOM bit is set even if the transmission failed. */
933 if (intstatus & (AT91_EMAC_TUND | AT91_EMAC_RTRY))
Paulius Zaleckas7a2f53e2008-07-17 11:01:26 +0300934 dev->stats.tx_errors += 1;
Andrew Victord4b77802006-03-24 11:50:17 +0200935
936 if (lp->skb) {
937 dev_kfree_skb_irq(lp->skb);
938 lp->skb = NULL;
939 dma_unmap_single(NULL, lp->skb_physaddr, lp->skb_length, DMA_TO_DEVICE);
940 }
941 netif_wake_queue(dev);
942 }
943
944 /* Work-around for Errata #11 */
945 if (intstatus & AT91_EMAC_RBNA) {
946 ctl = at91_emac_read(AT91_EMAC_CTL);
947 at91_emac_write(AT91_EMAC_CTL, ctl & ~AT91_EMAC_RE);
948 at91_emac_write(AT91_EMAC_CTL, ctl | AT91_EMAC_RE);
949 }
950
951 if (intstatus & AT91_EMAC_ROVR)
952 printk("%s: ROVR error\n", dev->name);
953
954 return IRQ_HANDLED;
955}
956
Andrew Victor51cc2102006-12-05 15:33:05 +0200957#ifdef CONFIG_NET_POLL_CONTROLLER
958static void at91ether_poll_controller(struct net_device *dev)
959{
960 unsigned long flags;
961
962 local_irq_save(flags);
963 at91ether_interrupt(dev->irq, dev);
964 local_irq_restore(flags);
965}
966#endif
967
Alexander Beregalov531c6802009-04-09 17:27:00 +0000968static const struct net_device_ops at91ether_netdev_ops = {
969 .ndo_open = at91ether_open,
970 .ndo_stop = at91ether_close,
971 .ndo_start_xmit = at91ether_start_xmit,
972 .ndo_get_stats = at91ether_stats,
973 .ndo_set_multicast_list = at91ether_set_multicast_list,
974 .ndo_set_mac_address = set_mac_address,
975 .ndo_do_ioctl = at91ether_ioctl,
976 .ndo_validate_addr = eth_validate_addr,
977 .ndo_change_mtu = eth_change_mtu,
978#ifdef CONFIG_NET_POLL_CONTROLLER
979 .ndo_poll_controller = at91ether_poll_controller,
980#endif
981};
982
Andrew Victord4b77802006-03-24 11:50:17 +0200983/*
984 * Initialize the ethernet interface
985 */
Andrew Victor427d2692006-06-20 12:10:57 +0200986static int __init at91ether_setup(unsigned long phy_type, unsigned short phy_address,
987 struct platform_device *pdev, struct clk *ether_clk)
Andrew Victord4b77802006-03-24 11:50:17 +0200988{
989 struct at91_eth_data *board_data = pdev->dev.platform_data;
990 struct net_device *dev;
991 struct at91_private *lp;
992 unsigned int val;
993 int res;
994
Andrew Victord4b77802006-03-24 11:50:17 +0200995 dev = alloc_etherdev(sizeof(struct at91_private));
996 if (!dev)
997 return -ENOMEM;
998
999 dev->base_addr = AT91_VA_BASE_EMAC;
Andrew Victor72729912006-09-27 09:44:11 +01001000 dev->irq = AT91RM9200_ID_EMAC;
Andrew Victord4b77802006-03-24 11:50:17 +02001001
1002 /* Install the interrupt handler */
1003 if (request_irq(dev->irq, at91ether_interrupt, 0, dev->name, dev)) {
1004 free_netdev(dev);
1005 return -EBUSY;
1006 }
1007
1008 /* Allocate memory for DMA Receive descriptors */
Andrew Victorc57ee092006-12-05 15:09:16 +02001009 lp = netdev_priv(dev);
Andrew Victord4b77802006-03-24 11:50:17 +02001010 lp->dlist = (struct recv_desc_bufs *) dma_alloc_coherent(NULL, sizeof(struct recv_desc_bufs), (dma_addr_t *) &lp->dlist_phys, GFP_KERNEL);
1011 if (lp->dlist == NULL) {
1012 free_irq(dev->irq, dev);
1013 free_netdev(dev);
1014 return -ENOMEM;
1015 }
1016 lp->board_data = *board_data;
Andrew Victor427d2692006-06-20 12:10:57 +02001017 lp->ether_clk = ether_clk;
Andrew Victord4b77802006-03-24 11:50:17 +02001018 platform_set_drvdata(pdev, dev);
1019
1020 spin_lock_init(&lp->lock);
1021
1022 ether_setup(dev);
Alexander Beregalov531c6802009-04-09 17:27:00 +00001023 dev->netdev_ops = &at91ether_netdev_ops;
Andrew Victord4b77802006-03-24 11:50:17 +02001024 dev->ethtool_ops = &at91ether_ethtool_ops;
1025
1026 SET_NETDEV_DEV(dev, &pdev->dev);
1027
1028 get_mac_address(dev); /* Get ethernet address and store it in dev->dev_addr */
1029 update_mac_address(dev); /* Program ethernet address into MAC */
1030
1031 at91_emac_write(AT91_EMAC_CTL, 0);
1032
1033 if (lp->board_data.is_rmii)
1034 at91_emac_write(AT91_EMAC_CFG, AT91_EMAC_CLK_DIV32 | AT91_EMAC_BIG | AT91_EMAC_RMII);
1035 else
1036 at91_emac_write(AT91_EMAC_CFG, AT91_EMAC_CLK_DIV32 | AT91_EMAC_BIG);
1037
1038 /* Perform PHY-specific initialization */
1039 spin_lock_irq(&lp->lock);
1040 enable_mdi();
1041 if ((phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) {
1042 read_phy(phy_address, MII_DSCR_REG, &val);
1043 if ((val & (1 << 10)) == 0) /* DSCR bit 10 is 0 -- fiber mode */
1044 lp->phy_media = PORT_FIBRE;
1045 } else if (machine_is_csb337()) {
1046 /* mix link activity status into LED2 link state */
1047 write_phy(phy_address, MII_LEDCTRL_REG, 0x0d22);
Andrew Victor2f036ac2008-04-15 21:10:11 +01001048 } else if (machine_is_ecbat91())
1049 write_phy(phy_address, MII_LEDCTRL_REG, 0x156A);
1050
Andrew Victord4b77802006-03-24 11:50:17 +02001051 disable_mdi();
1052 spin_unlock_irq(&lp->lock);
1053
1054 lp->mii.dev = dev; /* Support for ethtool */
1055 lp->mii.mdio_read = mdio_read;
1056 lp->mii.mdio_write = mdio_write;
Andrew Victorca5585e2006-06-20 11:59:05 +02001057 lp->mii.phy_id = phy_address;
1058 lp->mii.phy_id_mask = 0x1f;
1059 lp->mii.reg_num_mask = 0x1f;
Andrew Victord4b77802006-03-24 11:50:17 +02001060
1061 lp->phy_type = phy_type; /* Type of PHY connected */
1062 lp->phy_address = phy_address; /* MDI address of PHY */
1063
1064 /* Register the network interface */
1065 res = register_netdev(dev);
1066 if (res) {
1067 free_irq(dev->irq, dev);
1068 free_netdev(dev);
1069 dma_free_coherent(NULL, sizeof(struct recv_desc_bufs), lp->dlist, (dma_addr_t)lp->dlist_phys);
1070 return res;
1071 }
Andrew Victord4b77802006-03-24 11:50:17 +02001072
1073 /* Determine current link speed */
1074 spin_lock_irq(&lp->lock);
1075 enable_mdi();
Andrew Victor775637d2006-06-20 11:50:23 +02001076 update_linkspeed(dev, 0);
Andrew Victord4b77802006-03-24 11:50:17 +02001077 disable_mdi();
1078 spin_unlock_irq(&lp->lock);
1079 netif_carrier_off(dev); /* will be enabled in open() */
1080
Andrew Victor775637d2006-06-20 11:50:23 +02001081 /* If board has no PHY IRQ, use a timer to poll the PHY */
1082 if (!lp->board_data.phy_irq_pin) {
Andrew Victorcf425532006-12-05 15:21:19 +02001083 init_timer(&lp->check_timer);
1084 lp->check_timer.data = (unsigned long)dev;
1085 lp->check_timer.function = at91ether_check_link;
David Brownell71527ef2008-10-27 14:11:34 -07001086 } else if (lp->board_data.phy_irq_pin >= 32)
1087 gpio_request(lp->board_data.phy_irq_pin, "ethernet_phy");
Andrew Victor775637d2006-06-20 11:50:23 +02001088
Andrew Victord4b77802006-03-24 11:50:17 +02001089 /* Display ethernet banner */
Johannes Berge1749612008-10-27 15:59:26 -07001090 printk(KERN_INFO "%s: AT91 ethernet at 0x%08x int=%d %s%s (%pM)\n",
Joe Perches0795af52007-10-03 17:59:30 -07001091 dev->name, (uint) dev->base_addr, dev->irq,
1092 at91_emac_read(AT91_EMAC_CFG) & AT91_EMAC_SPD ? "100-" : "10-",
1093 at91_emac_read(AT91_EMAC_CFG) & AT91_EMAC_FD ? "FullDuplex" : "HalfDuplex",
Johannes Berge1749612008-10-27 15:59:26 -07001094 dev->dev_addr);
Andrew Victord4b77802006-03-24 11:50:17 +02001095 if ((phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID))
Andrew Victor427d2692006-06-20 12:10:57 +02001096 printk(KERN_INFO "%s: Davicom 9161 PHY %s\n", dev->name, (lp->phy_media == PORT_FIBRE) ? "(Fiber)" : "(Copper)");
Andrew Victord4b77802006-03-24 11:50:17 +02001097 else if (phy_type == MII_LXT971A_ID)
1098 printk(KERN_INFO "%s: Intel LXT971A PHY\n", dev->name);
1099 else if (phy_type == MII_RTL8201_ID)
1100 printk(KERN_INFO "%s: Realtek RTL8201(B)L PHY\n", dev->name);
1101 else if (phy_type == MII_BCM5221_ID)
1102 printk(KERN_INFO "%s: Broadcom BCM5221 PHY\n", dev->name);
1103 else if (phy_type == MII_DP83847_ID)
1104 printk(KERN_INFO "%s: National Semiconductor DP83847 PHY\n", dev->name);
Andrew Victor6b4aea72007-05-03 09:17:15 +02001105 else if (phy_type == MII_DP83848_ID)
1106 printk(KERN_INFO "%s: National Semiconductor DP83848 PHY\n", dev->name);
Andrew Victord4b77802006-03-24 11:50:17 +02001107 else if (phy_type == MII_AC101L_ID)
1108 printk(KERN_INFO "%s: Altima AC101L PHY\n", dev->name);
1109 else if (phy_type == MII_KS8721_ID)
1110 printk(KERN_INFO "%s: Micrel KS8721 PHY\n", dev->name);
Andrew Victor6b4aea72007-05-03 09:17:15 +02001111 else if (phy_type == MII_T78Q21x3_ID)
1112 printk(KERN_INFO "%s: Teridian 78Q21x3 PHY\n", dev->name);
1113 else if (phy_type == MII_LAN83C185_ID)
1114 printk(KERN_INFO "%s: SMSC LAN83C185 PHY\n", dev->name);
Andrew Victord4b77802006-03-24 11:50:17 +02001115
1116 return 0;
1117}
1118
1119/*
1120 * Detect MAC and PHY and perform initialization
1121 */
1122static int __init at91ether_probe(struct platform_device *pdev)
1123{
1124 unsigned int phyid1, phyid2;
1125 int detected = -1;
1126 unsigned long phy_id;
1127 unsigned short phy_address = 0;
Andrew Victor427d2692006-06-20 12:10:57 +02001128 struct clk *ether_clk;
Andrew Victord4b77802006-03-24 11:50:17 +02001129
1130 ether_clk = clk_get(&pdev->dev, "ether_clk");
Andrew Victor427d2692006-06-20 12:10:57 +02001131 if (IS_ERR(ether_clk)) {
Andrew Victord4b77802006-03-24 11:50:17 +02001132 printk(KERN_ERR "at91_ether: no clock defined\n");
1133 return -ENODEV;
1134 }
1135 clk_enable(ether_clk); /* Enable Peripheral clock */
1136
1137 while ((detected != 0) && (phy_address < 32)) {
1138 /* Read the PHY ID registers */
1139 enable_mdi();
1140 read_phy(phy_address, MII_PHYSID1, &phyid1);
1141 read_phy(phy_address, MII_PHYSID2, &phyid2);
1142 disable_mdi();
1143
1144 phy_id = (phyid1 << 16) | (phyid2 & 0xfff0);
1145 switch (phy_id) {
1146 case MII_DM9161_ID: /* Davicom 9161: PHY_ID1 = 0x181, PHY_ID2 = B881 */
1147 case MII_DM9161A_ID: /* Davicom 9161A: PHY_ID1 = 0x181, PHY_ID2 = B8A0 */
1148 case MII_LXT971A_ID: /* Intel LXT971A: PHY_ID1 = 0x13, PHY_ID2 = 78E0 */
1149 case MII_RTL8201_ID: /* Realtek RTL8201: PHY_ID1 = 0, PHY_ID2 = 0x8201 */
1150 case MII_BCM5221_ID: /* Broadcom BCM5221: PHY_ID1 = 0x40, PHY_ID2 = 0x61e0 */
1151 case MII_DP83847_ID: /* National Semiconductor DP83847: */
Andrew Victor6b4aea72007-05-03 09:17:15 +02001152 case MII_DP83848_ID: /* National Semiconductor DP83848: */
Andrew Victord4b77802006-03-24 11:50:17 +02001153 case MII_AC101L_ID: /* Altima AC101L: PHY_ID1 = 0x22, PHY_ID2 = 0x5520 */
1154 case MII_KS8721_ID: /* Micrel KS8721: PHY_ID1 = 0x22, PHY_ID2 = 0x1610 */
Andrew Victor6b4aea72007-05-03 09:17:15 +02001155 case MII_T78Q21x3_ID: /* Teridian 78Q21x3: PHY_ID1 = 0x0E, PHY_ID2 = 7237 */
1156 case MII_LAN83C185_ID: /* SMSC LAN83C185: PHY_ID1 = 0x0007, PHY_ID2 = 0xC0A1 */
Andrew Victor427d2692006-06-20 12:10:57 +02001157 detected = at91ether_setup(phy_id, phy_address, pdev, ether_clk);
Andrew Victord4b77802006-03-24 11:50:17 +02001158 break;
1159 }
1160
1161 phy_address++;
1162 }
1163
1164 clk_disable(ether_clk); /* Disable Peripheral clock */
1165
1166 return detected;
1167}
1168
1169static int __devexit at91ether_remove(struct platform_device *pdev)
1170{
Andrew Victorc57ee092006-12-05 15:09:16 +02001171 struct net_device *dev = platform_get_drvdata(pdev);
1172 struct at91_private *lp = netdev_priv(dev);
Andrew Victord4b77802006-03-24 11:50:17 +02001173
David Brownell71527ef2008-10-27 14:11:34 -07001174 if (lp->board_data.phy_irq_pin >= 32)
1175 gpio_free(lp->board_data.phy_irq_pin);
1176
Andrew Victorc57ee092006-12-05 15:09:16 +02001177 unregister_netdev(dev);
1178 free_irq(dev->irq, dev);
Andrew Victord4b77802006-03-24 11:50:17 +02001179 dma_free_coherent(NULL, sizeof(struct recv_desc_bufs), lp->dlist, (dma_addr_t)lp->dlist_phys);
Andrew Victor427d2692006-06-20 12:10:57 +02001180 clk_put(lp->ether_clk);
Andrew Victord4b77802006-03-24 11:50:17 +02001181
Andrew Victorc57ee092006-12-05 15:09:16 +02001182 platform_set_drvdata(pdev, NULL);
1183 free_netdev(dev);
Andrew Victord4b77802006-03-24 11:50:17 +02001184 return 0;
1185}
1186
Andrew Victor00e5edc2006-06-20 12:19:13 +02001187#ifdef CONFIG_PM
1188
1189static int at91ether_suspend(struct platform_device *pdev, pm_message_t mesg)
1190{
Andrew Victor00e5edc2006-06-20 12:19:13 +02001191 struct net_device *net_dev = platform_get_drvdata(pdev);
Andrew Victorc57ee092006-12-05 15:09:16 +02001192 struct at91_private *lp = netdev_priv(net_dev);
Andrew Victor00e5edc2006-06-20 12:19:13 +02001193 int phy_irq = lp->board_data.phy_irq_pin;
1194
1195 if (netif_running(net_dev)) {
1196 if (phy_irq)
1197 disable_irq(phy_irq);
1198
1199 netif_stop_queue(net_dev);
1200 netif_device_detach(net_dev);
1201
1202 clk_disable(lp->ether_clk);
1203 }
1204 return 0;
1205}
1206
1207static int at91ether_resume(struct platform_device *pdev)
1208{
Andrew Victor00e5edc2006-06-20 12:19:13 +02001209 struct net_device *net_dev = platform_get_drvdata(pdev);
Andrew Victorc57ee092006-12-05 15:09:16 +02001210 struct at91_private *lp = netdev_priv(net_dev);
Andrew Victor00e5edc2006-06-20 12:19:13 +02001211 int phy_irq = lp->board_data.phy_irq_pin;
1212
1213 if (netif_running(net_dev)) {
1214 clk_enable(lp->ether_clk);
1215
1216 netif_device_attach(net_dev);
1217 netif_start_queue(net_dev);
1218
1219 if (phy_irq)
1220 enable_irq(phy_irq);
1221 }
1222 return 0;
1223}
1224
1225#else
1226#define at91ether_suspend NULL
1227#define at91ether_resume NULL
1228#endif
1229
Andrew Victord4b77802006-03-24 11:50:17 +02001230static struct platform_driver at91ether_driver = {
1231 .probe = at91ether_probe,
1232 .remove = __devexit_p(at91ether_remove),
Andrew Victor00e5edc2006-06-20 12:19:13 +02001233 .suspend = at91ether_suspend,
1234 .resume = at91ether_resume,
Andrew Victord4b77802006-03-24 11:50:17 +02001235 .driver = {
1236 .name = DRV_NAME,
1237 .owner = THIS_MODULE,
1238 },
1239};
1240
1241static int __init at91ether_init(void)
1242{
1243 return platform_driver_register(&at91ether_driver);
1244}
1245
1246static void __exit at91ether_exit(void)
1247{
1248 platform_driver_unregister(&at91ether_driver);
1249}
1250
1251module_init(at91ether_init)
1252module_exit(at91ether_exit)
1253
1254MODULE_LICENSE("GPL");
1255MODULE_DESCRIPTION("AT91RM9200 EMAC Ethernet driver");
1256MODULE_AUTHOR("Andrew Victor");
Kay Sievers72abb462008-04-18 13:50:44 -07001257MODULE_ALIAS("platform:" DRV_NAME);