Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
Hirokazu Takata | 3264f97 | 2007-08-01 21:09:31 +0900 | [diff] [blame] | 2 | * linux/arch/m32r/platforms/mappi/setup.c |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3 | * |
| 4 | * Setup routines for Renesas MAPPI Board |
| 5 | * |
Hirokazu Takata | 316240f | 2005-07-07 17:59:32 -0700 | [diff] [blame] | 6 | * Copyright (c) 2001-2005 Hiroyuki Kondo, Hirokazu Takata, |
| 7 | * Hitoshi Yamamoto |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 8 | */ |
| 9 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10 | #include <linux/irq.h> |
| 11 | #include <linux/kernel.h> |
| 12 | #include <linux/init.h> |
Russell King | d052d1b | 2005-10-29 19:07:23 +0100 | [diff] [blame] | 13 | #include <linux/platform_device.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 14 | |
| 15 | #include <asm/system.h> |
| 16 | #include <asm/m32r.h> |
| 17 | #include <asm/io.h> |
| 18 | |
| 19 | #define irq2port(x) (M32R_ICU_CR1_PORTL + ((x - 1) * sizeof(unsigned long))) |
| 20 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 21 | icu_data_t icu_data[NR_IRQS]; |
| 22 | |
| 23 | static void disable_mappi_irq(unsigned int irq) |
| 24 | { |
| 25 | unsigned long port, data; |
| 26 | |
| 27 | port = irq2port(irq); |
| 28 | data = icu_data[irq].icucr|M32R_ICUCR_ILEVEL7; |
| 29 | outl(data, port); |
| 30 | } |
| 31 | |
| 32 | static void enable_mappi_irq(unsigned int irq) |
| 33 | { |
| 34 | unsigned long port, data; |
| 35 | |
| 36 | port = irq2port(irq); |
| 37 | data = icu_data[irq].icucr|M32R_ICUCR_IEN|M32R_ICUCR_ILEVEL6; |
| 38 | outl(data, port); |
| 39 | } |
| 40 | |
Thomas Gleixner | 1f12681 | 2011-01-19 18:27:59 +0100 | [diff] [blame] | 41 | static void mask_mappi(struct irq_data *data) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 42 | { |
Thomas Gleixner | 1f12681 | 2011-01-19 18:27:59 +0100 | [diff] [blame] | 43 | disable_mappi_irq(data->irq); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 44 | } |
| 45 | |
Thomas Gleixner | 1f12681 | 2011-01-19 18:27:59 +0100 | [diff] [blame] | 46 | static void unmask_mappi(struct irq_data *data) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 47 | { |
Thomas Gleixner | 1f12681 | 2011-01-19 18:27:59 +0100 | [diff] [blame] | 48 | enable_mappi_irq(data->irq); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 49 | } |
| 50 | |
Thomas Gleixner | 1f12681 | 2011-01-19 18:27:59 +0100 | [diff] [blame] | 51 | static void shutdown_mappi(struct irq_data *data) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 52 | { |
| 53 | unsigned long port; |
| 54 | |
Thomas Gleixner | 1f12681 | 2011-01-19 18:27:59 +0100 | [diff] [blame] | 55 | port = irq2port(data->irq); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 56 | outl(M32R_ICUCR_ILEVEL7, port); |
| 57 | } |
| 58 | |
Thomas Gleixner | 189e91f | 2009-06-16 15:33:26 -0700 | [diff] [blame] | 59 | static struct irq_chip mappi_irq_type = |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 60 | { |
Thomas Gleixner | 1f12681 | 2011-01-19 18:27:59 +0100 | [diff] [blame] | 61 | .name = "MAPPI-IRQ", |
| 62 | .irq_shutdown = shutdown_mappi, |
| 63 | .irq_mask = mask_mappi, |
| 64 | .irq_unmask = unmask_mappi, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 65 | }; |
| 66 | |
| 67 | void __init init_IRQ(void) |
| 68 | { |
| 69 | static int once = 0; |
| 70 | |
| 71 | if (once) |
| 72 | return; |
| 73 | else |
| 74 | once++; |
| 75 | |
| 76 | #ifdef CONFIG_NE2000 |
| 77 | /* INT0 : LAN controller (RTL8019AS) */ |
Thomas Gleixner | 27e5c5a | 2011-03-24 17:32:45 +0100 | [diff] [blame] | 78 | irq_set_chip_and_handler(M32R_IRQ_INT0, &mappi_irq_type, |
Thomas Gleixner | 1f12681 | 2011-01-19 18:27:59 +0100 | [diff] [blame] | 79 | handle_level_irq); |
Hirokazu Takata | 4fc09385 | 2007-07-26 10:41:19 -0700 | [diff] [blame] | 80 | icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 81 | disable_mappi_irq(M32R_IRQ_INT0); |
| 82 | #endif /* CONFIG_M32R_NE2000 */ |
| 83 | |
| 84 | /* MFT2 : system timer */ |
Thomas Gleixner | 27e5c5a | 2011-03-24 17:32:45 +0100 | [diff] [blame] | 85 | irq_set_chip_and_handler(M32R_IRQ_MFT2, &mappi_irq_type, |
Thomas Gleixner | 1f12681 | 2011-01-19 18:27:59 +0100 | [diff] [blame] | 86 | handle_level_irq); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 87 | icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; |
| 88 | disable_mappi_irq(M32R_IRQ_MFT2); |
| 89 | |
| 90 | #ifdef CONFIG_SERIAL_M32R_SIO |
| 91 | /* SIO0_R : uart receive data */ |
Thomas Gleixner | 27e5c5a | 2011-03-24 17:32:45 +0100 | [diff] [blame] | 92 | irq_set_chip_and_handler(M32R_IRQ_SIO0_R, &mappi_irq_type, |
Thomas Gleixner | 1f12681 | 2011-01-19 18:27:59 +0100 | [diff] [blame] | 93 | handle_level_irq); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 94 | icu_data[M32R_IRQ_SIO0_R].icucr = 0; |
| 95 | disable_mappi_irq(M32R_IRQ_SIO0_R); |
| 96 | |
| 97 | /* SIO0_S : uart send data */ |
Thomas Gleixner | 27e5c5a | 2011-03-24 17:32:45 +0100 | [diff] [blame] | 98 | irq_set_chip_and_handler(M32R_IRQ_SIO0_S, &mappi_irq_type, |
Thomas Gleixner | 1f12681 | 2011-01-19 18:27:59 +0100 | [diff] [blame] | 99 | handle_level_irq); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 100 | icu_data[M32R_IRQ_SIO0_S].icucr = 0; |
| 101 | disable_mappi_irq(M32R_IRQ_SIO0_S); |
| 102 | |
| 103 | /* SIO1_R : uart receive data */ |
Thomas Gleixner | 27e5c5a | 2011-03-24 17:32:45 +0100 | [diff] [blame] | 104 | irq_set_chip_and_handler(M32R_IRQ_SIO1_R, &mappi_irq_type, |
Thomas Gleixner | 1f12681 | 2011-01-19 18:27:59 +0100 | [diff] [blame] | 105 | handle_level_irq); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 106 | icu_data[M32R_IRQ_SIO1_R].icucr = 0; |
| 107 | disable_mappi_irq(M32R_IRQ_SIO1_R); |
| 108 | |
| 109 | /* SIO1_S : uart send data */ |
Thomas Gleixner | 27e5c5a | 2011-03-24 17:32:45 +0100 | [diff] [blame] | 110 | irq_set_chip_and_handler(M32R_IRQ_SIO1_S, &mappi_irq_type, |
Thomas Gleixner | 1f12681 | 2011-01-19 18:27:59 +0100 | [diff] [blame] | 111 | handle_level_irq); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 112 | icu_data[M32R_IRQ_SIO1_S].icucr = 0; |
| 113 | disable_mappi_irq(M32R_IRQ_SIO1_S); |
| 114 | #endif /* CONFIG_SERIAL_M32R_SIO */ |
| 115 | |
| 116 | #if defined(CONFIG_M32R_PCC) |
| 117 | /* INT1 : pccard0 interrupt */ |
Thomas Gleixner | 27e5c5a | 2011-03-24 17:32:45 +0100 | [diff] [blame] | 118 | irq_set_chip_and_handler(M32R_IRQ_INT1, &mappi_irq_type, |
Thomas Gleixner | 1f12681 | 2011-01-19 18:27:59 +0100 | [diff] [blame] | 119 | handle_level_irq); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 120 | icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD00; |
| 121 | disable_mappi_irq(M32R_IRQ_INT1); |
| 122 | |
| 123 | /* INT2 : pccard1 interrupt */ |
Thomas Gleixner | 27e5c5a | 2011-03-24 17:32:45 +0100 | [diff] [blame] | 124 | irq_set_chip_and_handler(M32R_IRQ_INT2, &mappi_irq_type, |
Thomas Gleixner | 1f12681 | 2011-01-19 18:27:59 +0100 | [diff] [blame] | 125 | handle_level_irq); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 126 | icu_data[M32R_IRQ_INT2].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD00; |
| 127 | disable_mappi_irq(M32R_IRQ_INT2); |
| 128 | #endif /* CONFIG_M32RPCC */ |
| 129 | } |
Hirokazu Takata | 316240f | 2005-07-07 17:59:32 -0700 | [diff] [blame] | 130 | |
| 131 | #if defined(CONFIG_FB_S1D13XXX) |
| 132 | |
| 133 | #include <video/s1d13xxxfb.h> |
| 134 | #include <asm/s1d13806.h> |
| 135 | |
| 136 | static struct s1d13xxxfb_pdata s1d13xxxfb_data = { |
| 137 | .initregs = s1d13xxxfb_initregs, |
| 138 | .initregssize = ARRAY_SIZE(s1d13xxxfb_initregs), |
| 139 | .platform_init_video = NULL, |
| 140 | #ifdef CONFIG_PM |
| 141 | .platform_suspend_video = NULL, |
| 142 | .platform_resume_video = NULL, |
| 143 | #endif |
| 144 | }; |
| 145 | |
| 146 | static struct resource s1d13xxxfb_resources[] = { |
| 147 | [0] = { |
| 148 | .start = 0x10200000UL, |
| 149 | .end = 0x1033FFFFUL, |
| 150 | .flags = IORESOURCE_MEM, |
| 151 | }, |
| 152 | [1] = { |
| 153 | .start = 0x10000000UL, |
| 154 | .end = 0x100001FFUL, |
| 155 | .flags = IORESOURCE_MEM, |
| 156 | } |
| 157 | }; |
| 158 | |
| 159 | static struct platform_device s1d13xxxfb_device = { |
| 160 | .name = S1D_DEVICENAME, |
| 161 | .id = 0, |
| 162 | .dev = { |
| 163 | .platform_data = &s1d13xxxfb_data, |
| 164 | }, |
| 165 | .num_resources = ARRAY_SIZE(s1d13xxxfb_resources), |
| 166 | .resource = s1d13xxxfb_resources, |
| 167 | }; |
| 168 | |
| 169 | static int __init platform_init(void) |
| 170 | { |
| 171 | platform_device_register(&s1d13xxxfb_device); |
| 172 | return 0; |
| 173 | } |
| 174 | arch_initcall(platform_init); |
| 175 | #endif |