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Juergen Beisert07bd1a62008-07-05 10:02:49 +02001/*
2 * MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
4 *
5 * Based on code from Freescale,
Dinh Nguyene24798e2010-04-22 16:28:42 +03006 * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
Juergen Beisert07bd1a62008-07-05 10:02:49 +02007 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version 2
11 * of the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
20 */
21
22#include <linux/init.h>
Dinh Nguyena3484ff2010-10-23 09:12:48 -050023#include <linux/interrupt.h>
Juergen Beisert07bd1a62008-07-05 10:02:49 +020024#include <linux/io.h>
25#include <linux/irq.h>
Shawn Guo1ab7ef12012-06-13 09:04:03 +080026#include <linux/irqdomain.h>
Juergen Beisert07bd1a62008-07-05 10:02:49 +020027#include <linux/gpio.h>
Shawn Guob78d8e52011-06-06 00:07:55 +080028#include <linux/platform_device.h>
29#include <linux/slab.h>
Shawn Guo2ce420d2011-06-06 13:22:41 +080030#include <linux/basic_mmio_gpio.h>
Shawn Guo8937cb62011-07-07 00:37:43 +080031#include <linux/of.h>
32#include <linux/of_device.h>
Paul Gortmakerbb207ef2011-07-03 13:38:09 -040033#include <linux/module.h>
Juergen Beisert07bd1a62008-07-05 10:02:49 +020034#include <asm-generic/bug.h>
Shawn Guo0e44b6e2011-09-21 21:24:04 +080035#include <asm/mach/irq.h>
Juergen Beisert07bd1a62008-07-05 10:02:49 +020036
Shawn Guoe7fc6ae2011-07-07 00:37:41 +080037enum mxc_gpio_hwtype {
38 IMX1_GPIO, /* runs on i.mx1 */
39 IMX21_GPIO, /* runs on i.mx21 and i.mx27 */
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +020040 IMX31_GPIO, /* runs on i.mx31 */
41 IMX35_GPIO, /* runs on all other i.mx */
Shawn Guoe7fc6ae2011-07-07 00:37:41 +080042};
43
44/* device type dependent stuff */
45struct mxc_gpio_hwdata {
46 unsigned dr_reg;
47 unsigned gdir_reg;
48 unsigned psr_reg;
49 unsigned icr1_reg;
50 unsigned icr2_reg;
51 unsigned imr_reg;
52 unsigned isr_reg;
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +020053 int edge_sel_reg;
Shawn Guoe7fc6ae2011-07-07 00:37:41 +080054 unsigned low_level;
55 unsigned high_level;
56 unsigned rise_edge;
57 unsigned fall_edge;
58};
59
Shawn Guob78d8e52011-06-06 00:07:55 +080060struct mxc_gpio_port {
61 struct list_head node;
62 void __iomem *base;
63 int irq;
64 int irq_high;
Shawn Guo1ab7ef12012-06-13 09:04:03 +080065 struct irq_domain *domain;
Shawn Guo2ce420d2011-06-06 13:22:41 +080066 struct bgpio_chip bgc;
Shawn Guob78d8e52011-06-06 00:07:55 +080067 u32 both_edges;
Shawn Guob78d8e52011-06-06 00:07:55 +080068};
69
Shawn Guoe7fc6ae2011-07-07 00:37:41 +080070static struct mxc_gpio_hwdata imx1_imx21_gpio_hwdata = {
71 .dr_reg = 0x1c,
72 .gdir_reg = 0x00,
73 .psr_reg = 0x24,
74 .icr1_reg = 0x28,
75 .icr2_reg = 0x2c,
76 .imr_reg = 0x30,
77 .isr_reg = 0x34,
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +020078 .edge_sel_reg = -EINVAL,
Shawn Guoe7fc6ae2011-07-07 00:37:41 +080079 .low_level = 0x03,
80 .high_level = 0x02,
81 .rise_edge = 0x00,
82 .fall_edge = 0x01,
83};
84
85static struct mxc_gpio_hwdata imx31_gpio_hwdata = {
86 .dr_reg = 0x00,
87 .gdir_reg = 0x04,
88 .psr_reg = 0x08,
89 .icr1_reg = 0x0c,
90 .icr2_reg = 0x10,
91 .imr_reg = 0x14,
92 .isr_reg = 0x18,
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +020093 .edge_sel_reg = -EINVAL,
94 .low_level = 0x00,
95 .high_level = 0x01,
96 .rise_edge = 0x02,
97 .fall_edge = 0x03,
98};
99
100static struct mxc_gpio_hwdata imx35_gpio_hwdata = {
101 .dr_reg = 0x00,
102 .gdir_reg = 0x04,
103 .psr_reg = 0x08,
104 .icr1_reg = 0x0c,
105 .icr2_reg = 0x10,
106 .imr_reg = 0x14,
107 .isr_reg = 0x18,
108 .edge_sel_reg = 0x1c,
Shawn Guoe7fc6ae2011-07-07 00:37:41 +0800109 .low_level = 0x00,
110 .high_level = 0x01,
111 .rise_edge = 0x02,
112 .fall_edge = 0x03,
113};
114
115static enum mxc_gpio_hwtype mxc_gpio_hwtype;
116static struct mxc_gpio_hwdata *mxc_gpio_hwdata;
117
118#define GPIO_DR (mxc_gpio_hwdata->dr_reg)
119#define GPIO_GDIR (mxc_gpio_hwdata->gdir_reg)
120#define GPIO_PSR (mxc_gpio_hwdata->psr_reg)
121#define GPIO_ICR1 (mxc_gpio_hwdata->icr1_reg)
122#define GPIO_ICR2 (mxc_gpio_hwdata->icr2_reg)
123#define GPIO_IMR (mxc_gpio_hwdata->imr_reg)
124#define GPIO_ISR (mxc_gpio_hwdata->isr_reg)
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200125#define GPIO_EDGE_SEL (mxc_gpio_hwdata->edge_sel_reg)
Shawn Guoe7fc6ae2011-07-07 00:37:41 +0800126
127#define GPIO_INT_LOW_LEV (mxc_gpio_hwdata->low_level)
128#define GPIO_INT_HIGH_LEV (mxc_gpio_hwdata->high_level)
129#define GPIO_INT_RISE_EDGE (mxc_gpio_hwdata->rise_edge)
130#define GPIO_INT_FALL_EDGE (mxc_gpio_hwdata->fall_edge)
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200131#define GPIO_INT_BOTH_EDGES 0x4
Shawn Guoe7fc6ae2011-07-07 00:37:41 +0800132
133static struct platform_device_id mxc_gpio_devtype[] = {
134 {
135 .name = "imx1-gpio",
136 .driver_data = IMX1_GPIO,
137 }, {
138 .name = "imx21-gpio",
139 .driver_data = IMX21_GPIO,
140 }, {
141 .name = "imx31-gpio",
142 .driver_data = IMX31_GPIO,
143 }, {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200144 .name = "imx35-gpio",
145 .driver_data = IMX35_GPIO,
146 }, {
Shawn Guoe7fc6ae2011-07-07 00:37:41 +0800147 /* sentinel */
148 }
149};
150
Shawn Guo8937cb62011-07-07 00:37:43 +0800151static const struct of_device_id mxc_gpio_dt_ids[] = {
152 { .compatible = "fsl,imx1-gpio", .data = &mxc_gpio_devtype[IMX1_GPIO], },
153 { .compatible = "fsl,imx21-gpio", .data = &mxc_gpio_devtype[IMX21_GPIO], },
154 { .compatible = "fsl,imx31-gpio", .data = &mxc_gpio_devtype[IMX31_GPIO], },
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200155 { .compatible = "fsl,imx35-gpio", .data = &mxc_gpio_devtype[IMX35_GPIO], },
Shawn Guo8937cb62011-07-07 00:37:43 +0800156 { /* sentinel */ }
157};
158
Shawn Guob78d8e52011-06-06 00:07:55 +0800159/*
160 * MX2 has one interrupt *for all* gpio ports. The list is used
161 * to save the references to all ports, so that mx2_gpio_irq_handler
162 * can walk through all interrupt status registers.
163 */
164static LIST_HEAD(mxc_gpio_ports);
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200165
166/* Note: This driver assumes 32 GPIOs are handled in one register */
167
Lennert Buytenhek4d935792010-11-29 11:16:23 +0100168static int gpio_set_irq_type(struct irq_data *d, u32 type)
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200169{
Shawn Guoe4ea9332011-06-07 16:25:37 +0800170 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
171 struct mxc_gpio_port *port = gc->private;
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200172 u32 bit, val;
Shawn Guo1ab7ef12012-06-13 09:04:03 +0800173 u32 gpio_idx = d->hwirq;
174 u32 gpio = port->bgc.gc.base + gpio_idx;
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200175 int edge;
176 void __iomem *reg = port->base;
177
Shawn Guo1ab7ef12012-06-13 09:04:03 +0800178 port->both_edges &= ~(1 << gpio_idx);
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200179 switch (type) {
Dmitry Baryshkov6cab4862008-07-27 04:23:31 +0100180 case IRQ_TYPE_EDGE_RISING:
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200181 edge = GPIO_INT_RISE_EDGE;
182 break;
Dmitry Baryshkov6cab4862008-07-27 04:23:31 +0100183 case IRQ_TYPE_EDGE_FALLING:
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200184 edge = GPIO_INT_FALL_EDGE;
185 break;
Guennadi Liakhovetski910862e2009-03-12 12:46:41 +0100186 case IRQ_TYPE_EDGE_BOTH:
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200187 if (GPIO_EDGE_SEL >= 0) {
188 edge = GPIO_INT_BOTH_EDGES;
Guennadi Liakhovetski910862e2009-03-12 12:46:41 +0100189 } else {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200190 val = gpio_get_value(gpio);
191 if (val) {
192 edge = GPIO_INT_LOW_LEV;
193 pr_debug("mxc: set GPIO %d to low trigger\n", gpio);
194 } else {
195 edge = GPIO_INT_HIGH_LEV;
196 pr_debug("mxc: set GPIO %d to high trigger\n", gpio);
197 }
Linus Torvaldsf948ad02012-07-26 13:56:38 -0700198 port->both_edges |= 1 << gpio_idx;
Guennadi Liakhovetski910862e2009-03-12 12:46:41 +0100199 }
Guennadi Liakhovetski910862e2009-03-12 12:46:41 +0100200 break;
Dmitry Baryshkov6cab4862008-07-27 04:23:31 +0100201 case IRQ_TYPE_LEVEL_LOW:
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200202 edge = GPIO_INT_LOW_LEV;
203 break;
Dmitry Baryshkov6cab4862008-07-27 04:23:31 +0100204 case IRQ_TYPE_LEVEL_HIGH:
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200205 edge = GPIO_INT_HIGH_LEV;
206 break;
Guennadi Liakhovetski910862e2009-03-12 12:46:41 +0100207 default:
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200208 return -EINVAL;
209 }
210
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200211 if (GPIO_EDGE_SEL >= 0) {
212 val = readl(port->base + GPIO_EDGE_SEL);
213 if (edge == GPIO_INT_BOTH_EDGES)
Linus Torvaldsf948ad02012-07-26 13:56:38 -0700214 writel(val | (1 << gpio_idx),
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200215 port->base + GPIO_EDGE_SEL);
216 else
Linus Torvaldsf948ad02012-07-26 13:56:38 -0700217 writel(val & ~(1 << gpio_idx),
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200218 port->base + GPIO_EDGE_SEL);
219 }
220
221 if (edge != GPIO_INT_BOTH_EDGES) {
Linus Torvaldsf948ad02012-07-26 13:56:38 -0700222 reg += GPIO_ICR1 + ((gpio_idx & 0x10) >> 2); /* lower or upper register */
223 bit = gpio_idx & 0xf;
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200224 val = readl(reg) & ~(0x3 << (bit << 1));
225 writel(val | (edge << (bit << 1)), reg);
226 }
227
Shawn Guo1ab7ef12012-06-13 09:04:03 +0800228 writel(1 << gpio_idx, port->base + GPIO_ISR);
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200229
230 return 0;
231}
232
Guennadi Liakhovetski910862e2009-03-12 12:46:41 +0100233static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio)
234{
235 void __iomem *reg = port->base;
236 u32 bit, val;
237 int edge;
238
239 reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */
240 bit = gpio & 0xf;
Shawn Guob78d8e52011-06-06 00:07:55 +0800241 val = readl(reg);
Guennadi Liakhovetski910862e2009-03-12 12:46:41 +0100242 edge = (val >> (bit << 1)) & 3;
243 val &= ~(0x3 << (bit << 1));
Uwe Kleine-König3d40f7f2010-02-05 22:14:37 +0100244 if (edge == GPIO_INT_HIGH_LEV) {
Guennadi Liakhovetski910862e2009-03-12 12:46:41 +0100245 edge = GPIO_INT_LOW_LEV;
246 pr_debug("mxc: switch GPIO %d to low trigger\n", gpio);
Uwe Kleine-König3d40f7f2010-02-05 22:14:37 +0100247 } else if (edge == GPIO_INT_LOW_LEV) {
Guennadi Liakhovetski910862e2009-03-12 12:46:41 +0100248 edge = GPIO_INT_HIGH_LEV;
249 pr_debug("mxc: switch GPIO %d to high trigger\n", gpio);
Uwe Kleine-König3d40f7f2010-02-05 22:14:37 +0100250 } else {
Guennadi Liakhovetski910862e2009-03-12 12:46:41 +0100251 pr_err("mxc: invalid configuration for GPIO %d: %x\n",
252 gpio, edge);
253 return;
254 }
Shawn Guob78d8e52011-06-06 00:07:55 +0800255 writel(val | (edge << (bit << 1)), reg);
Guennadi Liakhovetski910862e2009-03-12 12:46:41 +0100256}
257
Uwe Kleine-König3621f182010-02-08 21:02:30 +0100258/* handle 32 interrupts in one status register */
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200259static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat)
260{
Uwe Kleine-König3621f182010-02-08 21:02:30 +0100261 while (irq_stat != 0) {
262 int irqoffset = fls(irq_stat) - 1;
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200263
Uwe Kleine-König3621f182010-02-08 21:02:30 +0100264 if (port->both_edges & (1 << irqoffset))
265 mxc_flip_edge(port, irqoffset);
Guennadi Liakhovetski910862e2009-03-12 12:46:41 +0100266
Shawn Guo1ab7ef12012-06-13 09:04:03 +0800267 generic_handle_irq(irq_find_mapping(port->domain, irqoffset));
Guennadi Liakhovetski910862e2009-03-12 12:46:41 +0100268
Uwe Kleine-König3621f182010-02-08 21:02:30 +0100269 irq_stat &= ~(1 << irqoffset);
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200270 }
271}
272
Paulius Zaleckascfca8b52008-11-14 11:01:38 +0100273/* MX1 and MX3 has one interrupt *per* gpio port */
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200274static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc)
275{
276 u32 irq_stat;
Thomas Gleixner6845664a2011-03-24 13:25:22 +0100277 struct mxc_gpio_port *port = irq_get_handler_data(irq);
Shawn Guo0e44b6e2011-09-21 21:24:04 +0800278 struct irq_chip *chip = irq_get_chip(irq);
279
280 chained_irq_enter(chip, desc);
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200281
Shawn Guob78d8e52011-06-06 00:07:55 +0800282 irq_stat = readl(port->base + GPIO_ISR) & readl(port->base + GPIO_IMR);
Sascha Hauere2c97e72009-04-21 12:39:59 +0200283
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200284 mxc_gpio_irq_handler(port, irq_stat);
Shawn Guo0e44b6e2011-09-21 21:24:04 +0800285
286 chained_irq_exit(chip, desc);
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200287}
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200288
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200289/* MX2 has one interrupt *for all* gpio ports */
290static void mx2_gpio_irq_handler(u32 irq, struct irq_desc *desc)
291{
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200292 u32 irq_msk, irq_stat;
Shawn Guob78d8e52011-06-06 00:07:55 +0800293 struct mxc_gpio_port *port;
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200294
295 /* walk through all interrupt status registers */
Shawn Guob78d8e52011-06-06 00:07:55 +0800296 list_for_each_entry(port, &mxc_gpio_ports, node) {
297 irq_msk = readl(port->base + GPIO_IMR);
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200298 if (!irq_msk)
299 continue;
300
Shawn Guob78d8e52011-06-06 00:07:55 +0800301 irq_stat = readl(port->base + GPIO_ISR) & irq_msk;
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200302 if (irq_stat)
Shawn Guob78d8e52011-06-06 00:07:55 +0800303 mxc_gpio_irq_handler(port, irq_stat);
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200304 }
305}
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200306
Dinh Nguyena3484ff2010-10-23 09:12:48 -0500307/*
308 * Set interrupt number "irq" in the GPIO as a wake-up source.
309 * While system is running, all registered GPIO interrupts need to have
310 * wake-up enabled. When system is suspended, only selected GPIO interrupts
311 * need to have wake-up enabled.
312 * @param irq interrupt source number
313 * @param enable enable as wake-up if equal to non-zero
314 * @return This function returns 0 on success.
315 */
Lennert Buytenhek4d935792010-11-29 11:16:23 +0100316static int gpio_set_wake_irq(struct irq_data *d, u32 enable)
Dinh Nguyena3484ff2010-10-23 09:12:48 -0500317{
Shawn Guoe4ea9332011-06-07 16:25:37 +0800318 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
319 struct mxc_gpio_port *port = gc->private;
Shawn Guo1ab7ef12012-06-13 09:04:03 +0800320 u32 gpio_idx = d->hwirq;
Dinh Nguyena3484ff2010-10-23 09:12:48 -0500321
322 if (enable) {
323 if (port->irq_high && (gpio_idx >= 16))
324 enable_irq_wake(port->irq_high);
325 else
326 enable_irq_wake(port->irq);
327 } else {
328 if (port->irq_high && (gpio_idx >= 16))
329 disable_irq_wake(port->irq_high);
330 else
331 disable_irq_wake(port->irq);
332 }
333
334 return 0;
335}
336
Shawn Guo1ab7ef12012-06-13 09:04:03 +0800337static void __init mxc_gpio_init_gc(struct mxc_gpio_port *port, int irq_base)
Shawn Guoe4ea9332011-06-07 16:25:37 +0800338{
339 struct irq_chip_generic *gc;
340 struct irq_chip_type *ct;
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200341
Shawn Guo1ab7ef12012-06-13 09:04:03 +0800342 gc = irq_alloc_generic_chip("gpio-mxc", 1, irq_base,
Shawn Guoe4ea9332011-06-07 16:25:37 +0800343 port->base, handle_level_irq);
344 gc->private = port;
345
346 ct = gc->chip_types;
Shawn Guo591567a2011-07-19 21:16:56 +0800347 ct->chip.irq_ack = irq_gc_ack_set_bit;
Shawn Guoe4ea9332011-06-07 16:25:37 +0800348 ct->chip.irq_mask = irq_gc_mask_clr_bit;
349 ct->chip.irq_unmask = irq_gc_mask_set_bit;
350 ct->chip.irq_set_type = gpio_set_irq_type;
Shawn Guo591567a2011-07-19 21:16:56 +0800351 ct->chip.irq_set_wake = gpio_set_wake_irq;
Shawn Guoe4ea9332011-06-07 16:25:37 +0800352 ct->regs.ack = GPIO_ISR;
353 ct->regs.mask = GPIO_IMR;
354
355 irq_setup_generic_chip(gc, IRQ_MSK(32), IRQ_GC_INIT_NESTED_LOCK,
356 IRQ_NOREQUEST, 0);
357}
Thomas Gleixnerb5eee2f2011-04-04 14:29:58 +0200358
Shawn Guoe7fc6ae2011-07-07 00:37:41 +0800359static void __devinit mxc_gpio_get_hw(struct platform_device *pdev)
360{
Shawn Guo8937cb62011-07-07 00:37:43 +0800361 const struct of_device_id *of_id =
362 of_match_device(mxc_gpio_dt_ids, &pdev->dev);
363 enum mxc_gpio_hwtype hwtype;
364
365 if (of_id)
366 pdev->id_entry = of_id->data;
367 hwtype = pdev->id_entry->driver_data;
Shawn Guoe7fc6ae2011-07-07 00:37:41 +0800368
369 if (mxc_gpio_hwtype) {
370 /*
371 * The driver works with a reasonable presupposition,
372 * that is all gpio ports must be the same type when
373 * running on one soc.
374 */
375 BUG_ON(mxc_gpio_hwtype != hwtype);
376 return;
377 }
378
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200379 if (hwtype == IMX35_GPIO)
380 mxc_gpio_hwdata = &imx35_gpio_hwdata;
381 else if (hwtype == IMX31_GPIO)
Shawn Guoe7fc6ae2011-07-07 00:37:41 +0800382 mxc_gpio_hwdata = &imx31_gpio_hwdata;
383 else
384 mxc_gpio_hwdata = &imx1_imx21_gpio_hwdata;
385
386 mxc_gpio_hwtype = hwtype;
387}
388
Shawn Guo09ad8032011-08-14 00:14:02 +0800389static int mxc_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
390{
391 struct bgpio_chip *bgc = to_bgpio_chip(gc);
392 struct mxc_gpio_port *port =
393 container_of(bgc, struct mxc_gpio_port, bgc);
394
Shawn Guo1ab7ef12012-06-13 09:04:03 +0800395 return irq_find_mapping(port->domain, offset);
Shawn Guo09ad8032011-08-14 00:14:02 +0800396}
397
Shawn Guob78d8e52011-06-06 00:07:55 +0800398static int __devinit mxc_gpio_probe(struct platform_device *pdev)
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200399{
Shawn Guo8937cb62011-07-07 00:37:43 +0800400 struct device_node *np = pdev->dev.of_node;
Shawn Guob78d8e52011-06-06 00:07:55 +0800401 struct mxc_gpio_port *port;
402 struct resource *iores;
Shawn Guo1ab7ef12012-06-13 09:04:03 +0800403 int irq_base;
Shawn Guoe4ea9332011-06-07 16:25:37 +0800404 int err;
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200405
Shawn Guoe7fc6ae2011-07-07 00:37:41 +0800406 mxc_gpio_get_hw(pdev);
407
Shawn Guob78d8e52011-06-06 00:07:55 +0800408 port = kzalloc(sizeof(struct mxc_gpio_port), GFP_KERNEL);
409 if (!port)
410 return -ENOMEM;
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200411
Shawn Guob78d8e52011-06-06 00:07:55 +0800412 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
413 if (!iores) {
414 err = -ENODEV;
415 goto out_kfree;
416 }
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200417
Shawn Guob78d8e52011-06-06 00:07:55 +0800418 if (!request_mem_region(iores->start, resource_size(iores),
419 pdev->name)) {
420 err = -EBUSY;
421 goto out_kfree;
422 }
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200423
Shawn Guob78d8e52011-06-06 00:07:55 +0800424 port->base = ioremap(iores->start, resource_size(iores));
425 if (!port->base) {
426 err = -ENOMEM;
427 goto out_release_mem;
428 }
Baruch Siach14cb0de2010-07-06 14:03:22 +0300429
Shawn Guob78d8e52011-06-06 00:07:55 +0800430 port->irq_high = platform_get_irq(pdev, 1);
431 port->irq = platform_get_irq(pdev, 0);
432 if (port->irq < 0) {
433 err = -EINVAL;
434 goto out_iounmap;
435 }
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200436
Shawn Guob78d8e52011-06-06 00:07:55 +0800437 /* disable the interrupt and clear the status */
438 writel(0, port->base + GPIO_IMR);
439 writel(~0, port->base + GPIO_ISR);
440
Shawn Guoe7fc6ae2011-07-07 00:37:41 +0800441 if (mxc_gpio_hwtype == IMX21_GPIO) {
Uwe Kleine-König33a4e982012-06-06 11:49:23 +0200442 /*
443 * Setup one handler for all GPIO interrupts. Actually setting
444 * the handler is needed only once, but doing it for every port
445 * is more robust and easier.
446 */
447 irq_set_chained_handler(port->irq, mx2_gpio_irq_handler);
Shawn Guob78d8e52011-06-06 00:07:55 +0800448 } else {
449 /* setup one handler for each entry */
450 irq_set_chained_handler(port->irq, mx3_gpio_irq_handler);
451 irq_set_handler_data(port->irq, port);
452 if (port->irq_high > 0) {
453 /* setup handler for GPIO 16 to 31 */
454 irq_set_chained_handler(port->irq_high,
455 mx3_gpio_irq_handler);
456 irq_set_handler_data(port->irq_high, port);
457 }
Sascha Hauer8afaada2009-06-15 12:36:25 +0200458 }
459
Shawn Guo2ce420d2011-06-06 13:22:41 +0800460 err = bgpio_init(&port->bgc, &pdev->dev, 4,
461 port->base + GPIO_PSR,
462 port->base + GPIO_DR, NULL,
Shawn Guo3e11f7b2012-05-19 21:34:58 +0800463 port->base + GPIO_GDIR, NULL, 0);
Shawn Guob78d8e52011-06-06 00:07:55 +0800464 if (err)
465 goto out_iounmap;
466
Shawn Guo09ad8032011-08-14 00:14:02 +0800467 port->bgc.gc.to_irq = mxc_gpio_to_irq;
Shawn Guo7e6086d2012-08-05 14:01:26 +0800468 port->bgc.gc.base = (pdev->id < 0) ? of_alias_get_id(np, "gpio") * 32 :
469 pdev->id * 32;
Shawn Guo2ce420d2011-06-06 13:22:41 +0800470
471 err = gpiochip_add(&port->bgc.gc);
472 if (err)
473 goto out_bgpio_remove;
474
Shawn Guo1ab7ef12012-06-13 09:04:03 +0800475 irq_base = irq_alloc_descs(-1, 0, 32, numa_node_id());
476 if (irq_base < 0) {
477 err = irq_base;
478 goto out_gpiochip_remove;
479 }
480
481 port->domain = irq_domain_add_legacy(np, 32, irq_base, 0,
482 &irq_domain_simple_ops, NULL);
483 if (!port->domain) {
484 err = -ENODEV;
485 goto out_irqdesc_free;
486 }
Shawn Guo8937cb62011-07-07 00:37:43 +0800487
488 /* gpio-mxc can be a generic irq chip */
Shawn Guo1ab7ef12012-06-13 09:04:03 +0800489 mxc_gpio_init_gc(port, irq_base);
Shawn Guo8937cb62011-07-07 00:37:43 +0800490
Shawn Guob78d8e52011-06-06 00:07:55 +0800491 list_add_tail(&port->node, &mxc_gpio_ports);
492
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200493 return 0;
Shawn Guob78d8e52011-06-06 00:07:55 +0800494
Shawn Guo1ab7ef12012-06-13 09:04:03 +0800495out_irqdesc_free:
496 irq_free_descs(irq_base, 32);
497out_gpiochip_remove:
498 WARN_ON(gpiochip_remove(&port->bgc.gc) < 0);
Shawn Guo2ce420d2011-06-06 13:22:41 +0800499out_bgpio_remove:
500 bgpio_remove(&port->bgc);
Shawn Guob78d8e52011-06-06 00:07:55 +0800501out_iounmap:
502 iounmap(port->base);
503out_release_mem:
504 release_mem_region(iores->start, resource_size(iores));
505out_kfree:
506 kfree(port);
507 dev_info(&pdev->dev, "%s failed with errno %d\n", __func__, err);
508 return err;
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200509}
Shawn Guob78d8e52011-06-06 00:07:55 +0800510
511static struct platform_driver mxc_gpio_driver = {
512 .driver = {
513 .name = "gpio-mxc",
514 .owner = THIS_MODULE,
Shawn Guo8937cb62011-07-07 00:37:43 +0800515 .of_match_table = mxc_gpio_dt_ids,
Shawn Guob78d8e52011-06-06 00:07:55 +0800516 },
517 .probe = mxc_gpio_probe,
Shawn Guoe7fc6ae2011-07-07 00:37:41 +0800518 .id_table = mxc_gpio_devtype,
Shawn Guob78d8e52011-06-06 00:07:55 +0800519};
520
521static int __init gpio_mxc_init(void)
522{
523 return platform_driver_register(&mxc_gpio_driver);
524}
525postcore_initcall(gpio_mxc_init);
526
527MODULE_AUTHOR("Freescale Semiconductor, "
528 "Daniel Mack <danielncaiaq.de>, "
529 "Juergen Beisert <kernel@pengutronix.de>");
530MODULE_DESCRIPTION("Freescale MXC GPIO");
531MODULE_LICENSE("GPL");