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Carsten Otte043405e2007-10-10 17:16:19 +02001#/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This header defines architecture specific interfaces, x86 version
5 *
6 * This work is licensed under the terms of the GNU GPL, version 2. See
7 * the COPYING file in the top-level directory.
8 *
9 */
10
11#ifndef KVM_X86_H
12#define KVM_X86_H
13
14#include "kvm.h"
15
Zhang Xiantao34c16ee2007-10-20 15:34:38 +080016#include <linux/types.h>
17#include <linux/mm.h>
18
19#include <linux/kvm.h>
20#include <linux/kvm_para.h>
21
Zhang Xiantaocd6e8f82007-11-19 14:33:37 +080022#define CR3_PAE_RESERVED_BITS ((X86_CR3_PWT | X86_CR3_PCD) - 1)
23#define CR3_NONPAE_RESERVED_BITS ((PAGE_SIZE-1) & ~(X86_CR3_PWT | X86_CR3_PCD))
24#define CR3_L_MODE_RESERVED_BITS (CR3_NONPAE_RESERVED_BITS|0xFFFFFF0000000000ULL)
25
26#define KVM_GUEST_CR0_MASK \
27 (X86_CR0_PG | X86_CR0_PE | X86_CR0_WP | X86_CR0_NE \
28 | X86_CR0_NW | X86_CR0_CD)
29#define KVM_VM_CR0_ALWAYS_ON \
30 (X86_CR0_PG | X86_CR0_PE | X86_CR0_WP | X86_CR0_NE | X86_CR0_TS \
31 | X86_CR0_MP)
32#define KVM_GUEST_CR4_MASK \
33 (X86_CR4_VME | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_PGE | X86_CR4_VMXE)
34#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
35#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
36
37#define INVALID_PAGE (~(hpa_t)0)
38#define UNMAPPED_GVA (~(gpa_t)0)
39
40#define DE_VECTOR 0
41#define UD_VECTOR 6
42#define NM_VECTOR 7
43#define DF_VECTOR 8
44#define TS_VECTOR 10
45#define NP_VECTOR 11
46#define SS_VECTOR 12
47#define GP_VECTOR 13
48#define PF_VECTOR 14
49
50#define SELECTOR_TI_MASK (1 << 2)
51#define SELECTOR_RPL_MASK 0x03
52
53#define IOPL_SHIFT 12
54
Zhang Xiantaoe9b11c12007-11-14 20:38:21 +080055extern spinlock_t kvm_lock;
56extern struct list_head vm_list;
57
Zhang Xiantao2b3ccfa2007-11-19 14:56:05 +080058enum {
59 VCPU_REGS_RAX = 0,
60 VCPU_REGS_RCX = 1,
61 VCPU_REGS_RDX = 2,
62 VCPU_REGS_RBX = 3,
63 VCPU_REGS_RSP = 4,
64 VCPU_REGS_RBP = 5,
65 VCPU_REGS_RSI = 6,
66 VCPU_REGS_RDI = 7,
67#ifdef CONFIG_X86_64
68 VCPU_REGS_R8 = 8,
69 VCPU_REGS_R9 = 9,
70 VCPU_REGS_R10 = 10,
71 VCPU_REGS_R11 = 11,
72 VCPU_REGS_R12 = 12,
73 VCPU_REGS_R13 = 13,
74 VCPU_REGS_R14 = 14,
75 VCPU_REGS_R15 = 15,
76#endif
77 NR_VCPU_REGS
78};
79
80enum {
81 VCPU_SREG_CS,
82 VCPU_SREG_DS,
83 VCPU_SREG_ES,
84 VCPU_SREG_FS,
85 VCPU_SREG_GS,
86 VCPU_SREG_SS,
87 VCPU_SREG_TR,
88 VCPU_SREG_LDTR,
89};
90
91#include "x86_emulate.h"
92
Zhang Xiantao34c16ee2007-10-20 15:34:38 +080093struct kvm_vcpu {
94 KVM_VCPU_COMM;
95 u64 host_tsc;
96 int interrupt_window_open;
97 unsigned long irq_summary; /* bit vector: 1 per word in irq_pending */
98 DECLARE_BITMAP(irq_pending, KVM_NR_INTERRUPTS);
99 unsigned long regs[NR_VCPU_REGS]; /* for rsp: vcpu_load_rsp_rip() */
100 unsigned long rip; /* needs vcpu_load_rsp_rip() */
101
102 unsigned long cr0;
103 unsigned long cr2;
104 unsigned long cr3;
105 unsigned long cr4;
106 unsigned long cr8;
107 u64 pdptrs[4]; /* pae */
108 u64 shadow_efer;
109 u64 apic_base;
110 struct kvm_lapic *apic; /* kernel irqchip context */
111#define VCPU_MP_STATE_RUNNABLE 0
112#define VCPU_MP_STATE_UNINITIALIZED 1
113#define VCPU_MP_STATE_INIT_RECEIVED 2
114#define VCPU_MP_STATE_SIPI_RECEIVED 3
115#define VCPU_MP_STATE_HALTED 4
116 int mp_state;
117 int sipi_vector;
118 u64 ia32_misc_enable_msr;
119
120 struct kvm_mmu mmu;
121
122 struct kvm_mmu_memory_cache mmu_pte_chain_cache;
123 struct kvm_mmu_memory_cache mmu_rmap_desc_cache;
124 struct kvm_mmu_memory_cache mmu_page_cache;
125 struct kvm_mmu_memory_cache mmu_page_header_cache;
126
127 gfn_t last_pt_write_gfn;
128 int last_pt_write_count;
129 u64 *last_pte_updated;
130
131
132 struct i387_fxsave_struct host_fx_image;
133 struct i387_fxsave_struct guest_fx_image;
134
135 gva_t mmio_fault_cr2;
136 struct kvm_pio_request pio;
137 void *pio_data;
138
139 struct {
140 int active;
141 u8 save_iopl;
142 struct kvm_save_segment {
143 u16 selector;
144 unsigned long base;
145 u32 limit;
146 u32 ar;
147 } tr, es, ds, fs, gs;
148 } rmode;
149 int halt_request; /* real mode on Intel only */
150
151 int cpuid_nent;
152 struct kvm_cpuid_entry cpuid_entries[KVM_MAX_CPUID_ENTRIES];
153
154 /* emulate context */
155
156 struct x86_emulate_ctxt emulate_ctxt;
157};
158
Zhang Xiantaoea4a5ff2007-11-19 14:40:47 +0800159struct kvm_x86_ops {
160 int (*cpu_has_kvm_support)(void); /* __init */
161 int (*disabled_by_bios)(void); /* __init */
162 void (*hardware_enable)(void *dummy); /* __init */
163 void (*hardware_disable)(void *dummy);
164 void (*check_processor_compatibility)(void *rtn);
165 int (*hardware_setup)(void); /* __init */
166 void (*hardware_unsetup)(void); /* __exit */
167
168 /* Create, but do not attach this VCPU */
169 struct kvm_vcpu *(*vcpu_create)(struct kvm *kvm, unsigned id);
170 void (*vcpu_free)(struct kvm_vcpu *vcpu);
171 int (*vcpu_reset)(struct kvm_vcpu *vcpu);
172
173 void (*prepare_guest_switch)(struct kvm_vcpu *vcpu);
174 void (*vcpu_load)(struct kvm_vcpu *vcpu, int cpu);
175 void (*vcpu_put)(struct kvm_vcpu *vcpu);
176 void (*vcpu_decache)(struct kvm_vcpu *vcpu);
177
178 int (*set_guest_debug)(struct kvm_vcpu *vcpu,
179 struct kvm_debug_guest *dbg);
180 void (*guest_debug_pre)(struct kvm_vcpu *vcpu);
181 int (*get_msr)(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata);
182 int (*set_msr)(struct kvm_vcpu *vcpu, u32 msr_index, u64 data);
183 u64 (*get_segment_base)(struct kvm_vcpu *vcpu, int seg);
184 void (*get_segment)(struct kvm_vcpu *vcpu,
185 struct kvm_segment *var, int seg);
186 void (*set_segment)(struct kvm_vcpu *vcpu,
187 struct kvm_segment *var, int seg);
188 void (*get_cs_db_l_bits)(struct kvm_vcpu *vcpu, int *db, int *l);
189 void (*decache_cr4_guest_bits)(struct kvm_vcpu *vcpu);
190 void (*set_cr0)(struct kvm_vcpu *vcpu, unsigned long cr0);
191 void (*set_cr3)(struct kvm_vcpu *vcpu, unsigned long cr3);
192 void (*set_cr4)(struct kvm_vcpu *vcpu, unsigned long cr4);
193 void (*set_efer)(struct kvm_vcpu *vcpu, u64 efer);
194 void (*get_idt)(struct kvm_vcpu *vcpu, struct descriptor_table *dt);
195 void (*set_idt)(struct kvm_vcpu *vcpu, struct descriptor_table *dt);
196 void (*get_gdt)(struct kvm_vcpu *vcpu, struct descriptor_table *dt);
197 void (*set_gdt)(struct kvm_vcpu *vcpu, struct descriptor_table *dt);
198 unsigned long (*get_dr)(struct kvm_vcpu *vcpu, int dr);
199 void (*set_dr)(struct kvm_vcpu *vcpu, int dr, unsigned long value,
200 int *exception);
201 void (*cache_regs)(struct kvm_vcpu *vcpu);
202 void (*decache_regs)(struct kvm_vcpu *vcpu);
203 unsigned long (*get_rflags)(struct kvm_vcpu *vcpu);
204 void (*set_rflags)(struct kvm_vcpu *vcpu, unsigned long rflags);
205
206 void (*tlb_flush)(struct kvm_vcpu *vcpu);
207 void (*inject_page_fault)(struct kvm_vcpu *vcpu,
208 unsigned long addr, u32 err_code);
209
210 void (*inject_gp)(struct kvm_vcpu *vcpu, unsigned err_code);
211
212 void (*run)(struct kvm_vcpu *vcpu, struct kvm_run *run);
213 int (*handle_exit)(struct kvm_run *run, struct kvm_vcpu *vcpu);
214 void (*skip_emulated_instruction)(struct kvm_vcpu *vcpu);
215 void (*patch_hypercall)(struct kvm_vcpu *vcpu,
216 unsigned char *hypercall_addr);
217 int (*get_irq)(struct kvm_vcpu *vcpu);
218 void (*set_irq)(struct kvm_vcpu *vcpu, int vec);
219 void (*inject_pending_irq)(struct kvm_vcpu *vcpu);
220 void (*inject_pending_vectors)(struct kvm_vcpu *vcpu,
221 struct kvm_run *run);
222
223 int (*set_tss_addr)(struct kvm *kvm, unsigned int addr);
224};
225
Zhang Xiantao97896d02007-11-14 20:09:30 +0800226extern struct kvm_x86_ops *kvm_x86_ops;
227
Avi Kivity30677142007-10-28 18:48:59 +0200228int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t gva, u32 error_code);
Zhang Xiantao34c16ee2007-10-20 15:34:38 +0800229
230static inline void kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu)
231{
232 if (unlikely(vcpu->kvm->n_free_mmu_pages < KVM_MIN_FREE_MMU_PAGES))
233 __kvm_mmu_free_some_pages(vcpu);
234}
235
236static inline int kvm_mmu_reload(struct kvm_vcpu *vcpu)
237{
238 if (likely(vcpu->mmu.root_hpa != INVALID_PAGE))
239 return 0;
240
241 return kvm_mmu_load(vcpu);
242}
243
244static inline int is_long_mode(struct kvm_vcpu *vcpu)
245{
246#ifdef CONFIG_X86_64
247 return vcpu->shadow_efer & EFER_LME;
248#else
249 return 0;
250#endif
251}
252
253static inline int is_pae(struct kvm_vcpu *vcpu)
254{
255 return vcpu->cr4 & X86_CR4_PAE;
256}
257
258static inline int is_pse(struct kvm_vcpu *vcpu)
259{
260 return vcpu->cr4 & X86_CR4_PSE;
261}
262
263static inline int is_paging(struct kvm_vcpu *vcpu)
264{
265 return vcpu->cr0 & X86_CR0_PG;
266}
267
Carsten Ottea03490e2007-10-29 16:09:35 +0100268int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3);
Carsten Ottede7d7892007-10-30 18:44:25 +0100269int complete_pio(struct kvm_vcpu *vcpu);
Zhang Xiantaoec6d2732007-11-19 15:08:31 +0800270
271static inline struct kvm_mmu_page *page_header(hpa_t shadow_page)
272{
273 struct page *page = pfn_to_page(shadow_page >> PAGE_SHIFT);
274
275 return (struct kvm_mmu_page *)page_private(page);
276}
277
278static inline u16 read_fs(void)
279{
280 u16 seg;
281 asm("mov %%fs, %0" : "=g"(seg));
282 return seg;
283}
284
285static inline u16 read_gs(void)
286{
287 u16 seg;
288 asm("mov %%gs, %0" : "=g"(seg));
289 return seg;
290}
291
292static inline u16 read_ldt(void)
293{
294 u16 ldt;
295 asm("sldt %0" : "=g"(ldt));
296 return ldt;
297}
298
299static inline void load_fs(u16 sel)
300{
301 asm("mov %0, %%fs" : : "rm"(sel));
302}
303
304static inline void load_gs(u16 sel)
305{
306 asm("mov %0, %%gs" : : "rm"(sel));
307}
308
309#ifndef load_ldt
310static inline void load_ldt(u16 sel)
311{
312 asm("lldt %0" : : "rm"(sel));
313}
314#endif
315
316static inline void get_idt(struct descriptor_table *table)
317{
318 asm("sidt %0" : "=m"(*table));
319}
320
321static inline void get_gdt(struct descriptor_table *table)
322{
323 asm("sgdt %0" : "=m"(*table));
324}
325
326static inline unsigned long read_tr_base(void)
327{
328 u16 tr;
329 asm("str %0" : "=g"(tr));
330 return segment_base(tr);
331}
332
333#ifdef CONFIG_X86_64
334static inline unsigned long read_msr(unsigned long msr)
335{
336 u64 value;
337
338 rdmsrl(msr, value);
339 return value;
340}
341#endif
342
343static inline void fx_save(struct i387_fxsave_struct *image)
344{
345 asm("fxsave (%0)":: "r" (image));
346}
347
348static inline void fx_restore(struct i387_fxsave_struct *image)
349{
350 asm("fxrstor (%0)":: "r" (image));
351}
352
353static inline void fpu_init(void)
354{
355 asm("finit");
356}
357
358static inline u32 get_rdx_init_val(void)
359{
360 return 0x600; /* P6 family */
361}
362
363#define ASM_VMX_VMCLEAR_RAX ".byte 0x66, 0x0f, 0xc7, 0x30"
364#define ASM_VMX_VMLAUNCH ".byte 0x0f, 0x01, 0xc2"
365#define ASM_VMX_VMRESUME ".byte 0x0f, 0x01, 0xc3"
366#define ASM_VMX_VMPTRLD_RAX ".byte 0x0f, 0xc7, 0x30"
367#define ASM_VMX_VMREAD_RDX_RAX ".byte 0x0f, 0x78, 0xd0"
368#define ASM_VMX_VMWRITE_RAX_RDX ".byte 0x0f, 0x79, 0xd0"
369#define ASM_VMX_VMWRITE_RSP_RDX ".byte 0x0f, 0x79, 0xd4"
370#define ASM_VMX_VMXOFF ".byte 0x0f, 0x01, 0xc4"
371#define ASM_VMX_VMXON_RAX ".byte 0xf3, 0x0f, 0xc7, 0x30"
372
373#define MSR_IA32_TIME_STAMP_COUNTER 0x010
374
375#define TSS_IOPB_BASE_OFFSET 0x66
376#define TSS_BASE_SIZE 0x68
377#define TSS_IOPB_SIZE (65536 / 8)
378#define TSS_REDIRECTION_SIZE (256 / 8)
379#define RMODE_TSS_SIZE (TSS_BASE_SIZE + TSS_REDIRECTION_SIZE + TSS_IOPB_SIZE + 1)
Carsten Otte043405e2007-10-10 17:16:19 +0200380#endif