blob: 8888d894bf39765726d74790fae571a3cd6cbcac [file] [log] [blame]
Avi Kivity6aa8b732006-12-10 02:21:36 -08001/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
Nicolas Kaiser9611c182010-10-06 14:23:22 +02008 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
Avi Kivity6aa8b732006-12-10 02:21:36 -08009 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
Eddie Dong85f455f2007-07-06 12:20:49 +030019#include "irq.h"
Zhang Xiantao1d737c82007-12-14 09:35:10 +080020#include "mmu.h"
Avi Kivity00b27a32011-11-23 16:30:32 +020021#include "cpuid.h"
Andrey Smetanind62caab2015-11-10 15:36:33 +030022#include "lapic.h"
Avi Kivitye4956062007-06-28 14:15:57 -040023
Avi Kivityedf88412007-12-16 11:02:48 +020024#include <linux/kvm_host.h>
Avi Kivity6aa8b732006-12-10 02:21:36 -080025#include <linux/module.h>
Ahmed S. Darwish9d8f5492007-02-19 14:37:46 +020026#include <linux/kernel.h>
Avi Kivity6aa8b732006-12-10 02:21:36 -080027#include <linux/mm.h>
28#include <linux/highmem.h>
Alexey Dobriyane8edc6e2007-05-21 01:22:52 +040029#include <linux/sched.h>
Avi Kivityc7addb92007-09-16 18:58:32 +020030#include <linux/moduleparam.h>
Josh Triplette9bda3b2012-03-20 23:33:51 -070031#include <linux/mod_devicetable.h>
Steven Rostedt (Red Hat)af658dc2015-04-29 14:36:05 -040032#include <linux/trace_events.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090033#include <linux/slab.h>
Shane Wangcafd6652010-04-29 12:09:01 -040034#include <linux/tboot.h>
Jan Kiszkaf4124502014-03-07 20:03:13 +010035#include <linux/hrtimer.h>
Josh Poimboeuf935893a2017-06-28 10:11:06 -050036#include <linux/frame.h>
Dan Williamseb99bd62018-01-31 17:47:03 -080037#include <linux/nospec.h>
Marcelo Tosatti5fdbf972008-06-27 14:58:02 -030038#include "kvm_cache_regs.h"
Avi Kivity35920a32008-07-03 14:50:12 +030039#include "x86.h"
Avi Kivitye4956062007-06-28 14:15:57 -040040
Feng Wu28b835d2015-09-18 22:29:54 +080041#include <asm/cpu.h>
Avi Kivity6aa8b732006-12-10 02:21:36 -080042#include <asm/io.h>
Anthony Liguori3b3be0d2006-12-13 00:33:43 -080043#include <asm/desc.h>
Eduardo Habkost13673a92008-11-17 19:03:13 -020044#include <asm/vmx.h>
Eduardo Habkost6210e372008-11-17 19:03:16 -020045#include <asm/virtext.h>
Andi Kleena0861c02009-06-08 17:37:09 +080046#include <asm/mce.h>
Ingo Molnar952f07e2015-04-26 16:56:05 +020047#include <asm/fpu/internal.h>
Gleb Natapovd7cd9792011-10-05 14:01:23 +020048#include <asm/perf_event.h>
Paolo Bonzini81908bf2014-02-21 10:32:27 +010049#include <asm/debugreg.h>
Zhang Yanfei8f536b72012-12-06 23:43:34 +080050#include <asm/kexec.h>
Radim Krčmářdab20872015-02-09 22:44:07 +010051#include <asm/apic.h>
Feng Wuefc64402015-09-18 22:29:51 +080052#include <asm/irq_remapping.h>
Paolo Bonzinia175d512018-02-22 16:43:17 +010053#include <asm/microcode.h>
Thomas Gleixner7a2d2352018-04-29 15:01:37 +020054#include <asm/spec-ctrl.h>
Avi Kivity6aa8b732006-12-10 02:21:36 -080055
Marcelo Tosatti229456f2009-06-17 09:22:14 -030056#include "trace.h"
Wei Huang25462f72015-06-19 15:45:05 +020057#include "pmu.h"
Marcelo Tosatti229456f2009-06-17 09:22:14 -030058
Avi Kivity4ecac3f2008-05-13 13:23:38 +030059#define __ex(x) __kvm_handle_fault_on_reboot(x)
Avi Kivity5e520e62011-05-15 10:13:12 -040060#define __ex_clear(x, reg) \
61 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
Avi Kivity4ecac3f2008-05-13 13:23:38 +030062
Avi Kivity6aa8b732006-12-10 02:21:36 -080063MODULE_AUTHOR("Qumranet");
64MODULE_LICENSE("GPL");
65
Josh Triplette9bda3b2012-03-20 23:33:51 -070066static const struct x86_cpu_id vmx_cpu_id[] = {
67 X86_FEATURE_MATCH(X86_FEATURE_VMX),
68 {}
69};
70MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
71
Rusty Russell476bc002012-01-13 09:32:18 +103072static bool __read_mostly enable_vpid = 1;
Avi Kivity736caef2009-03-23 17:39:48 +020073module_param_named(vpid, enable_vpid, bool, 0444);
Sheng Yang2384d2b2008-01-17 15:14:33 +080074
Rusty Russell476bc002012-01-13 09:32:18 +103075static bool __read_mostly flexpriority_enabled = 1;
Avi Kivity736caef2009-03-23 17:39:48 +020076module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
Avi Kivity4c9fc8e2008-03-24 18:15:14 +020077
Rusty Russell476bc002012-01-13 09:32:18 +103078static bool __read_mostly enable_ept = 1;
Avi Kivity736caef2009-03-23 17:39:48 +020079module_param_named(ept, enable_ept, bool, S_IRUGO);
Sheng Yangd56f5462008-04-25 10:13:16 +080080
Rusty Russell476bc002012-01-13 09:32:18 +103081static bool __read_mostly enable_unrestricted_guest = 1;
Nitin A Kamble3a624e22009-06-08 11:34:16 -070082module_param_named(unrestricted_guest,
83 enable_unrestricted_guest, bool, S_IRUGO);
84
Xudong Hao83c3a332012-05-28 19:33:35 +080085static bool __read_mostly enable_ept_ad_bits = 1;
86module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
87
Avi Kivitya27685c2012-06-12 20:30:18 +030088static bool __read_mostly emulate_invalid_guest_state = true;
Avi Kivityc1f8bc02009-03-23 15:41:17 +020089module_param(emulate_invalid_guest_state, bool, S_IRUGO);
Mohammed Gamal04fa4d32008-08-17 16:39:48 +030090
Rusty Russell476bc002012-01-13 09:32:18 +103091static bool __read_mostly vmm_exclusive = 1;
Dongxiao Xub923e622010-05-11 18:29:45 +080092module_param(vmm_exclusive, bool, S_IRUGO);
93
Rusty Russell476bc002012-01-13 09:32:18 +103094static bool __read_mostly fasteoi = 1;
Kevin Tian58fbbf22011-08-30 13:56:17 +030095module_param(fasteoi, bool, S_IRUGO);
96
Yang Zhang5a717852013-04-11 19:25:16 +080097static bool __read_mostly enable_apicv = 1;
Yang Zhang01e439b2013-04-11 19:25:12 +080098module_param(enable_apicv, bool, S_IRUGO);
Yang Zhang83d4c282013-01-25 10:18:49 +080099
Abel Gordonabc4fc52013-04-18 14:35:25 +0300100static bool __read_mostly enable_shadow_vmcs = 1;
101module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
Nadav Har'El801d3422011-05-25 23:02:23 +0300102/*
103 * If nested=1, nested virtualization is supported, i.e., guests may use
104 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
105 * use VMX instructions.
106 */
Rusty Russell476bc002012-01-13 09:32:18 +1030107static bool __read_mostly nested = 0;
Nadav Har'El801d3422011-05-25 23:02:23 +0300108module_param(nested, bool, S_IRUGO);
109
Wanpeng Li20300092014-12-02 19:14:59 +0800110static u64 __read_mostly host_xss;
111
Kai Huang843e4332015-01-28 10:54:28 +0800112static bool __read_mostly enable_pml = 1;
113module_param_named(pml, enable_pml, bool, S_IRUGO);
114
Paolo Bonzini6236b782018-01-16 16:51:18 +0100115#define MSR_TYPE_R 1
116#define MSR_TYPE_W 2
117#define MSR_TYPE_RW 3
118
119#define MSR_BITMAP_MODE_X2APIC 1
120#define MSR_BITMAP_MODE_X2APIC_APICV 2
121#define MSR_BITMAP_MODE_LM 4
122
Haozhong Zhang64903d62015-10-20 15:39:09 +0800123#define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL
124
Yunhong Jiang64672c92016-06-13 14:19:59 -0700125/* Guest_tsc -> host_tsc conversion requires 64-bit division. */
126static int __read_mostly cpu_preemption_timer_multi;
127static bool __read_mostly enable_preemption_timer = 1;
128#ifdef CONFIG_X86_64
129module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
130#endif
131
Gleb Natapov50378782013-02-04 16:00:28 +0200132#define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
133#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
Avi Kivitycdc0e242009-12-06 17:21:14 +0200134#define KVM_VM_CR0_ALWAYS_ON \
135 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
Avi Kivity4c386092009-12-07 12:26:18 +0200136#define KVM_CR4_GUEST_OWNED_BITS \
137 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
Andy Lutomirski52ce3c22014-10-07 17:16:21 -0700138 | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
Avi Kivity4c386092009-12-07 12:26:18 +0200139
Avi Kivitycdc0e242009-12-06 17:21:14 +0200140#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
141#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
142
Avi Kivity78ac8b42010-04-08 18:19:35 +0300143#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
144
Jan Kiszkaf4124502014-03-07 20:03:13 +0100145#define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
146
Jan Dakinevich04c776e2018-02-23 11:42:18 +0100147#define VMX_VPID_EXTENT_SUPPORTED_MASK \
148 (VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT | \
149 VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT | \
150 VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT | \
151 VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT)
152
Zhai, Edwin4b8d54f2009-10-09 18:03:20 +0800153/*
154 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
155 * ple_gap: upper bound on the amount of time between two successive
156 * executions of PAUSE in a loop. Also indicate if ple enabled.
Rik van Riel00c25bc2011-01-04 09:51:33 -0500157 * According to test, this time is usually smaller than 128 cycles.
Zhai, Edwin4b8d54f2009-10-09 18:03:20 +0800158 * ple_window: upper bound on the amount of time a guest is allowed to execute
159 * in a PAUSE loop. Tests indicate that most spinlocks are held for
160 * less than 2^12 cycles
161 * Time is measured based on a counter that runs at the same rate as the TSC,
162 * refer SDM volume 3b section 21.6.13 & 22.1.3.
163 */
Radim Krčmářb4a2d312014-08-21 18:08:08 +0200164#define KVM_VMX_DEFAULT_PLE_GAP 128
165#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
166#define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2
167#define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
168#define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \
169 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
170
Zhai, Edwin4b8d54f2009-10-09 18:03:20 +0800171static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
172module_param(ple_gap, int, S_IRUGO);
173
174static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
175module_param(ple_window, int, S_IRUGO);
176
Radim Krčmářb4a2d312014-08-21 18:08:08 +0200177/* Default doubles per-vcpu window every exit. */
178static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
179module_param(ple_window_grow, int, S_IRUGO);
180
181/* Default resets per-vcpu window every exit to ple_window. */
182static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
183module_param(ple_window_shrink, int, S_IRUGO);
184
185/* Default is to compute the maximum so we can never overflow. */
186static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
187static int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
188module_param(ple_window_max, int, S_IRUGO);
189
Avi Kivity83287ea422012-09-16 15:10:57 +0300190extern const ulong vmx_return;
191
Konrad Rzeszutek Wilkaf6ce922018-07-02 12:29:30 +0200192static DEFINE_STATIC_KEY_FALSE(vmx_l1d_should_flush);
Nicolai Stange936f5662018-07-21 22:25:00 +0200193static DEFINE_STATIC_KEY_FALSE(vmx_l1d_flush_cond);
Thomas Gleixner6ccf6332018-07-13 16:23:21 +0200194static DEFINE_MUTEX(vmx_l1d_flush_mutex);
Konrad Rzeszutek Wilkaf6ce922018-07-02 12:29:30 +0200195
Thomas Gleixner641a2112018-07-13 16:23:19 +0200196/* Storage for pre module init parameter parsing */
197static enum vmx_l1d_flush_state __read_mostly vmentry_l1d_flush_param = VMENTER_L1D_FLUSH_AUTO;
Konrad Rzeszutek Wilkaf6ce922018-07-02 12:29:30 +0200198
199static const struct {
200 const char *option;
Paolo Bonzini87294122018-08-22 16:43:39 +0200201 bool for_parse;
Konrad Rzeszutek Wilkaf6ce922018-07-02 12:29:30 +0200202} vmentry_l1d_param[] = {
Paolo Bonzini87294122018-08-22 16:43:39 +0200203 [VMENTER_L1D_FLUSH_AUTO] = {"auto", true},
204 [VMENTER_L1D_FLUSH_NEVER] = {"never", true},
205 [VMENTER_L1D_FLUSH_COND] = {"cond", true},
206 [VMENTER_L1D_FLUSH_ALWAYS] = {"always", true},
207 [VMENTER_L1D_FLUSH_EPT_DISABLED] = {"EPT disabled", false},
208 [VMENTER_L1D_FLUSH_NOT_REQUIRED] = {"not required", false},
Konrad Rzeszutek Wilkaf6ce922018-07-02 12:29:30 +0200209};
210
Thomas Gleixner641a2112018-07-13 16:23:19 +0200211#define L1D_CACHE_ORDER 4
212static void *vmx_l1d_flush_pages;
213
214static int vmx_setup_l1d_flush(enum vmx_l1d_flush_state l1tf)
215{
216 struct page *page;
Nicolai Stange587d4992018-07-18 19:07:38 +0200217 unsigned int i;
Thomas Gleixner641a2112018-07-13 16:23:19 +0200218
Thomas Gleixner641a2112018-07-13 16:23:19 +0200219 if (!enable_ept) {
220 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_EPT_DISABLED;
221 return 0;
222 }
223
Paolo Bonzini383f1602018-08-05 16:07:46 +0200224 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) {
225 u64 msr;
226
227 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, msr);
228 if (msr & ARCH_CAP_SKIP_VMENTRY_L1DFLUSH) {
229 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED;
230 return 0;
231 }
232 }
233
Jiri Kosina2decbf52018-07-13 16:23:25 +0200234 /* If set to auto use the default l1tf mitigation method */
235 if (l1tf == VMENTER_L1D_FLUSH_AUTO) {
236 switch (l1tf_mitigation) {
237 case L1TF_MITIGATION_OFF:
238 l1tf = VMENTER_L1D_FLUSH_NEVER;
239 break;
240 case L1TF_MITIGATION_FLUSH_NOWARN:
241 case L1TF_MITIGATION_FLUSH:
242 case L1TF_MITIGATION_FLUSH_NOSMT:
243 l1tf = VMENTER_L1D_FLUSH_COND;
244 break;
245 case L1TF_MITIGATION_FULL:
246 case L1TF_MITIGATION_FULL_FORCE:
247 l1tf = VMENTER_L1D_FLUSH_ALWAYS;
248 break;
249 }
250 } else if (l1tf_mitigation == L1TF_MITIGATION_FULL_FORCE) {
251 l1tf = VMENTER_L1D_FLUSH_ALWAYS;
252 }
253
Thomas Gleixner641a2112018-07-13 16:23:19 +0200254 if (l1tf != VMENTER_L1D_FLUSH_NEVER && !vmx_l1d_flush_pages &&
255 !boot_cpu_has(X86_FEATURE_FLUSH_L1D)) {
256 page = alloc_pages(GFP_KERNEL, L1D_CACHE_ORDER);
257 if (!page)
258 return -ENOMEM;
259 vmx_l1d_flush_pages = page_address(page);
Nicolai Stange587d4992018-07-18 19:07:38 +0200260
261 /*
262 * Initialize each page with a different pattern in
263 * order to protect against KSM in the nested
264 * virtualization case.
265 */
266 for (i = 0; i < 1u << L1D_CACHE_ORDER; ++i) {
267 memset(vmx_l1d_flush_pages + i * PAGE_SIZE, i + 1,
268 PAGE_SIZE);
269 }
Thomas Gleixner641a2112018-07-13 16:23:19 +0200270 }
271
272 l1tf_vmx_mitigation = l1tf;
273
Thomas Gleixner4797c2f2018-07-13 16:23:22 +0200274 if (l1tf != VMENTER_L1D_FLUSH_NEVER)
275 static_branch_enable(&vmx_l1d_should_flush);
276 else
277 static_branch_disable(&vmx_l1d_should_flush);
Thomas Gleixnerdff09822018-07-13 16:23:20 +0200278
Nicolai Stange936f5662018-07-21 22:25:00 +0200279 if (l1tf == VMENTER_L1D_FLUSH_COND)
280 static_branch_enable(&vmx_l1d_flush_cond);
Thomas Gleixner4797c2f2018-07-13 16:23:22 +0200281 else
Nicolai Stange936f5662018-07-21 22:25:00 +0200282 static_branch_disable(&vmx_l1d_flush_cond);
Thomas Gleixner641a2112018-07-13 16:23:19 +0200283 return 0;
284}
285
286static int vmentry_l1d_flush_parse(const char *s)
Konrad Rzeszutek Wilkaf6ce922018-07-02 12:29:30 +0200287{
288 unsigned int i;
289
Thomas Gleixner641a2112018-07-13 16:23:19 +0200290 if (s) {
291 for (i = 0; i < ARRAY_SIZE(vmentry_l1d_param); i++) {
Paolo Bonzini87294122018-08-22 16:43:39 +0200292 if (vmentry_l1d_param[i].for_parse &&
293 sysfs_streq(s, vmentry_l1d_param[i].option))
294 return i;
Konrad Rzeszutek Wilkaf6ce922018-07-02 12:29:30 +0200295 }
296 }
Konrad Rzeszutek Wilkaf6ce922018-07-02 12:29:30 +0200297 return -EINVAL;
298}
299
Thomas Gleixner641a2112018-07-13 16:23:19 +0200300static int vmentry_l1d_flush_set(const char *s, const struct kernel_param *kp)
301{
Thomas Gleixner6ccf6332018-07-13 16:23:21 +0200302 int l1tf, ret;
Thomas Gleixner641a2112018-07-13 16:23:19 +0200303
Thomas Gleixner641a2112018-07-13 16:23:19 +0200304 l1tf = vmentry_l1d_flush_parse(s);
305 if (l1tf < 0)
306 return l1tf;
307
Paolo Bonzini87294122018-08-22 16:43:39 +0200308 if (!boot_cpu_has(X86_BUG_L1TF))
309 return 0;
310
Thomas Gleixner641a2112018-07-13 16:23:19 +0200311 /*
312 * Has vmx_init() run already? If not then this is the pre init
313 * parameter parsing. In that case just store the value and let
314 * vmx_init() do the proper setup after enable_ept has been
315 * established.
316 */
317 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO) {
318 vmentry_l1d_flush_param = l1tf;
319 return 0;
320 }
321
Thomas Gleixner6ccf6332018-07-13 16:23:21 +0200322 mutex_lock(&vmx_l1d_flush_mutex);
323 ret = vmx_setup_l1d_flush(l1tf);
324 mutex_unlock(&vmx_l1d_flush_mutex);
325 return ret;
Thomas Gleixner641a2112018-07-13 16:23:19 +0200326}
327
Konrad Rzeszutek Wilkaf6ce922018-07-02 12:29:30 +0200328static int vmentry_l1d_flush_get(char *s, const struct kernel_param *kp)
329{
Paolo Bonzini87294122018-08-22 16:43:39 +0200330 if (WARN_ON_ONCE(l1tf_vmx_mitigation >= ARRAY_SIZE(vmentry_l1d_param)))
331 return sprintf(s, "???\n");
332
Thomas Gleixner641a2112018-07-13 16:23:19 +0200333 return sprintf(s, "%s\n", vmentry_l1d_param[l1tf_vmx_mitigation].option);
Konrad Rzeszutek Wilkaf6ce922018-07-02 12:29:30 +0200334}
335
336static const struct kernel_param_ops vmentry_l1d_flush_ops = {
337 .set = vmentry_l1d_flush_set,
338 .get = vmentry_l1d_flush_get,
339};
Thomas Gleixner4797c2f2018-07-13 16:23:22 +0200340module_param_cb(vmentry_l1d_flush, &vmentry_l1d_flush_ops, NULL, 0644);
Konrad Rzeszutek Wilkaf6ce922018-07-02 12:29:30 +0200341
Gleb Natapov8bf00a52011-10-05 14:01:22 +0200342#define NR_AUTOLOAD_MSRS 8
Avi Kivity61d2ef22010-04-28 16:40:38 +0300343
Gregory Haskinsa2fa3e92007-07-27 08:13:10 -0400344struct vmcs {
345 u32 revision_id;
346 u32 abort;
347 char data[0];
348};
349
Nadav Har'Eld462b812011-05-24 15:26:10 +0300350/*
351 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
352 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
353 * loaded on this CPU (so we can clear them if the CPU goes down).
354 */
355struct loaded_vmcs {
356 struct vmcs *vmcs;
Jim Mattson355f4fb2016-10-28 08:29:39 -0700357 struct vmcs *shadow_vmcs;
Nadav Har'Eld462b812011-05-24 15:26:10 +0300358 int cpu;
359 int launched;
Paolo Bonzini6236b782018-01-16 16:51:18 +0100360 unsigned long *msr_bitmap;
Nadav Har'Eld462b812011-05-24 15:26:10 +0300361 struct list_head loaded_vmcss_on_cpu_link;
362};
363
Avi Kivity26bb0982009-09-07 11:14:12 +0300364struct shared_msr_entry {
365 unsigned index;
366 u64 data;
Avi Kivityd5696722009-12-02 12:28:47 +0200367 u64 mask;
Avi Kivity26bb0982009-09-07 11:14:12 +0300368};
369
Nadav Har'Elec378ae2011-05-25 23:02:54 +0300370/*
Nadav Har'Ela9d30f32011-05-25 23:03:55 +0300371 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
372 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
373 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
374 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
375 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
376 * More than one of these structures may exist, if L1 runs multiple L2 guests.
Jim Mattson46e24df2017-11-27 17:22:25 -0600377 * nested_vmx_run() will use the data here to build the vmcs02: a VMCS for the
Nadav Har'Ela9d30f32011-05-25 23:03:55 +0300378 * underlying hardware which will be used to run L2.
379 * This structure is packed to ensure that its layout is identical across
380 * machines (necessary for live migration).
381 * If there are changes in this struct, VMCS12_REVISION must be changed.
382 */
Nadav Har'El22bd0352011-05-25 23:05:57 +0300383typedef u64 natural_width;
Nadav Har'Ela9d30f32011-05-25 23:03:55 +0300384struct __packed vmcs12 {
385 /* According to the Intel spec, a VMCS region must start with the
386 * following two fields. Then follow implementation-specific data.
387 */
388 u32 revision_id;
389 u32 abort;
Nadav Har'El22bd0352011-05-25 23:05:57 +0300390
Nadav Har'El27d6c862011-05-25 23:06:59 +0300391 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
392 u32 padding[7]; /* room for future expansion */
393
Nadav Har'El22bd0352011-05-25 23:05:57 +0300394 u64 io_bitmap_a;
395 u64 io_bitmap_b;
396 u64 msr_bitmap;
397 u64 vm_exit_msr_store_addr;
398 u64 vm_exit_msr_load_addr;
399 u64 vm_entry_msr_load_addr;
400 u64 tsc_offset;
401 u64 virtual_apic_page_addr;
402 u64 apic_access_addr;
Wincy Van705699a2015-02-03 23:58:17 +0800403 u64 posted_intr_desc_addr;
Nadav Har'El22bd0352011-05-25 23:05:57 +0300404 u64 ept_pointer;
Wincy Van608406e2015-02-03 23:57:51 +0800405 u64 eoi_exit_bitmap0;
406 u64 eoi_exit_bitmap1;
407 u64 eoi_exit_bitmap2;
408 u64 eoi_exit_bitmap3;
Wanpeng Li81dc01f2014-12-04 19:11:07 +0800409 u64 xss_exit_bitmap;
Nadav Har'El22bd0352011-05-25 23:05:57 +0300410 u64 guest_physical_address;
411 u64 vmcs_link_pointer;
412 u64 guest_ia32_debugctl;
413 u64 guest_ia32_pat;
414 u64 guest_ia32_efer;
415 u64 guest_ia32_perf_global_ctrl;
416 u64 guest_pdptr0;
417 u64 guest_pdptr1;
418 u64 guest_pdptr2;
419 u64 guest_pdptr3;
Paolo Bonzini36be0b92014-02-24 12:30:04 +0100420 u64 guest_bndcfgs;
Nadav Har'El22bd0352011-05-25 23:05:57 +0300421 u64 host_ia32_pat;
422 u64 host_ia32_efer;
423 u64 host_ia32_perf_global_ctrl;
424 u64 padding64[8]; /* room for future expansion */
425 /*
426 * To allow migration of L1 (complete with its L2 guests) between
427 * machines of different natural widths (32 or 64 bit), we cannot have
428 * unsigned long fields with no explict size. We use u64 (aliased
429 * natural_width) instead. Luckily, x86 is little-endian.
430 */
431 natural_width cr0_guest_host_mask;
432 natural_width cr4_guest_host_mask;
433 natural_width cr0_read_shadow;
434 natural_width cr4_read_shadow;
435 natural_width cr3_target_value0;
436 natural_width cr3_target_value1;
437 natural_width cr3_target_value2;
438 natural_width cr3_target_value3;
439 natural_width exit_qualification;
440 natural_width guest_linear_address;
441 natural_width guest_cr0;
442 natural_width guest_cr3;
443 natural_width guest_cr4;
444 natural_width guest_es_base;
445 natural_width guest_cs_base;
446 natural_width guest_ss_base;
447 natural_width guest_ds_base;
448 natural_width guest_fs_base;
449 natural_width guest_gs_base;
450 natural_width guest_ldtr_base;
451 natural_width guest_tr_base;
452 natural_width guest_gdtr_base;
453 natural_width guest_idtr_base;
454 natural_width guest_dr7;
455 natural_width guest_rsp;
456 natural_width guest_rip;
457 natural_width guest_rflags;
458 natural_width guest_pending_dbg_exceptions;
459 natural_width guest_sysenter_esp;
460 natural_width guest_sysenter_eip;
461 natural_width host_cr0;
462 natural_width host_cr3;
463 natural_width host_cr4;
464 natural_width host_fs_base;
465 natural_width host_gs_base;
466 natural_width host_tr_base;
467 natural_width host_gdtr_base;
468 natural_width host_idtr_base;
469 natural_width host_ia32_sysenter_esp;
470 natural_width host_ia32_sysenter_eip;
471 natural_width host_rsp;
472 natural_width host_rip;
473 natural_width paddingl[8]; /* room for future expansion */
474 u32 pin_based_vm_exec_control;
475 u32 cpu_based_vm_exec_control;
476 u32 exception_bitmap;
477 u32 page_fault_error_code_mask;
478 u32 page_fault_error_code_match;
479 u32 cr3_target_count;
480 u32 vm_exit_controls;
481 u32 vm_exit_msr_store_count;
482 u32 vm_exit_msr_load_count;
483 u32 vm_entry_controls;
484 u32 vm_entry_msr_load_count;
485 u32 vm_entry_intr_info_field;
486 u32 vm_entry_exception_error_code;
487 u32 vm_entry_instruction_len;
488 u32 tpr_threshold;
489 u32 secondary_vm_exec_control;
490 u32 vm_instruction_error;
491 u32 vm_exit_reason;
492 u32 vm_exit_intr_info;
493 u32 vm_exit_intr_error_code;
494 u32 idt_vectoring_info_field;
495 u32 idt_vectoring_error_code;
496 u32 vm_exit_instruction_len;
497 u32 vmx_instruction_info;
498 u32 guest_es_limit;
499 u32 guest_cs_limit;
500 u32 guest_ss_limit;
501 u32 guest_ds_limit;
502 u32 guest_fs_limit;
503 u32 guest_gs_limit;
504 u32 guest_ldtr_limit;
505 u32 guest_tr_limit;
506 u32 guest_gdtr_limit;
507 u32 guest_idtr_limit;
508 u32 guest_es_ar_bytes;
509 u32 guest_cs_ar_bytes;
510 u32 guest_ss_ar_bytes;
511 u32 guest_ds_ar_bytes;
512 u32 guest_fs_ar_bytes;
513 u32 guest_gs_ar_bytes;
514 u32 guest_ldtr_ar_bytes;
515 u32 guest_tr_ar_bytes;
516 u32 guest_interruptibility_info;
517 u32 guest_activity_state;
518 u32 guest_sysenter_cs;
519 u32 host_ia32_sysenter_cs;
Jan Kiszka0238ea92013-03-13 11:31:24 +0100520 u32 vmx_preemption_timer_value;
521 u32 padding32[7]; /* room for future expansion */
Nadav Har'El22bd0352011-05-25 23:05:57 +0300522 u16 virtual_processor_id;
Wincy Van705699a2015-02-03 23:58:17 +0800523 u16 posted_intr_nv;
Nadav Har'El22bd0352011-05-25 23:05:57 +0300524 u16 guest_es_selector;
525 u16 guest_cs_selector;
526 u16 guest_ss_selector;
527 u16 guest_ds_selector;
528 u16 guest_fs_selector;
529 u16 guest_gs_selector;
530 u16 guest_ldtr_selector;
531 u16 guest_tr_selector;
Wincy Van608406e2015-02-03 23:57:51 +0800532 u16 guest_intr_status;
Nadav Har'El22bd0352011-05-25 23:05:57 +0300533 u16 host_es_selector;
534 u16 host_cs_selector;
535 u16 host_ss_selector;
536 u16 host_ds_selector;
537 u16 host_fs_selector;
538 u16 host_gs_selector;
539 u16 host_tr_selector;
Nadav Har'Ela9d30f32011-05-25 23:03:55 +0300540};
541
542/*
543 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
544 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
545 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
546 */
547#define VMCS12_REVISION 0x11e57ed0
548
549/*
550 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
551 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
552 * current implementation, 4K are reserved to avoid future complications.
553 */
554#define VMCS12_SIZE 0x1000
555
556/*
Nadav Har'Elec378ae2011-05-25 23:02:54 +0300557 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
558 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
559 */
560struct nested_vmx {
561 /* Has the level1 guest done vmxon? */
562 bool vmxon;
Bandan Das3573e222014-05-06 02:19:16 -0400563 gpa_t vmxon_ptr;
Nadav Har'Ela9d30f32011-05-25 23:03:55 +0300564
565 /* The guest-physical address of the current VMCS L1 keeps for L2 */
566 gpa_t current_vmptr;
567 /* The host-usable pointer to the above */
568 struct page *current_vmcs12_page;
569 struct vmcs12 *current_vmcs12;
David Matlack4f2777b2016-07-13 17:16:37 -0700570 /*
571 * Cache of the guest's VMCS, existing outside of guest memory.
572 * Loaded from guest memory during VMPTRLD. Flushed to guest
573 * memory during VMXOFF, VMCLEAR, VMPTRLD.
574 */
575 struct vmcs12 *cached_vmcs12;
Abel Gordon012f83c2013-04-18 14:39:25 +0300576 /*
577 * Indicates if the shadow vmcs must be updated with the
578 * data hold by vmcs12
579 */
580 bool sync_shadow_vmcs;
Nadav Har'Elff2f6fe2011-05-25 23:05:27 +0300581
Radim Krčmářdccbfcf2016-08-08 20:16:23 +0200582 bool change_vmcs01_virtual_x2apic_mode;
Nadav Har'El644d7112011-05-25 23:12:35 +0300583 /* L2 must run next, and mustn't decide to exit to L1. */
584 bool nested_run_pending;
Jim Mattson46e24df2017-11-27 17:22:25 -0600585
586 struct loaded_vmcs vmcs02;
587
Nadav Har'Elfe3ef052011-05-25 23:10:02 +0300588 /*
Jim Mattson46e24df2017-11-27 17:22:25 -0600589 * Guest pages referred to in the vmcs02 with host-physical
590 * pointers, so we must keep them pinned while L2 runs.
Nadav Har'Elfe3ef052011-05-25 23:10:02 +0300591 */
592 struct page *apic_access_page;
Wanpeng Lia7c0b072014-08-21 19:46:50 +0800593 struct page *virtual_apic_page;
Wincy Van705699a2015-02-03 23:58:17 +0800594 struct page *pi_desc_page;
595 struct pi_desc *pi_desc;
596 bool pi_pending;
597 u16 posted_intr_nv;
Jan Kiszkaf4124502014-03-07 20:03:13 +0100598
599 struct hrtimer preemption_timer;
600 bool preemption_timer_expired;
Jan Kiszka2996fca2014-06-16 13:59:43 +0200601
602 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
603 u64 vmcs01_debugctl;
Wincy Vanb9c237b2015-02-03 23:56:30 +0800604
Wanpeng Li5c614b32015-10-13 09:18:36 -0700605 u16 vpid02;
606 u16 last_vpid;
607
Wincy Vanb9c237b2015-02-03 23:56:30 +0800608 u32 nested_vmx_procbased_ctls_low;
609 u32 nested_vmx_procbased_ctls_high;
610 u32 nested_vmx_true_procbased_ctls_low;
611 u32 nested_vmx_secondary_ctls_low;
612 u32 nested_vmx_secondary_ctls_high;
613 u32 nested_vmx_pinbased_ctls_low;
614 u32 nested_vmx_pinbased_ctls_high;
615 u32 nested_vmx_exit_ctls_low;
616 u32 nested_vmx_exit_ctls_high;
617 u32 nested_vmx_true_exit_ctls_low;
618 u32 nested_vmx_entry_ctls_low;
619 u32 nested_vmx_entry_ctls_high;
620 u32 nested_vmx_true_entry_ctls_low;
621 u32 nested_vmx_misc_low;
622 u32 nested_vmx_misc_high;
623 u32 nested_vmx_ept_caps;
Wanpeng Li99b83ac2015-10-13 09:12:21 -0700624 u32 nested_vmx_vpid_caps;
Nadav Har'Elec378ae2011-05-25 23:02:54 +0300625};
626
Yang Zhang01e439b2013-04-11 19:25:12 +0800627#define POSTED_INTR_ON 0
Feng Wuebbfc762015-09-18 22:29:46 +0800628#define POSTED_INTR_SN 1
629
Yang Zhang01e439b2013-04-11 19:25:12 +0800630/* Posted-Interrupt Descriptor */
631struct pi_desc {
632 u32 pir[8]; /* Posted interrupt requested */
Feng Wu6ef15222015-09-18 22:29:45 +0800633 union {
634 struct {
635 /* bit 256 - Outstanding Notification */
636 u16 on : 1,
637 /* bit 257 - Suppress Notification */
638 sn : 1,
639 /* bit 271:258 - Reserved */
640 rsvd_1 : 14;
641 /* bit 279:272 - Notification Vector */
642 u8 nv;
643 /* bit 287:280 - Reserved */
644 u8 rsvd_2;
645 /* bit 319:288 - Notification Destination */
646 u32 ndst;
647 };
648 u64 control;
649 };
650 u32 rsvd[6];
Yang Zhang01e439b2013-04-11 19:25:12 +0800651} __aligned(64);
652
Yang Zhanga20ed542013-04-11 19:25:15 +0800653static bool pi_test_and_set_on(struct pi_desc *pi_desc)
654{
655 return test_and_set_bit(POSTED_INTR_ON,
656 (unsigned long *)&pi_desc->control);
657}
658
659static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
660{
661 return test_and_clear_bit(POSTED_INTR_ON,
662 (unsigned long *)&pi_desc->control);
663}
664
665static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
666{
667 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
668}
669
Feng Wuebbfc762015-09-18 22:29:46 +0800670static inline void pi_clear_sn(struct pi_desc *pi_desc)
671{
672 return clear_bit(POSTED_INTR_SN,
673 (unsigned long *)&pi_desc->control);
674}
675
676static inline void pi_set_sn(struct pi_desc *pi_desc)
677{
678 return set_bit(POSTED_INTR_SN,
679 (unsigned long *)&pi_desc->control);
680}
681
682static inline int pi_test_on(struct pi_desc *pi_desc)
683{
684 return test_bit(POSTED_INTR_ON,
685 (unsigned long *)&pi_desc->control);
686}
687
688static inline int pi_test_sn(struct pi_desc *pi_desc)
689{
690 return test_bit(POSTED_INTR_SN,
691 (unsigned long *)&pi_desc->control);
692}
693
Konrad Rzeszutek Wilk57e3ada2018-06-20 13:58:37 -0400694struct vmx_msrs {
695 unsigned int nr;
696 struct vmx_msr_entry val[NR_AUTOLOAD_MSRS];
697};
698
Gregory Haskinsa2fa3e92007-07-27 08:13:10 -0400699struct vcpu_vmx {
Rusty Russellfb3f0f52007-07-27 17:16:56 +1000700 struct kvm_vcpu vcpu;
Avi Kivity313dbd42008-07-17 18:04:30 +0300701 unsigned long host_rsp;
Avi Kivity29bd8a72007-09-10 17:27:03 +0300702 u8 fail;
Avi Kivity9d58b932011-03-07 16:52:07 +0200703 bool nmi_known_unmasked;
Paolo Bonzini6236b782018-01-16 16:51:18 +0100704 u8 msr_bitmap_mode;
Avi Kivity51aa01d2010-07-20 14:31:20 +0300705 u32 exit_intr_info;
Avi Kivity1155f762007-11-22 11:30:47 +0200706 u32 idt_vectoring_info;
Avi Kivity6de12732011-03-07 12:51:22 +0200707 ulong rflags;
Avi Kivity26bb0982009-09-07 11:14:12 +0300708 struct shared_msr_entry *guest_msrs;
Gregory Haskinsa2fa3e92007-07-27 08:13:10 -0400709 int nmsrs;
710 int save_nmsrs;
Yang Zhanga547c6d2013-04-11 19:25:10 +0800711 unsigned long host_idt_base;
Gregory Haskinsa2fa3e92007-07-27 08:13:10 -0400712#ifdef CONFIG_X86_64
Avi Kivity44ea2b12009-09-06 15:55:37 +0300713 u64 msr_host_kernel_gs_base;
714 u64 msr_guest_kernel_gs_base;
Gregory Haskinsa2fa3e92007-07-27 08:13:10 -0400715#endif
Ashok Raj70131292018-02-01 22:59:43 +0100716
KarimAllah Ahmed755502f2018-02-01 22:59:44 +0100717 u64 arch_capabilities;
KarimAllah Ahmede5a83412018-02-01 22:59:45 +0100718 u64 spec_ctrl;
KarimAllah Ahmed755502f2018-02-01 22:59:44 +0100719
Gleb Natapov2961e8762013-11-25 15:37:13 +0200720 u32 vm_entry_controls_shadow;
721 u32 vm_exit_controls_shadow;
Nadav Har'Eld462b812011-05-24 15:26:10 +0300722 /*
723 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
724 * non-nested (L1) guest, it always points to vmcs01. For a nested
725 * guest (L2), it points to a different VMCS.
726 */
727 struct loaded_vmcs vmcs01;
728 struct loaded_vmcs *loaded_vmcs;
729 bool __launched; /* temporary, used in vmx_vcpu_run */
Avi Kivity61d2ef22010-04-28 16:40:38 +0300730 struct msr_autoload {
Konrad Rzeszutek Wilk57e3ada2018-06-20 13:58:37 -0400731 struct vmx_msrs guest;
732 struct vmx_msrs host;
Avi Kivity61d2ef22010-04-28 16:40:38 +0300733 } msr_autoload;
Gregory Haskinsa2fa3e92007-07-27 08:13:10 -0400734 struct {
735 int loaded;
736 u16 fs_sel, gs_sel, ldt_sel;
Avi Kivityb2da15a2012-05-13 19:53:24 +0300737#ifdef CONFIG_X86_64
738 u16 ds_sel, es_sel;
739#endif
Laurent Vivier152d3f22007-08-23 16:33:11 +0200740 int gs_ldt_reload_needed;
741 int fs_reload_needed;
Liu, Jinsongda8999d2014-02-24 10:55:46 +0000742 u64 msr_host_bndcfgs;
Andy Lutomirskid974baa2014-10-08 09:02:13 -0700743 unsigned long vmcs_host_cr4; /* May not match real cr4 */
Mike Dayd77c26f2007-10-08 09:02:08 -0400744 } host_state;
Avi Kivity9c8cba32007-11-22 11:42:59 +0200745 struct {
Avi Kivity7ffd92c2009-06-09 14:10:45 +0300746 int vm86_active;
Avi Kivity78ac8b42010-04-08 18:19:35 +0300747 ulong save_rflags;
Avi Kivityf5f7b2f2012-08-21 17:07:00 +0300748 struct kvm_segment segs[8];
749 } rmode;
750 struct {
751 u32 bitmask; /* 4 bits per segment (1 bit per field) */
Avi Kivity7ffd92c2009-06-09 14:10:45 +0300752 struct kvm_save_segment {
753 u16 selector;
754 unsigned long base;
755 u32 limit;
756 u32 ar;
Avi Kivityf5f7b2f2012-08-21 17:07:00 +0300757 } seg[8];
Avi Kivity2fb92db2011-04-27 19:42:18 +0300758 } segment_cache;
Sheng Yang2384d2b2008-01-17 15:14:33 +0800759 int vpid;
Mohammed Gamal04fa4d32008-08-17 16:39:48 +0300760 bool emulation_required;
Jan Kiszka3b86cd92008-09-26 09:30:57 +0200761
762 /* Support for vnmi-less CPUs */
763 int soft_vnmi_blocked;
764 ktime_t entry_time;
765 s64 vnmi_blocked_time;
Andi Kleena0861c02009-06-08 17:37:09 +0800766 u32 exit_reason;
Sheng Yang4e47c7a2009-12-18 16:48:47 +0800767
Yang Zhang01e439b2013-04-11 19:25:12 +0800768 /* Posted interrupt descriptor */
769 struct pi_desc pi_desc;
770
Nadav Har'Elec378ae2011-05-25 23:02:54 +0300771 /* Support for a guest hypervisor (nested VMX) */
772 struct nested_vmx nested;
Radim Krčmářa7653ec2014-08-21 18:08:07 +0200773
774 /* Dynamic PLE window. */
775 int ple_window;
776 bool ple_window_dirty;
Kai Huang843e4332015-01-28 10:54:28 +0800777
778 /* Support for PML */
779#define PML_ENTITY_NUM 512
780 struct page *pml_pg;
Owen Hofmann2680d6d2016-03-01 13:36:13 -0800781
Yunhong Jiang64672c92016-06-13 14:19:59 -0700782 /* apic deadline value in host tsc */
783 u64 hv_deadline_tsc;
784
Owen Hofmann2680d6d2016-03-01 13:36:13 -0800785 u64 current_tsc_ratio;
Xiao Guangrong1be0e612016-03-22 16:51:18 +0800786
787 bool guest_pkru_valid;
788 u32 guest_pkru;
789 u32 host_pkru;
Haozhong Zhang3b840802016-06-22 14:59:54 +0800790
Haozhong Zhang37e4c992016-06-22 14:59:55 +0800791 /*
792 * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
793 * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included
794 * in msr_ia32_feature_control_valid_bits.
795 */
Haozhong Zhang3b840802016-06-22 14:59:54 +0800796 u64 msr_ia32_feature_control;
Haozhong Zhang37e4c992016-06-22 14:59:55 +0800797 u64 msr_ia32_feature_control_valid_bits;
Gregory Haskinsa2fa3e92007-07-27 08:13:10 -0400798};
799
Avi Kivity2fb92db2011-04-27 19:42:18 +0300800enum segment_cache_field {
801 SEG_FIELD_SEL = 0,
802 SEG_FIELD_BASE = 1,
803 SEG_FIELD_LIMIT = 2,
804 SEG_FIELD_AR = 3,
805
806 SEG_FIELD_NR = 4
807};
808
Gregory Haskinsa2fa3e92007-07-27 08:13:10 -0400809static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
810{
Rusty Russellfb3f0f52007-07-27 17:16:56 +1000811 return container_of(vcpu, struct vcpu_vmx, vcpu);
Gregory Haskinsa2fa3e92007-07-27 08:13:10 -0400812}
813
Feng Wuefc64402015-09-18 22:29:51 +0800814static struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu)
815{
816 return &(to_vmx(vcpu)->pi_desc);
817}
818
Nadav Har'El22bd0352011-05-25 23:05:57 +0300819#define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
820#define FIELD(number, name) [number] = VMCS12_OFFSET(name)
821#define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
822 [number##_HIGH] = VMCS12_OFFSET(name)+4
823
Abel Gordon4607c2d2013-04-18 14:35:55 +0300824
Bandan Dasfe2b2012014-04-21 15:20:14 -0400825static unsigned long shadow_read_only_fields[] = {
Abel Gordon4607c2d2013-04-18 14:35:55 +0300826 /*
827 * We do NOT shadow fields that are modified when L0
828 * traps and emulates any vmx instruction (e.g. VMPTRLD,
829 * VMXON...) executed by L1.
830 * For example, VM_INSTRUCTION_ERROR is read
831 * by L1 if a vmx instruction fails (part of the error path).
832 * Note the code assumes this logic. If for some reason
833 * we start shadowing these fields then we need to
834 * force a shadow sync when L0 emulates vmx instructions
835 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
836 * by nested_vmx_failValid)
837 */
838 VM_EXIT_REASON,
839 VM_EXIT_INTR_INFO,
840 VM_EXIT_INSTRUCTION_LEN,
841 IDT_VECTORING_INFO_FIELD,
842 IDT_VECTORING_ERROR_CODE,
843 VM_EXIT_INTR_ERROR_CODE,
844 EXIT_QUALIFICATION,
845 GUEST_LINEAR_ADDRESS,
846 GUEST_PHYSICAL_ADDRESS
847};
Bandan Dasfe2b2012014-04-21 15:20:14 -0400848static int max_shadow_read_only_fields =
Abel Gordon4607c2d2013-04-18 14:35:55 +0300849 ARRAY_SIZE(shadow_read_only_fields);
850
Bandan Dasfe2b2012014-04-21 15:20:14 -0400851static unsigned long shadow_read_write_fields[] = {
Wanpeng Lia7c0b072014-08-21 19:46:50 +0800852 TPR_THRESHOLD,
Abel Gordon4607c2d2013-04-18 14:35:55 +0300853 GUEST_RIP,
854 GUEST_RSP,
855 GUEST_CR0,
856 GUEST_CR3,
857 GUEST_CR4,
858 GUEST_INTERRUPTIBILITY_INFO,
859 GUEST_RFLAGS,
860 GUEST_CS_SELECTOR,
861 GUEST_CS_AR_BYTES,
862 GUEST_CS_LIMIT,
863 GUEST_CS_BASE,
864 GUEST_ES_BASE,
Paolo Bonzini36be0b92014-02-24 12:30:04 +0100865 GUEST_BNDCFGS,
Abel Gordon4607c2d2013-04-18 14:35:55 +0300866 CR0_GUEST_HOST_MASK,
867 CR0_READ_SHADOW,
868 CR4_READ_SHADOW,
869 TSC_OFFSET,
870 EXCEPTION_BITMAP,
871 CPU_BASED_VM_EXEC_CONTROL,
872 VM_ENTRY_EXCEPTION_ERROR_CODE,
873 VM_ENTRY_INTR_INFO_FIELD,
874 VM_ENTRY_INSTRUCTION_LEN,
875 VM_ENTRY_EXCEPTION_ERROR_CODE,
876 HOST_FS_BASE,
877 HOST_GS_BASE,
878 HOST_FS_SELECTOR,
879 HOST_GS_SELECTOR
880};
Bandan Dasfe2b2012014-04-21 15:20:14 -0400881static int max_shadow_read_write_fields =
Abel Gordon4607c2d2013-04-18 14:35:55 +0300882 ARRAY_SIZE(shadow_read_write_fields);
883
Mathias Krause772e0312012-08-30 01:30:19 +0200884static const unsigned short vmcs_field_to_offset_table[] = {
Nadav Har'El22bd0352011-05-25 23:05:57 +0300885 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
Wincy Van705699a2015-02-03 23:58:17 +0800886 FIELD(POSTED_INTR_NV, posted_intr_nv),
Nadav Har'El22bd0352011-05-25 23:05:57 +0300887 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
888 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
889 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
890 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
891 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
892 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
893 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
894 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
Wincy Van608406e2015-02-03 23:57:51 +0800895 FIELD(GUEST_INTR_STATUS, guest_intr_status),
Nadav Har'El22bd0352011-05-25 23:05:57 +0300896 FIELD(HOST_ES_SELECTOR, host_es_selector),
897 FIELD(HOST_CS_SELECTOR, host_cs_selector),
898 FIELD(HOST_SS_SELECTOR, host_ss_selector),
899 FIELD(HOST_DS_SELECTOR, host_ds_selector),
900 FIELD(HOST_FS_SELECTOR, host_fs_selector),
901 FIELD(HOST_GS_SELECTOR, host_gs_selector),
902 FIELD(HOST_TR_SELECTOR, host_tr_selector),
903 FIELD64(IO_BITMAP_A, io_bitmap_a),
904 FIELD64(IO_BITMAP_B, io_bitmap_b),
905 FIELD64(MSR_BITMAP, msr_bitmap),
906 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
907 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
908 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
909 FIELD64(TSC_OFFSET, tsc_offset),
910 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
911 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
Wincy Van705699a2015-02-03 23:58:17 +0800912 FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
Nadav Har'El22bd0352011-05-25 23:05:57 +0300913 FIELD64(EPT_POINTER, ept_pointer),
Wincy Van608406e2015-02-03 23:57:51 +0800914 FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
915 FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
916 FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
917 FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
Wanpeng Li81dc01f2014-12-04 19:11:07 +0800918 FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
Nadav Har'El22bd0352011-05-25 23:05:57 +0300919 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
920 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
921 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
922 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
923 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
924 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
925 FIELD64(GUEST_PDPTR0, guest_pdptr0),
926 FIELD64(GUEST_PDPTR1, guest_pdptr1),
927 FIELD64(GUEST_PDPTR2, guest_pdptr2),
928 FIELD64(GUEST_PDPTR3, guest_pdptr3),
Paolo Bonzini36be0b92014-02-24 12:30:04 +0100929 FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
Nadav Har'El22bd0352011-05-25 23:05:57 +0300930 FIELD64(HOST_IA32_PAT, host_ia32_pat),
931 FIELD64(HOST_IA32_EFER, host_ia32_efer),
932 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
933 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
934 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
935 FIELD(EXCEPTION_BITMAP, exception_bitmap),
936 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
937 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
938 FIELD(CR3_TARGET_COUNT, cr3_target_count),
939 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
940 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
941 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
942 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
943 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
944 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
945 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
946 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
947 FIELD(TPR_THRESHOLD, tpr_threshold),
948 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
949 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
950 FIELD(VM_EXIT_REASON, vm_exit_reason),
951 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
952 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
953 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
954 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
955 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
956 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
957 FIELD(GUEST_ES_LIMIT, guest_es_limit),
958 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
959 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
960 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
961 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
962 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
963 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
964 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
965 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
966 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
967 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
968 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
969 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
970 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
971 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
972 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
973 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
974 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
975 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
976 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
977 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
978 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
Jan Kiszka0238ea92013-03-13 11:31:24 +0100979 FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
Nadav Har'El22bd0352011-05-25 23:05:57 +0300980 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
981 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
982 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
983 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
984 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
985 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
986 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
987 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
988 FIELD(EXIT_QUALIFICATION, exit_qualification),
989 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
990 FIELD(GUEST_CR0, guest_cr0),
991 FIELD(GUEST_CR3, guest_cr3),
992 FIELD(GUEST_CR4, guest_cr4),
993 FIELD(GUEST_ES_BASE, guest_es_base),
994 FIELD(GUEST_CS_BASE, guest_cs_base),
995 FIELD(GUEST_SS_BASE, guest_ss_base),
996 FIELD(GUEST_DS_BASE, guest_ds_base),
997 FIELD(GUEST_FS_BASE, guest_fs_base),
998 FIELD(GUEST_GS_BASE, guest_gs_base),
999 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
1000 FIELD(GUEST_TR_BASE, guest_tr_base),
1001 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
1002 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
1003 FIELD(GUEST_DR7, guest_dr7),
1004 FIELD(GUEST_RSP, guest_rsp),
1005 FIELD(GUEST_RIP, guest_rip),
1006 FIELD(GUEST_RFLAGS, guest_rflags),
1007 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
1008 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
1009 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
1010 FIELD(HOST_CR0, host_cr0),
1011 FIELD(HOST_CR3, host_cr3),
1012 FIELD(HOST_CR4, host_cr4),
1013 FIELD(HOST_FS_BASE, host_fs_base),
1014 FIELD(HOST_GS_BASE, host_gs_base),
1015 FIELD(HOST_TR_BASE, host_tr_base),
1016 FIELD(HOST_GDTR_BASE, host_gdtr_base),
1017 FIELD(HOST_IDTR_BASE, host_idtr_base),
1018 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
1019 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
1020 FIELD(HOST_RSP, host_rsp),
1021 FIELD(HOST_RIP, host_rip),
1022};
Nadav Har'El22bd0352011-05-25 23:05:57 +03001023
1024static inline short vmcs_field_to_offset(unsigned long field)
1025{
Dan Williamseb99bd62018-01-31 17:47:03 -08001026 const size_t size = ARRAY_SIZE(vmcs_field_to_offset_table);
1027 unsigned short offset;
Paolo Bonzinia2ae9df2014-11-04 18:31:19 +01001028
Dan Williamseb99bd62018-01-31 17:47:03 -08001029 BUILD_BUG_ON(size > SHRT_MAX);
1030 if (field >= size)
Andrew Honig012df712018-01-10 10:12:03 -08001031 return -ENOENT;
1032
Dan Williamseb99bd62018-01-31 17:47:03 -08001033 field = array_index_nospec(field, size);
1034 offset = vmcs_field_to_offset_table[field];
1035 if (offset == 0)
Paolo Bonzinia2ae9df2014-11-04 18:31:19 +01001036 return -ENOENT;
Dan Williamseb99bd62018-01-31 17:47:03 -08001037 return offset;
Nadav Har'El22bd0352011-05-25 23:05:57 +03001038}
1039
Nadav Har'Ela9d30f32011-05-25 23:03:55 +03001040static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
1041{
David Matlack4f2777b2016-07-13 17:16:37 -07001042 return to_vmx(vcpu)->nested.cached_vmcs12;
Nadav Har'Ela9d30f32011-05-25 23:03:55 +03001043}
1044
1045static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
1046{
Paolo Bonzini54bf36a2015-04-08 15:39:23 +02001047 struct page *page = kvm_vcpu_gfn_to_page(vcpu, addr >> PAGE_SHIFT);
Xiao Guangrong32cad842012-08-03 15:42:52 +08001048 if (is_error_page(page))
Nadav Har'Ela9d30f32011-05-25 23:03:55 +03001049 return NULL;
Xiao Guangrong32cad842012-08-03 15:42:52 +08001050
Nadav Har'Ela9d30f32011-05-25 23:03:55 +03001051 return page;
1052}
1053
1054static void nested_release_page(struct page *page)
1055{
1056 kvm_release_page_dirty(page);
1057}
1058
1059static void nested_release_page_clean(struct page *page)
1060{
1061 kvm_release_page_clean(page);
1062}
1063
Nadav Har'Elbfd0a562013-08-05 11:07:17 +03001064static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
Sheng Yang4e1096d2008-07-06 19:16:51 +08001065static u64 construct_eptp(unsigned long root_hpa);
Dongxiao Xu4610c9c2010-05-11 18:29:48 +08001066static void kvm_cpu_vmxon(u64 addr);
1067static void kvm_cpu_vmxoff(void);
Wanpeng Lif53cd632014-12-02 19:14:58 +08001068static bool vmx_xsaves_supported(void);
Gleb Natapov776e58e2011-03-13 12:34:27 +02001069static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
Orit Wassermanb246dd52012-05-31 14:49:22 +03001070static void vmx_set_segment(struct kvm_vcpu *vcpu,
1071 struct kvm_segment *var, int seg);
1072static void vmx_get_segment(struct kvm_vcpu *vcpu,
1073 struct kvm_segment *var, int seg);
Gleb Natapovd99e4152012-12-20 16:57:45 +02001074static bool guest_state_valid(struct kvm_vcpu *vcpu);
1075static u32 vmx_segment_access_rights(struct kvm_segment *var);
Abel Gordonc3114422013-04-18 14:38:55 +03001076static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
Abel Gordon16f5b902013-04-18 14:38:25 +03001077static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
Tang Chena255d472014-09-16 18:41:58 +08001078static int alloc_identity_pagetable(struct kvm *kvm);
Paolo Bonzini6236b782018-01-16 16:51:18 +01001079static void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu);
Ashok Raj70131292018-02-01 22:59:43 +01001080static void __always_inline vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
1081 u32 msr, int type);
Avi Kivity75880a02007-06-20 11:20:04 +03001082
Avi Kivity6aa8b732006-12-10 02:21:36 -08001083static DEFINE_PER_CPU(struct vmcs *, vmxarea);
1084static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
Nadav Har'Eld462b812011-05-24 15:26:10 +03001085/*
1086 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
1087 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
1088 */
1089static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
Avi Kivity3444d7d2010-07-26 18:32:38 +03001090static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
Avi Kivity6aa8b732006-12-10 02:21:36 -08001091
Feng Wubf9f6ac2015-09-18 22:29:55 +08001092/*
1093 * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
1094 * can find which vCPU should be waken up.
1095 */
1096static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
1097static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
1098
Avi Kivity3e7c73e2009-02-24 21:46:19 +02001099static unsigned long *vmx_io_bitmap_a;
1100static unsigned long *vmx_io_bitmap_b;
Abel Gordon4607c2d2013-04-18 14:35:55 +03001101static unsigned long *vmx_vmread_bitmap;
1102static unsigned long *vmx_vmwrite_bitmap;
He, Qingfdef3ad2007-04-30 09:45:24 +03001103
Avi Kivity110312c2010-12-21 12:54:20 +02001104static bool cpu_has_load_ia32_efer;
Gleb Natapov8bf00a52011-10-05 14:01:22 +02001105static bool cpu_has_load_perf_global_ctrl;
Avi Kivity110312c2010-12-21 12:54:20 +02001106
Sheng Yang2384d2b2008-01-17 15:14:33 +08001107static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
1108static DEFINE_SPINLOCK(vmx_vpid_lock);
1109
Yang, Sheng1c3d14fe2007-07-29 11:07:42 +03001110static struct vmcs_config {
Avi Kivity6aa8b732006-12-10 02:21:36 -08001111 int size;
1112 int order;
Jan Dakinevich9ac7e3e2016-09-04 21:23:15 +03001113 u32 basic_cap;
Avi Kivity6aa8b732006-12-10 02:21:36 -08001114 u32 revision_id;
Yang, Sheng1c3d14fe2007-07-29 11:07:42 +03001115 u32 pin_based_exec_ctrl;
1116 u32 cpu_based_exec_ctrl;
Sheng Yangf78e0e22007-10-29 09:40:42 +08001117 u32 cpu_based_2nd_exec_ctrl;
Yang, Sheng1c3d14fe2007-07-29 11:07:42 +03001118 u32 vmexit_ctrl;
1119 u32 vmentry_ctrl;
1120} vmcs_config;
Avi Kivity6aa8b732006-12-10 02:21:36 -08001121
Hannes Ederefff9e52008-11-28 17:02:06 +01001122static struct vmx_capability {
Sheng Yangd56f5462008-04-25 10:13:16 +08001123 u32 ept;
1124 u32 vpid;
1125} vmx_capability;
1126
Avi Kivity6aa8b732006-12-10 02:21:36 -08001127#define VMX_SEGMENT_FIELD(seg) \
1128 [VCPU_SREG_##seg] = { \
1129 .selector = GUEST_##seg##_SELECTOR, \
1130 .base = GUEST_##seg##_BASE, \
1131 .limit = GUEST_##seg##_LIMIT, \
1132 .ar_bytes = GUEST_##seg##_AR_BYTES, \
1133 }
1134
Mathias Krause772e0312012-08-30 01:30:19 +02001135static const struct kvm_vmx_segment_field {
Avi Kivity6aa8b732006-12-10 02:21:36 -08001136 unsigned selector;
1137 unsigned base;
1138 unsigned limit;
1139 unsigned ar_bytes;
1140} kvm_vmx_segment_fields[] = {
1141 VMX_SEGMENT_FIELD(CS),
1142 VMX_SEGMENT_FIELD(DS),
1143 VMX_SEGMENT_FIELD(ES),
1144 VMX_SEGMENT_FIELD(FS),
1145 VMX_SEGMENT_FIELD(GS),
1146 VMX_SEGMENT_FIELD(SS),
1147 VMX_SEGMENT_FIELD(TR),
1148 VMX_SEGMENT_FIELD(LDTR),
1149};
1150
Avi Kivity26bb0982009-09-07 11:14:12 +03001151static u64 host_efer;
1152
Avi Kivity6de4f3a2009-05-31 22:58:47 +03001153static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
1154
Avi Kivity4d56c8a2007-04-19 14:28:44 +03001155/*
Brian Gerst8c065852010-07-17 09:03:26 -04001156 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
Avi Kivity4d56c8a2007-04-19 14:28:44 +03001157 * away by decrementing the array size.
1158 */
Avi Kivity6aa8b732006-12-10 02:21:36 -08001159static const u32 vmx_msr_index[] = {
Avi Kivity05b3e0c2006-12-13 00:33:45 -08001160#ifdef CONFIG_X86_64
Avi Kivity44ea2b12009-09-06 15:55:37 +03001161 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
Avi Kivity6aa8b732006-12-10 02:21:36 -08001162#endif
Brian Gerst8c065852010-07-17 09:03:26 -04001163 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
Avi Kivity6aa8b732006-12-10 02:21:36 -08001164};
Avi Kivity6aa8b732006-12-10 02:21:36 -08001165
Jan Kiszka5bb16012016-02-09 20:14:21 +01001166static inline bool is_exception_n(u32 intr_info, u8 vector)
Avi Kivity6aa8b732006-12-10 02:21:36 -08001167{
1168 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1169 INTR_INFO_VALID_MASK)) ==
Jan Kiszka5bb16012016-02-09 20:14:21 +01001170 (INTR_TYPE_HARD_EXCEPTION | vector | INTR_INFO_VALID_MASK);
1171}
1172
Jan Kiszka6f054852016-02-09 20:15:18 +01001173static inline bool is_debug(u32 intr_info)
1174{
1175 return is_exception_n(intr_info, DB_VECTOR);
1176}
1177
1178static inline bool is_breakpoint(u32 intr_info)
1179{
1180 return is_exception_n(intr_info, BP_VECTOR);
1181}
1182
Jan Kiszka5bb16012016-02-09 20:14:21 +01001183static inline bool is_page_fault(u32 intr_info)
1184{
1185 return is_exception_n(intr_info, PF_VECTOR);
Avi Kivity6aa8b732006-12-10 02:21:36 -08001186}
1187
Gui Jianfeng31299942010-03-15 17:29:09 +08001188static inline bool is_no_device(u32 intr_info)
Anthony Liguori2ab455c2007-04-27 09:29:49 +03001189{
Jan Kiszka5bb16012016-02-09 20:14:21 +01001190 return is_exception_n(intr_info, NM_VECTOR);
Anthony Liguori2ab455c2007-04-27 09:29:49 +03001191}
1192
Gui Jianfeng31299942010-03-15 17:29:09 +08001193static inline bool is_invalid_opcode(u32 intr_info)
Anthony Liguori7aa81cc2007-09-17 14:57:50 -05001194{
Jan Kiszka5bb16012016-02-09 20:14:21 +01001195 return is_exception_n(intr_info, UD_VECTOR);
Anthony Liguori7aa81cc2007-09-17 14:57:50 -05001196}
1197
Gui Jianfeng31299942010-03-15 17:29:09 +08001198static inline bool is_external_interrupt(u32 intr_info)
Avi Kivity6aa8b732006-12-10 02:21:36 -08001199{
1200 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1201 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1202}
1203
Gui Jianfeng31299942010-03-15 17:29:09 +08001204static inline bool is_machine_check(u32 intr_info)
Andi Kleena0861c02009-06-08 17:37:09 +08001205{
1206 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1207 INTR_INFO_VALID_MASK)) ==
1208 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
1209}
1210
Linus Torvalds587da2b2018-03-20 12:16:59 -07001211/* Undocumented: icebp/int1 */
1212static inline bool is_icebp(u32 intr_info)
1213{
1214 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1215 == (INTR_TYPE_PRIV_SW_EXCEPTION | INTR_INFO_VALID_MASK);
1216}
1217
Gui Jianfeng31299942010-03-15 17:29:09 +08001218static inline bool cpu_has_vmx_msr_bitmap(void)
Sheng Yang25c5f222008-03-28 13:18:56 +08001219{
Sheng Yang04547152009-04-01 15:52:31 +08001220 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
Sheng Yang25c5f222008-03-28 13:18:56 +08001221}
1222
Gui Jianfeng31299942010-03-15 17:29:09 +08001223static inline bool cpu_has_vmx_tpr_shadow(void)
Yang, Sheng6e5d8652007-09-12 18:03:11 +08001224{
Sheng Yang04547152009-04-01 15:52:31 +08001225 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
Yang, Sheng6e5d8652007-09-12 18:03:11 +08001226}
1227
Paolo Bonzini35754c92015-07-29 12:05:37 +02001228static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu)
Yang, Sheng6e5d8652007-09-12 18:03:11 +08001229{
Paolo Bonzini35754c92015-07-29 12:05:37 +02001230 return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu);
Yang, Sheng6e5d8652007-09-12 18:03:11 +08001231}
1232
Gui Jianfeng31299942010-03-15 17:29:09 +08001233static inline bool cpu_has_secondary_exec_ctrls(void)
Sheng Yangf78e0e22007-10-29 09:40:42 +08001234{
Sheng Yang04547152009-04-01 15:52:31 +08001235 return vmcs_config.cpu_based_exec_ctrl &
1236 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
Sheng Yangf78e0e22007-10-29 09:40:42 +08001237}
1238
Avi Kivity774ead32007-12-26 13:57:04 +02001239static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
Sheng Yangf78e0e22007-10-29 09:40:42 +08001240{
Sheng Yang04547152009-04-01 15:52:31 +08001241 return vmcs_config.cpu_based_2nd_exec_ctrl &
1242 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1243}
1244
Yang Zhang8d146952013-01-25 10:18:50 +08001245static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1246{
1247 return vmcs_config.cpu_based_2nd_exec_ctrl &
1248 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
1249}
1250
Yang Zhang83d4c282013-01-25 10:18:49 +08001251static inline bool cpu_has_vmx_apic_register_virt(void)
1252{
1253 return vmcs_config.cpu_based_2nd_exec_ctrl &
1254 SECONDARY_EXEC_APIC_REGISTER_VIRT;
1255}
1256
Yang Zhangc7c9c562013-01-25 10:18:51 +08001257static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1258{
1259 return vmcs_config.cpu_based_2nd_exec_ctrl &
1260 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1261}
1262
Yunhong Jiang64672c92016-06-13 14:19:59 -07001263/*
1264 * Comment's format: document - errata name - stepping - processor name.
1265 * Refer from
1266 * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
1267 */
1268static u32 vmx_preemption_cpu_tfms[] = {
1269/* 323344.pdf - BA86 - D0 - Xeon 7500 Series */
12700x000206E6,
1271/* 323056.pdf - AAX65 - C2 - Xeon L3406 */
1272/* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
1273/* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
12740x00020652,
1275/* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
12760x00020655,
1277/* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */
1278/* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */
1279/*
1280 * 320767.pdf - AAP86 - B1 -
1281 * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
1282 */
12830x000106E5,
1284/* 321333.pdf - AAM126 - C0 - Xeon 3500 */
12850x000106A0,
1286/* 321333.pdf - AAM126 - C1 - Xeon 3500 */
12870x000106A1,
1288/* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
12890x000106A4,
1290 /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
1291 /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
1292 /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
12930x000106A5,
1294};
1295
1296static inline bool cpu_has_broken_vmx_preemption_timer(void)
1297{
1298 u32 eax = cpuid_eax(0x00000001), i;
1299
1300 /* Clear the reserved bits */
1301 eax &= ~(0x3U << 14 | 0xfU << 28);
Wei Yongjun03f6a222016-07-04 15:13:07 +00001302 for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
Yunhong Jiang64672c92016-06-13 14:19:59 -07001303 if (eax == vmx_preemption_cpu_tfms[i])
1304 return true;
1305
1306 return false;
1307}
1308
1309static inline bool cpu_has_vmx_preemption_timer(void)
1310{
Yunhong Jiang64672c92016-06-13 14:19:59 -07001311 return vmcs_config.pin_based_exec_ctrl &
1312 PIN_BASED_VMX_PREEMPTION_TIMER;
1313}
1314
Yang Zhang01e439b2013-04-11 19:25:12 +08001315static inline bool cpu_has_vmx_posted_intr(void)
1316{
Paolo Bonzinid6a858d2015-09-28 11:58:14 +02001317 return IS_ENABLED(CONFIG_X86_LOCAL_APIC) &&
1318 vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
Yang Zhang01e439b2013-04-11 19:25:12 +08001319}
1320
1321static inline bool cpu_has_vmx_apicv(void)
1322{
1323 return cpu_has_vmx_apic_register_virt() &&
1324 cpu_has_vmx_virtual_intr_delivery() &&
1325 cpu_has_vmx_posted_intr();
1326}
1327
Sheng Yang04547152009-04-01 15:52:31 +08001328static inline bool cpu_has_vmx_flexpriority(void)
1329{
1330 return cpu_has_vmx_tpr_shadow() &&
1331 cpu_has_vmx_virtualize_apic_accesses();
Sheng Yangf78e0e22007-10-29 09:40:42 +08001332}
1333
Marcelo Tosattie7997942009-06-11 12:07:40 -03001334static inline bool cpu_has_vmx_ept_execute_only(void)
1335{
Gui Jianfeng31299942010-03-15 17:29:09 +08001336 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
Marcelo Tosattie7997942009-06-11 12:07:40 -03001337}
1338
Marcelo Tosattie7997942009-06-11 12:07:40 -03001339static inline bool cpu_has_vmx_ept_2m_page(void)
1340{
Gui Jianfeng31299942010-03-15 17:29:09 +08001341 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
Marcelo Tosattie7997942009-06-11 12:07:40 -03001342}
1343
Sheng Yang878403b2010-01-05 19:02:29 +08001344static inline bool cpu_has_vmx_ept_1g_page(void)
1345{
Gui Jianfeng31299942010-03-15 17:29:09 +08001346 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
Sheng Yang878403b2010-01-05 19:02:29 +08001347}
1348
Sheng Yang4bc9b982010-06-02 14:05:24 +08001349static inline bool cpu_has_vmx_ept_4levels(void)
1350{
1351 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1352}
1353
Xudong Hao83c3a332012-05-28 19:33:35 +08001354static inline bool cpu_has_vmx_ept_ad_bits(void)
1355{
1356 return vmx_capability.ept & VMX_EPT_AD_BIT;
1357}
1358
Gui Jianfeng31299942010-03-15 17:29:09 +08001359static inline bool cpu_has_vmx_invept_context(void)
Sheng Yangd56f5462008-04-25 10:13:16 +08001360{
Gui Jianfeng31299942010-03-15 17:29:09 +08001361 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
Sheng Yangd56f5462008-04-25 10:13:16 +08001362}
1363
Gui Jianfeng31299942010-03-15 17:29:09 +08001364static inline bool cpu_has_vmx_invept_global(void)
Sheng Yangd56f5462008-04-25 10:13:16 +08001365{
Gui Jianfeng31299942010-03-15 17:29:09 +08001366 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
Sheng Yangd56f5462008-04-25 10:13:16 +08001367}
1368
Gui Jianfeng518c8ae2010-06-04 08:51:39 +08001369static inline bool cpu_has_vmx_invvpid_single(void)
1370{
1371 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1372}
1373
Gui Jianfengb9d762f2010-06-07 10:32:29 +08001374static inline bool cpu_has_vmx_invvpid_global(void)
1375{
1376 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1377}
1378
Wanpeng Li2df19692017-03-23 05:30:08 -07001379static inline bool cpu_has_vmx_invvpid(void)
1380{
1381 return vmx_capability.vpid & VMX_VPID_INVVPID_BIT;
1382}
1383
Gui Jianfeng31299942010-03-15 17:29:09 +08001384static inline bool cpu_has_vmx_ept(void)
Sheng Yangd56f5462008-04-25 10:13:16 +08001385{
Sheng Yang04547152009-04-01 15:52:31 +08001386 return vmcs_config.cpu_based_2nd_exec_ctrl &
1387 SECONDARY_EXEC_ENABLE_EPT;
Sheng Yangd56f5462008-04-25 10:13:16 +08001388}
1389
Gui Jianfeng31299942010-03-15 17:29:09 +08001390static inline bool cpu_has_vmx_unrestricted_guest(void)
Nitin A Kamble3a624e22009-06-08 11:34:16 -07001391{
1392 return vmcs_config.cpu_based_2nd_exec_ctrl &
1393 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1394}
1395
Gui Jianfeng31299942010-03-15 17:29:09 +08001396static inline bool cpu_has_vmx_ple(void)
Zhai, Edwin4b8d54f2009-10-09 18:03:20 +08001397{
1398 return vmcs_config.cpu_based_2nd_exec_ctrl &
1399 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1400}
1401
Jan Dakinevich9ac7e3e2016-09-04 21:23:15 +03001402static inline bool cpu_has_vmx_basic_inout(void)
1403{
1404 return (((u64)vmcs_config.basic_cap << 32) & VMX_BASIC_INOUT);
1405}
1406
Paolo Bonzini35754c92015-07-29 12:05:37 +02001407static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
Sheng Yangf78e0e22007-10-29 09:40:42 +08001408{
Paolo Bonzini35754c92015-07-29 12:05:37 +02001409 return flexpriority_enabled && lapic_in_kernel(vcpu);
Sheng Yangf78e0e22007-10-29 09:40:42 +08001410}
1411
Gui Jianfeng31299942010-03-15 17:29:09 +08001412static inline bool cpu_has_vmx_vpid(void)
Sheng Yang2384d2b2008-01-17 15:14:33 +08001413{
Sheng Yang04547152009-04-01 15:52:31 +08001414 return vmcs_config.cpu_based_2nd_exec_ctrl &
1415 SECONDARY_EXEC_ENABLE_VPID;
Sheng Yang2384d2b2008-01-17 15:14:33 +08001416}
1417
Gui Jianfeng31299942010-03-15 17:29:09 +08001418static inline bool cpu_has_vmx_rdtscp(void)
Sheng Yang4e47c7a2009-12-18 16:48:47 +08001419{
1420 return vmcs_config.cpu_based_2nd_exec_ctrl &
1421 SECONDARY_EXEC_RDTSCP;
1422}
1423
Mao, Junjiead756a12012-07-02 01:18:48 +00001424static inline bool cpu_has_vmx_invpcid(void)
1425{
1426 return vmcs_config.cpu_based_2nd_exec_ctrl &
1427 SECONDARY_EXEC_ENABLE_INVPCID;
1428}
1429
Gui Jianfeng31299942010-03-15 17:29:09 +08001430static inline bool cpu_has_virtual_nmis(void)
Sheng Yangf08864b2008-05-15 18:23:25 +08001431{
1432 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1433}
1434
Sheng Yangf5f48ee2010-06-30 12:25:15 +08001435static inline bool cpu_has_vmx_wbinvd_exit(void)
1436{
1437 return vmcs_config.cpu_based_2nd_exec_ctrl &
1438 SECONDARY_EXEC_WBINVD_EXITING;
1439}
1440
Abel Gordonabc4fc52013-04-18 14:35:25 +03001441static inline bool cpu_has_vmx_shadow_vmcs(void)
1442{
1443 u64 vmx_msr;
1444 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1445 /* check if the cpu supports writing r/o exit information fields */
1446 if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1447 return false;
1448
1449 return vmcs_config.cpu_based_2nd_exec_ctrl &
1450 SECONDARY_EXEC_SHADOW_VMCS;
1451}
1452
Kai Huang843e4332015-01-28 10:54:28 +08001453static inline bool cpu_has_vmx_pml(void)
1454{
1455 return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1456}
1457
Haozhong Zhang64903d62015-10-20 15:39:09 +08001458static inline bool cpu_has_vmx_tsc_scaling(void)
1459{
1460 return vmcs_config.cpu_based_2nd_exec_ctrl &
1461 SECONDARY_EXEC_TSC_SCALING;
1462}
1463
Sheng Yang04547152009-04-01 15:52:31 +08001464static inline bool report_flexpriority(void)
1465{
1466 return flexpriority_enabled;
1467}
1468
Nadav Har'Elfe3ef052011-05-25 23:10:02 +03001469static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1470{
1471 return vmcs12->cpu_based_vm_exec_control & bit;
1472}
1473
1474static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1475{
1476 return (vmcs12->cpu_based_vm_exec_control &
1477 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1478 (vmcs12->secondary_vm_exec_control & bit);
1479}
1480
Nadav Har'Elf5c43682013-08-05 11:07:20 +03001481static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
Nadav Har'El644d7112011-05-25 23:12:35 +03001482{
1483 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1484}
1485
Jan Kiszkaf4124502014-03-07 20:03:13 +01001486static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1487{
1488 return vmcs12->pin_based_vm_exec_control &
1489 PIN_BASED_VMX_PREEMPTION_TIMER;
1490}
1491
Nadav Har'El155a97a2013-08-05 11:07:16 +03001492static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1493{
1494 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1495}
1496
Wanpeng Li81dc01f2014-12-04 19:11:07 +08001497static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1498{
1499 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES) &&
1500 vmx_xsaves_supported();
1501}
1502
Wincy Vanf2b93282015-02-03 23:56:03 +08001503static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1504{
1505 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1506}
1507
Wanpeng Li5c614b32015-10-13 09:18:36 -07001508static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12)
1509{
1510 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID);
1511}
1512
Wincy Van82f0dd42015-02-03 23:57:18 +08001513static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1514{
1515 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1516}
1517
Wincy Van608406e2015-02-03 23:57:51 +08001518static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1519{
1520 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1521}
1522
Wincy Van705699a2015-02-03 23:58:17 +08001523static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1524{
1525 return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1526}
1527
Jim Mattson3f618a02016-12-12 11:01:37 -08001528static inline bool is_nmi(u32 intr_info)
Nadav Har'El644d7112011-05-25 23:12:35 +03001529{
1530 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
Jim Mattson3f618a02016-12-12 11:01:37 -08001531 == (INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK);
Nadav Har'El644d7112011-05-25 23:12:35 +03001532}
1533
Jan Kiszka533558b2014-01-04 18:47:20 +01001534static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1535 u32 exit_intr_info,
1536 unsigned long exit_qualification);
Nadav Har'El7c177932011-05-25 23:12:04 +03001537static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1538 struct vmcs12 *vmcs12,
1539 u32 reason, unsigned long qualification);
1540
Rusty Russell8b9cf982007-07-30 16:31:43 +10001541static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
Avi Kivity7725f0b2006-12-13 00:34:01 -08001542{
1543 int i;
1544
Gregory Haskinsa2fa3e92007-07-27 08:13:10 -04001545 for (i = 0; i < vmx->nmsrs; ++i)
Avi Kivity26bb0982009-09-07 11:14:12 +03001546 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
Eddie Donga75beee2007-05-17 18:55:15 +03001547 return i;
1548 return -1;
1549}
1550
Sheng Yang2384d2b2008-01-17 15:14:33 +08001551static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1552{
1553 struct {
1554 u64 vpid : 16;
1555 u64 rsvd : 48;
1556 u64 gva;
1557 } operand = { vpid, 0, gva };
1558
Avi Kivity4ecac3f2008-05-13 13:23:38 +03001559 asm volatile (__ex(ASM_VMX_INVVPID)
Sheng Yang2384d2b2008-01-17 15:14:33 +08001560 /* CF==1 or ZF==1 --> rc = -1 */
1561 "; ja 1f ; ud2 ; 1:"
1562 : : "a"(&operand), "c"(ext) : "cc", "memory");
1563}
1564
Sheng Yang14394422008-04-28 12:24:45 +08001565static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1566{
1567 struct {
1568 u64 eptp, gpa;
1569 } operand = {eptp, gpa};
1570
Avi Kivity4ecac3f2008-05-13 13:23:38 +03001571 asm volatile (__ex(ASM_VMX_INVEPT)
Sheng Yang14394422008-04-28 12:24:45 +08001572 /* CF==1 or ZF==1 --> rc = -1 */
1573 "; ja 1f ; ud2 ; 1:\n"
1574 : : "a" (&operand), "c" (ext) : "cc", "memory");
1575}
1576
Avi Kivity26bb0982009-09-07 11:14:12 +03001577static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
Eddie Donga75beee2007-05-17 18:55:15 +03001578{
1579 int i;
1580
Rusty Russell8b9cf982007-07-30 16:31:43 +10001581 i = __find_msr_index(vmx, msr);
Eddie Donga75beee2007-05-17 18:55:15 +03001582 if (i >= 0)
Gregory Haskinsa2fa3e92007-07-27 08:13:10 -04001583 return &vmx->guest_msrs[i];
Al Viro8b6d44c2007-02-09 16:38:40 +00001584 return NULL;
Avi Kivity7725f0b2006-12-13 00:34:01 -08001585}
1586
Avi Kivity6aa8b732006-12-10 02:21:36 -08001587static void vmcs_clear(struct vmcs *vmcs)
1588{
1589 u64 phys_addr = __pa(vmcs);
1590 u8 error;
1591
Avi Kivity4ecac3f2008-05-13 13:23:38 +03001592 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
Avi Kivity16d8f722010-12-21 16:51:50 +02001593 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
Avi Kivity6aa8b732006-12-10 02:21:36 -08001594 : "cc", "memory");
1595 if (error)
1596 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1597 vmcs, phys_addr);
1598}
1599
Nadav Har'Eld462b812011-05-24 15:26:10 +03001600static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1601{
1602 vmcs_clear(loaded_vmcs->vmcs);
Jim Mattson355f4fb2016-10-28 08:29:39 -07001603 if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
1604 vmcs_clear(loaded_vmcs->shadow_vmcs);
Nadav Har'Eld462b812011-05-24 15:26:10 +03001605 loaded_vmcs->cpu = -1;
1606 loaded_vmcs->launched = 0;
1607}
1608
Dongxiao Xu7725b892010-05-11 18:29:38 +08001609static void vmcs_load(struct vmcs *vmcs)
1610{
1611 u64 phys_addr = __pa(vmcs);
1612 u8 error;
1613
1614 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
Avi Kivity16d8f722010-12-21 16:51:50 +02001615 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
Dongxiao Xu7725b892010-05-11 18:29:38 +08001616 : "cc", "memory");
1617 if (error)
Nadav Har'El2844d842011-05-25 23:16:40 +03001618 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
Dongxiao Xu7725b892010-05-11 18:29:38 +08001619 vmcs, phys_addr);
1620}
1621
Dave Young2965faa2015-09-09 15:38:55 -07001622#ifdef CONFIG_KEXEC_CORE
Zhang Yanfei8f536b72012-12-06 23:43:34 +08001623/*
1624 * This bitmap is used to indicate whether the vmclear
1625 * operation is enabled on all cpus. All disabled by
1626 * default.
1627 */
1628static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1629
1630static inline void crash_enable_local_vmclear(int cpu)
1631{
1632 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1633}
1634
1635static inline void crash_disable_local_vmclear(int cpu)
1636{
1637 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1638}
1639
1640static inline int crash_local_vmclear_enabled(int cpu)
1641{
1642 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1643}
1644
1645static void crash_vmclear_local_loaded_vmcss(void)
1646{
1647 int cpu = raw_smp_processor_id();
1648 struct loaded_vmcs *v;
1649
1650 if (!crash_local_vmclear_enabled(cpu))
1651 return;
1652
1653 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1654 loaded_vmcss_on_cpu_link)
1655 vmcs_clear(v->vmcs);
1656}
1657#else
1658static inline void crash_enable_local_vmclear(int cpu) { }
1659static inline void crash_disable_local_vmclear(int cpu) { }
Dave Young2965faa2015-09-09 15:38:55 -07001660#endif /* CONFIG_KEXEC_CORE */
Zhang Yanfei8f536b72012-12-06 23:43:34 +08001661
Nadav Har'Eld462b812011-05-24 15:26:10 +03001662static void __loaded_vmcs_clear(void *arg)
Avi Kivity6aa8b732006-12-10 02:21:36 -08001663{
Nadav Har'Eld462b812011-05-24 15:26:10 +03001664 struct loaded_vmcs *loaded_vmcs = arg;
Ingo Molnard3b2c332007-01-05 16:36:23 -08001665 int cpu = raw_smp_processor_id();
Avi Kivity6aa8b732006-12-10 02:21:36 -08001666
Nadav Har'Eld462b812011-05-24 15:26:10 +03001667 if (loaded_vmcs->cpu != cpu)
1668 return; /* vcpu migration can race with cpu offline */
1669 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
Avi Kivity6aa8b732006-12-10 02:21:36 -08001670 per_cpu(current_vmcs, cpu) = NULL;
Zhang Yanfei8f536b72012-12-06 23:43:34 +08001671 crash_disable_local_vmclear(cpu);
Nadav Har'Eld462b812011-05-24 15:26:10 +03001672 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
Xiao Guangrong5a560f82012-11-28 20:54:14 +08001673
1674 /*
1675 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1676 * is before setting loaded_vmcs->vcpu to -1 which is done in
1677 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1678 * then adds the vmcs into percpu list before it is deleted.
1679 */
1680 smp_wmb();
1681
Nadav Har'Eld462b812011-05-24 15:26:10 +03001682 loaded_vmcs_init(loaded_vmcs);
Zhang Yanfei8f536b72012-12-06 23:43:34 +08001683 crash_enable_local_vmclear(cpu);
Avi Kivity6aa8b732006-12-10 02:21:36 -08001684}
1685
Nadav Har'Eld462b812011-05-24 15:26:10 +03001686static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
Avi Kivity8d0be2b2007-02-12 00:54:46 -08001687{
Xiao Guangronge6c7d322012-11-28 20:53:15 +08001688 int cpu = loaded_vmcs->cpu;
1689
1690 if (cpu != -1)
1691 smp_call_function_single(cpu,
1692 __loaded_vmcs_clear, loaded_vmcs, 1);
Avi Kivity8d0be2b2007-02-12 00:54:46 -08001693}
1694
Wanpeng Lidd5f5342015-09-23 18:26:57 +08001695static inline void vpid_sync_vcpu_single(int vpid)
Sheng Yang2384d2b2008-01-17 15:14:33 +08001696{
Wanpeng Lidd5f5342015-09-23 18:26:57 +08001697 if (vpid == 0)
Sheng Yang2384d2b2008-01-17 15:14:33 +08001698 return;
1699
Gui Jianfeng518c8ae2010-06-04 08:51:39 +08001700 if (cpu_has_vmx_invvpid_single())
Wanpeng Lidd5f5342015-09-23 18:26:57 +08001701 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0);
Sheng Yang2384d2b2008-01-17 15:14:33 +08001702}
1703
Gui Jianfengb9d762f2010-06-07 10:32:29 +08001704static inline void vpid_sync_vcpu_global(void)
1705{
1706 if (cpu_has_vmx_invvpid_global())
1707 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1708}
1709
Wanpeng Lidd5f5342015-09-23 18:26:57 +08001710static inline void vpid_sync_context(int vpid)
Gui Jianfengb9d762f2010-06-07 10:32:29 +08001711{
1712 if (cpu_has_vmx_invvpid_single())
Wanpeng Lidd5f5342015-09-23 18:26:57 +08001713 vpid_sync_vcpu_single(vpid);
Gui Jianfengb9d762f2010-06-07 10:32:29 +08001714 else
1715 vpid_sync_vcpu_global();
1716}
1717
Sheng Yang14394422008-04-28 12:24:45 +08001718static inline void ept_sync_global(void)
1719{
1720 if (cpu_has_vmx_invept_global())
1721 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1722}
1723
1724static inline void ept_sync_context(u64 eptp)
1725{
Avi Kivity089d0342009-03-23 18:26:32 +02001726 if (enable_ept) {
Sheng Yang14394422008-04-28 12:24:45 +08001727 if (cpu_has_vmx_invept_context())
1728 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1729 else
1730 ept_sync_global();
1731 }
1732}
1733
Paolo Bonzini8a86aea92015-12-03 15:56:55 +01001734static __always_inline void vmcs_check16(unsigned long field)
1735{
1736 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1737 "16-bit accessor invalid for 64-bit field");
1738 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1739 "16-bit accessor invalid for 64-bit high field");
1740 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1741 "16-bit accessor invalid for 32-bit high field");
1742 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1743 "16-bit accessor invalid for natural width field");
1744}
1745
1746static __always_inline void vmcs_check32(unsigned long field)
1747{
1748 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1749 "32-bit accessor invalid for 16-bit field");
1750 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1751 "32-bit accessor invalid for natural width field");
1752}
1753
1754static __always_inline void vmcs_check64(unsigned long field)
1755{
1756 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1757 "64-bit accessor invalid for 16-bit field");
1758 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1759 "64-bit accessor invalid for 64-bit high field");
1760 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1761 "64-bit accessor invalid for 32-bit field");
1762 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1763 "64-bit accessor invalid for natural width field");
1764}
1765
1766static __always_inline void vmcs_checkl(unsigned long field)
1767{
1768 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1769 "Natural width accessor invalid for 16-bit field");
1770 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1771 "Natural width accessor invalid for 64-bit field");
1772 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1773 "Natural width accessor invalid for 64-bit high field");
1774 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1775 "Natural width accessor invalid for 32-bit field");
1776}
1777
1778static __always_inline unsigned long __vmcs_readl(unsigned long field)
Avi Kivity6aa8b732006-12-10 02:21:36 -08001779{
Avi Kivity5e520e62011-05-15 10:13:12 -04001780 unsigned long value;
Avi Kivity6aa8b732006-12-10 02:21:36 -08001781
Avi Kivity5e520e62011-05-15 10:13:12 -04001782 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1783 : "=a"(value) : "d"(field) : "cc");
Avi Kivity6aa8b732006-12-10 02:21:36 -08001784 return value;
1785}
1786
Avi Kivity96304212011-05-15 10:13:13 -04001787static __always_inline u16 vmcs_read16(unsigned long field)
Avi Kivity6aa8b732006-12-10 02:21:36 -08001788{
Paolo Bonzini8a86aea92015-12-03 15:56:55 +01001789 vmcs_check16(field);
1790 return __vmcs_readl(field);
Avi Kivity6aa8b732006-12-10 02:21:36 -08001791}
1792
Avi Kivity96304212011-05-15 10:13:13 -04001793static __always_inline u32 vmcs_read32(unsigned long field)
Avi Kivity6aa8b732006-12-10 02:21:36 -08001794{
Paolo Bonzini8a86aea92015-12-03 15:56:55 +01001795 vmcs_check32(field);
1796 return __vmcs_readl(field);
Avi Kivity6aa8b732006-12-10 02:21:36 -08001797}
1798
Avi Kivity96304212011-05-15 10:13:13 -04001799static __always_inline u64 vmcs_read64(unsigned long field)
Avi Kivity6aa8b732006-12-10 02:21:36 -08001800{
Paolo Bonzini8a86aea92015-12-03 15:56:55 +01001801 vmcs_check64(field);
Avi Kivity05b3e0c2006-12-13 00:33:45 -08001802#ifdef CONFIG_X86_64
Paolo Bonzini8a86aea92015-12-03 15:56:55 +01001803 return __vmcs_readl(field);
Avi Kivity6aa8b732006-12-10 02:21:36 -08001804#else
Paolo Bonzini8a86aea92015-12-03 15:56:55 +01001805 return __vmcs_readl(field) | ((u64)__vmcs_readl(field+1) << 32);
Avi Kivity6aa8b732006-12-10 02:21:36 -08001806#endif
1807}
1808
Paolo Bonzini8a86aea92015-12-03 15:56:55 +01001809static __always_inline unsigned long vmcs_readl(unsigned long field)
1810{
1811 vmcs_checkl(field);
1812 return __vmcs_readl(field);
1813}
1814
Avi Kivitye52de1b2007-01-05 16:36:56 -08001815static noinline void vmwrite_error(unsigned long field, unsigned long value)
1816{
1817 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1818 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1819 dump_stack();
1820}
1821
Paolo Bonzini8a86aea92015-12-03 15:56:55 +01001822static __always_inline void __vmcs_writel(unsigned long field, unsigned long value)
Avi Kivity6aa8b732006-12-10 02:21:36 -08001823{
1824 u8 error;
1825
Avi Kivity4ecac3f2008-05-13 13:23:38 +03001826 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
Mike Dayd77c26f2007-10-08 09:02:08 -04001827 : "=q"(error) : "a"(value), "d"(field) : "cc");
Avi Kivitye52de1b2007-01-05 16:36:56 -08001828 if (unlikely(error))
1829 vmwrite_error(field, value);
Avi Kivity6aa8b732006-12-10 02:21:36 -08001830}
1831
Paolo Bonzini8a86aea92015-12-03 15:56:55 +01001832static __always_inline void vmcs_write16(unsigned long field, u16 value)
Avi Kivity6aa8b732006-12-10 02:21:36 -08001833{
Paolo Bonzini8a86aea92015-12-03 15:56:55 +01001834 vmcs_check16(field);
1835 __vmcs_writel(field, value);
Avi Kivity6aa8b732006-12-10 02:21:36 -08001836}
1837
Paolo Bonzini8a86aea92015-12-03 15:56:55 +01001838static __always_inline void vmcs_write32(unsigned long field, u32 value)
Avi Kivity6aa8b732006-12-10 02:21:36 -08001839{
Paolo Bonzini8a86aea92015-12-03 15:56:55 +01001840 vmcs_check32(field);
1841 __vmcs_writel(field, value);
Avi Kivity6aa8b732006-12-10 02:21:36 -08001842}
1843
Paolo Bonzini8a86aea92015-12-03 15:56:55 +01001844static __always_inline void vmcs_write64(unsigned long field, u64 value)
Avi Kivity6aa8b732006-12-10 02:21:36 -08001845{
Paolo Bonzini8a86aea92015-12-03 15:56:55 +01001846 vmcs_check64(field);
1847 __vmcs_writel(field, value);
Avi Kivity7682f2d2008-05-12 19:25:43 +03001848#ifndef CONFIG_X86_64
Avi Kivity6aa8b732006-12-10 02:21:36 -08001849 asm volatile ("");
Paolo Bonzini8a86aea92015-12-03 15:56:55 +01001850 __vmcs_writel(field+1, value >> 32);
Avi Kivity6aa8b732006-12-10 02:21:36 -08001851#endif
1852}
1853
Paolo Bonzini8a86aea92015-12-03 15:56:55 +01001854static __always_inline void vmcs_writel(unsigned long field, unsigned long value)
Anthony Liguori2ab455c2007-04-27 09:29:49 +03001855{
Paolo Bonzini8a86aea92015-12-03 15:56:55 +01001856 vmcs_checkl(field);
1857 __vmcs_writel(field, value);
Anthony Liguori2ab455c2007-04-27 09:29:49 +03001858}
1859
Paolo Bonzini8a86aea92015-12-03 15:56:55 +01001860static __always_inline void vmcs_clear_bits(unsigned long field, u32 mask)
Anthony Liguori2ab455c2007-04-27 09:29:49 +03001861{
Paolo Bonzini8a86aea92015-12-03 15:56:55 +01001862 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1863 "vmcs_clear_bits does not support 64-bit fields");
1864 __vmcs_writel(field, __vmcs_readl(field) & ~mask);
1865}
1866
1867static __always_inline void vmcs_set_bits(unsigned long field, u32 mask)
1868{
1869 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1870 "vmcs_set_bits does not support 64-bit fields");
1871 __vmcs_writel(field, __vmcs_readl(field) | mask);
Anthony Liguori2ab455c2007-04-27 09:29:49 +03001872}
1873
Paolo Bonzini8391ce42016-07-07 14:58:33 +02001874static inline void vm_entry_controls_reset_shadow(struct vcpu_vmx *vmx)
1875{
1876 vmx->vm_entry_controls_shadow = vmcs_read32(VM_ENTRY_CONTROLS);
1877}
1878
Gleb Natapov2961e8762013-11-25 15:37:13 +02001879static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1880{
1881 vmcs_write32(VM_ENTRY_CONTROLS, val);
1882 vmx->vm_entry_controls_shadow = val;
1883}
1884
1885static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1886{
1887 if (vmx->vm_entry_controls_shadow != val)
1888 vm_entry_controls_init(vmx, val);
1889}
1890
1891static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1892{
1893 return vmx->vm_entry_controls_shadow;
1894}
1895
1896
1897static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1898{
1899 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1900}
1901
1902static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1903{
1904 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1905}
1906
Paolo Bonzini8391ce42016-07-07 14:58:33 +02001907static inline void vm_exit_controls_reset_shadow(struct vcpu_vmx *vmx)
1908{
1909 vmx->vm_exit_controls_shadow = vmcs_read32(VM_EXIT_CONTROLS);
1910}
1911
Gleb Natapov2961e8762013-11-25 15:37:13 +02001912static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1913{
1914 vmcs_write32(VM_EXIT_CONTROLS, val);
1915 vmx->vm_exit_controls_shadow = val;
1916}
1917
1918static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1919{
1920 if (vmx->vm_exit_controls_shadow != val)
1921 vm_exit_controls_init(vmx, val);
1922}
1923
1924static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1925{
1926 return vmx->vm_exit_controls_shadow;
1927}
1928
1929
1930static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1931{
1932 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1933}
1934
1935static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1936{
1937 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1938}
1939
Avi Kivity2fb92db2011-04-27 19:42:18 +03001940static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1941{
1942 vmx->segment_cache.bitmask = 0;
1943}
1944
1945static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1946 unsigned field)
1947{
1948 bool ret;
1949 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1950
1951 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1952 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1953 vmx->segment_cache.bitmask = 0;
1954 }
1955 ret = vmx->segment_cache.bitmask & mask;
1956 vmx->segment_cache.bitmask |= mask;
1957 return ret;
1958}
1959
1960static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1961{
1962 u16 *p = &vmx->segment_cache.seg[seg].selector;
1963
1964 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1965 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1966 return *p;
1967}
1968
1969static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1970{
1971 ulong *p = &vmx->segment_cache.seg[seg].base;
1972
1973 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1974 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1975 return *p;
1976}
1977
1978static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1979{
1980 u32 *p = &vmx->segment_cache.seg[seg].limit;
1981
1982 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1983 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1984 return *p;
1985}
1986
1987static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1988{
1989 u32 *p = &vmx->segment_cache.seg[seg].ar;
1990
1991 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1992 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1993 return *p;
1994}
1995
Avi Kivityabd3f2d2007-05-02 17:57:40 +03001996static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1997{
1998 u32 eb;
1999
Jan Kiszkafd7373c2010-01-20 18:20:20 +01002000 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
Eric Northup54a20552015-11-03 18:03:53 +01002001 (1u << NM_VECTOR) | (1u << DB_VECTOR) | (1u << AC_VECTOR);
Jan Kiszkafd7373c2010-01-20 18:20:20 +01002002 if ((vcpu->guest_debug &
2003 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
2004 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
2005 eb |= 1u << BP_VECTOR;
Avi Kivity7ffd92c2009-06-09 14:10:45 +03002006 if (to_vmx(vcpu)->rmode.vm86_active)
Avi Kivityabd3f2d2007-05-02 17:57:40 +03002007 eb = ~0;
Avi Kivity089d0342009-03-23 18:26:32 +02002008 if (enable_ept)
Sheng Yang14394422008-04-28 12:24:45 +08002009 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
Avi Kivity02daab22009-12-30 12:40:26 +02002010 if (vcpu->fpu_active)
2011 eb &= ~(1u << NM_VECTOR);
Nadav Har'El36cf24e2011-05-25 23:15:08 +03002012
2013 /* When we are running a nested L2 guest and L1 specified for it a
2014 * certain exception bitmap, we must trap the same exceptions and pass
2015 * them to L1. When running L2, we will only handle the exceptions
2016 * specified above if L1 did not want them.
2017 */
2018 if (is_guest_mode(vcpu))
2019 eb |= get_vmcs12(vcpu)->exception_bitmap;
2020
Avi Kivityabd3f2d2007-05-02 17:57:40 +03002021 vmcs_write32(EXCEPTION_BITMAP, eb);
2022}
2023
Ashok Raj70131292018-02-01 22:59:43 +01002024/*
KarimAllah Ahmede5a83412018-02-01 22:59:45 +01002025 * Check if MSR is intercepted for currently loaded MSR bitmap.
2026 */
2027static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr)
2028{
2029 unsigned long *msr_bitmap;
2030 int f = sizeof(unsigned long);
2031
2032 if (!cpu_has_vmx_msr_bitmap())
2033 return true;
2034
2035 msr_bitmap = to_vmx(vcpu)->loaded_vmcs->msr_bitmap;
2036
2037 if (msr <= 0x1fff) {
2038 return !!test_bit(msr, msr_bitmap + 0x800 / f);
2039 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2040 msr &= 0x1fff;
2041 return !!test_bit(msr, msr_bitmap + 0xc00 / f);
2042 }
2043
2044 return true;
2045}
2046
2047/*
Ashok Raj70131292018-02-01 22:59:43 +01002048 * Check if MSR is intercepted for L01 MSR bitmap.
2049 */
2050static bool msr_write_intercepted_l01(struct kvm_vcpu *vcpu, u32 msr)
2051{
2052 unsigned long *msr_bitmap;
2053 int f = sizeof(unsigned long);
2054
2055 if (!cpu_has_vmx_msr_bitmap())
2056 return true;
2057
2058 msr_bitmap = to_vmx(vcpu)->vmcs01.msr_bitmap;
2059
2060 if (msr <= 0x1fff) {
2061 return !!test_bit(msr, msr_bitmap + 0x800 / f);
2062 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2063 msr &= 0x1fff;
2064 return !!test_bit(msr, msr_bitmap + 0xc00 / f);
2065 }
2066
2067 return true;
2068}
2069
Gleb Natapov2961e8762013-11-25 15:37:13 +02002070static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
2071 unsigned long entry, unsigned long exit)
Gleb Natapov8bf00a52011-10-05 14:01:22 +02002072{
Gleb Natapov2961e8762013-11-25 15:37:13 +02002073 vm_entry_controls_clearbit(vmx, entry);
2074 vm_exit_controls_clearbit(vmx, exit);
Gleb Natapov8bf00a52011-10-05 14:01:22 +02002075}
2076
Konrad Rzeszutek Wilk1555f9e2018-06-20 20:11:39 -04002077static int find_msr(struct vmx_msrs *m, unsigned int msr)
2078{
2079 unsigned int i;
2080
2081 for (i = 0; i < m->nr; ++i) {
2082 if (m->val[i].index == msr)
2083 return i;
2084 }
2085 return -ENOENT;
2086}
2087
Avi Kivity61d2ef22010-04-28 16:40:38 +03002088static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
2089{
Konrad Rzeszutek Wilk1555f9e2018-06-20 20:11:39 -04002090 int i;
Avi Kivity61d2ef22010-04-28 16:40:38 +03002091 struct msr_autoload *m = &vmx->msr_autoload;
2092
Gleb Natapov8bf00a52011-10-05 14:01:22 +02002093 switch (msr) {
2094 case MSR_EFER:
2095 if (cpu_has_load_ia32_efer) {
Gleb Natapov2961e8762013-11-25 15:37:13 +02002096 clear_atomic_switch_msr_special(vmx,
2097 VM_ENTRY_LOAD_IA32_EFER,
Gleb Natapov8bf00a52011-10-05 14:01:22 +02002098 VM_EXIT_LOAD_IA32_EFER);
2099 return;
2100 }
2101 break;
2102 case MSR_CORE_PERF_GLOBAL_CTRL:
2103 if (cpu_has_load_perf_global_ctrl) {
Gleb Natapov2961e8762013-11-25 15:37:13 +02002104 clear_atomic_switch_msr_special(vmx,
Gleb Natapov8bf00a52011-10-05 14:01:22 +02002105 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
2106 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2107 return;
2108 }
2109 break;
Avi Kivity110312c2010-12-21 12:54:20 +02002110 }
Konrad Rzeszutek Wilk1555f9e2018-06-20 20:11:39 -04002111 i = find_msr(&m->guest, msr);
2112 if (i < 0)
Konrad Rzeszutek Wilk5d3eaa22018-06-20 22:00:47 -04002113 goto skip_guest;
Konrad Rzeszutek Wilk57e3ada2018-06-20 13:58:37 -04002114 --m->guest.nr;
Konrad Rzeszutek Wilk57e3ada2018-06-20 13:58:37 -04002115 m->guest.val[i] = m->guest.val[m->guest.nr];
Konrad Rzeszutek Wilk57e3ada2018-06-20 13:58:37 -04002116 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
Konrad Rzeszutek Wilk5d3eaa22018-06-20 22:00:47 -04002117
2118skip_guest:
2119 i = find_msr(&m->host, msr);
2120 if (i < 0)
2121 return;
2122
2123 --m->host.nr;
2124 m->host.val[i] = m->host.val[m->host.nr];
Konrad Rzeszutek Wilk57e3ada2018-06-20 13:58:37 -04002125 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
Avi Kivity61d2ef22010-04-28 16:40:38 +03002126}
2127
Gleb Natapov2961e8762013-11-25 15:37:13 +02002128static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
2129 unsigned long entry, unsigned long exit,
2130 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
2131 u64 guest_val, u64 host_val)
Gleb Natapov8bf00a52011-10-05 14:01:22 +02002132{
2133 vmcs_write64(guest_val_vmcs, guest_val);
2134 vmcs_write64(host_val_vmcs, host_val);
Gleb Natapov2961e8762013-11-25 15:37:13 +02002135 vm_entry_controls_setbit(vmx, entry);
2136 vm_exit_controls_setbit(vmx, exit);
Gleb Natapov8bf00a52011-10-05 14:01:22 +02002137}
2138
Avi Kivity61d2ef22010-04-28 16:40:38 +03002139static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
Konrad Rzeszutek Wilkc45ff812018-06-20 22:01:22 -04002140 u64 guest_val, u64 host_val, bool entry_only)
Avi Kivity61d2ef22010-04-28 16:40:38 +03002141{
Konrad Rzeszutek Wilkc45ff812018-06-20 22:01:22 -04002142 int i, j = 0;
Avi Kivity61d2ef22010-04-28 16:40:38 +03002143 struct msr_autoload *m = &vmx->msr_autoload;
2144
Gleb Natapov8bf00a52011-10-05 14:01:22 +02002145 switch (msr) {
2146 case MSR_EFER:
2147 if (cpu_has_load_ia32_efer) {
Gleb Natapov2961e8762013-11-25 15:37:13 +02002148 add_atomic_switch_msr_special(vmx,
2149 VM_ENTRY_LOAD_IA32_EFER,
Gleb Natapov8bf00a52011-10-05 14:01:22 +02002150 VM_EXIT_LOAD_IA32_EFER,
2151 GUEST_IA32_EFER,
2152 HOST_IA32_EFER,
2153 guest_val, host_val);
2154 return;
2155 }
2156 break;
2157 case MSR_CORE_PERF_GLOBAL_CTRL:
2158 if (cpu_has_load_perf_global_ctrl) {
Gleb Natapov2961e8762013-11-25 15:37:13 +02002159 add_atomic_switch_msr_special(vmx,
Gleb Natapov8bf00a52011-10-05 14:01:22 +02002160 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
2161 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
2162 GUEST_IA32_PERF_GLOBAL_CTRL,
2163 HOST_IA32_PERF_GLOBAL_CTRL,
2164 guest_val, host_val);
2165 return;
2166 }
2167 break;
Radim Krčmář7099e2e2016-03-04 15:08:42 +01002168 case MSR_IA32_PEBS_ENABLE:
2169 /* PEBS needs a quiescent period after being disabled (to write
2170 * a record). Disabling PEBS through VMX MSR swapping doesn't
2171 * provide that period, so a CPU could write host's record into
2172 * guest's memory.
2173 */
2174 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
Avi Kivity110312c2010-12-21 12:54:20 +02002175 }
2176
Konrad Rzeszutek Wilk1555f9e2018-06-20 20:11:39 -04002177 i = find_msr(&m->guest, msr);
Konrad Rzeszutek Wilkc45ff812018-06-20 22:01:22 -04002178 if (!entry_only)
2179 j = find_msr(&m->host, msr);
2180
Konrad Rzeszutek Wilk5d3eaa22018-06-20 22:00:47 -04002181 if (i == NR_AUTOLOAD_MSRS || j == NR_AUTOLOAD_MSRS) {
Michael S. Tsirkin60266202013-10-31 00:34:56 +02002182 printk_once(KERN_WARNING "Not enough msr switch entries. "
Gleb Natapove7fc6f93b2011-10-05 14:01:24 +02002183 "Can't add msr %x\n", msr);
2184 return;
Konrad Rzeszutek Wilk5d3eaa22018-06-20 22:00:47 -04002185 }
2186 if (i < 0) {
Konrad Rzeszutek Wilk1555f9e2018-06-20 20:11:39 -04002187 i = m->guest.nr++;
Konrad Rzeszutek Wilk57e3ada2018-06-20 13:58:37 -04002188 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
Konrad Rzeszutek Wilk5d3eaa22018-06-20 22:00:47 -04002189 }
Konrad Rzeszutek Wilkc45ff812018-06-20 22:01:22 -04002190 m->guest.val[i].index = msr;
2191 m->guest.val[i].value = guest_val;
2192
2193 if (entry_only)
2194 return;
2195
Konrad Rzeszutek Wilk5d3eaa22018-06-20 22:00:47 -04002196 if (j < 0) {
2197 j = m->host.nr++;
Konrad Rzeszutek Wilk57e3ada2018-06-20 13:58:37 -04002198 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
Avi Kivity61d2ef22010-04-28 16:40:38 +03002199 }
Konrad Rzeszutek Wilk5d3eaa22018-06-20 22:00:47 -04002200 m->host.val[j].index = msr;
2201 m->host.val[j].value = host_val;
Avi Kivity61d2ef22010-04-28 16:40:38 +03002202}
2203
Avi Kivity33ed6322007-05-02 16:54:03 +03002204static void reload_tss(void)
2205{
Avi Kivity33ed6322007-05-02 16:54:03 +03002206 /*
2207 * VT restores TR but not its size. Useless.
2208 */
Christoph Lameter89cbc762014-08-17 12:30:40 -05002209 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
Avi Kivitya5f61302008-02-20 17:57:21 +02002210 struct desc_struct *descs;
Avi Kivity33ed6322007-05-02 16:54:03 +03002211
Avi Kivityd3591922010-07-26 18:32:39 +03002212 descs = (void *)gdt->address;
Avi Kivity33ed6322007-05-02 16:54:03 +03002213 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
2214 load_TR_desc();
Avi Kivity33ed6322007-05-02 16:54:03 +03002215}
2216
Avi Kivity92c0d902009-10-29 11:00:16 +02002217static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
Eddie Dong2cc51562007-05-21 07:28:09 +03002218{
Paolo Bonzini844a5fe2016-03-08 12:13:39 +01002219 u64 guest_efer = vmx->vcpu.arch.efer;
2220 u64 ignore_bits = 0;
Eddie Dong2cc51562007-05-21 07:28:09 +03002221
Paolo Bonzini844a5fe2016-03-08 12:13:39 +01002222 if (!enable_ept) {
2223 /*
2224 * NX is needed to handle CR0.WP=1, CR4.SMEP=1. Testing
2225 * host CPUID is more efficient than testing guest CPUID
2226 * or CR4. Host SMEP is anyway a requirement for guest SMEP.
2227 */
2228 if (boot_cpu_has(X86_FEATURE_SMEP))
2229 guest_efer |= EFER_NX;
2230 else if (!(guest_efer & EFER_NX))
2231 ignore_bits |= EFER_NX;
2232 }
Roel Kluin3a34a882009-08-04 02:08:45 -07002233
Avi Kivity51c6cf62007-08-29 03:48:05 +03002234 /*
Paolo Bonzini844a5fe2016-03-08 12:13:39 +01002235 * LMA and LME handled by hardware; SCE meaningless outside long mode.
Avi Kivity51c6cf62007-08-29 03:48:05 +03002236 */
Paolo Bonzini844a5fe2016-03-08 12:13:39 +01002237 ignore_bits |= EFER_SCE;
Avi Kivity51c6cf62007-08-29 03:48:05 +03002238#ifdef CONFIG_X86_64
2239 ignore_bits |= EFER_LMA | EFER_LME;
2240 /* SCE is meaningful only in long mode on Intel */
2241 if (guest_efer & EFER_LMA)
2242 ignore_bits &= ~(u64)EFER_SCE;
2243#endif
Avi Kivity84ad33e2010-04-28 16:42:29 +03002244
2245 clear_atomic_switch_msr(vmx, MSR_EFER);
Andy Lutomirskif6577a5f2014-11-07 18:25:18 -08002246
2247 /*
2248 * On EPT, we can't emulate NX, so we must switch EFER atomically.
2249 * On CPUs that support "load IA32_EFER", always switch EFER
2250 * atomically, since it's faster than switching it manually.
2251 */
2252 if (cpu_has_load_ia32_efer ||
2253 (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
Avi Kivity84ad33e2010-04-28 16:42:29 +03002254 if (!(guest_efer & EFER_LMA))
2255 guest_efer &= ~EFER_LME;
Andy Lutomirski54b98bf2014-11-10 11:19:15 -08002256 if (guest_efer != host_efer)
2257 add_atomic_switch_msr(vmx, MSR_EFER,
Konrad Rzeszutek Wilkc45ff812018-06-20 22:01:22 -04002258 guest_efer, host_efer, false);
Avi Kivity84ad33e2010-04-28 16:42:29 +03002259 return false;
Paolo Bonzini844a5fe2016-03-08 12:13:39 +01002260 } else {
2261 guest_efer &= ~ignore_bits;
2262 guest_efer |= host_efer & ignore_bits;
Avi Kivity84ad33e2010-04-28 16:42:29 +03002263
Paolo Bonzini844a5fe2016-03-08 12:13:39 +01002264 vmx->guest_msrs[efer_offset].data = guest_efer;
2265 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
2266
2267 return true;
2268 }
Avi Kivity51c6cf62007-08-29 03:48:05 +03002269}
2270
Gleb Natapov2d49ec72010-02-25 12:43:09 +02002271static unsigned long segment_base(u16 selector)
2272{
Christoph Lameter89cbc762014-08-17 12:30:40 -05002273 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
Gleb Natapov2d49ec72010-02-25 12:43:09 +02002274 struct desc_struct *d;
2275 unsigned long table_base;
2276 unsigned long v;
2277
2278 if (!(selector & ~3))
2279 return 0;
2280
Avi Kivityd3591922010-07-26 18:32:39 +03002281 table_base = gdt->address;
Gleb Natapov2d49ec72010-02-25 12:43:09 +02002282
2283 if (selector & 4) { /* from ldt */
2284 u16 ldt_selector = kvm_read_ldt();
2285
2286 if (!(ldt_selector & ~3))
2287 return 0;
2288
2289 table_base = segment_base(ldt_selector);
2290 }
2291 d = (struct desc_struct *)(table_base + (selector & ~7));
2292 v = get_desc_base(d);
2293#ifdef CONFIG_X86_64
2294 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
2295 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
2296#endif
2297 return v;
2298}
2299
2300static inline unsigned long kvm_read_tr_base(void)
2301{
2302 u16 tr;
2303 asm("str %0" : "=g"(tr));
2304 return segment_base(tr);
2305}
2306
Avi Kivity04d2cc72007-09-10 18:10:54 +03002307static void vmx_save_host_state(struct kvm_vcpu *vcpu)
Avi Kivity33ed6322007-05-02 16:54:03 +03002308{
Avi Kivity04d2cc72007-09-10 18:10:54 +03002309 struct vcpu_vmx *vmx = to_vmx(vcpu);
Avi Kivity26bb0982009-09-07 11:14:12 +03002310 int i;
Avi Kivity04d2cc72007-09-10 18:10:54 +03002311
Gregory Haskinsa2fa3e92007-07-27 08:13:10 -04002312 if (vmx->host_state.loaded)
Avi Kivity33ed6322007-05-02 16:54:03 +03002313 return;
2314
Gregory Haskinsa2fa3e92007-07-27 08:13:10 -04002315 vmx->host_state.loaded = 1;
Avi Kivity33ed6322007-05-02 16:54:03 +03002316 /*
2317 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
2318 * allow segment selectors with cpl > 0 or ti == 1.
2319 */
Avi Kivityd6e88ae2008-07-10 16:53:33 +03002320 vmx->host_state.ldt_sel = kvm_read_ldt();
Laurent Vivier152d3f22007-08-23 16:33:11 +02002321 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
Avi Kivity9581d442010-10-19 16:46:55 +02002322 savesegment(fs, vmx->host_state.fs_sel);
Laurent Vivier152d3f22007-08-23 16:33:11 +02002323 if (!(vmx->host_state.fs_sel & 7)) {
Gregory Haskinsa2fa3e92007-07-27 08:13:10 -04002324 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
Laurent Vivier152d3f22007-08-23 16:33:11 +02002325 vmx->host_state.fs_reload_needed = 0;
2326 } else {
Avi Kivity33ed6322007-05-02 16:54:03 +03002327 vmcs_write16(HOST_FS_SELECTOR, 0);
Laurent Vivier152d3f22007-08-23 16:33:11 +02002328 vmx->host_state.fs_reload_needed = 1;
Avi Kivity33ed6322007-05-02 16:54:03 +03002329 }
Avi Kivity9581d442010-10-19 16:46:55 +02002330 savesegment(gs, vmx->host_state.gs_sel);
Gregory Haskinsa2fa3e92007-07-27 08:13:10 -04002331 if (!(vmx->host_state.gs_sel & 7))
2332 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
Avi Kivity33ed6322007-05-02 16:54:03 +03002333 else {
2334 vmcs_write16(HOST_GS_SELECTOR, 0);
Laurent Vivier152d3f22007-08-23 16:33:11 +02002335 vmx->host_state.gs_ldt_reload_needed = 1;
Avi Kivity33ed6322007-05-02 16:54:03 +03002336 }
2337
2338#ifdef CONFIG_X86_64
Avi Kivityb2da15a2012-05-13 19:53:24 +03002339 savesegment(ds, vmx->host_state.ds_sel);
2340 savesegment(es, vmx->host_state.es_sel);
2341#endif
2342
2343#ifdef CONFIG_X86_64
Avi Kivity33ed6322007-05-02 16:54:03 +03002344 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
2345 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
2346#else
Gregory Haskinsa2fa3e92007-07-27 08:13:10 -04002347 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
2348 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
Avi Kivity33ed6322007-05-02 16:54:03 +03002349#endif
Avi Kivity707c0872007-05-02 17:33:43 +03002350
2351#ifdef CONFIG_X86_64
Avi Kivityc8770e72010-11-11 12:37:26 +02002352 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2353 if (is_long_mode(&vmx->vcpu))
Avi Kivity44ea2b12009-09-06 15:55:37 +03002354 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
Avi Kivity707c0872007-05-02 17:33:43 +03002355#endif
Liu, Jinsongda8999d2014-02-24 10:55:46 +00002356 if (boot_cpu_has(X86_FEATURE_MPX))
2357 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
Avi Kivity26bb0982009-09-07 11:14:12 +03002358 for (i = 0; i < vmx->save_nmsrs; ++i)
2359 kvm_set_shared_msr(vmx->guest_msrs[i].index,
Avi Kivityd5696722009-12-02 12:28:47 +02002360 vmx->guest_msrs[i].data,
2361 vmx->guest_msrs[i].mask);
Avi Kivity33ed6322007-05-02 16:54:03 +03002362}
2363
Avi Kivitya9b21b62008-06-24 11:48:49 +03002364static void __vmx_load_host_state(struct vcpu_vmx *vmx)
Avi Kivity33ed6322007-05-02 16:54:03 +03002365{
Gregory Haskinsa2fa3e92007-07-27 08:13:10 -04002366 if (!vmx->host_state.loaded)
Avi Kivity33ed6322007-05-02 16:54:03 +03002367 return;
2368
Avi Kivitye1beb1d2007-11-18 13:50:24 +02002369 ++vmx->vcpu.stat.host_state_reload;
Gregory Haskinsa2fa3e92007-07-27 08:13:10 -04002370 vmx->host_state.loaded = 0;
Avi Kivityc8770e72010-11-11 12:37:26 +02002371#ifdef CONFIG_X86_64
2372 if (is_long_mode(&vmx->vcpu))
2373 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2374#endif
Laurent Vivier152d3f22007-08-23 16:33:11 +02002375 if (vmx->host_state.gs_ldt_reload_needed) {
Avi Kivityd6e88ae2008-07-10 16:53:33 +03002376 kvm_load_ldt(vmx->host_state.ldt_sel);
Avi Kivity33ed6322007-05-02 16:54:03 +03002377#ifdef CONFIG_X86_64
Avi Kivity9581d442010-10-19 16:46:55 +02002378 load_gs_index(vmx->host_state.gs_sel);
Avi Kivity9581d442010-10-19 16:46:55 +02002379#else
2380 loadsegment(gs, vmx->host_state.gs_sel);
Avi Kivity33ed6322007-05-02 16:54:03 +03002381#endif
Avi Kivity33ed6322007-05-02 16:54:03 +03002382 }
Avi Kivity0a77fe42010-10-19 18:48:35 +02002383 if (vmx->host_state.fs_reload_needed)
2384 loadsegment(fs, vmx->host_state.fs_sel);
Avi Kivityb2da15a2012-05-13 19:53:24 +03002385#ifdef CONFIG_X86_64
2386 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
2387 loadsegment(ds, vmx->host_state.ds_sel);
2388 loadsegment(es, vmx->host_state.es_sel);
2389 }
Avi Kivityb2da15a2012-05-13 19:53:24 +03002390#endif
Laurent Vivier152d3f22007-08-23 16:33:11 +02002391 reload_tss();
Avi Kivity44ea2b12009-09-06 15:55:37 +03002392#ifdef CONFIG_X86_64
Avi Kivityc8770e72010-11-11 12:37:26 +02002393 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
Avi Kivity44ea2b12009-09-06 15:55:37 +03002394#endif
Liu, Jinsongda8999d2014-02-24 10:55:46 +00002395 if (vmx->host_state.msr_host_bndcfgs)
2396 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
Suresh Siddhab1a74bf2012-09-20 11:01:49 -07002397 /*
2398 * If the FPU is not active (through the host task or
2399 * the guest vcpu), then restore the cr0.TS bit.
2400 */
Ingo Molnar3c6dffa2015-04-28 12:28:08 +02002401 if (!fpregs_active() && !vmx->vcpu.guest_fpu_loaded)
Suresh Siddhab1a74bf2012-09-20 11:01:49 -07002402 stts();
Christoph Lameter89cbc762014-08-17 12:30:40 -05002403 load_gdt(this_cpu_ptr(&host_gdt));
Avi Kivity33ed6322007-05-02 16:54:03 +03002404}
2405
Avi Kivitya9b21b62008-06-24 11:48:49 +03002406static void vmx_load_host_state(struct vcpu_vmx *vmx)
2407{
2408 preempt_disable();
2409 __vmx_load_host_state(vmx);
2410 preempt_enable();
2411}
2412
Feng Wu28b835d2015-09-18 22:29:54 +08002413static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
2414{
2415 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2416 struct pi_desc old, new;
2417 unsigned int dest;
2418
Paolo Bonzini58d2fb12017-06-06 12:57:06 +02002419 /*
2420 * In case of hot-plug or hot-unplug, we may have to undo
2421 * vmx_vcpu_pi_put even if there is no assigned device. And we
2422 * always keep PI.NDST up to date for simplicity: it makes the
2423 * code easier, and CPU migration is not a fast path.
2424 */
2425 if (!pi_test_sn(pi_desc) && vcpu->cpu == cpu)
Feng Wu28b835d2015-09-18 22:29:54 +08002426 return;
2427
Paolo Bonzini58d2fb12017-06-06 12:57:06 +02002428 /*
2429 * First handle the simple case where no cmpxchg is necessary; just
2430 * allow posting non-urgent interrupts.
2431 *
2432 * If the 'nv' field is POSTED_INTR_WAKEUP_VECTOR, do not change
2433 * PI.NDST: pi_post_block will do it for us and the wakeup_handler
2434 * expects the VCPU to be on the blocked_vcpu_list that matches
2435 * PI.NDST.
2436 */
2437 if (pi_desc->nv == POSTED_INTR_WAKEUP_VECTOR ||
2438 vcpu->cpu == cpu) {
2439 pi_clear_sn(pi_desc);
2440 return;
2441 }
2442
2443 /* The full case. */
Feng Wu28b835d2015-09-18 22:29:54 +08002444 do {
2445 old.control = new.control = pi_desc->control;
2446
Paolo Bonzini58d2fb12017-06-06 12:57:06 +02002447 dest = cpu_physical_id(cpu);
Feng Wu28b835d2015-09-18 22:29:54 +08002448
Paolo Bonzini58d2fb12017-06-06 12:57:06 +02002449 if (x2apic_enabled())
2450 new.ndst = dest;
2451 else
2452 new.ndst = (dest << 8) & 0xFF00;
Feng Wu28b835d2015-09-18 22:29:54 +08002453
Feng Wu28b835d2015-09-18 22:29:54 +08002454 new.sn = 0;
Paolo Bonziniea37f612017-09-28 17:58:41 +02002455 } while (cmpxchg64(&pi_desc->control, old.control,
2456 new.control) != old.control);
Feng Wu28b835d2015-09-18 22:29:54 +08002457}
Xiao Guangrong1be0e612016-03-22 16:51:18 +08002458
Peter Feinerc95ba922016-08-17 09:36:47 -07002459static void decache_tsc_multiplier(struct vcpu_vmx *vmx)
2460{
2461 vmx->current_tsc_ratio = vmx->vcpu.arch.tsc_scaling_ratio;
2462 vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio);
2463}
2464
Avi Kivity6aa8b732006-12-10 02:21:36 -08002465/*
2466 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2467 * vcpu mutex is already taken.
2468 */
Avi Kivity15ad7142007-07-11 18:17:21 +03002469static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
Avi Kivity6aa8b732006-12-10 02:21:36 -08002470{
Gregory Haskinsa2fa3e92007-07-27 08:13:10 -04002471 struct vcpu_vmx *vmx = to_vmx(vcpu);
Dongxiao Xu4610c9c2010-05-11 18:29:48 +08002472 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
Jim Mattsonb80c76e2016-07-29 18:56:53 -07002473 bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
Avi Kivity6aa8b732006-12-10 02:21:36 -08002474
Dongxiao Xu4610c9c2010-05-11 18:29:48 +08002475 if (!vmm_exclusive)
2476 kvm_cpu_vmxon(phys_addr);
Jim Mattsonb80c76e2016-07-29 18:56:53 -07002477 else if (!already_loaded)
Nadav Har'Eld462b812011-05-24 15:26:10 +03002478 loaded_vmcs_clear(vmx->loaded_vmcs);
Avi Kivity6aa8b732006-12-10 02:21:36 -08002479
Jim Mattsonb80c76e2016-07-29 18:56:53 -07002480 if (!already_loaded) {
Dongxiao Xu92fe13b2010-05-11 18:29:42 +08002481 local_irq_disable();
Zhang Yanfei8f536b72012-12-06 23:43:34 +08002482 crash_disable_local_vmclear(cpu);
Xiao Guangrong5a560f82012-11-28 20:54:14 +08002483
2484 /*
2485 * Read loaded_vmcs->cpu should be before fetching
2486 * loaded_vmcs->loaded_vmcss_on_cpu_link.
2487 * See the comments in __loaded_vmcs_clear().
2488 */
2489 smp_rmb();
2490
Nadav Har'Eld462b812011-05-24 15:26:10 +03002491 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
2492 &per_cpu(loaded_vmcss_on_cpu, cpu));
Zhang Yanfei8f536b72012-12-06 23:43:34 +08002493 crash_enable_local_vmclear(cpu);
Dongxiao Xu92fe13b2010-05-11 18:29:42 +08002494 local_irq_enable();
Jim Mattsonb80c76e2016-07-29 18:56:53 -07002495 }
2496
2497 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
2498 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
2499 vmcs_load(vmx->loaded_vmcs->vmcs);
Ashok Raj70131292018-02-01 22:59:43 +01002500 indirect_branch_prediction_barrier();
Jim Mattsonb80c76e2016-07-29 18:56:53 -07002501 }
2502
2503 if (!already_loaded) {
2504 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
2505 unsigned long sysenter_esp;
2506
2507 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
Dongxiao Xu92fe13b2010-05-11 18:29:42 +08002508
Avi Kivity6aa8b732006-12-10 02:21:36 -08002509 /*
2510 * Linux uses per-cpu TSS and GDT, so set these when switching
2511 * processors.
2512 */
Avi Kivityd6e88ae2008-07-10 16:53:33 +03002513 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
Avi Kivityd3591922010-07-26 18:32:39 +03002514 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
Avi Kivity6aa8b732006-12-10 02:21:36 -08002515
2516 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
2517 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
Haozhong Zhangff2c3a12015-10-20 15:39:10 +08002518
Nadav Har'Eld462b812011-05-24 15:26:10 +03002519 vmx->loaded_vmcs->cpu = cpu;
Avi Kivity6aa8b732006-12-10 02:21:36 -08002520 }
Feng Wu28b835d2015-09-18 22:29:54 +08002521
Owen Hofmann2680d6d2016-03-01 13:36:13 -08002522 /* Setup TSC multiplier */
2523 if (kvm_has_tsc_control &&
Peter Feinerc95ba922016-08-17 09:36:47 -07002524 vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio)
2525 decache_tsc_multiplier(vmx);
Owen Hofmann2680d6d2016-03-01 13:36:13 -08002526
Feng Wu28b835d2015-09-18 22:29:54 +08002527 vmx_vcpu_pi_load(vcpu, cpu);
Xiao Guangrong1be0e612016-03-22 16:51:18 +08002528 vmx->host_pkru = read_pkru();
Feng Wu28b835d2015-09-18 22:29:54 +08002529}
2530
2531static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
2532{
2533 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2534
2535 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
Yang Zhanga0052192016-06-13 09:56:56 +08002536 !irq_remapping_cap(IRQ_POSTING_CAP) ||
2537 !kvm_vcpu_apicv_active(vcpu))
Feng Wu28b835d2015-09-18 22:29:54 +08002538 return;
2539
2540 /* Set SN when the vCPU is preempted */
2541 if (vcpu->preempted)
2542 pi_set_sn(pi_desc);
Avi Kivity6aa8b732006-12-10 02:21:36 -08002543}
2544
2545static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
2546{
Feng Wu28b835d2015-09-18 22:29:54 +08002547 vmx_vcpu_pi_put(vcpu);
2548
Avi Kivitya9b21b62008-06-24 11:48:49 +03002549 __vmx_load_host_state(to_vmx(vcpu));
Dongxiao Xu4610c9c2010-05-11 18:29:48 +08002550 if (!vmm_exclusive) {
Nadav Har'Eld462b812011-05-24 15:26:10 +03002551 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
2552 vcpu->cpu = -1;
Dongxiao Xu4610c9c2010-05-11 18:29:48 +08002553 kvm_cpu_vmxoff();
2554 }
Avi Kivity6aa8b732006-12-10 02:21:36 -08002555}
2556
Avi Kivity5fd86fc2007-05-02 20:40:00 +03002557static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
2558{
Avi Kivity81231c62010-01-24 16:26:40 +02002559 ulong cr0;
2560
Avi Kivity5fd86fc2007-05-02 20:40:00 +03002561 if (vcpu->fpu_active)
2562 return;
2563 vcpu->fpu_active = 1;
Avi Kivity81231c62010-01-24 16:26:40 +02002564 cr0 = vmcs_readl(GUEST_CR0);
2565 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
2566 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
2567 vmcs_writel(GUEST_CR0, cr0);
Avi Kivity5fd86fc2007-05-02 20:40:00 +03002568 update_exception_bitmap(vcpu);
Avi Kivityedcafe32009-12-30 18:07:40 +02002569 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
Nadav Har'El36cf24e2011-05-25 23:15:08 +03002570 if (is_guest_mode(vcpu))
2571 vcpu->arch.cr0_guest_owned_bits &=
2572 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
Avi Kivityedcafe32009-12-30 18:07:40 +02002573 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
Avi Kivity5fd86fc2007-05-02 20:40:00 +03002574}
2575
Avi Kivityedcafe32009-12-30 18:07:40 +02002576static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
2577
Nadav Har'Elfe3ef052011-05-25 23:10:02 +03002578/*
2579 * Return the cr0 value that a nested guest would read. This is a combination
2580 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2581 * its hypervisor (cr0_read_shadow).
2582 */
2583static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
2584{
2585 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
2586 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
2587}
2588static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
2589{
2590 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
2591 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
2592}
2593
Avi Kivity5fd86fc2007-05-02 20:40:00 +03002594static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
2595{
Nadav Har'El36cf24e2011-05-25 23:15:08 +03002596 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
2597 * set this *before* calling this function.
2598 */
Avi Kivityedcafe32009-12-30 18:07:40 +02002599 vmx_decache_cr0_guest_bits(vcpu);
Avi Kivity81231c62010-01-24 16:26:40 +02002600 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
Avi Kivity5fd86fc2007-05-02 20:40:00 +03002601 update_exception_bitmap(vcpu);
Avi Kivityedcafe32009-12-30 18:07:40 +02002602 vcpu->arch.cr0_guest_owned_bits = 0;
2603 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
Nadav Har'El36cf24e2011-05-25 23:15:08 +03002604 if (is_guest_mode(vcpu)) {
2605 /*
2606 * L1's specified read shadow might not contain the TS bit,
2607 * so now that we turned on shadowing of this bit, we need to
2608 * set this bit of the shadow. Like in nested_vmx_run we need
2609 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
2610 * up-to-date here because we just decached cr0.TS (and we'll
2611 * only update vmcs12->guest_cr0 on nested exit).
2612 */
2613 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2614 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
2615 (vcpu->arch.cr0 & X86_CR0_TS);
2616 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
2617 } else
2618 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
Avi Kivity5fd86fc2007-05-02 20:40:00 +03002619}
2620
Avi Kivity6aa8b732006-12-10 02:21:36 -08002621static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2622{
Avi Kivity78ac8b42010-04-08 18:19:35 +03002623 unsigned long rflags, save_rflags;
Avi Kivity345dcaa2009-08-12 15:29:37 +03002624
Avi Kivity6de12732011-03-07 12:51:22 +02002625 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2626 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2627 rflags = vmcs_readl(GUEST_RFLAGS);
2628 if (to_vmx(vcpu)->rmode.vm86_active) {
2629 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2630 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2631 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2632 }
2633 to_vmx(vcpu)->rflags = rflags;
Avi Kivity78ac8b42010-04-08 18:19:35 +03002634 }
Avi Kivity6de12732011-03-07 12:51:22 +02002635 return to_vmx(vcpu)->rflags;
Avi Kivity6aa8b732006-12-10 02:21:36 -08002636}
2637
2638static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2639{
Avi Kivity6de12732011-03-07 12:51:22 +02002640 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2641 to_vmx(vcpu)->rflags = rflags;
Avi Kivity78ac8b42010-04-08 18:19:35 +03002642 if (to_vmx(vcpu)->rmode.vm86_active) {
2643 to_vmx(vcpu)->rmode.save_rflags = rflags;
Glauber de Oliveira Costa053de042008-01-30 13:31:27 +01002644 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
Avi Kivity78ac8b42010-04-08 18:19:35 +03002645 }
Avi Kivity6aa8b732006-12-10 02:21:36 -08002646 vmcs_writel(GUEST_RFLAGS, rflags);
2647}
2648
Huaitong Hanbe94f6b2016-03-22 16:51:20 +08002649static u32 vmx_get_pkru(struct kvm_vcpu *vcpu)
2650{
2651 return to_vmx(vcpu)->guest_pkru;
2652}
2653
Paolo Bonzini37ccdcb2014-05-20 14:29:47 +02002654static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
Glauber Costa2809f5d2009-05-12 16:21:05 -04002655{
2656 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2657 int ret = 0;
2658
2659 if (interruptibility & GUEST_INTR_STATE_STI)
Jan Kiszka48005f62010-02-19 19:38:07 +01002660 ret |= KVM_X86_SHADOW_INT_STI;
Glauber Costa2809f5d2009-05-12 16:21:05 -04002661 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
Jan Kiszka48005f62010-02-19 19:38:07 +01002662 ret |= KVM_X86_SHADOW_INT_MOV_SS;
Glauber Costa2809f5d2009-05-12 16:21:05 -04002663
Paolo Bonzini37ccdcb2014-05-20 14:29:47 +02002664 return ret;
Glauber Costa2809f5d2009-05-12 16:21:05 -04002665}
2666
2667static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2668{
2669 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2670 u32 interruptibility = interruptibility_old;
2671
2672 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2673
Jan Kiszka48005f62010-02-19 19:38:07 +01002674 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
Glauber Costa2809f5d2009-05-12 16:21:05 -04002675 interruptibility |= GUEST_INTR_STATE_MOV_SS;
Jan Kiszka48005f62010-02-19 19:38:07 +01002676 else if (mask & KVM_X86_SHADOW_INT_STI)
Glauber Costa2809f5d2009-05-12 16:21:05 -04002677 interruptibility |= GUEST_INTR_STATE_STI;
2678
2679 if ((interruptibility != interruptibility_old))
2680 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2681}
2682
Avi Kivity6aa8b732006-12-10 02:21:36 -08002683static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2684{
2685 unsigned long rip;
Avi Kivity6aa8b732006-12-10 02:21:36 -08002686
Marcelo Tosatti5fdbf972008-06-27 14:58:02 -03002687 rip = kvm_rip_read(vcpu);
Avi Kivity6aa8b732006-12-10 02:21:36 -08002688 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
Marcelo Tosatti5fdbf972008-06-27 14:58:02 -03002689 kvm_rip_write(vcpu, rip);
Avi Kivity6aa8b732006-12-10 02:21:36 -08002690
Glauber Costa2809f5d2009-05-12 16:21:05 -04002691 /* skipping an emulated instruction also counts */
2692 vmx_set_interrupt_shadow(vcpu, 0);
Avi Kivity6aa8b732006-12-10 02:21:36 -08002693}
2694
Nadav Har'El0b6ac342011-05-25 23:13:36 +03002695/*
2696 * KVM wants to inject page-faults which it got to the guest. This function
2697 * checks whether in a nested guest, we need to inject them to L1 or L2.
Nadav Har'El0b6ac342011-05-25 23:13:36 +03002698 */
Gleb Natapove011c662013-09-25 12:51:35 +03002699static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
Nadav Har'El0b6ac342011-05-25 23:13:36 +03002700{
2701 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2702
Gleb Natapove011c662013-09-25 12:51:35 +03002703 if (!(vmcs12->exception_bitmap & (1u << nr)))
Nadav Har'El0b6ac342011-05-25 23:13:36 +03002704 return 0;
2705
Wanpeng Lia29fd272017-06-05 05:19:09 -07002706 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
Jan Kiszka533558b2014-01-04 18:47:20 +01002707 vmcs_read32(VM_EXIT_INTR_INFO),
2708 vmcs_readl(EXIT_QUALIFICATION));
Nadav Har'El0b6ac342011-05-25 23:13:36 +03002709 return 1;
2710}
2711
Avi Kivity298101d2007-11-25 13:41:11 +02002712static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
Joerg Roedelce7ddec2010-04-22 12:33:13 +02002713 bool has_error_code, u32 error_code,
2714 bool reinject)
Avi Kivity298101d2007-11-25 13:41:11 +02002715{
Jan Kiszka77ab6db2008-07-14 12:28:51 +02002716 struct vcpu_vmx *vmx = to_vmx(vcpu);
Jan Kiszka8ab2d2e2008-12-15 13:52:10 +01002717 u32 intr_info = nr | INTR_INFO_VALID_MASK;
Jan Kiszka77ab6db2008-07-14 12:28:51 +02002718
Gleb Natapove011c662013-09-25 12:51:35 +03002719 if (!reinject && is_guest_mode(vcpu) &&
2720 nested_vmx_check_exception(vcpu, nr))
Nadav Har'El0b6ac342011-05-25 23:13:36 +03002721 return;
2722
Jan Kiszka8ab2d2e2008-12-15 13:52:10 +01002723 if (has_error_code) {
Jan Kiszka77ab6db2008-07-14 12:28:51 +02002724 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
Jan Kiszka8ab2d2e2008-12-15 13:52:10 +01002725 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2726 }
Jan Kiszka77ab6db2008-07-14 12:28:51 +02002727
Avi Kivity7ffd92c2009-06-09 14:10:45 +03002728 if (vmx->rmode.vm86_active) {
Serge E. Hallyn71f98332011-04-13 09:12:54 -05002729 int inc_eip = 0;
2730 if (kvm_exception_is_soft(nr))
2731 inc_eip = vcpu->arch.event_exit_inst_len;
2732 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
Mohammed Gamala92601b2010-09-19 14:34:07 +02002733 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
Jan Kiszka77ab6db2008-07-14 12:28:51 +02002734 return;
2735 }
2736
Sean Christopherson94b4fed2018-03-23 09:34:00 -07002737 WARN_ON_ONCE(vmx->emulation_required);
2738
Gleb Natapov66fd3f72009-05-11 13:35:50 +03002739 if (kvm_exception_is_soft(nr)) {
2740 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2741 vmx->vcpu.arch.event_exit_inst_len);
Jan Kiszka8ab2d2e2008-12-15 13:52:10 +01002742 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2743 } else
2744 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2745
2746 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
Avi Kivity298101d2007-11-25 13:41:11 +02002747}
2748
Sheng Yang4e47c7a2009-12-18 16:48:47 +08002749static bool vmx_rdtscp_supported(void)
2750{
2751 return cpu_has_vmx_rdtscp();
2752}
2753
Mao, Junjiead756a12012-07-02 01:18:48 +00002754static bool vmx_invpcid_supported(void)
2755{
2756 return cpu_has_vmx_invpcid() && enable_ept;
2757}
2758
Avi Kivity6aa8b732006-12-10 02:21:36 -08002759/*
Eddie Donga75beee2007-05-17 18:55:15 +03002760 * Swap MSR entry in host/guest MSR entry array.
2761 */
Rusty Russell8b9cf982007-07-30 16:31:43 +10002762static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
Eddie Donga75beee2007-05-17 18:55:15 +03002763{
Avi Kivity26bb0982009-09-07 11:14:12 +03002764 struct shared_msr_entry tmp;
Gregory Haskinsa2fa3e92007-07-27 08:13:10 -04002765
2766 tmp = vmx->guest_msrs[to];
2767 vmx->guest_msrs[to] = vmx->guest_msrs[from];
2768 vmx->guest_msrs[from] = tmp;
Eddie Donga75beee2007-05-17 18:55:15 +03002769}
2770
2771/*
Avi Kivitye38aea32007-04-19 13:22:48 +03002772 * Set up the vmcs to automatically save and restore system
2773 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2774 * mode, as fiddling with msrs is very expensive.
2775 */
Rusty Russell8b9cf982007-07-30 16:31:43 +10002776static void setup_msrs(struct vcpu_vmx *vmx)
Avi Kivitye38aea32007-04-19 13:22:48 +03002777{
Avi Kivity26bb0982009-09-07 11:14:12 +03002778 int save_nmsrs, index;
Avi Kivitye38aea32007-04-19 13:22:48 +03002779
Eddie Donga75beee2007-05-17 18:55:15 +03002780 save_nmsrs = 0;
Avi Kivity4d56c8a2007-04-19 14:28:44 +03002781#ifdef CONFIG_X86_64
Rusty Russell8b9cf982007-07-30 16:31:43 +10002782 if (is_long_mode(&vmx->vcpu)) {
Rusty Russell8b9cf982007-07-30 16:31:43 +10002783 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
Eddie Donga75beee2007-05-17 18:55:15 +03002784 if (index >= 0)
Rusty Russell8b9cf982007-07-30 16:31:43 +10002785 move_msr_up(vmx, index, save_nmsrs++);
2786 index = __find_msr_index(vmx, MSR_LSTAR);
Eddie Donga75beee2007-05-17 18:55:15 +03002787 if (index >= 0)
Rusty Russell8b9cf982007-07-30 16:31:43 +10002788 move_msr_up(vmx, index, save_nmsrs++);
2789 index = __find_msr_index(vmx, MSR_CSTAR);
Eddie Donga75beee2007-05-17 18:55:15 +03002790 if (index >= 0)
Rusty Russell8b9cf982007-07-30 16:31:43 +10002791 move_msr_up(vmx, index, save_nmsrs++);
Sheng Yang4e47c7a2009-12-18 16:48:47 +08002792 index = __find_msr_index(vmx, MSR_TSC_AUX);
Xiao Guangrong1cea0ce2015-09-09 14:05:57 +08002793 if (index >= 0 && guest_cpuid_has_rdtscp(&vmx->vcpu))
Sheng Yang4e47c7a2009-12-18 16:48:47 +08002794 move_msr_up(vmx, index, save_nmsrs++);
Eddie Donga75beee2007-05-17 18:55:15 +03002795 /*
Brian Gerst8c065852010-07-17 09:03:26 -04002796 * MSR_STAR is only needed on long mode guests, and only
Eddie Donga75beee2007-05-17 18:55:15 +03002797 * if efer.sce is enabled.
2798 */
Brian Gerst8c065852010-07-17 09:03:26 -04002799 index = __find_msr_index(vmx, MSR_STAR);
Avi Kivityf6801df2010-01-21 15:31:50 +02002800 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
Rusty Russell8b9cf982007-07-30 16:31:43 +10002801 move_msr_up(vmx, index, save_nmsrs++);
Avi Kivity4d56c8a2007-04-19 14:28:44 +03002802 }
Eddie Donga75beee2007-05-17 18:55:15 +03002803#endif
Avi Kivity92c0d902009-10-29 11:00:16 +02002804 index = __find_msr_index(vmx, MSR_EFER);
2805 if (index >= 0 && update_transition_efer(vmx, index))
Avi Kivity26bb0982009-09-07 11:14:12 +03002806 move_msr_up(vmx, index, save_nmsrs++);
Avi Kivity4d56c8a2007-04-19 14:28:44 +03002807
Avi Kivity26bb0982009-09-07 11:14:12 +03002808 vmx->save_nmsrs = save_nmsrs;
Avi Kivity58972972009-02-24 22:26:47 +02002809
Yang Zhang8d146952013-01-25 10:18:50 +08002810 if (cpu_has_vmx_msr_bitmap())
Paolo Bonzini6236b782018-01-16 16:51:18 +01002811 vmx_update_msr_bitmap(&vmx->vcpu);
Avi Kivitye38aea32007-04-19 13:22:48 +03002812}
2813
2814/*
Avi Kivity6aa8b732006-12-10 02:21:36 -08002815 * reads and returns guest's timestamp counter "register"
Haozhong Zhangbe7b2632015-10-20 15:39:11 +08002816 * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset
2817 * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3
Avi Kivity6aa8b732006-12-10 02:21:36 -08002818 */
Haozhong Zhangbe7b2632015-10-20 15:39:11 +08002819static u64 guest_read_tsc(struct kvm_vcpu *vcpu)
Avi Kivity6aa8b732006-12-10 02:21:36 -08002820{
2821 u64 host_tsc, tsc_offset;
2822
Andy Lutomirski4ea16362015-06-25 18:44:07 +02002823 host_tsc = rdtsc();
Avi Kivity6aa8b732006-12-10 02:21:36 -08002824 tsc_offset = vmcs_read64(TSC_OFFSET);
Haozhong Zhangbe7b2632015-10-20 15:39:11 +08002825 return kvm_scale_tsc(vcpu, host_tsc) + tsc_offset;
Avi Kivity6aa8b732006-12-10 02:21:36 -08002826}
2827
2828/*
Zachary Amsden99e3e302010-08-19 22:07:17 -10002829 * writes 'offset' into guest's timestamp counter offset register
Avi Kivity6aa8b732006-12-10 02:21:36 -08002830 */
Zachary Amsden99e3e302010-08-19 22:07:17 -10002831static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
Avi Kivity6aa8b732006-12-10 02:21:36 -08002832{
Nadav Har'El27fc51b2011-08-02 15:54:52 +03002833 if (is_guest_mode(vcpu)) {
Nadav Har'El79918252011-05-25 23:15:39 +03002834 /*
Nadav Har'El27fc51b2011-08-02 15:54:52 +03002835 * We're here if L1 chose not to trap WRMSR to TSC. According
2836 * to the spec, this should set L1's TSC; The offset that L1
2837 * set for L2 remains unchanged, and still needs to be added
2838 * to the newly set TSC to get L2's TSC.
Nadav Har'El79918252011-05-25 23:15:39 +03002839 */
Nadav Har'El27fc51b2011-08-02 15:54:52 +03002840 struct vmcs12 *vmcs12;
Nadav Har'El27fc51b2011-08-02 15:54:52 +03002841 /* recalculate vmcs02.TSC_OFFSET: */
2842 vmcs12 = get_vmcs12(vcpu);
2843 vmcs_write64(TSC_OFFSET, offset +
2844 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2845 vmcs12->tsc_offset : 0));
2846 } else {
Yoshihiro YUNOMAE489223e2013-06-12 16:43:44 +09002847 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2848 vmcs_read64(TSC_OFFSET), offset);
Nadav Har'El27fc51b2011-08-02 15:54:52 +03002849 vmcs_write64(TSC_OFFSET, offset);
2850 }
Avi Kivity6aa8b732006-12-10 02:21:36 -08002851}
2852
Nadav Har'El801d3422011-05-25 23:02:23 +03002853static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2854{
2855 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2856 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2857}
2858
2859/*
2860 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2861 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2862 * all guests if the "nested" module option is off, and can also be disabled
2863 * for a single guest by disabling its VMX cpuid bit.
2864 */
2865static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2866{
2867 return nested && guest_cpuid_has_vmx(vcpu);
2868}
2869
Avi Kivity6aa8b732006-12-10 02:21:36 -08002870/*
Nadav Har'Elb87a51a2011-05-25 23:04:25 +03002871 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2872 * returned for the various VMX controls MSRs when nested VMX is enabled.
2873 * The same values should also be used to verify that vmcs12 control fields are
2874 * valid during nested entry from L1 to L2.
2875 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2876 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2877 * bit in the high half is on if the corresponding bit in the control field
2878 * may be on. See also vmx_control_verify().
Nadav Har'Elb87a51a2011-05-25 23:04:25 +03002879 */
Wincy Vanb9c237b2015-02-03 23:56:30 +08002880static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
Nadav Har'Elb87a51a2011-05-25 23:04:25 +03002881{
2882 /*
2883 * Note that as a general rule, the high half of the MSRs (bits in
2884 * the control fields which may be 1) should be initialized by the
2885 * intersection of the underlying hardware's MSR (i.e., features which
2886 * can be supported) and the list of features we want to expose -
2887 * because they are known to be properly supported in our code.
2888 * Also, usually, the low half of the MSRs (bits which must be 1) can
2889 * be set to 0, meaning that L1 may turn off any of these bits. The
2890 * reason is that if one of these bits is necessary, it will appear
2891 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2892 * fields of vmcs01 and vmcs02, will turn these bits off - and
2893 * nested_vmx_exit_handled() will not pass related exits to L1.
2894 * These rules have exceptions below.
2895 */
2896
2897 /* pin-based controls */
Jan Kiszkaeabeaac2013-03-13 11:30:50 +01002898 rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
Wincy Vanb9c237b2015-02-03 23:56:30 +08002899 vmx->nested.nested_vmx_pinbased_ctls_low,
2900 vmx->nested.nested_vmx_pinbased_ctls_high);
2901 vmx->nested.nested_vmx_pinbased_ctls_low |=
2902 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2903 vmx->nested.nested_vmx_pinbased_ctls_high &=
2904 PIN_BASED_EXT_INTR_MASK |
2905 PIN_BASED_NMI_EXITING |
2906 PIN_BASED_VIRTUAL_NMIS;
2907 vmx->nested.nested_vmx_pinbased_ctls_high |=
2908 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
Jan Kiszka0238ea92013-03-13 11:31:24 +01002909 PIN_BASED_VMX_PREEMPTION_TIMER;
Andrey Smetanind62caab2015-11-10 15:36:33 +03002910 if (kvm_vcpu_apicv_active(&vmx->vcpu))
Wincy Van705699a2015-02-03 23:58:17 +08002911 vmx->nested.nested_vmx_pinbased_ctls_high |=
2912 PIN_BASED_POSTED_INTR;
Nadav Har'Elb87a51a2011-05-25 23:04:25 +03002913
Jan Kiszka3dbcd8d2014-06-16 13:59:40 +02002914 /* exit controls */
Arthur Chunqi Lic0dfee52013-08-06 18:41:45 +08002915 rdmsr(MSR_IA32_VMX_EXIT_CTLS,
Wincy Vanb9c237b2015-02-03 23:56:30 +08002916 vmx->nested.nested_vmx_exit_ctls_low,
2917 vmx->nested.nested_vmx_exit_ctls_high);
2918 vmx->nested.nested_vmx_exit_ctls_low =
2919 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
Bandan Dase0ba1a62014-04-19 18:17:46 -04002920
Wincy Vanb9c237b2015-02-03 23:56:30 +08002921 vmx->nested.nested_vmx_exit_ctls_high &=
Nadav Har'Elb87a51a2011-05-25 23:04:25 +03002922#ifdef CONFIG_X86_64
Arthur Chunqi Lic0dfee52013-08-06 18:41:45 +08002923 VM_EXIT_HOST_ADDR_SPACE_SIZE |
Nadav Har'Elb87a51a2011-05-25 23:04:25 +03002924#endif
Jan Kiszkaf4124502014-03-07 20:03:13 +01002925 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
Wincy Vanb9c237b2015-02-03 23:56:30 +08002926 vmx->nested.nested_vmx_exit_ctls_high |=
2927 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
Jan Kiszkaf4124502014-03-07 20:03:13 +01002928 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
Bandan Dase0ba1a62014-04-19 18:17:46 -04002929 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2930
Paolo Bonzinia87036a2016-03-08 09:52:13 +01002931 if (kvm_mpx_supported())
Wincy Vanb9c237b2015-02-03 23:56:30 +08002932 vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
Nadav Har'Elb87a51a2011-05-25 23:04:25 +03002933
Jan Kiszka2996fca2014-06-16 13:59:43 +02002934 /* We support free control of debug control saving. */
Wincy Vanb9c237b2015-02-03 23:56:30 +08002935 vmx->nested.nested_vmx_true_exit_ctls_low =
2936 vmx->nested.nested_vmx_exit_ctls_low &
Jan Kiszka2996fca2014-06-16 13:59:43 +02002937 ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2938
Nadav Har'Elb87a51a2011-05-25 23:04:25 +03002939 /* entry controls */
2940 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
Wincy Vanb9c237b2015-02-03 23:56:30 +08002941 vmx->nested.nested_vmx_entry_ctls_low,
2942 vmx->nested.nested_vmx_entry_ctls_high);
2943 vmx->nested.nested_vmx_entry_ctls_low =
2944 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2945 vmx->nested.nested_vmx_entry_ctls_high &=
Jan Kiszka57435342013-08-06 10:39:56 +02002946#ifdef CONFIG_X86_64
2947 VM_ENTRY_IA32E_MODE |
2948#endif
2949 VM_ENTRY_LOAD_IA32_PAT;
Wincy Vanb9c237b2015-02-03 23:56:30 +08002950 vmx->nested.nested_vmx_entry_ctls_high |=
2951 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
Paolo Bonzinia87036a2016-03-08 09:52:13 +01002952 if (kvm_mpx_supported())
Wincy Vanb9c237b2015-02-03 23:56:30 +08002953 vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
Jan Kiszka57435342013-08-06 10:39:56 +02002954
Jan Kiszka2996fca2014-06-16 13:59:43 +02002955 /* We support free control of debug control loading. */
Wincy Vanb9c237b2015-02-03 23:56:30 +08002956 vmx->nested.nested_vmx_true_entry_ctls_low =
2957 vmx->nested.nested_vmx_entry_ctls_low &
Jan Kiszka2996fca2014-06-16 13:59:43 +02002958 ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2959
Nadav Har'Elb87a51a2011-05-25 23:04:25 +03002960 /* cpu-based controls */
2961 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
Wincy Vanb9c237b2015-02-03 23:56:30 +08002962 vmx->nested.nested_vmx_procbased_ctls_low,
2963 vmx->nested.nested_vmx_procbased_ctls_high);
2964 vmx->nested.nested_vmx_procbased_ctls_low =
2965 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2966 vmx->nested.nested_vmx_procbased_ctls_high &=
Jan Kiszkaa294c9b2013-10-23 17:43:09 +01002967 CPU_BASED_VIRTUAL_INTR_PENDING |
2968 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
Nadav Har'Elb87a51a2011-05-25 23:04:25 +03002969 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2970 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2971 CPU_BASED_CR3_STORE_EXITING |
2972#ifdef CONFIG_X86_64
2973 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2974#endif
2975 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
Mihai Donțu5f3d45e2015-07-05 20:08:57 +03002976 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG |
2977 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING |
2978 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING |
2979 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
Nadav Har'Elb87a51a2011-05-25 23:04:25 +03002980 /*
2981 * We can allow some features even when not supported by the
2982 * hardware. For example, L1 can specify an MSR bitmap - and we
2983 * can use it to avoid exits to L1 - even when L0 runs L2
2984 * without MSR bitmaps.
2985 */
Wincy Vanb9c237b2015-02-03 23:56:30 +08002986 vmx->nested.nested_vmx_procbased_ctls_high |=
2987 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
Jan Kiszka560b7ee2014-06-16 13:59:42 +02002988 CPU_BASED_USE_MSR_BITMAPS;
Nadav Har'Elb87a51a2011-05-25 23:04:25 +03002989
Jan Kiszka3dcdf3e2014-06-16 13:59:41 +02002990 /* We support free control of CR3 access interception. */
Wincy Vanb9c237b2015-02-03 23:56:30 +08002991 vmx->nested.nested_vmx_true_procbased_ctls_low =
2992 vmx->nested.nested_vmx_procbased_ctls_low &
Jan Kiszka3dcdf3e2014-06-16 13:59:41 +02002993 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2994
Nadav Har'Elb87a51a2011-05-25 23:04:25 +03002995 /* secondary cpu-based controls */
2996 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
Wincy Vanb9c237b2015-02-03 23:56:30 +08002997 vmx->nested.nested_vmx_secondary_ctls_low,
2998 vmx->nested.nested_vmx_secondary_ctls_high);
2999 vmx->nested.nested_vmx_secondary_ctls_low = 0;
3000 vmx->nested.nested_vmx_secondary_ctls_high &=
Jan Kiszkad6851fb2013-02-23 22:34:39 +01003001 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
Jan Kiszkab3a2a902015-03-23 19:27:19 +01003002 SECONDARY_EXEC_RDTSCP |
Wincy Vanf2b93282015-02-03 23:56:03 +08003003 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
Wanpeng Li5c614b32015-10-13 09:18:36 -07003004 SECONDARY_EXEC_ENABLE_VPID |
Wincy Van82f0dd42015-02-03 23:57:18 +08003005 SECONDARY_EXEC_APIC_REGISTER_VIRT |
Wincy Van608406e2015-02-03 23:57:51 +08003006 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
Wanpeng Li81dc01f2014-12-04 19:11:07 +08003007 SECONDARY_EXEC_WBINVD_EXITING |
Dan Williamsdfa169b2016-06-02 11:17:24 -07003008 SECONDARY_EXEC_XSAVES;
Jan Kiszkac18911a2013-03-13 16:06:41 +01003009
Nadav Har'Elafa61f72013-08-07 14:59:22 +02003010 if (enable_ept) {
3011 /* nested EPT: emulate EPT also to L1 */
Wincy Vanb9c237b2015-02-03 23:56:30 +08003012 vmx->nested.nested_vmx_secondary_ctls_high |=
Radim Krčmář0790ec12015-03-17 14:02:32 +01003013 SECONDARY_EXEC_ENABLE_EPT;
Wincy Vanb9c237b2015-02-03 23:56:30 +08003014 vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
Jan Kiszkad3134db2013-10-23 14:40:31 +01003015 VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
3016 VMX_EPT_INVEPT_BIT;
Bandan Das02120c42016-07-12 18:18:52 -04003017 if (cpu_has_vmx_ept_execute_only())
3018 vmx->nested.nested_vmx_ept_caps |=
3019 VMX_EPT_EXECUTE_ONLY_BIT;
Wincy Vanb9c237b2015-02-03 23:56:30 +08003020 vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept;
Bandan Das45e11812016-08-02 16:32:36 -04003021 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT |
3022 VMX_EPT_EXTENT_CONTEXT_BIT;
Nadav Har'Elafa61f72013-08-07 14:59:22 +02003023 } else
Wincy Vanb9c237b2015-02-03 23:56:30 +08003024 vmx->nested.nested_vmx_ept_caps = 0;
Nadav Har'Elafa61f72013-08-07 14:59:22 +02003025
Paolo Bonzinief697a72016-03-18 16:58:38 +01003026 /*
3027 * Old versions of KVM use the single-context version without
3028 * checking for support, so declare that it is supported even
3029 * though it is treated as global context. The alternative is
3030 * not failing the single-context invvpid, and it is worse.
3031 */
Wanpeng Li089d7b62015-10-13 09:18:37 -07003032 if (enable_vpid)
3033 vmx->nested.nested_vmx_vpid_caps = VMX_VPID_INVVPID_BIT |
Jan Dakinevich04c776e2018-02-23 11:42:18 +01003034 VMX_VPID_EXTENT_SUPPORTED_MASK;
Wanpeng Li089d7b62015-10-13 09:18:37 -07003035 else
3036 vmx->nested.nested_vmx_vpid_caps = 0;
Wanpeng Li99b83ac2015-10-13 09:12:21 -07003037
Radim Krčmář0790ec12015-03-17 14:02:32 +01003038 if (enable_unrestricted_guest)
3039 vmx->nested.nested_vmx_secondary_ctls_high |=
3040 SECONDARY_EXEC_UNRESTRICTED_GUEST;
3041
Jan Kiszkac18911a2013-03-13 16:06:41 +01003042 /* miscellaneous data */
Wincy Vanb9c237b2015-02-03 23:56:30 +08003043 rdmsr(MSR_IA32_VMX_MISC,
3044 vmx->nested.nested_vmx_misc_low,
3045 vmx->nested.nested_vmx_misc_high);
3046 vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
3047 vmx->nested.nested_vmx_misc_low |=
3048 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
Jan Kiszkaf4124502014-03-07 20:03:13 +01003049 VMX_MISC_ACTIVITY_HLT;
Wincy Vanb9c237b2015-02-03 23:56:30 +08003050 vmx->nested.nested_vmx_misc_high = 0;
Nadav Har'Elb87a51a2011-05-25 23:04:25 +03003051}
3052
3053static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
3054{
3055 /*
3056 * Bits 0 in high must be 0, and bits 1 in low must be 1.
3057 */
3058 return ((control & high) | low) == control;
3059}
3060
3061static inline u64 vmx_control_msr(u32 low, u32 high)
3062{
3063 return low | ((u64)high << 32);
3064}
3065
Jan Kiszkacae50132014-01-04 18:47:22 +01003066/* Returns 0 on success, non-0 otherwise. */
Nadav Har'Elb87a51a2011-05-25 23:04:25 +03003067static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
3068{
Wincy Vanb9c237b2015-02-03 23:56:30 +08003069 struct vcpu_vmx *vmx = to_vmx(vcpu);
3070
Nadav Har'Elb87a51a2011-05-25 23:04:25 +03003071 switch (msr_index) {
Nadav Har'Elb87a51a2011-05-25 23:04:25 +03003072 case MSR_IA32_VMX_BASIC:
3073 /*
3074 * This MSR reports some information about VMX support. We
3075 * should return information about the VMX we emulate for the
3076 * guest, and the VMCS structure we give it - not about the
3077 * VMX support of the underlying hardware.
3078 */
Jan Kiszka3dbcd8d2014-06-16 13:59:40 +02003079 *pdata = VMCS12_REVISION | VMX_BASIC_TRUE_CTLS |
Nadav Har'Elb87a51a2011-05-25 23:04:25 +03003080 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
3081 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
Jan Dakinevich9ac7e3e2016-09-04 21:23:15 +03003082 if (cpu_has_vmx_basic_inout())
3083 *pdata |= VMX_BASIC_INOUT;
Nadav Har'Elb87a51a2011-05-25 23:04:25 +03003084 break;
3085 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3086 case MSR_IA32_VMX_PINBASED_CTLS:
Wincy Vanb9c237b2015-02-03 23:56:30 +08003087 *pdata = vmx_control_msr(
3088 vmx->nested.nested_vmx_pinbased_ctls_low,
3089 vmx->nested.nested_vmx_pinbased_ctls_high);
Nadav Har'Elb87a51a2011-05-25 23:04:25 +03003090 break;
3091 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
Wincy Vanb9c237b2015-02-03 23:56:30 +08003092 *pdata = vmx_control_msr(
3093 vmx->nested.nested_vmx_true_procbased_ctls_low,
3094 vmx->nested.nested_vmx_procbased_ctls_high);
Jan Kiszka3dcdf3e2014-06-16 13:59:41 +02003095 break;
Nadav Har'Elb87a51a2011-05-25 23:04:25 +03003096 case MSR_IA32_VMX_PROCBASED_CTLS:
Wincy Vanb9c237b2015-02-03 23:56:30 +08003097 *pdata = vmx_control_msr(
3098 vmx->nested.nested_vmx_procbased_ctls_low,
3099 vmx->nested.nested_vmx_procbased_ctls_high);
Nadav Har'Elb87a51a2011-05-25 23:04:25 +03003100 break;
3101 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
Wincy Vanb9c237b2015-02-03 23:56:30 +08003102 *pdata = vmx_control_msr(
3103 vmx->nested.nested_vmx_true_exit_ctls_low,
3104 vmx->nested.nested_vmx_exit_ctls_high);
Jan Kiszka2996fca2014-06-16 13:59:43 +02003105 break;
Nadav Har'Elb87a51a2011-05-25 23:04:25 +03003106 case MSR_IA32_VMX_EXIT_CTLS:
Wincy Vanb9c237b2015-02-03 23:56:30 +08003107 *pdata = vmx_control_msr(
3108 vmx->nested.nested_vmx_exit_ctls_low,
3109 vmx->nested.nested_vmx_exit_ctls_high);
Nadav Har'Elb87a51a2011-05-25 23:04:25 +03003110 break;
3111 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
Wincy Vanb9c237b2015-02-03 23:56:30 +08003112 *pdata = vmx_control_msr(
3113 vmx->nested.nested_vmx_true_entry_ctls_low,
3114 vmx->nested.nested_vmx_entry_ctls_high);
Jan Kiszka2996fca2014-06-16 13:59:43 +02003115 break;
Nadav Har'Elb87a51a2011-05-25 23:04:25 +03003116 case MSR_IA32_VMX_ENTRY_CTLS:
Wincy Vanb9c237b2015-02-03 23:56:30 +08003117 *pdata = vmx_control_msr(
3118 vmx->nested.nested_vmx_entry_ctls_low,
3119 vmx->nested.nested_vmx_entry_ctls_high);
Nadav Har'Elb87a51a2011-05-25 23:04:25 +03003120 break;
3121 case MSR_IA32_VMX_MISC:
Wincy Vanb9c237b2015-02-03 23:56:30 +08003122 *pdata = vmx_control_msr(
3123 vmx->nested.nested_vmx_misc_low,
3124 vmx->nested.nested_vmx_misc_high);
Nadav Har'Elb87a51a2011-05-25 23:04:25 +03003125 break;
3126 /*
3127 * These MSRs specify bits which the guest must keep fixed (on or off)
3128 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
3129 * We picked the standard core2 setting.
3130 */
3131#define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
3132#define VMXON_CR4_ALWAYSON X86_CR4_VMXE
3133 case MSR_IA32_VMX_CR0_FIXED0:
3134 *pdata = VMXON_CR0_ALWAYSON;
3135 break;
3136 case MSR_IA32_VMX_CR0_FIXED1:
3137 *pdata = -1ULL;
3138 break;
3139 case MSR_IA32_VMX_CR4_FIXED0:
3140 *pdata = VMXON_CR4_ALWAYSON;
3141 break;
3142 case MSR_IA32_VMX_CR4_FIXED1:
3143 *pdata = -1ULL;
3144 break;
3145 case MSR_IA32_VMX_VMCS_ENUM:
Jan Kiszka53814172014-06-16 13:59:44 +02003146 *pdata = 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */
Nadav Har'Elb87a51a2011-05-25 23:04:25 +03003147 break;
3148 case MSR_IA32_VMX_PROCBASED_CTLS2:
Wincy Vanb9c237b2015-02-03 23:56:30 +08003149 *pdata = vmx_control_msr(
3150 vmx->nested.nested_vmx_secondary_ctls_low,
3151 vmx->nested.nested_vmx_secondary_ctls_high);
Nadav Har'Elb87a51a2011-05-25 23:04:25 +03003152 break;
3153 case MSR_IA32_VMX_EPT_VPID_CAP:
Wanpeng Li089d7b62015-10-13 09:18:37 -07003154 *pdata = vmx->nested.nested_vmx_ept_caps |
3155 ((u64)vmx->nested.nested_vmx_vpid_caps << 32);
Nadav Har'Elb87a51a2011-05-25 23:04:25 +03003156 break;
3157 default:
Nadav Har'Elb87a51a2011-05-25 23:04:25 +03003158 return 1;
Nadav Har'Elb3897a42013-07-08 19:12:35 +08003159 }
3160
Nadav Har'Elb87a51a2011-05-25 23:04:25 +03003161 return 0;
3162}
3163
Haozhong Zhang37e4c992016-06-22 14:59:55 +08003164static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
3165 uint64_t val)
3166{
3167 uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
3168
3169 return !(val & ~valid_bits);
3170}
3171
Tom Lendacky62d88fc2018-02-21 13:39:51 -06003172static int vmx_get_msr_feature(struct kvm_msr_entry *msr)
3173{
3174 return 1;
3175}
3176
Nadav Har'Elb87a51a2011-05-25 23:04:25 +03003177/*
Avi Kivity6aa8b732006-12-10 02:21:36 -08003178 * Reads an msr value (of 'msr_index') into 'pdata'.
3179 * Returns 0 on success, non-0 otherwise.
3180 * Assumes vcpu_load() was already called.
3181 */
Paolo Bonzini609e36d2015-04-08 15:30:38 +02003182static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
Avi Kivity6aa8b732006-12-10 02:21:36 -08003183{
Avi Kivity26bb0982009-09-07 11:14:12 +03003184 struct shared_msr_entry *msr;
Avi Kivity6aa8b732006-12-10 02:21:36 -08003185
Paolo Bonzini609e36d2015-04-08 15:30:38 +02003186 switch (msr_info->index) {
Avi Kivity05b3e0c2006-12-13 00:33:45 -08003187#ifdef CONFIG_X86_64
Avi Kivity6aa8b732006-12-10 02:21:36 -08003188 case MSR_FS_BASE:
Paolo Bonzini609e36d2015-04-08 15:30:38 +02003189 msr_info->data = vmcs_readl(GUEST_FS_BASE);
Avi Kivity6aa8b732006-12-10 02:21:36 -08003190 break;
3191 case MSR_GS_BASE:
Paolo Bonzini609e36d2015-04-08 15:30:38 +02003192 msr_info->data = vmcs_readl(GUEST_GS_BASE);
Avi Kivity6aa8b732006-12-10 02:21:36 -08003193 break;
Avi Kivity44ea2b12009-09-06 15:55:37 +03003194 case MSR_KERNEL_GS_BASE:
3195 vmx_load_host_state(to_vmx(vcpu));
Paolo Bonzini609e36d2015-04-08 15:30:38 +02003196 msr_info->data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
Avi Kivity44ea2b12009-09-06 15:55:37 +03003197 break;
Avi Kivity26bb0982009-09-07 11:14:12 +03003198#endif
Avi Kivity6aa8b732006-12-10 02:21:36 -08003199 case MSR_EFER:
Paolo Bonzini609e36d2015-04-08 15:30:38 +02003200 return kvm_get_msr_common(vcpu, msr_info);
Jaswinder Singh Rajputaf24a4e2009-05-15 18:42:05 +05303201 case MSR_IA32_TSC:
Haozhong Zhangbe7b2632015-10-20 15:39:11 +08003202 msr_info->data = guest_read_tsc(vcpu);
Avi Kivity6aa8b732006-12-10 02:21:36 -08003203 break;
KarimAllah Ahmede5a83412018-02-01 22:59:45 +01003204 case MSR_IA32_SPEC_CTRL:
3205 if (!msr_info->host_initiated &&
Konrad Rzeszutek Wilk99318ec2018-04-25 22:04:25 -04003206 !guest_cpuid_has_spec_ctrl(vcpu))
KarimAllah Ahmede5a83412018-02-01 22:59:45 +01003207 return 1;
3208
3209 msr_info->data = to_vmx(vcpu)->spec_ctrl;
3210 break;
KarimAllah Ahmed755502f2018-02-01 22:59:44 +01003211 case MSR_IA32_ARCH_CAPABILITIES:
3212 if (!msr_info->host_initiated &&
3213 !guest_cpuid_has_arch_capabilities(vcpu))
3214 return 1;
3215 msr_info->data = to_vmx(vcpu)->arch_capabilities;
3216 break;
Avi Kivity6aa8b732006-12-10 02:21:36 -08003217 case MSR_IA32_SYSENTER_CS:
Paolo Bonzini609e36d2015-04-08 15:30:38 +02003218 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
Avi Kivity6aa8b732006-12-10 02:21:36 -08003219 break;
3220 case MSR_IA32_SYSENTER_EIP:
Paolo Bonzini609e36d2015-04-08 15:30:38 +02003221 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
Avi Kivity6aa8b732006-12-10 02:21:36 -08003222 break;
3223 case MSR_IA32_SYSENTER_ESP:
Paolo Bonzini609e36d2015-04-08 15:30:38 +02003224 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
Avi Kivity6aa8b732006-12-10 02:21:36 -08003225 break;
Liu, Jinsong0dd376e2014-02-24 10:56:53 +00003226 case MSR_IA32_BNDCFGS:
Haozhong Zhangcce8d2e2017-07-04 10:27:41 +08003227 if (!kvm_mpx_supported() ||
3228 (!msr_info->host_initiated && !guest_cpuid_has_mpx(vcpu)))
Paolo Bonzini93c4adc2014-03-05 23:19:52 +01003229 return 1;
Paolo Bonzini609e36d2015-04-08 15:30:38 +02003230 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
Liu, Jinsong0dd376e2014-02-24 10:56:53 +00003231 break;
Ashok Rajc45dcc72016-06-22 14:59:56 +08003232 case MSR_IA32_MCG_EXT_CTL:
3233 if (!msr_info->host_initiated &&
3234 !(to_vmx(vcpu)->msr_ia32_feature_control &
3235 FEATURE_CONTROL_LMCE))
Jan Kiszkacae50132014-01-04 18:47:22 +01003236 return 1;
Ashok Rajc45dcc72016-06-22 14:59:56 +08003237 msr_info->data = vcpu->arch.mcg_ext_ctl;
3238 break;
Jan Kiszkacae50132014-01-04 18:47:22 +01003239 case MSR_IA32_FEATURE_CONTROL:
Haozhong Zhang3b840802016-06-22 14:59:54 +08003240 msr_info->data = to_vmx(vcpu)->msr_ia32_feature_control;
Jan Kiszkacae50132014-01-04 18:47:22 +01003241 break;
3242 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3243 if (!nested_vmx_allowed(vcpu))
3244 return 1;
Paolo Bonzini609e36d2015-04-08 15:30:38 +02003245 return vmx_get_vmx_msr(vcpu, msr_info->index, &msr_info->data);
Wanpeng Li20300092014-12-02 19:14:59 +08003246 case MSR_IA32_XSS:
3247 if (!vmx_xsaves_supported())
3248 return 1;
Paolo Bonzini609e36d2015-04-08 15:30:38 +02003249 msr_info->data = vcpu->arch.ia32_xss;
Wanpeng Li20300092014-12-02 19:14:59 +08003250 break;
Sheng Yang4e47c7a2009-12-18 16:48:47 +08003251 case MSR_TSC_AUX:
Haozhong Zhang81b1b9c2015-12-14 23:13:38 +08003252 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
Sheng Yang4e47c7a2009-12-18 16:48:47 +08003253 return 1;
3254 /* Otherwise falls through */
Avi Kivity6aa8b732006-12-10 02:21:36 -08003255 default:
Paolo Bonzini609e36d2015-04-08 15:30:38 +02003256 msr = find_msr_entry(to_vmx(vcpu), msr_info->index);
Avi Kivity3bab1f52006-12-29 16:49:48 -08003257 if (msr) {
Paolo Bonzini609e36d2015-04-08 15:30:38 +02003258 msr_info->data = msr->data;
Avi Kivity3bab1f52006-12-29 16:49:48 -08003259 break;
Avi Kivity6aa8b732006-12-10 02:21:36 -08003260 }
Paolo Bonzini609e36d2015-04-08 15:30:38 +02003261 return kvm_get_msr_common(vcpu, msr_info);
Avi Kivity6aa8b732006-12-10 02:21:36 -08003262 }
3263
Avi Kivity6aa8b732006-12-10 02:21:36 -08003264 return 0;
3265}
3266
Jan Kiszkacae50132014-01-04 18:47:22 +01003267static void vmx_leave_nested(struct kvm_vcpu *vcpu);
3268
Avi Kivity6aa8b732006-12-10 02:21:36 -08003269/*
3270 * Writes msr value into into the appropriate "register".
3271 * Returns 0 on success, non-0 otherwise.
3272 * Assumes vcpu_load() was already called.
3273 */
Will Auld8fe8ab42012-11-29 12:42:12 -08003274static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
Avi Kivity6aa8b732006-12-10 02:21:36 -08003275{
Gregory Haskinsa2fa3e92007-07-27 08:13:10 -04003276 struct vcpu_vmx *vmx = to_vmx(vcpu);
Avi Kivity26bb0982009-09-07 11:14:12 +03003277 struct shared_msr_entry *msr;
Eddie Dong2cc51562007-05-21 07:28:09 +03003278 int ret = 0;
Will Auld8fe8ab42012-11-29 12:42:12 -08003279 u32 msr_index = msr_info->index;
3280 u64 data = msr_info->data;
Eddie Dong2cc51562007-05-21 07:28:09 +03003281
Avi Kivity6aa8b732006-12-10 02:21:36 -08003282 switch (msr_index) {
Avi Kivity3bab1f52006-12-29 16:49:48 -08003283 case MSR_EFER:
Will Auld8fe8ab42012-11-29 12:42:12 -08003284 ret = kvm_set_msr_common(vcpu, msr_info);
Eddie Dong2cc51562007-05-21 07:28:09 +03003285 break;
Avi Kivity16175a72009-03-23 22:13:44 +02003286#ifdef CONFIG_X86_64
Avi Kivity6aa8b732006-12-10 02:21:36 -08003287 case MSR_FS_BASE:
Avi Kivity2fb92db2011-04-27 19:42:18 +03003288 vmx_segment_cache_clear(vmx);
Avi Kivity6aa8b732006-12-10 02:21:36 -08003289 vmcs_writel(GUEST_FS_BASE, data);
3290 break;
3291 case MSR_GS_BASE:
Avi Kivity2fb92db2011-04-27 19:42:18 +03003292 vmx_segment_cache_clear(vmx);
Avi Kivity6aa8b732006-12-10 02:21:36 -08003293 vmcs_writel(GUEST_GS_BASE, data);
3294 break;
Avi Kivity44ea2b12009-09-06 15:55:37 +03003295 case MSR_KERNEL_GS_BASE:
3296 vmx_load_host_state(vmx);
3297 vmx->msr_guest_kernel_gs_base = data;
3298 break;
Avi Kivity6aa8b732006-12-10 02:21:36 -08003299#endif
3300 case MSR_IA32_SYSENTER_CS:
3301 vmcs_write32(GUEST_SYSENTER_CS, data);
3302 break;
3303 case MSR_IA32_SYSENTER_EIP:
Avi Kivityf5b42c32007-03-06 12:05:53 +02003304 vmcs_writel(GUEST_SYSENTER_EIP, data);
Avi Kivity6aa8b732006-12-10 02:21:36 -08003305 break;
3306 case MSR_IA32_SYSENTER_ESP:
Avi Kivityf5b42c32007-03-06 12:05:53 +02003307 vmcs_writel(GUEST_SYSENTER_ESP, data);
Avi Kivity6aa8b732006-12-10 02:21:36 -08003308 break;
Liu, Jinsong0dd376e2014-02-24 10:56:53 +00003309 case MSR_IA32_BNDCFGS:
Haozhong Zhangcce8d2e2017-07-04 10:27:41 +08003310 if (!kvm_mpx_supported() ||
3311 (!msr_info->host_initiated && !guest_cpuid_has_mpx(vcpu)))
Paolo Bonzini93c4adc2014-03-05 23:19:52 +01003312 return 1;
Jim Mattson07592d62017-05-23 11:52:54 -07003313 if (is_noncanonical_address(data & PAGE_MASK) ||
3314 (data & MSR_IA32_BNDCFGS_RSVD))
3315 return 1;
Liu, Jinsong0dd376e2014-02-24 10:56:53 +00003316 vmcs_write64(GUEST_BNDCFGS, data);
3317 break;
Jaswinder Singh Rajputaf24a4e2009-05-15 18:42:05 +05303318 case MSR_IA32_TSC:
Will Auld8fe8ab42012-11-29 12:42:12 -08003319 kvm_write_tsc(vcpu, msr_info);
Avi Kivity6aa8b732006-12-10 02:21:36 -08003320 break;
KarimAllah Ahmede5a83412018-02-01 22:59:45 +01003321 case MSR_IA32_SPEC_CTRL:
3322 if (!msr_info->host_initiated &&
Konrad Rzeszutek Wilk99318ec2018-04-25 22:04:25 -04003323 !guest_cpuid_has_spec_ctrl(vcpu))
KarimAllah Ahmede5a83412018-02-01 22:59:45 +01003324 return 1;
3325
3326 /* The STIBP bit doesn't fault even if it's not advertised */
Konrad Rzeszutek Wilkbf3da842018-05-09 21:41:38 +02003327 if (data & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD))
KarimAllah Ahmede5a83412018-02-01 22:59:45 +01003328 return 1;
3329
3330 vmx->spec_ctrl = data;
3331
3332 if (!data)
3333 break;
3334
3335 /*
3336 * For non-nested:
3337 * When it's written (to non-zero) for the first time, pass
3338 * it through.
3339 *
3340 * For nested:
3341 * The handling of the MSR bitmap for L2 guests is done in
3342 * nested_vmx_merge_msr_bitmap. We should not touch the
3343 * vmcs02.msr_bitmap here since it gets completely overwritten
3344 * in the merging. We update the vmcs01 here for L1 as well
3345 * since it will end up touching the MSR anyway now.
3346 */
3347 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap,
3348 MSR_IA32_SPEC_CTRL,
3349 MSR_TYPE_RW);
3350 break;
Ashok Raj70131292018-02-01 22:59:43 +01003351 case MSR_IA32_PRED_CMD:
3352 if (!msr_info->host_initiated &&
3353 !guest_cpuid_has_ibpb(vcpu))
3354 return 1;
3355
3356 if (data & ~PRED_CMD_IBPB)
3357 return 1;
3358
3359 if (!data)
3360 break;
3361
3362 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
3363
3364 /*
3365 * For non-nested:
3366 * When it's written (to non-zero) for the first time, pass
3367 * it through.
3368 *
3369 * For nested:
3370 * The handling of the MSR bitmap for L2 guests is done in
3371 * nested_vmx_merge_msr_bitmap. We should not touch the
3372 * vmcs02.msr_bitmap here since it gets completely overwritten
3373 * in the merging.
3374 */
3375 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap, MSR_IA32_PRED_CMD,
3376 MSR_TYPE_W);
3377 break;
KarimAllah Ahmed755502f2018-02-01 22:59:44 +01003378 case MSR_IA32_ARCH_CAPABILITIES:
3379 if (!msr_info->host_initiated)
3380 return 1;
3381 vmx->arch_capabilities = data;
3382 break;
Sheng Yang468d4722008-10-09 16:01:55 +08003383 case MSR_IA32_CR_PAT:
3384 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
Nadav Amit45666542014-09-18 22:39:44 +03003385 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
3386 return 1;
Sheng Yang468d4722008-10-09 16:01:55 +08003387 vmcs_write64(GUEST_IA32_PAT, data);
3388 vcpu->arch.pat = data;
3389 break;
3390 }
Will Auld8fe8ab42012-11-29 12:42:12 -08003391 ret = kvm_set_msr_common(vcpu, msr_info);
Sheng Yang4e47c7a2009-12-18 16:48:47 +08003392 break;
Will Auldba904632012-11-29 12:42:50 -08003393 case MSR_IA32_TSC_ADJUST:
3394 ret = kvm_set_msr_common(vcpu, msr_info);
Sheng Yang4e47c7a2009-12-18 16:48:47 +08003395 break;
Ashok Rajc45dcc72016-06-22 14:59:56 +08003396 case MSR_IA32_MCG_EXT_CTL:
3397 if ((!msr_info->host_initiated &&
3398 !(to_vmx(vcpu)->msr_ia32_feature_control &
3399 FEATURE_CONTROL_LMCE)) ||
3400 (data & ~MCG_EXT_CTL_LMCE_EN))
3401 return 1;
3402 vcpu->arch.mcg_ext_ctl = data;
3403 break;
Jan Kiszkacae50132014-01-04 18:47:22 +01003404 case MSR_IA32_FEATURE_CONTROL:
Haozhong Zhang37e4c992016-06-22 14:59:55 +08003405 if (!vmx_feature_control_msr_valid(vcpu, data) ||
Haozhong Zhang3b840802016-06-22 14:59:54 +08003406 (to_vmx(vcpu)->msr_ia32_feature_control &
Jan Kiszkacae50132014-01-04 18:47:22 +01003407 FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
3408 return 1;
Haozhong Zhang3b840802016-06-22 14:59:54 +08003409 vmx->msr_ia32_feature_control = data;
Jan Kiszkacae50132014-01-04 18:47:22 +01003410 if (msr_info->host_initiated && data == 0)
3411 vmx_leave_nested(vcpu);
3412 break;
3413 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3414 return 1; /* they are read-only */
Wanpeng Li20300092014-12-02 19:14:59 +08003415 case MSR_IA32_XSS:
3416 if (!vmx_xsaves_supported())
3417 return 1;
3418 /*
3419 * The only supported bit as of Skylake is bit 8, but
3420 * it is not supported on KVM.
3421 */
3422 if (data != 0)
3423 return 1;
3424 vcpu->arch.ia32_xss = data;
3425 if (vcpu->arch.ia32_xss != host_xss)
3426 add_atomic_switch_msr(vmx, MSR_IA32_XSS,
Konrad Rzeszutek Wilkc45ff812018-06-20 22:01:22 -04003427 vcpu->arch.ia32_xss, host_xss, false);
Wanpeng Li20300092014-12-02 19:14:59 +08003428 else
3429 clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
3430 break;
Sheng Yang4e47c7a2009-12-18 16:48:47 +08003431 case MSR_TSC_AUX:
Haozhong Zhang81b1b9c2015-12-14 23:13:38 +08003432 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
Sheng Yang4e47c7a2009-12-18 16:48:47 +08003433 return 1;
3434 /* Check reserved bit, higher 32 bits should be zero */
3435 if ((data >> 32) != 0)
3436 return 1;
3437 /* Otherwise falls through */
Avi Kivity6aa8b732006-12-10 02:21:36 -08003438 default:
Rusty Russell8b9cf982007-07-30 16:31:43 +10003439 msr = find_msr_entry(vmx, msr_index);
Avi Kivity3bab1f52006-12-29 16:49:48 -08003440 if (msr) {
Andy Honig8b3c3102014-08-27 11:16:44 -07003441 u64 old_msr_data = msr->data;
Avi Kivity3bab1f52006-12-29 16:49:48 -08003442 msr->data = data;
Avi Kivity2225fd52012-04-18 15:03:04 +03003443 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
3444 preempt_disable();
Andy Honig8b3c3102014-08-27 11:16:44 -07003445 ret = kvm_set_shared_msr(msr->index, msr->data,
3446 msr->mask);
Avi Kivity2225fd52012-04-18 15:03:04 +03003447 preempt_enable();
Andy Honig8b3c3102014-08-27 11:16:44 -07003448 if (ret)
3449 msr->data = old_msr_data;
Avi Kivity2225fd52012-04-18 15:03:04 +03003450 }
Avi Kivity3bab1f52006-12-29 16:49:48 -08003451 break;
Avi Kivity6aa8b732006-12-10 02:21:36 -08003452 }
Will Auld8fe8ab42012-11-29 12:42:12 -08003453 ret = kvm_set_msr_common(vcpu, msr_info);
Avi Kivity6aa8b732006-12-10 02:21:36 -08003454 }
3455
Eddie Dong2cc51562007-05-21 07:28:09 +03003456 return ret;
Avi Kivity6aa8b732006-12-10 02:21:36 -08003457}
3458
Marcelo Tosatti5fdbf972008-06-27 14:58:02 -03003459static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
Avi Kivity6aa8b732006-12-10 02:21:36 -08003460{
Marcelo Tosatti5fdbf972008-06-27 14:58:02 -03003461 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
3462 switch (reg) {
3463 case VCPU_REGS_RSP:
3464 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
3465 break;
3466 case VCPU_REGS_RIP:
3467 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
3468 break;
Avi Kivity6de4f3a2009-05-31 22:58:47 +03003469 case VCPU_EXREG_PDPTR:
3470 if (enable_ept)
3471 ept_save_pdptrs(vcpu);
3472 break;
Marcelo Tosatti5fdbf972008-06-27 14:58:02 -03003473 default:
3474 break;
3475 }
Avi Kivity6aa8b732006-12-10 02:21:36 -08003476}
3477
Avi Kivity6aa8b732006-12-10 02:21:36 -08003478static __init int cpu_has_kvm_support(void)
3479{
Eduardo Habkost6210e372008-11-17 19:03:16 -02003480 return cpu_has_vmx();
Avi Kivity6aa8b732006-12-10 02:21:36 -08003481}
3482
3483static __init int vmx_disabled_by_bios(void)
3484{
3485 u64 msr;
3486
3487 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
Shane Wangcafd6652010-04-29 12:09:01 -04003488 if (msr & FEATURE_CONTROL_LOCKED) {
Joseph Cihula23f3e992011-02-08 11:45:56 -08003489 /* launched w/ TXT and VMX disabled */
Shane Wangcafd6652010-04-29 12:09:01 -04003490 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3491 && tboot_enabled())
3492 return 1;
Joseph Cihula23f3e992011-02-08 11:45:56 -08003493 /* launched w/o TXT and VMX only enabled w/ TXT */
Shane Wangcafd6652010-04-29 12:09:01 -04003494 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
Joseph Cihula23f3e992011-02-08 11:45:56 -08003495 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
Shane Wangf9335af2010-11-17 11:40:17 +08003496 && !tboot_enabled()) {
3497 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
Joseph Cihula23f3e992011-02-08 11:45:56 -08003498 "activate TXT before enabling KVM\n");
Shane Wangcafd6652010-04-29 12:09:01 -04003499 return 1;
Shane Wangf9335af2010-11-17 11:40:17 +08003500 }
Joseph Cihula23f3e992011-02-08 11:45:56 -08003501 /* launched w/o TXT and VMX disabled */
3502 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3503 && !tboot_enabled())
3504 return 1;
Shane Wangcafd6652010-04-29 12:09:01 -04003505 }
3506
3507 return 0;
Avi Kivity6aa8b732006-12-10 02:21:36 -08003508}
3509
Dongxiao Xu7725b892010-05-11 18:29:38 +08003510static void kvm_cpu_vmxon(u64 addr)
3511{
Alexander Shishkin1c5ac212016-03-29 17:43:10 +03003512 intel_pt_handle_vmx(1);
3513
Dongxiao Xu7725b892010-05-11 18:29:38 +08003514 asm volatile (ASM_VMX_VMXON_RAX
3515 : : "a"(&addr), "m"(addr)
3516 : "memory", "cc");
3517}
3518
Radim Krčmář13a34e02014-08-28 15:13:03 +02003519static int hardware_enable(void)
Avi Kivity6aa8b732006-12-10 02:21:36 -08003520{
3521 int cpu = raw_smp_processor_id();
3522 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
Shane Wangcafd6652010-04-29 12:09:01 -04003523 u64 old, test_bits;
Avi Kivity6aa8b732006-12-10 02:21:36 -08003524
Andy Lutomirski1e02ce42014-10-24 15:58:08 -07003525 if (cr4_read_shadow() & X86_CR4_VMXE)
Alexander Graf10474ae2009-09-15 11:37:46 +02003526 return -EBUSY;
3527
Nadav Har'Eld462b812011-05-24 15:26:10 +03003528 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
Feng Wubf9f6ac2015-09-18 22:29:55 +08003529 INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
3530 spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
Zhang Yanfei8f536b72012-12-06 23:43:34 +08003531
3532 /*
3533 * Now we can enable the vmclear operation in kdump
3534 * since the loaded_vmcss_on_cpu list on this cpu
3535 * has been initialized.
3536 *
3537 * Though the cpu is not in VMX operation now, there
3538 * is no problem to enable the vmclear operation
3539 * for the loaded_vmcss_on_cpu list is empty!
3540 */
3541 crash_enable_local_vmclear(cpu);
3542
Avi Kivity6aa8b732006-12-10 02:21:36 -08003543 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
Shane Wangcafd6652010-04-29 12:09:01 -04003544
3545 test_bits = FEATURE_CONTROL_LOCKED;
3546 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
3547 if (tboot_enabled())
3548 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
3549
3550 if ((old & test_bits) != test_bits) {
Avi Kivity6aa8b732006-12-10 02:21:36 -08003551 /* enable and lock */
Shane Wangcafd6652010-04-29 12:09:01 -04003552 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
3553 }
Andy Lutomirski375074c2014-10-24 15:58:07 -07003554 cr4_set_bits(X86_CR4_VMXE);
Alexander Graf10474ae2009-09-15 11:37:46 +02003555
Dongxiao Xu4610c9c2010-05-11 18:29:48 +08003556 if (vmm_exclusive) {
3557 kvm_cpu_vmxon(phys_addr);
3558 ept_sync_global();
3559 }
Alexander Graf10474ae2009-09-15 11:37:46 +02003560
Christoph Lameter89cbc762014-08-17 12:30:40 -05003561 native_store_gdt(this_cpu_ptr(&host_gdt));
Avi Kivity3444d7d2010-07-26 18:32:38 +03003562
Alexander Graf10474ae2009-09-15 11:37:46 +02003563 return 0;
Avi Kivity6aa8b732006-12-10 02:21:36 -08003564}
3565
Nadav Har'Eld462b812011-05-24 15:26:10 +03003566static void vmclear_local_loaded_vmcss(void)
Avi Kivity543e4242008-05-13 16:22:47 +03003567{
3568 int cpu = raw_smp_processor_id();
Nadav Har'Eld462b812011-05-24 15:26:10 +03003569 struct loaded_vmcs *v, *n;
Avi Kivity543e4242008-05-13 16:22:47 +03003570
Nadav Har'Eld462b812011-05-24 15:26:10 +03003571 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
3572 loaded_vmcss_on_cpu_link)
3573 __loaded_vmcs_clear(v);
Avi Kivity543e4242008-05-13 16:22:47 +03003574}
3575
Eduardo Habkost710ff4a2008-11-17 19:03:18 -02003576
3577/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3578 * tricks.
3579 */
3580static void kvm_cpu_vmxoff(void)
3581{
3582 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
Alexander Shishkin1c5ac212016-03-29 17:43:10 +03003583
3584 intel_pt_handle_vmx(0);
Eduardo Habkost710ff4a2008-11-17 19:03:18 -02003585}
3586
Radim Krčmář13a34e02014-08-28 15:13:03 +02003587static void hardware_disable(void)
Avi Kivity6aa8b732006-12-10 02:21:36 -08003588{
Dongxiao Xu4610c9c2010-05-11 18:29:48 +08003589 if (vmm_exclusive) {
Nadav Har'Eld462b812011-05-24 15:26:10 +03003590 vmclear_local_loaded_vmcss();
Dongxiao Xu4610c9c2010-05-11 18:29:48 +08003591 kvm_cpu_vmxoff();
3592 }
Andy Lutomirski375074c2014-10-24 15:58:07 -07003593 cr4_clear_bits(X86_CR4_VMXE);
Avi Kivity6aa8b732006-12-10 02:21:36 -08003594}
3595
Yang, Sheng1c3d14fe2007-07-29 11:07:42 +03003596static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
Mike Dayd77c26f2007-10-08 09:02:08 -04003597 u32 msr, u32 *result)
Avi Kivity6aa8b732006-12-10 02:21:36 -08003598{
3599 u32 vmx_msr_low, vmx_msr_high;
Yang, Sheng1c3d14fe2007-07-29 11:07:42 +03003600 u32 ctl = ctl_min | ctl_opt;
3601
3602 rdmsr(msr, vmx_msr_low, vmx_msr_high);
3603
3604 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
3605 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
3606
3607 /* Ensure minimum (required) set of control bits are supported. */
3608 if (ctl_min & ~ctl)
Yang, Sheng002c7f72007-07-31 14:23:01 +03003609 return -EIO;
Yang, Sheng1c3d14fe2007-07-29 11:07:42 +03003610
3611 *result = ctl;
3612 return 0;
3613}
3614
Avi Kivity110312c2010-12-21 12:54:20 +02003615static __init bool allow_1_setting(u32 msr, u32 ctl)
3616{
3617 u32 vmx_msr_low, vmx_msr_high;
3618
3619 rdmsr(msr, vmx_msr_low, vmx_msr_high);
3620 return vmx_msr_high & ctl;
3621}
3622
Yang, Sheng002c7f72007-07-31 14:23:01 +03003623static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
Yang, Sheng1c3d14fe2007-07-29 11:07:42 +03003624{
3625 u32 vmx_msr_low, vmx_msr_high;
Sheng Yangd56f5462008-04-25 10:13:16 +08003626 u32 min, opt, min2, opt2;
Yang, Sheng1c3d14fe2007-07-29 11:07:42 +03003627 u32 _pin_based_exec_control = 0;
3628 u32 _cpu_based_exec_control = 0;
Sheng Yangf78e0e22007-10-29 09:40:42 +08003629 u32 _cpu_based_2nd_exec_control = 0;
Yang, Sheng1c3d14fe2007-07-29 11:07:42 +03003630 u32 _vmexit_control = 0;
3631 u32 _vmentry_control = 0;
3632
Raghavendra K T10166742012-02-07 23:19:20 +05303633 min = CPU_BASED_HLT_EXITING |
Yang, Sheng1c3d14fe2007-07-29 11:07:42 +03003634#ifdef CONFIG_X86_64
3635 CPU_BASED_CR8_LOAD_EXITING |
3636 CPU_BASED_CR8_STORE_EXITING |
3637#endif
Sheng Yangd56f5462008-04-25 10:13:16 +08003638 CPU_BASED_CR3_LOAD_EXITING |
3639 CPU_BASED_CR3_STORE_EXITING |
Yang, Sheng1c3d14fe2007-07-29 11:07:42 +03003640 CPU_BASED_USE_IO_BITMAPS |
3641 CPU_BASED_MOV_DR_EXITING |
Marcelo Tosattia7052892008-09-23 13:18:35 -03003642 CPU_BASED_USE_TSC_OFFSETING |
Sheng Yang59708672009-12-15 13:29:54 +08003643 CPU_BASED_MWAIT_EXITING |
3644 CPU_BASED_MONITOR_EXITING |
Avi Kivityfee84b02011-11-10 14:57:25 +02003645 CPU_BASED_INVLPG_EXITING |
3646 CPU_BASED_RDPMC_EXITING;
Anthony Liguori443381a2010-12-06 10:53:38 -06003647
Sheng Yangf78e0e22007-10-29 09:40:42 +08003648 opt = CPU_BASED_TPR_SHADOW |
Sheng Yang25c5f222008-03-28 13:18:56 +08003649 CPU_BASED_USE_MSR_BITMAPS |
Sheng Yangf78e0e22007-10-29 09:40:42 +08003650 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
Yang, Sheng1c3d14fe2007-07-29 11:07:42 +03003651 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
3652 &_cpu_based_exec_control) < 0)
Yang, Sheng002c7f72007-07-31 14:23:01 +03003653 return -EIO;
Yang, Sheng6e5d8652007-09-12 18:03:11 +08003654#ifdef CONFIG_X86_64
3655 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3656 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
3657 ~CPU_BASED_CR8_STORE_EXITING;
3658#endif
Sheng Yangf78e0e22007-10-29 09:40:42 +08003659 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
Sheng Yangd56f5462008-04-25 10:13:16 +08003660 min2 = 0;
3661 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
Yang Zhang8d146952013-01-25 10:18:50 +08003662 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
Sheng Yang2384d2b2008-01-17 15:14:33 +08003663 SECONDARY_EXEC_WBINVD_EXITING |
Sheng Yangd56f5462008-04-25 10:13:16 +08003664 SECONDARY_EXEC_ENABLE_VPID |
Nitin A Kamble3a624e22009-06-08 11:34:16 -07003665 SECONDARY_EXEC_ENABLE_EPT |
Zhai, Edwin4b8d54f2009-10-09 18:03:20 +08003666 SECONDARY_EXEC_UNRESTRICTED_GUEST |
Sheng Yang4e47c7a2009-12-18 16:48:47 +08003667 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
Mao, Junjiead756a12012-07-02 01:18:48 +00003668 SECONDARY_EXEC_RDTSCP |
Yang Zhang83d4c282013-01-25 10:18:49 +08003669 SECONDARY_EXEC_ENABLE_INVPCID |
Yang Zhangc7c9c562013-01-25 10:18:51 +08003670 SECONDARY_EXEC_APIC_REGISTER_VIRT |
Abel Gordonabc4fc52013-04-18 14:35:25 +03003671 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
Wanpeng Li20300092014-12-02 19:14:59 +08003672 SECONDARY_EXEC_SHADOW_VMCS |
Kai Huang843e4332015-01-28 10:54:28 +08003673 SECONDARY_EXEC_XSAVES |
Xiao Guangrong8b3e34e2015-09-09 14:05:51 +08003674 SECONDARY_EXEC_ENABLE_PML |
Haozhong Zhang64903d62015-10-20 15:39:09 +08003675 SECONDARY_EXEC_TSC_SCALING;
Sheng Yangd56f5462008-04-25 10:13:16 +08003676 if (adjust_vmx_controls(min2, opt2,
3677 MSR_IA32_VMX_PROCBASED_CTLS2,
Sheng Yangf78e0e22007-10-29 09:40:42 +08003678 &_cpu_based_2nd_exec_control) < 0)
3679 return -EIO;
3680 }
3681#ifndef CONFIG_X86_64
3682 if (!(_cpu_based_2nd_exec_control &
3683 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
3684 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
3685#endif
Yang Zhang83d4c282013-01-25 10:18:49 +08003686
3687 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3688 _cpu_based_2nd_exec_control &= ~(
Yang Zhang8d146952013-01-25 10:18:50 +08003689 SECONDARY_EXEC_APIC_REGISTER_VIRT |
Yang Zhangc7c9c562013-01-25 10:18:51 +08003690 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3691 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
Yang Zhang83d4c282013-01-25 10:18:49 +08003692
Sheng Yangd56f5462008-04-25 10:13:16 +08003693 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
Marcelo Tosattia7052892008-09-23 13:18:35 -03003694 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3695 enabled */
Gleb Natapov5fff7d22009-08-27 18:41:30 +03003696 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
3697 CPU_BASED_CR3_STORE_EXITING |
3698 CPU_BASED_INVLPG_EXITING);
Sheng Yangd56f5462008-04-25 10:13:16 +08003699 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
3700 vmx_capability.ept, vmx_capability.vpid);
3701 }
Yang, Sheng1c3d14fe2007-07-29 11:07:42 +03003702
Paolo Bonzini91fa0f82016-06-15 20:55:08 +02003703 min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
Yang, Sheng1c3d14fe2007-07-29 11:07:42 +03003704#ifdef CONFIG_X86_64
3705 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
3706#endif
Yang Zhanga547c6d2013-04-11 19:25:10 +08003707 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
Paolo Bonzini91fa0f82016-06-15 20:55:08 +02003708 VM_EXIT_CLEAR_BNDCFGS;
Yang, Sheng1c3d14fe2007-07-29 11:07:42 +03003709 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
3710 &_vmexit_control) < 0)
Yang, Sheng002c7f72007-07-31 14:23:01 +03003711 return -EIO;
Yang, Sheng1c3d14fe2007-07-29 11:07:42 +03003712
Yang Zhang01e439b2013-04-11 19:25:12 +08003713 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
Yunhong Jiang64672c92016-06-13 14:19:59 -07003714 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR |
3715 PIN_BASED_VMX_PREEMPTION_TIMER;
Yang Zhang01e439b2013-04-11 19:25:12 +08003716 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
3717 &_pin_based_exec_control) < 0)
3718 return -EIO;
3719
Paolo Bonzini1c17c3e2016-07-08 11:53:38 +02003720 if (cpu_has_broken_vmx_preemption_timer())
3721 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
Yang Zhang01e439b2013-04-11 19:25:12 +08003722 if (!(_cpu_based_2nd_exec_control &
Paolo Bonzini91fa0f82016-06-15 20:55:08 +02003723 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
Yang Zhang01e439b2013-04-11 19:25:12 +08003724 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
3725
Paolo Bonzinic845f9c2014-02-21 10:55:44 +01003726 min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
Liu, Jinsongda8999d2014-02-24 10:55:46 +00003727 opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
Yang, Sheng1c3d14fe2007-07-29 11:07:42 +03003728 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
3729 &_vmentry_control) < 0)
Yang, Sheng002c7f72007-07-31 14:23:01 +03003730 return -EIO;
Avi Kivity6aa8b732006-12-10 02:21:36 -08003731
Nguyen Anh Quynhc68876f2006-12-29 16:49:54 -08003732 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
Yang, Sheng1c3d14fe2007-07-29 11:07:42 +03003733
3734 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3735 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
Yang, Sheng002c7f72007-07-31 14:23:01 +03003736 return -EIO;
Yang, Sheng1c3d14fe2007-07-29 11:07:42 +03003737
3738#ifdef CONFIG_X86_64
3739 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3740 if (vmx_msr_high & (1u<<16))
Yang, Sheng002c7f72007-07-31 14:23:01 +03003741 return -EIO;
Yang, Sheng1c3d14fe2007-07-29 11:07:42 +03003742#endif
3743
3744 /* Require Write-Back (WB) memory type for VMCS accesses. */
3745 if (((vmx_msr_high >> 18) & 15) != 6)
Yang, Sheng002c7f72007-07-31 14:23:01 +03003746 return -EIO;
Yang, Sheng1c3d14fe2007-07-29 11:07:42 +03003747
Yang, Sheng002c7f72007-07-31 14:23:01 +03003748 vmcs_conf->size = vmx_msr_high & 0x1fff;
Paolo Bonzini16cb0252016-09-05 15:57:00 +02003749 vmcs_conf->order = get_order(vmcs_conf->size);
Jan Dakinevich9ac7e3e2016-09-04 21:23:15 +03003750 vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
Yang, Sheng002c7f72007-07-31 14:23:01 +03003751 vmcs_conf->revision_id = vmx_msr_low;
Yang, Sheng1c3d14fe2007-07-29 11:07:42 +03003752
Yang, Sheng002c7f72007-07-31 14:23:01 +03003753 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
3754 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
Sheng Yangf78e0e22007-10-29 09:40:42 +08003755 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
Yang, Sheng002c7f72007-07-31 14:23:01 +03003756 vmcs_conf->vmexit_ctrl = _vmexit_control;
3757 vmcs_conf->vmentry_ctrl = _vmentry_control;
Yang, Sheng1c3d14fe2007-07-29 11:07:42 +03003758
Avi Kivity110312c2010-12-21 12:54:20 +02003759 cpu_has_load_ia32_efer =
3760 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3761 VM_ENTRY_LOAD_IA32_EFER)
3762 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3763 VM_EXIT_LOAD_IA32_EFER);
3764
Gleb Natapov8bf00a52011-10-05 14:01:22 +02003765 cpu_has_load_perf_global_ctrl =
3766 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3767 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
3768 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3769 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
3770
3771 /*
3772 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
Andrea Gelminibb3541f2016-05-21 14:14:44 +02003773 * but due to errata below it can't be used. Workaround is to use
Gleb Natapov8bf00a52011-10-05 14:01:22 +02003774 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3775 *
3776 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3777 *
3778 * AAK155 (model 26)
3779 * AAP115 (model 30)
3780 * AAT100 (model 37)
3781 * BC86,AAY89,BD102 (model 44)
3782 * BA97 (model 46)
3783 *
3784 */
3785 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3786 switch (boot_cpu_data.x86_model) {
3787 case 26:
3788 case 30:
3789 case 37:
3790 case 44:
3791 case 46:
3792 cpu_has_load_perf_global_ctrl = false;
3793 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3794 "does not work properly. Using workaround\n");
3795 break;
3796 default:
3797 break;
3798 }
3799 }
3800
Borislav Petkov782511b2016-04-04 22:25:03 +02003801 if (boot_cpu_has(X86_FEATURE_XSAVES))
Wanpeng Li20300092014-12-02 19:14:59 +08003802 rdmsrl(MSR_IA32_XSS, host_xss);
3803
Yang, Sheng1c3d14fe2007-07-29 11:07:42 +03003804 return 0;
Nguyen Anh Quynhc68876f2006-12-29 16:49:54 -08003805}
Avi Kivity6aa8b732006-12-10 02:21:36 -08003806
3807static struct vmcs *alloc_vmcs_cpu(int cpu)
3808{
3809 int node = cpu_to_node(cpu);
3810 struct page *pages;
3811 struct vmcs *vmcs;
3812
Vlastimil Babka96db8002015-09-08 15:03:50 -07003813 pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
Avi Kivity6aa8b732006-12-10 02:21:36 -08003814 if (!pages)
3815 return NULL;
3816 vmcs = page_address(pages);
Yang, Sheng1c3d14fe2007-07-29 11:07:42 +03003817 memset(vmcs, 0, vmcs_config.size);
3818 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
Avi Kivity6aa8b732006-12-10 02:21:36 -08003819 return vmcs;
3820}
3821
Avi Kivity6aa8b732006-12-10 02:21:36 -08003822static void free_vmcs(struct vmcs *vmcs)
3823{
Yang, Sheng1c3d14fe2007-07-29 11:07:42 +03003824 free_pages((unsigned long)vmcs, vmcs_config.order);
Avi Kivity6aa8b732006-12-10 02:21:36 -08003825}
3826
Nadav Har'Eld462b812011-05-24 15:26:10 +03003827/*
3828 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3829 */
3830static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3831{
3832 if (!loaded_vmcs->vmcs)
3833 return;
3834 loaded_vmcs_clear(loaded_vmcs);
3835 free_vmcs(loaded_vmcs->vmcs);
3836 loaded_vmcs->vmcs = NULL;
Paolo Bonzini6236b782018-01-16 16:51:18 +01003837 if (loaded_vmcs->msr_bitmap)
3838 free_page((unsigned long)loaded_vmcs->msr_bitmap);
Jim Mattson355f4fb2016-10-28 08:29:39 -07003839 WARN_ON(loaded_vmcs->shadow_vmcs != NULL);
Nadav Har'Eld462b812011-05-24 15:26:10 +03003840}
3841
Paolo Bonziniff546f92018-01-11 12:16:15 +01003842static struct vmcs *alloc_vmcs(void)
3843{
3844 return alloc_vmcs_cpu(raw_smp_processor_id());
3845}
3846
3847static int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3848{
3849 loaded_vmcs->vmcs = alloc_vmcs();
3850 if (!loaded_vmcs->vmcs)
3851 return -ENOMEM;
3852
3853 loaded_vmcs->shadow_vmcs = NULL;
3854 loaded_vmcs_init(loaded_vmcs);
Paolo Bonzini6236b782018-01-16 16:51:18 +01003855
3856 if (cpu_has_vmx_msr_bitmap()) {
3857 loaded_vmcs->msr_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
3858 if (!loaded_vmcs->msr_bitmap)
3859 goto out_vmcs;
3860 memset(loaded_vmcs->msr_bitmap, 0xff, PAGE_SIZE);
3861 }
Paolo Bonziniff546f92018-01-11 12:16:15 +01003862 return 0;
Paolo Bonzini6236b782018-01-16 16:51:18 +01003863
3864out_vmcs:
3865 free_loaded_vmcs(loaded_vmcs);
3866 return -ENOMEM;
Paolo Bonziniff546f92018-01-11 12:16:15 +01003867}
3868
Sam Ravnborg39959582007-06-01 00:47:13 -07003869static void free_kvm_area(void)
Avi Kivity6aa8b732006-12-10 02:21:36 -08003870{
3871 int cpu;
3872
Zachary Amsden3230bb42009-09-29 11:38:37 -10003873 for_each_possible_cpu(cpu) {
Avi Kivity6aa8b732006-12-10 02:21:36 -08003874 free_vmcs(per_cpu(vmxarea, cpu));
Zachary Amsden3230bb42009-09-29 11:38:37 -10003875 per_cpu(vmxarea, cpu) = NULL;
3876 }
Avi Kivity6aa8b732006-12-10 02:21:36 -08003877}
3878
Bandan Dasfe2b2012014-04-21 15:20:14 -04003879static void init_vmcs_shadow_fields(void)
3880{
3881 int i, j;
3882
3883 /* No checks for read only fields yet */
3884
3885 for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3886 switch (shadow_read_write_fields[i]) {
3887 case GUEST_BNDCFGS:
Paolo Bonzinia87036a2016-03-08 09:52:13 +01003888 if (!kvm_mpx_supported())
Bandan Dasfe2b2012014-04-21 15:20:14 -04003889 continue;
3890 break;
3891 default:
3892 break;
3893 }
3894
3895 if (j < i)
3896 shadow_read_write_fields[j] =
3897 shadow_read_write_fields[i];
3898 j++;
3899 }
3900 max_shadow_read_write_fields = j;
3901
3902 /* shadowed fields guest access without vmexit */
3903 for (i = 0; i < max_shadow_read_write_fields; i++) {
3904 clear_bit(shadow_read_write_fields[i],
3905 vmx_vmwrite_bitmap);
3906 clear_bit(shadow_read_write_fields[i],
3907 vmx_vmread_bitmap);
3908 }
3909 for (i = 0; i < max_shadow_read_only_fields; i++)
3910 clear_bit(shadow_read_only_fields[i],
3911 vmx_vmread_bitmap);
3912}
3913
Avi Kivity6aa8b732006-12-10 02:21:36 -08003914static __init int alloc_kvm_area(void)
3915{
3916 int cpu;
3917
Zachary Amsden3230bb42009-09-29 11:38:37 -10003918 for_each_possible_cpu(cpu) {
Avi Kivity6aa8b732006-12-10 02:21:36 -08003919 struct vmcs *vmcs;
3920
3921 vmcs = alloc_vmcs_cpu(cpu);
3922 if (!vmcs) {
3923 free_kvm_area();
3924 return -ENOMEM;
3925 }
3926
3927 per_cpu(vmxarea, cpu) = vmcs;
3928 }
3929 return 0;
3930}
3931
Gleb Natapov14168782013-01-21 15:36:49 +02003932static bool emulation_required(struct kvm_vcpu *vcpu)
3933{
3934 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3935}
3936
Gleb Natapov91b0aa22013-01-21 15:36:47 +02003937static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
Gleb Natapovd99e4152012-12-20 16:57:45 +02003938 struct kvm_segment *save)
Avi Kivity6aa8b732006-12-10 02:21:36 -08003939{
Gleb Natapovd99e4152012-12-20 16:57:45 +02003940 if (!emulate_invalid_guest_state) {
3941 /*
3942 * CS and SS RPL should be equal during guest entry according
3943 * to VMX spec, but in reality it is not always so. Since vcpu
3944 * is in the middle of the transition from real mode to
3945 * protected mode it is safe to assume that RPL 0 is a good
3946 * default value.
3947 */
3948 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
Nadav Amitb32a9912015-03-29 16:33:04 +03003949 save->selector &= ~SEGMENT_RPL_MASK;
3950 save->dpl = save->selector & SEGMENT_RPL_MASK;
Gleb Natapovd99e4152012-12-20 16:57:45 +02003951 save->s = 1;
Avi Kivity6aa8b732006-12-10 02:21:36 -08003952 }
Gleb Natapovd99e4152012-12-20 16:57:45 +02003953 vmx_set_segment(vcpu, save, seg);
Avi Kivity6aa8b732006-12-10 02:21:36 -08003954}
3955
3956static void enter_pmode(struct kvm_vcpu *vcpu)
3957{
3958 unsigned long flags;
Mohammed Gamala89a8fb2008-08-17 16:42:16 +03003959 struct vcpu_vmx *vmx = to_vmx(vcpu);
Avi Kivity6aa8b732006-12-10 02:21:36 -08003960
Gleb Natapovd99e4152012-12-20 16:57:45 +02003961 /*
3962 * Update real mode segment cache. It may be not up-to-date if sement
3963 * register was written while vcpu was in a guest mode.
3964 */
3965 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3966 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3967 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3968 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3969 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3970 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3971
Avi Kivity7ffd92c2009-06-09 14:10:45 +03003972 vmx->rmode.vm86_active = 0;
Avi Kivity6aa8b732006-12-10 02:21:36 -08003973
Avi Kivity2fb92db2011-04-27 19:42:18 +03003974 vmx_segment_cache_clear(vmx);
3975
Avi Kivityf5f7b2f2012-08-21 17:07:00 +03003976 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
Avi Kivity6aa8b732006-12-10 02:21:36 -08003977
3978 flags = vmcs_readl(GUEST_RFLAGS);
Avi Kivity78ac8b42010-04-08 18:19:35 +03003979 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3980 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
Avi Kivity6aa8b732006-12-10 02:21:36 -08003981 vmcs_writel(GUEST_RFLAGS, flags);
3982
Rusty Russell66aee912007-07-17 23:34:16 +10003983 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3984 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
Avi Kivity6aa8b732006-12-10 02:21:36 -08003985
3986 update_exception_bitmap(vcpu);
3987
Gleb Natapov91b0aa22013-01-21 15:36:47 +02003988 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3989 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3990 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3991 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3992 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3993 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
Avi Kivity6aa8b732006-12-10 02:21:36 -08003994}
3995
Avi Kivityf5f7b2f2012-08-21 17:07:00 +03003996static void fix_rmode_seg(int seg, struct kvm_segment *save)
Avi Kivity6aa8b732006-12-10 02:21:36 -08003997{
Mathias Krause772e0312012-08-30 01:30:19 +02003998 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
Gleb Natapovd99e4152012-12-20 16:57:45 +02003999 struct kvm_segment var = *save;
Avi Kivity6aa8b732006-12-10 02:21:36 -08004000
Gleb Natapovd99e4152012-12-20 16:57:45 +02004001 var.dpl = 0x3;
4002 if (seg == VCPU_SREG_CS)
4003 var.type = 0x3;
4004
4005 if (!emulate_invalid_guest_state) {
4006 var.selector = var.base >> 4;
4007 var.base = var.base & 0xffff0;
4008 var.limit = 0xffff;
4009 var.g = 0;
4010 var.db = 0;
4011 var.present = 1;
4012 var.s = 1;
4013 var.l = 0;
4014 var.unusable = 0;
4015 var.type = 0x3;
4016 var.avl = 0;
4017 if (save->base & 0xf)
4018 printk_once(KERN_WARNING "kvm: segment base is not "
4019 "paragraph aligned when entering "
4020 "protected mode (seg=%d)", seg);
4021 }
4022
4023 vmcs_write16(sf->selector, var.selector);
Chao Peng7c3bab12017-02-21 03:50:01 -05004024 vmcs_writel(sf->base, var.base);
Gleb Natapovd99e4152012-12-20 16:57:45 +02004025 vmcs_write32(sf->limit, var.limit);
4026 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
Avi Kivity6aa8b732006-12-10 02:21:36 -08004027}
4028
4029static void enter_rmode(struct kvm_vcpu *vcpu)
4030{
4031 unsigned long flags;
Mohammed Gamala89a8fb2008-08-17 16:42:16 +03004032 struct vcpu_vmx *vmx = to_vmx(vcpu);
Avi Kivity6aa8b732006-12-10 02:21:36 -08004033
Avi Kivityf5f7b2f2012-08-21 17:07:00 +03004034 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
4035 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
4036 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
4037 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
4038 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
Gleb Natapovc6ad11532012-12-12 19:10:51 +02004039 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
4040 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
Avi Kivityf5f7b2f2012-08-21 17:07:00 +03004041
Avi Kivity7ffd92c2009-06-09 14:10:45 +03004042 vmx->rmode.vm86_active = 1;
Avi Kivity6aa8b732006-12-10 02:21:36 -08004043
Gleb Natapov776e58e2011-03-13 12:34:27 +02004044 /*
4045 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
Jan Kiszka4918c6c2013-03-15 08:38:56 +01004046 * vcpu. Warn the user that an update is overdue.
Gleb Natapov776e58e2011-03-13 12:34:27 +02004047 */
Jan Kiszka4918c6c2013-03-15 08:38:56 +01004048 if (!vcpu->kvm->arch.tss_addr)
Gleb Natapov776e58e2011-03-13 12:34:27 +02004049 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
4050 "called before entering vcpu\n");
Gleb Natapov776e58e2011-03-13 12:34:27 +02004051
Avi Kivity2fb92db2011-04-27 19:42:18 +03004052 vmx_segment_cache_clear(vmx);
4053
Jan Kiszka4918c6c2013-03-15 08:38:56 +01004054 vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
Avi Kivity6aa8b732006-12-10 02:21:36 -08004055 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
Avi Kivity6aa8b732006-12-10 02:21:36 -08004056 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4057
4058 flags = vmcs_readl(GUEST_RFLAGS);
Avi Kivity78ac8b42010-04-08 18:19:35 +03004059 vmx->rmode.save_rflags = flags;
Avi Kivity6aa8b732006-12-10 02:21:36 -08004060
Glauber de Oliveira Costa053de042008-01-30 13:31:27 +01004061 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
Avi Kivity6aa8b732006-12-10 02:21:36 -08004062
4063 vmcs_writel(GUEST_RFLAGS, flags);
Rusty Russell66aee912007-07-17 23:34:16 +10004064 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
Avi Kivity6aa8b732006-12-10 02:21:36 -08004065 update_exception_bitmap(vcpu);
4066
Gleb Natapovd99e4152012-12-20 16:57:45 +02004067 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
4068 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
4069 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
4070 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
4071 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
4072 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
Mohammed Gamala89a8fb2008-08-17 16:42:16 +03004073
Eddie Dong8668a3c2007-10-10 14:26:45 +08004074 kvm_mmu_reset_context(vcpu);
Avi Kivity6aa8b732006-12-10 02:21:36 -08004075}
4076
Amit Shah401d10d2009-02-20 22:53:37 +05304077static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
4078{
4079 struct vcpu_vmx *vmx = to_vmx(vcpu);
Avi Kivity26bb0982009-09-07 11:14:12 +03004080 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
4081
4082 if (!msr)
4083 return;
Amit Shah401d10d2009-02-20 22:53:37 +05304084
Avi Kivity44ea2b12009-09-06 15:55:37 +03004085 /*
4086 * Force kernel_gs_base reloading before EFER changes, as control
4087 * of this msr depends on is_long_mode().
4088 */
4089 vmx_load_host_state(to_vmx(vcpu));
Avi Kivityf6801df2010-01-21 15:31:50 +02004090 vcpu->arch.efer = efer;
Amit Shah401d10d2009-02-20 22:53:37 +05304091 if (efer & EFER_LMA) {
Gleb Natapov2961e8762013-11-25 15:37:13 +02004092 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
Amit Shah401d10d2009-02-20 22:53:37 +05304093 msr->data = efer;
4094 } else {
Gleb Natapov2961e8762013-11-25 15:37:13 +02004095 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
Amit Shah401d10d2009-02-20 22:53:37 +05304096
4097 msr->data = efer & ~EFER_LME;
4098 }
4099 setup_msrs(vmx);
4100}
4101
Avi Kivity05b3e0c2006-12-13 00:33:45 -08004102#ifdef CONFIG_X86_64
Avi Kivity6aa8b732006-12-10 02:21:36 -08004103
4104static void enter_lmode(struct kvm_vcpu *vcpu)
4105{
4106 u32 guest_tr_ar;
4107
Avi Kivity2fb92db2011-04-27 19:42:18 +03004108 vmx_segment_cache_clear(to_vmx(vcpu));
4109
Avi Kivity6aa8b732006-12-10 02:21:36 -08004110 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
Andy Lutomirski4d283ec2015-08-13 13:18:48 -07004111 if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
Jan Kiszkabd801582011-09-12 11:26:22 +02004112 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
4113 __func__);
Avi Kivity6aa8b732006-12-10 02:21:36 -08004114 vmcs_write32(GUEST_TR_AR_BYTES,
Andy Lutomirski4d283ec2015-08-13 13:18:48 -07004115 (guest_tr_ar & ~VMX_AR_TYPE_MASK)
4116 | VMX_AR_TYPE_BUSY_64_TSS);
Avi Kivity6aa8b732006-12-10 02:21:36 -08004117 }
Avi Kivityda38f432010-07-06 11:30:49 +03004118 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
Avi Kivity6aa8b732006-12-10 02:21:36 -08004119}
4120
4121static void exit_lmode(struct kvm_vcpu *vcpu)
4122{
Gleb Natapov2961e8762013-11-25 15:37:13 +02004123 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
Avi Kivityda38f432010-07-06 11:30:49 +03004124 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
Avi Kivity6aa8b732006-12-10 02:21:36 -08004125}
4126
4127#endif
4128
Wanpeng Lidd5f5342015-09-23 18:26:57 +08004129static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid)
Sheng Yang2384d2b2008-01-17 15:14:33 +08004130{
Wanpeng Lidd5f5342015-09-23 18:26:57 +08004131 vpid_sync_context(vpid);
Xiao Guangrongdd180b32010-07-03 16:02:42 +08004132 if (enable_ept) {
4133 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
4134 return;
Sheng Yang4e1096d2008-07-06 19:16:51 +08004135 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
Xiao Guangrongdd180b32010-07-03 16:02:42 +08004136 }
Sheng Yang2384d2b2008-01-17 15:14:33 +08004137}
4138
Wanpeng Lidd5f5342015-09-23 18:26:57 +08004139static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
4140{
4141 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid);
4142}
4143
Jim Mattson8386ff52017-03-16 13:53:59 -07004144static void vmx_flush_tlb_ept_only(struct kvm_vcpu *vcpu)
4145{
4146 if (enable_ept)
4147 vmx_flush_tlb(vcpu);
4148}
4149
Avi Kivitye8467fd2009-12-29 18:43:06 +02004150static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
4151{
4152 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
4153
4154 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
4155 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
4156}
4157
Avi Kivityaff48ba2010-12-05 18:56:11 +02004158static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
4159{
4160 if (enable_ept && is_paging(vcpu))
4161 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
4162 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
4163}
4164
Anthony Liguori25c4c272007-04-27 09:29:21 +03004165static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
Avi Kivity399badf2007-01-05 16:36:38 -08004166{
Avi Kivityfc78f512009-12-07 12:16:48 +02004167 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
4168
4169 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
4170 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
Avi Kivity399badf2007-01-05 16:36:38 -08004171}
4172
Sheng Yang14394422008-04-28 12:24:45 +08004173static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
4174{
Gleb Natapovd0d538b2013-10-09 19:13:19 +03004175 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
4176
Avi Kivity6de4f3a2009-05-31 22:58:47 +03004177 if (!test_bit(VCPU_EXREG_PDPTR,
4178 (unsigned long *)&vcpu->arch.regs_dirty))
4179 return;
4180
Sheng Yang14394422008-04-28 12:24:45 +08004181 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
Gleb Natapovd0d538b2013-10-09 19:13:19 +03004182 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
4183 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
4184 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
4185 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
Sheng Yang14394422008-04-28 12:24:45 +08004186 }
4187}
4188
Avi Kivity8f5d5492009-05-31 18:41:29 +03004189static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
4190{
Gleb Natapovd0d538b2013-10-09 19:13:19 +03004191 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
4192
Avi Kivity8f5d5492009-05-31 18:41:29 +03004193 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
Gleb Natapovd0d538b2013-10-09 19:13:19 +03004194 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
4195 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
4196 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
4197 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
Avi Kivity8f5d5492009-05-31 18:41:29 +03004198 }
Avi Kivity6de4f3a2009-05-31 22:58:47 +03004199
4200 __set_bit(VCPU_EXREG_PDPTR,
4201 (unsigned long *)&vcpu->arch.regs_avail);
4202 __set_bit(VCPU_EXREG_PDPTR,
4203 (unsigned long *)&vcpu->arch.regs_dirty);
Avi Kivity8f5d5492009-05-31 18:41:29 +03004204}
4205
Nadav Har'El5e1746d2011-05-25 23:03:24 +03004206static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
Sheng Yang14394422008-04-28 12:24:45 +08004207
4208static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
4209 unsigned long cr0,
4210 struct kvm_vcpu *vcpu)
4211{
Marcelo Tosatti5233dd52011-06-06 14:27:47 -03004212 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
4213 vmx_decache_cr3(vcpu);
Sheng Yang14394422008-04-28 12:24:45 +08004214 if (!(cr0 & X86_CR0_PG)) {
4215 /* From paging/starting to nonpaging */
4216 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
Sheng Yang65267ea2008-06-18 14:43:38 +08004217 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
Sheng Yang14394422008-04-28 12:24:45 +08004218 (CPU_BASED_CR3_LOAD_EXITING |
4219 CPU_BASED_CR3_STORE_EXITING));
4220 vcpu->arch.cr0 = cr0;
Avi Kivityfc78f512009-12-07 12:16:48 +02004221 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
Sheng Yang14394422008-04-28 12:24:45 +08004222 } else if (!is_paging(vcpu)) {
4223 /* From nonpaging to paging */
4224 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
Sheng Yang65267ea2008-06-18 14:43:38 +08004225 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
Sheng Yang14394422008-04-28 12:24:45 +08004226 ~(CPU_BASED_CR3_LOAD_EXITING |
4227 CPU_BASED_CR3_STORE_EXITING));
4228 vcpu->arch.cr0 = cr0;
Avi Kivityfc78f512009-12-07 12:16:48 +02004229 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
Sheng Yang14394422008-04-28 12:24:45 +08004230 }
Sheng Yang95eb84a2009-08-19 09:52:18 +08004231
4232 if (!(cr0 & X86_CR0_WP))
4233 *hw_cr0 &= ~X86_CR0_WP;
Sheng Yang14394422008-04-28 12:24:45 +08004234}
4235
Avi Kivity6aa8b732006-12-10 02:21:36 -08004236static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
4237{
Avi Kivity7ffd92c2009-06-09 14:10:45 +03004238 struct vcpu_vmx *vmx = to_vmx(vcpu);
Nitin A Kamble3a624e22009-06-08 11:34:16 -07004239 unsigned long hw_cr0;
4240
Gleb Natapov50378782013-02-04 16:00:28 +02004241 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
Nitin A Kamble3a624e22009-06-08 11:34:16 -07004242 if (enable_unrestricted_guest)
Gleb Natapov50378782013-02-04 16:00:28 +02004243 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
Gleb Natapov218e7632013-01-21 15:36:45 +02004244 else {
Gleb Natapov50378782013-02-04 16:00:28 +02004245 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
Sheng Yang14394422008-04-28 12:24:45 +08004246
Gleb Natapov218e7632013-01-21 15:36:45 +02004247 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
4248 enter_pmode(vcpu);
Avi Kivity6aa8b732006-12-10 02:21:36 -08004249
Gleb Natapov218e7632013-01-21 15:36:45 +02004250 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
4251 enter_rmode(vcpu);
4252 }
Avi Kivity6aa8b732006-12-10 02:21:36 -08004253
Avi Kivity05b3e0c2006-12-13 00:33:45 -08004254#ifdef CONFIG_X86_64
Avi Kivityf6801df2010-01-21 15:31:50 +02004255 if (vcpu->arch.efer & EFER_LME) {
Rusty Russell707d92fa2007-07-17 23:19:08 +10004256 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
Avi Kivity6aa8b732006-12-10 02:21:36 -08004257 enter_lmode(vcpu);
Rusty Russell707d92fa2007-07-17 23:19:08 +10004258 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
Avi Kivity6aa8b732006-12-10 02:21:36 -08004259 exit_lmode(vcpu);
4260 }
4261#endif
4262
Avi Kivity089d0342009-03-23 18:26:32 +02004263 if (enable_ept)
Sheng Yang14394422008-04-28 12:24:45 +08004264 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
4265
Avi Kivity02daab22009-12-30 12:40:26 +02004266 if (!vcpu->fpu_active)
Avi Kivity81231c62010-01-24 16:26:40 +02004267 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
Avi Kivity02daab22009-12-30 12:40:26 +02004268
Avi Kivity6aa8b732006-12-10 02:21:36 -08004269 vmcs_writel(CR0_READ_SHADOW, cr0);
Sheng Yang14394422008-04-28 12:24:45 +08004270 vmcs_writel(GUEST_CR0, hw_cr0);
Zhang Xiantaoad312c72007-12-13 23:50:52 +08004271 vcpu->arch.cr0 = cr0;
Gleb Natapov14168782013-01-21 15:36:49 +02004272
4273 /* depends on vcpu->arch.cr0 to be set to a new value */
4274 vmx->emulation_required = emulation_required(vcpu);
Avi Kivity6aa8b732006-12-10 02:21:36 -08004275}
4276
Sheng Yang14394422008-04-28 12:24:45 +08004277static u64 construct_eptp(unsigned long root_hpa)
4278{
4279 u64 eptp;
4280
4281 /* TODO write the value reading from MSR */
4282 eptp = VMX_EPT_DEFAULT_MT |
4283 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
Xudong Haob38f9932012-05-28 19:33:36 +08004284 if (enable_ept_ad_bits)
4285 eptp |= VMX_EPT_AD_ENABLE_BIT;
Sheng Yang14394422008-04-28 12:24:45 +08004286 eptp |= (root_hpa & PAGE_MASK);
4287
4288 return eptp;
4289}
4290
Avi Kivity6aa8b732006-12-10 02:21:36 -08004291static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
4292{
Sheng Yang14394422008-04-28 12:24:45 +08004293 unsigned long guest_cr3;
4294 u64 eptp;
4295
4296 guest_cr3 = cr3;
Avi Kivity089d0342009-03-23 18:26:32 +02004297 if (enable_ept) {
Sheng Yang14394422008-04-28 12:24:45 +08004298 eptp = construct_eptp(cr3);
4299 vmcs_write64(EPT_POINTER, eptp);
Jan Kiszka59ab5a82013-08-08 16:26:29 +02004300 if (is_paging(vcpu) || is_guest_mode(vcpu))
4301 guest_cr3 = kvm_read_cr3(vcpu);
4302 else
4303 guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
Marcelo Tosatti7c93be42009-10-26 16:48:33 -02004304 ept_load_pdptrs(vcpu);
Sheng Yang14394422008-04-28 12:24:45 +08004305 }
4306
Sheng Yang2384d2b2008-01-17 15:14:33 +08004307 vmx_flush_tlb(vcpu);
Sheng Yang14394422008-04-28 12:24:45 +08004308 vmcs_writel(GUEST_CR3, guest_cr3);
Avi Kivity6aa8b732006-12-10 02:21:36 -08004309}
4310
Nadav Har'El5e1746d2011-05-25 23:03:24 +03004311static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
Avi Kivity6aa8b732006-12-10 02:21:36 -08004312{
Ben Serebrin085e68e2015-04-16 11:58:05 -07004313 /*
4314 * Pass through host's Machine Check Enable value to hw_cr4, which
4315 * is in force while we are in guest mode. Do not let guests control
4316 * this bit, even if host CR4.MCE == 0.
4317 */
4318 unsigned long hw_cr4 =
4319 (cr4_read_shadow() & X86_CR4_MCE) |
4320 (cr4 & ~X86_CR4_MCE) |
4321 (to_vmx(vcpu)->rmode.vm86_active ?
4322 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
Sheng Yang14394422008-04-28 12:24:45 +08004323
Nadav Har'El5e1746d2011-05-25 23:03:24 +03004324 if (cr4 & X86_CR4_VMXE) {
4325 /*
4326 * To use VMXON (and later other VMX instructions), a guest
4327 * must first be able to turn on cr4.VMXE (see handle_vmon()).
4328 * So basically the check on whether to allow nested VMX
4329 * is here.
4330 */
4331 if (!nested_vmx_allowed(vcpu))
4332 return 1;
Jan Kiszka1a0d74e2013-03-07 14:08:07 +01004333 }
4334 if (to_vmx(vcpu)->nested.vmxon &&
4335 ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
Nadav Har'El5e1746d2011-05-25 23:03:24 +03004336 return 1;
4337
Zhang Xiantaoad312c72007-12-13 23:50:52 +08004338 vcpu->arch.cr4 = cr4;
Avi Kivitybc230082009-12-08 12:14:42 +02004339 if (enable_ept) {
4340 if (!is_paging(vcpu)) {
4341 hw_cr4 &= ~X86_CR4_PAE;
4342 hw_cr4 |= X86_CR4_PSE;
4343 } else if (!(cr4 & X86_CR4_PAE)) {
4344 hw_cr4 &= ~X86_CR4_PAE;
4345 }
4346 }
Sheng Yang14394422008-04-28 12:24:45 +08004347
Radim Krčmář656ec4a2015-11-02 22:20:00 +01004348 if (!enable_unrestricted_guest && !is_paging(vcpu))
4349 /*
Huaitong Handdba2622016-03-22 16:51:15 +08004350 * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
4351 * hardware. To emulate this behavior, SMEP/SMAP/PKU needs
4352 * to be manually disabled when guest switches to non-paging
4353 * mode.
4354 *
4355 * If !enable_unrestricted_guest, the CPU is always running
4356 * with CR0.PG=1 and CR4 needs to be modified.
4357 * If enable_unrestricted_guest, the CPU automatically
4358 * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
Radim Krčmář656ec4a2015-11-02 22:20:00 +01004359 */
Huaitong Handdba2622016-03-22 16:51:15 +08004360 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
Radim Krčmář656ec4a2015-11-02 22:20:00 +01004361
Sheng Yang14394422008-04-28 12:24:45 +08004362 vmcs_writel(CR4_READ_SHADOW, cr4);
4363 vmcs_writel(GUEST_CR4, hw_cr4);
Nadav Har'El5e1746d2011-05-25 23:03:24 +03004364 return 0;
Avi Kivity6aa8b732006-12-10 02:21:36 -08004365}
4366
Avi Kivity6aa8b732006-12-10 02:21:36 -08004367static void vmx_get_segment(struct kvm_vcpu *vcpu,
4368 struct kvm_segment *var, int seg)
4369{
Avi Kivitya9179492011-01-03 14:28:52 +02004370 struct vcpu_vmx *vmx = to_vmx(vcpu);
Avi Kivity6aa8b732006-12-10 02:21:36 -08004371 u32 ar;
4372
Gleb Natapovc6ad11532012-12-12 19:10:51 +02004373 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
Avi Kivityf5f7b2f2012-08-21 17:07:00 +03004374 *var = vmx->rmode.segs[seg];
Avi Kivitya9179492011-01-03 14:28:52 +02004375 if (seg == VCPU_SREG_TR
Avi Kivity2fb92db2011-04-27 19:42:18 +03004376 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
Avi Kivityf5f7b2f2012-08-21 17:07:00 +03004377 return;
Avi Kivity1390a282012-08-21 17:07:08 +03004378 var->base = vmx_read_guest_seg_base(vmx, seg);
4379 var->selector = vmx_read_guest_seg_selector(vmx, seg);
4380 return;
Avi Kivitya9179492011-01-03 14:28:52 +02004381 }
Avi Kivity2fb92db2011-04-27 19:42:18 +03004382 var->base = vmx_read_guest_seg_base(vmx, seg);
4383 var->limit = vmx_read_guest_seg_limit(vmx, seg);
4384 var->selector = vmx_read_guest_seg_selector(vmx, seg);
4385 ar = vmx_read_guest_seg_ar(vmx, seg);
Gleb Natapov03617c12013-06-28 13:17:18 +03004386 var->unusable = (ar >> 16) & 1;
Avi Kivity6aa8b732006-12-10 02:21:36 -08004387 var->type = ar & 15;
4388 var->s = (ar >> 4) & 1;
4389 var->dpl = (ar >> 5) & 3;
Gleb Natapov03617c12013-06-28 13:17:18 +03004390 /*
4391 * Some userspaces do not preserve unusable property. Since usable
4392 * segment has to be present according to VMX spec we can use present
4393 * property to amend userspace bug by making unusable segment always
4394 * nonpresent. vmx_segment_access_rights() already marks nonpresent
4395 * segment as unusable.
4396 */
4397 var->present = !var->unusable;
Avi Kivity6aa8b732006-12-10 02:21:36 -08004398 var->avl = (ar >> 12) & 1;
4399 var->l = (ar >> 13) & 1;
4400 var->db = (ar >> 14) & 1;
4401 var->g = (ar >> 15) & 1;
Avi Kivity6aa8b732006-12-10 02:21:36 -08004402}
4403
Avi Kivitya9179492011-01-03 14:28:52 +02004404static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
4405{
Avi Kivitya9179492011-01-03 14:28:52 +02004406 struct kvm_segment s;
4407
4408 if (to_vmx(vcpu)->rmode.vm86_active) {
4409 vmx_get_segment(vcpu, &s, seg);
4410 return s.base;
4411 }
Avi Kivity2fb92db2011-04-27 19:42:18 +03004412 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
Avi Kivitya9179492011-01-03 14:28:52 +02004413}
4414
Marcelo Tosattib09408d2013-01-07 19:27:06 -02004415static int vmx_get_cpl(struct kvm_vcpu *vcpu)
Izik Eidus2e4d2652008-03-24 19:38:34 +02004416{
Marcelo Tosattib09408d2013-01-07 19:27:06 -02004417 struct vcpu_vmx *vmx = to_vmx(vcpu);
4418
Paolo Bonziniae9fedc2014-05-14 09:39:49 +02004419 if (unlikely(vmx->rmode.vm86_active))
Izik Eidus2e4d2652008-03-24 19:38:34 +02004420 return 0;
Paolo Bonziniae9fedc2014-05-14 09:39:49 +02004421 else {
4422 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
Andy Lutomirski4d283ec2015-08-13 13:18:48 -07004423 return VMX_AR_DPL(ar);
Avi Kivity69c73022011-03-07 15:26:44 +02004424 }
Avi Kivity69c73022011-03-07 15:26:44 +02004425}
4426
Avi Kivity653e3102007-05-07 10:55:37 +03004427static u32 vmx_segment_access_rights(struct kvm_segment *var)
Avi Kivity6aa8b732006-12-10 02:21:36 -08004428{
Avi Kivity6aa8b732006-12-10 02:21:36 -08004429 u32 ar;
4430
Avi Kivityf0495f92012-06-07 17:06:10 +03004431 if (var->unusable || !var->present)
Avi Kivity6aa8b732006-12-10 02:21:36 -08004432 ar = 1 << 16;
4433 else {
4434 ar = var->type & 15;
4435 ar |= (var->s & 1) << 4;
4436 ar |= (var->dpl & 3) << 5;
4437 ar |= (var->present & 1) << 7;
4438 ar |= (var->avl & 1) << 12;
4439 ar |= (var->l & 1) << 13;
4440 ar |= (var->db & 1) << 14;
4441 ar |= (var->g & 1) << 15;
4442 }
Avi Kivity653e3102007-05-07 10:55:37 +03004443
4444 return ar;
4445}
4446
4447static void vmx_set_segment(struct kvm_vcpu *vcpu,
4448 struct kvm_segment *var, int seg)
4449{
Avi Kivity7ffd92c2009-06-09 14:10:45 +03004450 struct vcpu_vmx *vmx = to_vmx(vcpu);
Mathias Krause772e0312012-08-30 01:30:19 +02004451 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
Avi Kivity653e3102007-05-07 10:55:37 +03004452
Avi Kivity2fb92db2011-04-27 19:42:18 +03004453 vmx_segment_cache_clear(vmx);
4454
Gleb Natapov1ecd50a2012-12-12 19:10:54 +02004455 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
4456 vmx->rmode.segs[seg] = *var;
4457 if (seg == VCPU_SREG_TR)
4458 vmcs_write16(sf->selector, var->selector);
4459 else if (var->s)
4460 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
Gleb Natapovd99e4152012-12-20 16:57:45 +02004461 goto out;
Avi Kivity653e3102007-05-07 10:55:37 +03004462 }
Gleb Natapov1ecd50a2012-12-12 19:10:54 +02004463
Avi Kivity653e3102007-05-07 10:55:37 +03004464 vmcs_writel(sf->base, var->base);
4465 vmcs_write32(sf->limit, var->limit);
4466 vmcs_write16(sf->selector, var->selector);
Nitin A Kamble3a624e22009-06-08 11:34:16 -07004467
4468 /*
4469 * Fix the "Accessed" bit in AR field of segment registers for older
4470 * qemu binaries.
4471 * IA32 arch specifies that at the time of processor reset the
4472 * "Accessed" bit in the AR field of segment registers is 1. And qemu
Guo Chao0fa06072012-06-28 15:16:19 +08004473 * is setting it to 0 in the userland code. This causes invalid guest
Nitin A Kamble3a624e22009-06-08 11:34:16 -07004474 * state vmexit when "unrestricted guest" mode is turned on.
4475 * Fix for this setup issue in cpu_reset is being pushed in the qemu
4476 * tree. Newer qemu binaries with that qemu fix would not need this
4477 * kvm hack.
4478 */
4479 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
Gleb Natapovf924d662012-12-12 19:10:55 +02004480 var->type |= 0x1; /* Accessed */
Nitin A Kamble3a624e22009-06-08 11:34:16 -07004481
Gleb Natapovf924d662012-12-12 19:10:55 +02004482 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
Gleb Natapovd99e4152012-12-20 16:57:45 +02004483
4484out:
Paolo Bonzini98eb2f82014-03-27 09:51:52 +01004485 vmx->emulation_required = emulation_required(vcpu);
Avi Kivity6aa8b732006-12-10 02:21:36 -08004486}
4487
Avi Kivity6aa8b732006-12-10 02:21:36 -08004488static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
4489{
Avi Kivity2fb92db2011-04-27 19:42:18 +03004490 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
Avi Kivity6aa8b732006-12-10 02:21:36 -08004491
4492 *db = (ar >> 14) & 1;
4493 *l = (ar >> 13) & 1;
4494}
4495
Gleb Natapov89a27f42010-02-16 10:51:48 +02004496static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
Avi Kivity6aa8b732006-12-10 02:21:36 -08004497{
Gleb Natapov89a27f42010-02-16 10:51:48 +02004498 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
4499 dt->address = vmcs_readl(GUEST_IDTR_BASE);
Avi Kivity6aa8b732006-12-10 02:21:36 -08004500}
4501
Gleb Natapov89a27f42010-02-16 10:51:48 +02004502static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
Avi Kivity6aa8b732006-12-10 02:21:36 -08004503{
Gleb Natapov89a27f42010-02-16 10:51:48 +02004504 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
4505 vmcs_writel(GUEST_IDTR_BASE, dt->address);
Avi Kivity6aa8b732006-12-10 02:21:36 -08004506}
4507
Gleb Natapov89a27f42010-02-16 10:51:48 +02004508static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
Avi Kivity6aa8b732006-12-10 02:21:36 -08004509{
Gleb Natapov89a27f42010-02-16 10:51:48 +02004510 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
4511 dt->address = vmcs_readl(GUEST_GDTR_BASE);
Avi Kivity6aa8b732006-12-10 02:21:36 -08004512}
4513
Gleb Natapov89a27f42010-02-16 10:51:48 +02004514static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
Avi Kivity6aa8b732006-12-10 02:21:36 -08004515{
Gleb Natapov89a27f42010-02-16 10:51:48 +02004516 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
4517 vmcs_writel(GUEST_GDTR_BASE, dt->address);
Avi Kivity6aa8b732006-12-10 02:21:36 -08004518}
4519
Mohammed Gamal648dfaa2008-08-17 16:38:32 +03004520static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
4521{
4522 struct kvm_segment var;
4523 u32 ar;
4524
4525 vmx_get_segment(vcpu, &var, seg);
Gleb Natapov07f42f52012-12-12 19:10:49 +02004526 var.dpl = 0x3;
Gleb Natapov0647f4a2012-12-12 19:10:50 +02004527 if (seg == VCPU_SREG_CS)
4528 var.type = 0x3;
Mohammed Gamal648dfaa2008-08-17 16:38:32 +03004529 ar = vmx_segment_access_rights(&var);
4530
4531 if (var.base != (var.selector << 4))
4532 return false;
Gleb Natapov89efbed2012-12-20 16:57:44 +02004533 if (var.limit != 0xffff)
Mohammed Gamal648dfaa2008-08-17 16:38:32 +03004534 return false;
Gleb Natapov07f42f52012-12-12 19:10:49 +02004535 if (ar != 0xf3)
Mohammed Gamal648dfaa2008-08-17 16:38:32 +03004536 return false;
4537
4538 return true;
4539}
4540
4541static bool code_segment_valid(struct kvm_vcpu *vcpu)
4542{
4543 struct kvm_segment cs;
4544 unsigned int cs_rpl;
4545
4546 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
Nadav Amitb32a9912015-03-29 16:33:04 +03004547 cs_rpl = cs.selector & SEGMENT_RPL_MASK;
Mohammed Gamal648dfaa2008-08-17 16:38:32 +03004548
Avi Kivity1872a3f2009-01-04 23:26:52 +02004549 if (cs.unusable)
4550 return false;
Andy Lutomirski4d283ec2015-08-13 13:18:48 -07004551 if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
Mohammed Gamal648dfaa2008-08-17 16:38:32 +03004552 return false;
4553 if (!cs.s)
4554 return false;
Andy Lutomirski4d283ec2015-08-13 13:18:48 -07004555 if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
Mohammed Gamal648dfaa2008-08-17 16:38:32 +03004556 if (cs.dpl > cs_rpl)
4557 return false;
Avi Kivity1872a3f2009-01-04 23:26:52 +02004558 } else {
Mohammed Gamal648dfaa2008-08-17 16:38:32 +03004559 if (cs.dpl != cs_rpl)
4560 return false;
4561 }
4562 if (!cs.present)
4563 return false;
4564
4565 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
4566 return true;
4567}
4568
4569static bool stack_segment_valid(struct kvm_vcpu *vcpu)
4570{
4571 struct kvm_segment ss;
4572 unsigned int ss_rpl;
4573
4574 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
Nadav Amitb32a9912015-03-29 16:33:04 +03004575 ss_rpl = ss.selector & SEGMENT_RPL_MASK;
Mohammed Gamal648dfaa2008-08-17 16:38:32 +03004576
Avi Kivity1872a3f2009-01-04 23:26:52 +02004577 if (ss.unusable)
4578 return true;
4579 if (ss.type != 3 && ss.type != 7)
Mohammed Gamal648dfaa2008-08-17 16:38:32 +03004580 return false;
4581 if (!ss.s)
4582 return false;
4583 if (ss.dpl != ss_rpl) /* DPL != RPL */
4584 return false;
4585 if (!ss.present)
4586 return false;
4587
4588 return true;
4589}
4590
4591static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
4592{
4593 struct kvm_segment var;
4594 unsigned int rpl;
4595
4596 vmx_get_segment(vcpu, &var, seg);
Nadav Amitb32a9912015-03-29 16:33:04 +03004597 rpl = var.selector & SEGMENT_RPL_MASK;
Mohammed Gamal648dfaa2008-08-17 16:38:32 +03004598
Avi Kivity1872a3f2009-01-04 23:26:52 +02004599 if (var.unusable)
4600 return true;
Mohammed Gamal648dfaa2008-08-17 16:38:32 +03004601 if (!var.s)
4602 return false;
4603 if (!var.present)
4604 return false;
Andy Lutomirski4d283ec2015-08-13 13:18:48 -07004605 if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
Mohammed Gamal648dfaa2008-08-17 16:38:32 +03004606 if (var.dpl < rpl) /* DPL < RPL */
4607 return false;
4608 }
4609
4610 /* TODO: Add other members to kvm_segment_field to allow checking for other access
4611 * rights flags
4612 */
4613 return true;
4614}
4615
4616static bool tr_valid(struct kvm_vcpu *vcpu)
4617{
4618 struct kvm_segment tr;
4619
4620 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
4621
Avi Kivity1872a3f2009-01-04 23:26:52 +02004622 if (tr.unusable)
4623 return false;
Nadav Amitb32a9912015-03-29 16:33:04 +03004624 if (tr.selector & SEGMENT_TI_MASK) /* TI = 1 */
Mohammed Gamal648dfaa2008-08-17 16:38:32 +03004625 return false;
Avi Kivity1872a3f2009-01-04 23:26:52 +02004626 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
Mohammed Gamal648dfaa2008-08-17 16:38:32 +03004627 return false;
4628 if (!tr.present)
4629 return false;
4630
4631 return true;
4632}
4633
4634static bool ldtr_valid(struct kvm_vcpu *vcpu)
4635{
4636 struct kvm_segment ldtr;
4637
4638 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
4639
Avi Kivity1872a3f2009-01-04 23:26:52 +02004640 if (ldtr.unusable)
4641 return true;
Nadav Amitb32a9912015-03-29 16:33:04 +03004642 if (ldtr.selector & SEGMENT_TI_MASK) /* TI = 1 */
Mohammed Gamal648dfaa2008-08-17 16:38:32 +03004643 return false;
4644 if (ldtr.type != 2)
4645 return false;
4646 if (!ldtr.present)
4647 return false;
4648
4649 return true;
4650}
4651
4652static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
4653{
4654 struct kvm_segment cs, ss;
4655
4656 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4657 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4658
Nadav Amitb32a9912015-03-29 16:33:04 +03004659 return ((cs.selector & SEGMENT_RPL_MASK) ==
4660 (ss.selector & SEGMENT_RPL_MASK));
Mohammed Gamal648dfaa2008-08-17 16:38:32 +03004661}
4662
4663/*
4664 * Check if guest state is valid. Returns true if valid, false if
4665 * not.
4666 * We assume that registers are always usable
4667 */
4668static bool guest_state_valid(struct kvm_vcpu *vcpu)
4669{
Gleb Natapovc5e97c82013-01-21 15:36:43 +02004670 if (enable_unrestricted_guest)
4671 return true;
4672
Mohammed Gamal648dfaa2008-08-17 16:38:32 +03004673 /* real mode guest state checks */
Gleb Natapovf13882d2013-04-14 16:07:37 +03004674 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
Mohammed Gamal648dfaa2008-08-17 16:38:32 +03004675 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
4676 return false;
4677 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
4678 return false;
4679 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
4680 return false;
4681 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
4682 return false;
4683 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
4684 return false;
4685 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
4686 return false;
4687 } else {
4688 /* protected mode guest state checks */
4689 if (!cs_ss_rpl_check(vcpu))
4690 return false;
4691 if (!code_segment_valid(vcpu))
4692 return false;
4693 if (!stack_segment_valid(vcpu))
4694 return false;
4695 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
4696 return false;
4697 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
4698 return false;
4699 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
4700 return false;
4701 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
4702 return false;
4703 if (!tr_valid(vcpu))
4704 return false;
4705 if (!ldtr_valid(vcpu))
4706 return false;
4707 }
4708 /* TODO:
4709 * - Add checks on RIP
4710 * - Add checks on RFLAGS
4711 */
4712
4713 return true;
4714}
4715
Mike Dayd77c26f2007-10-08 09:02:08 -04004716static int init_rmode_tss(struct kvm *kvm)
Avi Kivity6aa8b732006-12-10 02:21:36 -08004717{
Xiao Guangrong40dcaa92011-03-09 15:41:04 +08004718 gfn_t fn;
Izik Eidus195aefd2007-10-01 22:14:18 +02004719 u16 data = 0;
Paolo Bonzini1f755a82014-09-16 13:37:40 +02004720 int idx, r;
Avi Kivity6aa8b732006-12-10 02:21:36 -08004721
Xiao Guangrong40dcaa92011-03-09 15:41:04 +08004722 idx = srcu_read_lock(&kvm->srcu);
Jan Kiszka4918c6c2013-03-15 08:38:56 +01004723 fn = kvm->arch.tss_addr >> PAGE_SHIFT;
Izik Eidus195aefd2007-10-01 22:14:18 +02004724 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4725 if (r < 0)
Marcelo Tosatti10589a42007-12-20 19:18:22 -05004726 goto out;
Izik Eidus195aefd2007-10-01 22:14:18 +02004727 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
Sheng Yang464d17c2008-08-13 14:10:33 +08004728 r = kvm_write_guest_page(kvm, fn++, &data,
4729 TSS_IOPB_BASE_OFFSET, sizeof(u16));
Izik Eidus195aefd2007-10-01 22:14:18 +02004730 if (r < 0)
Marcelo Tosatti10589a42007-12-20 19:18:22 -05004731 goto out;
Izik Eidus195aefd2007-10-01 22:14:18 +02004732 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
4733 if (r < 0)
Marcelo Tosatti10589a42007-12-20 19:18:22 -05004734 goto out;
Izik Eidus195aefd2007-10-01 22:14:18 +02004735 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4736 if (r < 0)
Marcelo Tosatti10589a42007-12-20 19:18:22 -05004737 goto out;
Izik Eidus195aefd2007-10-01 22:14:18 +02004738 data = ~0;
Marcelo Tosatti10589a42007-12-20 19:18:22 -05004739 r = kvm_write_guest_page(kvm, fn, &data,
4740 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
4741 sizeof(u8));
Marcelo Tosatti10589a42007-12-20 19:18:22 -05004742out:
Xiao Guangrong40dcaa92011-03-09 15:41:04 +08004743 srcu_read_unlock(&kvm->srcu, idx);
Paolo Bonzini1f755a82014-09-16 13:37:40 +02004744 return r;
Avi Kivity6aa8b732006-12-10 02:21:36 -08004745}
4746
Sheng Yangb7ebfb02008-04-25 21:44:52 +08004747static int init_rmode_identity_map(struct kvm *kvm)
4748{
Tang Chenf51770e2014-09-16 18:41:59 +08004749 int i, idx, r = 0;
Dan Williamsba049e92016-01-15 16:56:11 -08004750 kvm_pfn_t identity_map_pfn;
Sheng Yangb7ebfb02008-04-25 21:44:52 +08004751 u32 tmp;
4752
Avi Kivity089d0342009-03-23 18:26:32 +02004753 if (!enable_ept)
Tang Chenf51770e2014-09-16 18:41:59 +08004754 return 0;
Tang Chena255d472014-09-16 18:41:58 +08004755
4756 /* Protect kvm->arch.ept_identity_pagetable_done. */
4757 mutex_lock(&kvm->slots_lock);
4758
Tang Chenf51770e2014-09-16 18:41:59 +08004759 if (likely(kvm->arch.ept_identity_pagetable_done))
Tang Chena255d472014-09-16 18:41:58 +08004760 goto out2;
Tang Chena255d472014-09-16 18:41:58 +08004761
Sheng Yangb927a3c2009-07-21 10:42:48 +08004762 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
Tang Chena255d472014-09-16 18:41:58 +08004763
4764 r = alloc_identity_pagetable(kvm);
Tang Chenf51770e2014-09-16 18:41:59 +08004765 if (r < 0)
Tang Chena255d472014-09-16 18:41:58 +08004766 goto out2;
4767
Xiao Guangrong40dcaa92011-03-09 15:41:04 +08004768 idx = srcu_read_lock(&kvm->srcu);
Sheng Yangb7ebfb02008-04-25 21:44:52 +08004769 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
4770 if (r < 0)
4771 goto out;
4772 /* Set up identity-mapping pagetable for EPT in real mode */
4773 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
4774 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
4775 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
4776 r = kvm_write_guest_page(kvm, identity_map_pfn,
4777 &tmp, i * sizeof(tmp), sizeof(tmp));
4778 if (r < 0)
4779 goto out;
4780 }
4781 kvm->arch.ept_identity_pagetable_done = true;
Tang Chenf51770e2014-09-16 18:41:59 +08004782
Sheng Yangb7ebfb02008-04-25 21:44:52 +08004783out:
Xiao Guangrong40dcaa92011-03-09 15:41:04 +08004784 srcu_read_unlock(&kvm->srcu, idx);
Tang Chena255d472014-09-16 18:41:58 +08004785
4786out2:
4787 mutex_unlock(&kvm->slots_lock);
Tang Chenf51770e2014-09-16 18:41:59 +08004788 return r;
Sheng Yangb7ebfb02008-04-25 21:44:52 +08004789}
4790
Avi Kivity6aa8b732006-12-10 02:21:36 -08004791static void seg_setup(int seg)
4792{
Mathias Krause772e0312012-08-30 01:30:19 +02004793 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
Nitin A Kamble3a624e22009-06-08 11:34:16 -07004794 unsigned int ar;
Avi Kivity6aa8b732006-12-10 02:21:36 -08004795
4796 vmcs_write16(sf->selector, 0);
4797 vmcs_writel(sf->base, 0);
4798 vmcs_write32(sf->limit, 0xffff);
Gleb Natapovd54d07b2012-12-20 16:57:46 +02004799 ar = 0x93;
4800 if (seg == VCPU_SREG_CS)
4801 ar |= 0x08; /* code segment */
Nitin A Kamble3a624e22009-06-08 11:34:16 -07004802
4803 vmcs_write32(sf->ar_bytes, ar);
Avi Kivity6aa8b732006-12-10 02:21:36 -08004804}
4805
Sheng Yangf78e0e22007-10-29 09:40:42 +08004806static int alloc_apic_access_page(struct kvm *kvm)
4807{
Xiao Guangrong44841412012-09-07 14:14:20 +08004808 struct page *page;
Sheng Yangf78e0e22007-10-29 09:40:42 +08004809 int r = 0;
4810
Marcelo Tosatti79fac952009-12-23 14:35:26 -02004811 mutex_lock(&kvm->slots_lock);
Tang Chenc24ae0d2014-09-24 15:57:58 +08004812 if (kvm->arch.apic_access_page_done)
Sheng Yangf78e0e22007-10-29 09:40:42 +08004813 goto out;
Paolo Bonzini1d8007b2015-10-12 13:38:32 +02004814 r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
4815 APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
Sheng Yangf78e0e22007-10-29 09:40:42 +08004816 if (r)
4817 goto out;
Izik Eidus72dc67a2008-02-10 18:04:15 +02004818
Tang Chen73a6d942014-09-11 13:38:00 +08004819 page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
Xiao Guangrong44841412012-09-07 14:14:20 +08004820 if (is_error_page(page)) {
4821 r = -EFAULT;
4822 goto out;
4823 }
4824
Tang Chenc24ae0d2014-09-24 15:57:58 +08004825 /*
4826 * Do not pin the page in memory, so that memory hot-unplug
4827 * is able to migrate it.
4828 */
4829 put_page(page);
4830 kvm->arch.apic_access_page_done = true;
Sheng Yangf78e0e22007-10-29 09:40:42 +08004831out:
Marcelo Tosatti79fac952009-12-23 14:35:26 -02004832 mutex_unlock(&kvm->slots_lock);
Sheng Yangf78e0e22007-10-29 09:40:42 +08004833 return r;
4834}
4835
Sheng Yangb7ebfb02008-04-25 21:44:52 +08004836static int alloc_identity_pagetable(struct kvm *kvm)
4837{
Tang Chena255d472014-09-16 18:41:58 +08004838 /* Called with kvm->slots_lock held. */
4839
Sheng Yangb7ebfb02008-04-25 21:44:52 +08004840 int r = 0;
4841
Tang Chena255d472014-09-16 18:41:58 +08004842 BUG_ON(kvm->arch.ept_identity_pagetable_done);
4843
Paolo Bonzini1d8007b2015-10-12 13:38:32 +02004844 r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
4845 kvm->arch.ept_identity_map_addr, PAGE_SIZE);
Sheng Yangb7ebfb02008-04-25 21:44:52 +08004846
Sheng Yangb7ebfb02008-04-25 21:44:52 +08004847 return r;
4848}
4849
Wanpeng Li991e7a02015-09-16 17:30:05 +08004850static int allocate_vpid(void)
Sheng Yang2384d2b2008-01-17 15:14:33 +08004851{
4852 int vpid;
4853
Avi Kivity919818a2009-03-23 18:01:29 +02004854 if (!enable_vpid)
Wanpeng Li991e7a02015-09-16 17:30:05 +08004855 return 0;
Sheng Yang2384d2b2008-01-17 15:14:33 +08004856 spin_lock(&vmx_vpid_lock);
4857 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
Wanpeng Li991e7a02015-09-16 17:30:05 +08004858 if (vpid < VMX_NR_VPIDS)
Sheng Yang2384d2b2008-01-17 15:14:33 +08004859 __set_bit(vpid, vmx_vpid_bitmap);
Wanpeng Li991e7a02015-09-16 17:30:05 +08004860 else
4861 vpid = 0;
Sheng Yang2384d2b2008-01-17 15:14:33 +08004862 spin_unlock(&vmx_vpid_lock);
Wanpeng Li991e7a02015-09-16 17:30:05 +08004863 return vpid;
Sheng Yang2384d2b2008-01-17 15:14:33 +08004864}
4865
Wanpeng Li991e7a02015-09-16 17:30:05 +08004866static void free_vpid(int vpid)
Lai Jiangshancdbecfc2010-04-17 16:41:47 +08004867{
Wanpeng Li991e7a02015-09-16 17:30:05 +08004868 if (!enable_vpid || vpid == 0)
Lai Jiangshancdbecfc2010-04-17 16:41:47 +08004869 return;
4870 spin_lock(&vmx_vpid_lock);
Wanpeng Li991e7a02015-09-16 17:30:05 +08004871 __clear_bit(vpid, vmx_vpid_bitmap);
Lai Jiangshancdbecfc2010-04-17 16:41:47 +08004872 spin_unlock(&vmx_vpid_lock);
4873}
4874
Paolo Bonzini6236b782018-01-16 16:51:18 +01004875static void __always_inline vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4876 u32 msr, int type)
Sheng Yang25c5f222008-03-28 13:18:56 +08004877{
Avi Kivity3e7c73e2009-02-24 21:46:19 +02004878 int f = sizeof(unsigned long);
Sheng Yang25c5f222008-03-28 13:18:56 +08004879
4880 if (!cpu_has_vmx_msr_bitmap())
4881 return;
4882
4883 /*
4884 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4885 * have the write-low and read-high bitmap offsets the wrong way round.
4886 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4887 */
Sheng Yang25c5f222008-03-28 13:18:56 +08004888 if (msr <= 0x1fff) {
Yang Zhang8d146952013-01-25 10:18:50 +08004889 if (type & MSR_TYPE_R)
4890 /* read-low */
4891 __clear_bit(msr, msr_bitmap + 0x000 / f);
4892
4893 if (type & MSR_TYPE_W)
4894 /* write-low */
4895 __clear_bit(msr, msr_bitmap + 0x800 / f);
4896
Sheng Yang25c5f222008-03-28 13:18:56 +08004897 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4898 msr &= 0x1fff;
Yang Zhang8d146952013-01-25 10:18:50 +08004899 if (type & MSR_TYPE_R)
4900 /* read-high */
4901 __clear_bit(msr, msr_bitmap + 0x400 / f);
4902
4903 if (type & MSR_TYPE_W)
4904 /* write-high */
4905 __clear_bit(msr, msr_bitmap + 0xc00 / f);
4906
4907 }
4908}
4909
Paolo Bonzini6236b782018-01-16 16:51:18 +01004910static void __always_inline vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4911 u32 msr, int type)
Yang Zhang8d146952013-01-25 10:18:50 +08004912{
4913 int f = sizeof(unsigned long);
4914
4915 if (!cpu_has_vmx_msr_bitmap())
4916 return;
4917
4918 /*
4919 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4920 * have the write-low and read-high bitmap offsets the wrong way round.
4921 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4922 */
4923 if (msr <= 0x1fff) {
4924 if (type & MSR_TYPE_R)
4925 /* read-low */
4926 __set_bit(msr, msr_bitmap + 0x000 / f);
4927
4928 if (type & MSR_TYPE_W)
4929 /* write-low */
4930 __set_bit(msr, msr_bitmap + 0x800 / f);
4931
4932 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4933 msr &= 0x1fff;
4934 if (type & MSR_TYPE_R)
4935 /* read-high */
4936 __set_bit(msr, msr_bitmap + 0x400 / f);
4937
4938 if (type & MSR_TYPE_W)
4939 /* write-high */
4940 __set_bit(msr, msr_bitmap + 0xc00 / f);
4941
Sheng Yang25c5f222008-03-28 13:18:56 +08004942 }
Sheng Yang25c5f222008-03-28 13:18:56 +08004943}
4944
Paolo Bonzini6236b782018-01-16 16:51:18 +01004945static void __always_inline vmx_set_intercept_for_msr(unsigned long *msr_bitmap,
4946 u32 msr, int type, bool value)
4947{
4948 if (value)
4949 vmx_enable_intercept_for_msr(msr_bitmap, msr, type);
4950 else
4951 vmx_disable_intercept_for_msr(msr_bitmap, msr, type);
4952}
4953
Wincy Vanf2b93282015-02-03 23:56:03 +08004954/*
4955 * If a msr is allowed by L0, we should check whether it is allowed by L1.
4956 * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4957 */
4958static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
4959 unsigned long *msr_bitmap_nested,
4960 u32 msr, int type)
4961{
4962 int f = sizeof(unsigned long);
4963
4964 if (!cpu_has_vmx_msr_bitmap()) {
4965 WARN_ON(1);
4966 return;
4967 }
4968
4969 /*
4970 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4971 * have the write-low and read-high bitmap offsets the wrong way round.
4972 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4973 */
4974 if (msr <= 0x1fff) {
4975 if (type & MSR_TYPE_R &&
4976 !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
4977 /* read-low */
4978 __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
4979
4980 if (type & MSR_TYPE_W &&
4981 !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
4982 /* write-low */
4983 __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
4984
4985 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4986 msr &= 0x1fff;
4987 if (type & MSR_TYPE_R &&
4988 !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
4989 /* read-high */
4990 __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
4991
4992 if (type & MSR_TYPE_W &&
4993 !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
4994 /* write-high */
4995 __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
4996
4997 }
4998}
4999
Paolo Bonzini6236b782018-01-16 16:51:18 +01005000static u8 vmx_msr_bitmap_mode(struct kvm_vcpu *vcpu)
Avi Kivity58972972009-02-24 22:26:47 +02005001{
Paolo Bonzini6236b782018-01-16 16:51:18 +01005002 u8 mode = 0;
5003
5004 if (cpu_has_secondary_exec_ctrls() &&
5005 (vmcs_read32(SECONDARY_VM_EXEC_CONTROL) &
5006 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
5007 mode |= MSR_BITMAP_MODE_X2APIC;
5008 if (enable_apicv && kvm_vcpu_apicv_active(vcpu))
5009 mode |= MSR_BITMAP_MODE_X2APIC_APICV;
5010 }
5011
5012 if (is_long_mode(vcpu))
5013 mode |= MSR_BITMAP_MODE_LM;
5014
5015 return mode;
Yang Zhang8d146952013-01-25 10:18:50 +08005016}
5017
Paolo Bonzini6236b782018-01-16 16:51:18 +01005018#define X2APIC_MSR(r) (APIC_BASE_MSR + ((r) >> 4))
5019
5020static void vmx_update_msr_bitmap_x2apic(unsigned long *msr_bitmap,
5021 u8 mode)
Yang Zhang8d146952013-01-25 10:18:50 +08005022{
Paolo Bonzini6236b782018-01-16 16:51:18 +01005023 int msr;
5024
5025 for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
5026 unsigned word = msr / BITS_PER_LONG;
5027 msr_bitmap[word] = (mode & MSR_BITMAP_MODE_X2APIC_APICV) ? 0 : ~0;
5028 msr_bitmap[word + (0x800 / sizeof(long))] = ~0;
5029 }
5030
5031 if (mode & MSR_BITMAP_MODE_X2APIC) {
5032 /*
5033 * TPR reads and writes can be virtualized even if virtual interrupt
5034 * delivery is not in use.
5035 */
5036 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_RW);
5037 if (mode & MSR_BITMAP_MODE_X2APIC_APICV) {
5038 vmx_enable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TMCCT), MSR_TYPE_R);
5039 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_EOI), MSR_TYPE_W);
5040 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_SELF_IPI), MSR_TYPE_W);
5041 }
Wanpeng Lif6e90f92016-09-22 07:43:25 +08005042 }
Yang Zhang8d146952013-01-25 10:18:50 +08005043}
5044
Paolo Bonzini6236b782018-01-16 16:51:18 +01005045static void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu)
Yang Zhang8d146952013-01-25 10:18:50 +08005046{
Paolo Bonzini6236b782018-01-16 16:51:18 +01005047 struct vcpu_vmx *vmx = to_vmx(vcpu);
5048 unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
5049 u8 mode = vmx_msr_bitmap_mode(vcpu);
5050 u8 changed = mode ^ vmx->msr_bitmap_mode;
Yang Zhang8d146952013-01-25 10:18:50 +08005051
Paolo Bonzini6236b782018-01-16 16:51:18 +01005052 if (!changed)
5053 return;
5054
5055 vmx_set_intercept_for_msr(msr_bitmap, MSR_KERNEL_GS_BASE, MSR_TYPE_RW,
5056 !(mode & MSR_BITMAP_MODE_LM));
5057
5058 if (changed & (MSR_BITMAP_MODE_X2APIC | MSR_BITMAP_MODE_X2APIC_APICV))
5059 vmx_update_msr_bitmap_x2apic(msr_bitmap, mode);
5060
5061 vmx->msr_bitmap_mode = mode;
Avi Kivity58972972009-02-24 22:26:47 +02005062}
5063
Andrey Smetanind62caab2015-11-10 15:36:33 +03005064static bool vmx_get_enable_apicv(void)
Paolo Bonzinid50ab6c2015-07-29 11:49:59 +02005065{
Andrey Smetanind62caab2015-11-10 15:36:33 +03005066 return enable_apicv;
Paolo Bonzinid50ab6c2015-07-29 11:49:59 +02005067}
5068
David Matlackb7649e12017-08-01 14:00:40 -07005069static void nested_mark_vmcs12_pages_dirty(struct kvm_vcpu *vcpu)
5070{
5071 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5072 gfn_t gfn;
5073
5074 /*
5075 * Don't need to mark the APIC access page dirty; it is never
5076 * written to by the CPU during APIC virtualization.
5077 */
5078
5079 if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
5080 gfn = vmcs12->virtual_apic_page_addr >> PAGE_SHIFT;
5081 kvm_vcpu_mark_page_dirty(vcpu, gfn);
5082 }
5083
5084 if (nested_cpu_has_posted_intr(vmcs12)) {
5085 gfn = vmcs12->posted_intr_desc_addr >> PAGE_SHIFT;
5086 kvm_vcpu_mark_page_dirty(vcpu, gfn);
5087 }
5088}
5089
5090
David Hildenbrand1edccf22017-01-25 11:58:58 +01005091static void vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
Wincy Van705699a2015-02-03 23:58:17 +08005092{
5093 struct vcpu_vmx *vmx = to_vmx(vcpu);
5094 int max_irr;
5095 void *vapic_page;
5096 u16 status;
5097
David Matlackb7649e12017-08-01 14:00:40 -07005098 if (!vmx->nested.pi_desc || !vmx->nested.pi_pending)
5099 return;
Wincy Van705699a2015-02-03 23:58:17 +08005100
David Matlackb7649e12017-08-01 14:00:40 -07005101 vmx->nested.pi_pending = false;
5102 if (!pi_test_and_clear_on(vmx->nested.pi_desc))
5103 return;
Wincy Van705699a2015-02-03 23:58:17 +08005104
David Matlackb7649e12017-08-01 14:00:40 -07005105 max_irr = find_last_bit((unsigned long *)vmx->nested.pi_desc->pir, 256);
5106 if (max_irr != 256) {
Wincy Van705699a2015-02-03 23:58:17 +08005107 vapic_page = kmap(vmx->nested.virtual_apic_page);
Wincy Van705699a2015-02-03 23:58:17 +08005108 __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page);
5109 kunmap(vmx->nested.virtual_apic_page);
5110
5111 status = vmcs_read16(GUEST_INTR_STATUS);
5112 if ((u8)max_irr > ((u8)status & 0xff)) {
5113 status &= ~0xff;
5114 status |= (u8)max_irr;
5115 vmcs_write16(GUEST_INTR_STATUS, status);
5116 }
5117 }
David Matlackb7649e12017-08-01 14:00:40 -07005118
5119 nested_mark_vmcs12_pages_dirty(vcpu);
Wincy Van705699a2015-02-03 23:58:17 +08005120}
5121
Radim Krčmář21bc8dc2015-02-16 15:36:33 +01005122static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu)
5123{
5124#ifdef CONFIG_SMP
5125 if (vcpu->mode == IN_GUEST_MODE) {
Feng Wu28b835d2015-09-18 22:29:54 +08005126 /*
Haozhong Zhang3ffbe622017-09-18 09:56:50 +08005127 * The vector of interrupt to be delivered to vcpu had
5128 * been set in PIR before this function.
Feng Wu28b835d2015-09-18 22:29:54 +08005129 *
Haozhong Zhang3ffbe622017-09-18 09:56:50 +08005130 * Following cases will be reached in this block, and
5131 * we always send a notification event in all cases as
5132 * explained below.
5133 *
5134 * Case 1: vcpu keeps in non-root mode. Sending a
5135 * notification event posts the interrupt to vcpu.
5136 *
5137 * Case 2: vcpu exits to root mode and is still
5138 * runnable. PIR will be synced to vIRR before the
5139 * next vcpu entry. Sending a notification event in
5140 * this case has no effect, as vcpu is not in root
5141 * mode.
5142 *
5143 * Case 3: vcpu exits to root mode and is blocked.
5144 * vcpu_block() has already synced PIR to vIRR and
5145 * never blocks vcpu if vIRR is not cleared. Therefore,
5146 * a blocked vcpu here does not wait for any requested
5147 * interrupts in PIR, and sending a notification event
5148 * which has no effect is safe here.
Feng Wu28b835d2015-09-18 22:29:54 +08005149 */
Feng Wu28b835d2015-09-18 22:29:54 +08005150
Radim Krčmář21bc8dc2015-02-16 15:36:33 +01005151 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
5152 POSTED_INTR_VECTOR);
5153 return true;
5154 }
5155#endif
5156 return false;
5157}
5158
Wincy Van705699a2015-02-03 23:58:17 +08005159static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
5160 int vector)
5161{
5162 struct vcpu_vmx *vmx = to_vmx(vcpu);
5163
5164 if (is_guest_mode(vcpu) &&
5165 vector == vmx->nested.posted_intr_nv) {
Wincy Van705699a2015-02-03 23:58:17 +08005166 /*
5167 * If a posted intr is not recognized by hardware,
5168 * we will accomplish it in the next vmentry.
5169 */
5170 vmx->nested.pi_pending = true;
5171 kvm_make_request(KVM_REQ_EVENT, vcpu);
Liran Alonba882892017-11-09 20:27:20 +02005172 /* the PIR and ON have been set by L1. */
5173 if (!kvm_vcpu_trigger_posted_interrupt(vcpu))
5174 kvm_vcpu_kick(vcpu);
Wincy Van705699a2015-02-03 23:58:17 +08005175 return 0;
5176 }
5177 return -1;
5178}
Avi Kivity6aa8b732006-12-10 02:21:36 -08005179/*
Yang Zhanga20ed542013-04-11 19:25:15 +08005180 * Send interrupt to vcpu via posted interrupt way.
5181 * 1. If target vcpu is running(non-root mode), send posted interrupt
5182 * notification to vcpu and hardware will sync PIR to vIRR atomically.
5183 * 2. If target vcpu isn't running(root mode), kick it to pick up the
5184 * interrupt from PIR in next vmentry.
5185 */
5186static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
5187{
5188 struct vcpu_vmx *vmx = to_vmx(vcpu);
5189 int r;
5190
Wincy Van705699a2015-02-03 23:58:17 +08005191 r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
5192 if (!r)
5193 return;
5194
Yang Zhanga20ed542013-04-11 19:25:15 +08005195 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
5196 return;
5197
5198 r = pi_test_and_set_on(&vmx->pi_desc);
5199 kvm_make_request(KVM_REQ_EVENT, vcpu);
Radim Krčmář21bc8dc2015-02-16 15:36:33 +01005200 if (r || !kvm_vcpu_trigger_posted_interrupt(vcpu))
Yang Zhanga20ed542013-04-11 19:25:15 +08005201 kvm_vcpu_kick(vcpu);
5202}
5203
5204static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
5205{
5206 struct vcpu_vmx *vmx = to_vmx(vcpu);
5207
5208 if (!pi_test_and_clear_on(&vmx->pi_desc))
5209 return;
5210
5211 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
5212}
5213
Avi Kivity6aa8b732006-12-10 02:21:36 -08005214/*
Nadav Har'Ela3a8ff82011-05-25 23:09:01 +03005215 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
5216 * will not change in the lifetime of the guest.
5217 * Note that host-state that does change is set elsewhere. E.g., host-state
5218 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
5219 */
Yang Zhanga547c6d2013-04-11 19:25:10 +08005220static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
Nadav Har'Ela3a8ff82011-05-25 23:09:01 +03005221{
5222 u32 low32, high32;
5223 unsigned long tmpl;
5224 struct desc_ptr dt;
Andy Lutomirskid974baa2014-10-08 09:02:13 -07005225 unsigned long cr4;
Nadav Har'Ela3a8ff82011-05-25 23:09:01 +03005226
Suresh Siddhab1a74bf2012-09-20 11:01:49 -07005227 vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS); /* 22.2.3 */
Nadav Har'Ela3a8ff82011-05-25 23:09:01 +03005228 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
5229
Andy Lutomirskid974baa2014-10-08 09:02:13 -07005230 /* Save the most likely value for this task's CR4 in the VMCS. */
Andy Lutomirski1e02ce42014-10-24 15:58:08 -07005231 cr4 = cr4_read_shadow();
Andy Lutomirskid974baa2014-10-08 09:02:13 -07005232 vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */
5233 vmx->host_state.vmcs_host_cr4 = cr4;
5234
Nadav Har'Ela3a8ff82011-05-25 23:09:01 +03005235 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
Avi Kivityb2da15a2012-05-13 19:53:24 +03005236#ifdef CONFIG_X86_64
5237 /*
5238 * Load null selectors, so we can avoid reloading them in
5239 * __vmx_load_host_state(), in case userspace uses the null selectors
5240 * too (the expected case).
5241 */
5242 vmcs_write16(HOST_DS_SELECTOR, 0);
5243 vmcs_write16(HOST_ES_SELECTOR, 0);
5244#else
Nadav Har'Ela3a8ff82011-05-25 23:09:01 +03005245 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
5246 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
Avi Kivityb2da15a2012-05-13 19:53:24 +03005247#endif
Nadav Har'Ela3a8ff82011-05-25 23:09:01 +03005248 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
5249 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
5250
5251 native_store_idt(&dt);
5252 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
Yang Zhanga547c6d2013-04-11 19:25:10 +08005253 vmx->host_idt_base = dt.address;
Nadav Har'Ela3a8ff82011-05-25 23:09:01 +03005254
Avi Kivity83287ea422012-09-16 15:10:57 +03005255 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
Nadav Har'Ela3a8ff82011-05-25 23:09:01 +03005256
5257 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
5258 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
5259 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
5260 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
5261
5262 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
5263 rdmsr(MSR_IA32_CR_PAT, low32, high32);
5264 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
5265 }
5266}
5267
Nadav Har'Elbf8179a2011-05-25 23:09:31 +03005268static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
5269{
5270 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
5271 if (enable_ept)
5272 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
Nadav Har'Elfe3ef052011-05-25 23:10:02 +03005273 if (is_guest_mode(&vmx->vcpu))
5274 vmx->vcpu.arch.cr4_guest_owned_bits &=
5275 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
Nadav Har'Elbf8179a2011-05-25 23:09:31 +03005276 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
5277}
5278
Yang Zhang01e439b2013-04-11 19:25:12 +08005279static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
5280{
5281 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
5282
Andrey Smetanind62caab2015-11-10 15:36:33 +03005283 if (!kvm_vcpu_apicv_active(&vmx->vcpu))
Yang Zhang01e439b2013-04-11 19:25:12 +08005284 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
Yunhong Jiang64672c92016-06-13 14:19:59 -07005285 /* Enable the preemption timer dynamically */
5286 pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
Yang Zhang01e439b2013-04-11 19:25:12 +08005287 return pin_based_exec_ctrl;
5288}
5289
Andrey Smetanind62caab2015-11-10 15:36:33 +03005290static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
5291{
5292 struct vcpu_vmx *vmx = to_vmx(vcpu);
5293
5294 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
Roman Kagan3ce424e2016-05-18 17:48:20 +03005295 if (cpu_has_secondary_exec_ctrls()) {
5296 if (kvm_vcpu_apicv_active(vcpu))
5297 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
5298 SECONDARY_EXEC_APIC_REGISTER_VIRT |
5299 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5300 else
5301 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
5302 SECONDARY_EXEC_APIC_REGISTER_VIRT |
5303 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5304 }
5305
5306 if (cpu_has_vmx_msr_bitmap())
Paolo Bonzini6236b782018-01-16 16:51:18 +01005307 vmx_update_msr_bitmap(vcpu);
Andrey Smetanind62caab2015-11-10 15:36:33 +03005308}
5309
Nadav Har'Elbf8179a2011-05-25 23:09:31 +03005310static u32 vmx_exec_control(struct vcpu_vmx *vmx)
5311{
5312 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
Paolo Bonzinid16c2932014-02-21 10:36:37 +01005313
5314 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
5315 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5316
Paolo Bonzini35754c92015-07-29 12:05:37 +02005317 if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
Nadav Har'Elbf8179a2011-05-25 23:09:31 +03005318 exec_control &= ~CPU_BASED_TPR_SHADOW;
5319#ifdef CONFIG_X86_64
5320 exec_control |= CPU_BASED_CR8_STORE_EXITING |
5321 CPU_BASED_CR8_LOAD_EXITING;
5322#endif
5323 }
5324 if (!enable_ept)
5325 exec_control |= CPU_BASED_CR3_STORE_EXITING |
5326 CPU_BASED_CR3_LOAD_EXITING |
5327 CPU_BASED_INVLPG_EXITING;
5328 return exec_control;
5329}
5330
5331static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
5332{
5333 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
Paolo Bonzini35754c92015-07-29 12:05:37 +02005334 if (!cpu_need_virtualize_apic_accesses(&vmx->vcpu))
Nadav Har'Elbf8179a2011-05-25 23:09:31 +03005335 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
5336 if (vmx->vpid == 0)
5337 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
5338 if (!enable_ept) {
5339 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
5340 enable_unrestricted_guest = 0;
Mao, Junjiead756a12012-07-02 01:18:48 +00005341 /* Enable INVPCID for non-ept guests may cause performance regression. */
5342 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
Nadav Har'Elbf8179a2011-05-25 23:09:31 +03005343 }
5344 if (!enable_unrestricted_guest)
5345 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
5346 if (!ple_gap)
5347 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
Andrey Smetanind62caab2015-11-10 15:36:33 +03005348 if (!kvm_vcpu_apicv_active(&vmx->vcpu))
Yang Zhangc7c9c562013-01-25 10:18:51 +08005349 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
5350 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
Yang Zhang8d146952013-01-25 10:18:50 +08005351 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
Abel Gordonabc4fc52013-04-18 14:35:25 +03005352 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
5353 (handle_vmptrld).
5354 We can NOT enable shadow_vmcs here because we don't have yet
5355 a current VMCS12
5356 */
5357 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
Kai Huanga3eaa862015-11-04 13:46:05 +08005358
5359 if (!enable_pml)
5360 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
Kai Huang843e4332015-01-28 10:54:28 +08005361
Nadav Har'Elbf8179a2011-05-25 23:09:31 +03005362 return exec_control;
5363}
5364
Xiao Guangrongce88dec2011-07-12 03:33:44 +08005365static void ept_set_mmio_spte_mask(void)
5366{
5367 /*
5368 * EPT Misconfigurations can be generated if the value of bits 2:0
5369 * of an EPT paging-structure entry is 110b (write/execute).
Xiao Guangrong885032b2013-06-07 16:51:23 +08005370 * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
Xiao Guangrongce88dec2011-07-12 03:33:44 +08005371 * spte.
5372 */
Xiao Guangrong885032b2013-06-07 16:51:23 +08005373 kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
Xiao Guangrongce88dec2011-07-12 03:33:44 +08005374}
5375
Wanpeng Lif53cd632014-12-02 19:14:58 +08005376#define VMX_XSS_EXIT_BITMAP 0
Nadav Har'Ela3a8ff82011-05-25 23:09:01 +03005377/*
Avi Kivity6aa8b732006-12-10 02:21:36 -08005378 * Sets up the vmcs for emulated real mode.
5379 */
Rusty Russell8b9cf982007-07-30 16:31:43 +10005380static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
Avi Kivity6aa8b732006-12-10 02:21:36 -08005381{
Jan Kiszka2e4ce7f2011-06-01 12:57:30 +02005382#ifdef CONFIG_X86_64
Avi Kivity6aa8b732006-12-10 02:21:36 -08005383 unsigned long a;
Jan Kiszka2e4ce7f2011-06-01 12:57:30 +02005384#endif
Avi Kivity6aa8b732006-12-10 02:21:36 -08005385 int i;
Avi Kivity6aa8b732006-12-10 02:21:36 -08005386
Avi Kivity6aa8b732006-12-10 02:21:36 -08005387 /* I/O */
Avi Kivity3e7c73e2009-02-24 21:46:19 +02005388 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
5389 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
Avi Kivity6aa8b732006-12-10 02:21:36 -08005390
Abel Gordon4607c2d2013-04-18 14:35:55 +03005391 if (enable_shadow_vmcs) {
5392 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
5393 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
5394 }
Sheng Yang25c5f222008-03-28 13:18:56 +08005395 if (cpu_has_vmx_msr_bitmap())
Paolo Bonzini6236b782018-01-16 16:51:18 +01005396 vmcs_write64(MSR_BITMAP, __pa(vmx->vmcs01.msr_bitmap));
Sheng Yang25c5f222008-03-28 13:18:56 +08005397
Avi Kivity6aa8b732006-12-10 02:21:36 -08005398 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
5399
Avi Kivity6aa8b732006-12-10 02:21:36 -08005400 /* Control */
Yang Zhang01e439b2013-04-11 19:25:12 +08005401 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
Yunhong Jiang64672c92016-06-13 14:19:59 -07005402 vmx->hv_deadline_tsc = -1;
Yang, Sheng6e5d8652007-09-12 18:03:11 +08005403
Nadav Har'Elbf8179a2011-05-25 23:09:31 +03005404 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
Avi Kivity6aa8b732006-12-10 02:21:36 -08005405
Dan Williamsdfa169b2016-06-02 11:17:24 -07005406 if (cpu_has_secondary_exec_ctrls()) {
Nadav Har'Elbf8179a2011-05-25 23:09:31 +03005407 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
5408 vmx_secondary_exec_control(vmx));
Dan Williamsdfa169b2016-06-02 11:17:24 -07005409 }
Sheng Yangf78e0e22007-10-29 09:40:42 +08005410
Andrey Smetanind62caab2015-11-10 15:36:33 +03005411 if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
Yang Zhangc7c9c562013-01-25 10:18:51 +08005412 vmcs_write64(EOI_EXIT_BITMAP0, 0);
5413 vmcs_write64(EOI_EXIT_BITMAP1, 0);
5414 vmcs_write64(EOI_EXIT_BITMAP2, 0);
5415 vmcs_write64(EOI_EXIT_BITMAP3, 0);
5416
5417 vmcs_write16(GUEST_INTR_STATUS, 0);
Yang Zhang01e439b2013-04-11 19:25:12 +08005418
Li RongQing0bcf2612015-12-03 13:29:34 +08005419 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
Yang Zhang01e439b2013-04-11 19:25:12 +08005420 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
Yang Zhangc7c9c562013-01-25 10:18:51 +08005421 }
5422
Zhai, Edwin4b8d54f2009-10-09 18:03:20 +08005423 if (ple_gap) {
5424 vmcs_write32(PLE_GAP, ple_gap);
Radim Krčmářa7653ec2014-08-21 18:08:07 +02005425 vmx->ple_window = ple_window;
5426 vmx->ple_window_dirty = true;
Zhai, Edwin4b8d54f2009-10-09 18:03:20 +08005427 }
5428
Xiao Guangrongc3707952011-07-12 03:28:04 +08005429 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
5430 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
Avi Kivity6aa8b732006-12-10 02:21:36 -08005431 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
5432
Avi Kivity9581d442010-10-19 16:46:55 +02005433 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
5434 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
Yang Zhanga547c6d2013-04-11 19:25:10 +08005435 vmx_set_constant_host_state(vmx);
Avi Kivity05b3e0c2006-12-13 00:33:45 -08005436#ifdef CONFIG_X86_64
Avi Kivity6aa8b732006-12-10 02:21:36 -08005437 rdmsrl(MSR_FS_BASE, a);
5438 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
5439 rdmsrl(MSR_GS_BASE, a);
5440 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
5441#else
5442 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
5443 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
5444#endif
5445
Eddie Dong2cc51562007-05-21 07:28:09 +03005446 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
5447 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
Konrad Rzeszutek Wilk57e3ada2018-06-20 13:58:37 -04005448 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host.val));
Eddie Dong2cc51562007-05-21 07:28:09 +03005449 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
Konrad Rzeszutek Wilk57e3ada2018-06-20 13:58:37 -04005450 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest.val));
Avi Kivity6aa8b732006-12-10 02:21:36 -08005451
Radim Krčmář74545702015-04-27 15:11:25 +02005452 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
5453 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
Sheng Yang468d4722008-10-09 16:01:55 +08005454
Paolo Bonzini03916db2014-07-24 14:21:57 +02005455 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
Avi Kivity6aa8b732006-12-10 02:21:36 -08005456 u32 index = vmx_msr_index[i];
5457 u32 data_low, data_high;
Gregory Haskinsa2fa3e92007-07-27 08:13:10 -04005458 int j = vmx->nmsrs;
Avi Kivity6aa8b732006-12-10 02:21:36 -08005459
5460 if (rdmsr_safe(index, &data_low, &data_high) < 0)
5461 continue;
Avi Kivity432bd6c2007-01-31 23:48:13 -08005462 if (wrmsr_safe(index, data_low, data_high) < 0)
5463 continue;
Avi Kivity26bb0982009-09-07 11:14:12 +03005464 vmx->guest_msrs[j].index = i;
5465 vmx->guest_msrs[j].data = 0;
Avi Kivityd5696722009-12-02 12:28:47 +02005466 vmx->guest_msrs[j].mask = -1ull;
Gregory Haskinsa2fa3e92007-07-27 08:13:10 -04005467 ++vmx->nmsrs;
Avi Kivity6aa8b732006-12-10 02:21:36 -08005468 }
Avi Kivity6aa8b732006-12-10 02:21:36 -08005469
Paolo Bonzinif56c8ee2018-08-05 16:07:47 +02005470 vmx->arch_capabilities = kvm_get_arch_capabilities();
Gleb Natapov2961e8762013-11-25 15:37:13 +02005471
5472 vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
Avi Kivity6aa8b732006-12-10 02:21:36 -08005473
5474 /* 22.2.1, 20.8.1 */
Gleb Natapov2961e8762013-11-25 15:37:13 +02005475 vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
Yang, Sheng1c3d14fe2007-07-29 11:07:42 +03005476
Avi Kivitye00c8cf2007-10-21 11:00:39 +02005477 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
Nadav Har'Elbf8179a2011-05-25 23:09:31 +03005478 set_cr4_guest_host_mask(vmx);
Avi Kivitye00c8cf2007-10-21 11:00:39 +02005479
Wanpeng Lif53cd632014-12-02 19:14:58 +08005480 if (vmx_xsaves_supported())
5481 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
5482
Peter Feiner4e595162016-07-07 14:49:58 -07005483 if (enable_pml) {
5484 ASSERT(vmx->pml_pg);
5485 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
5486 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
5487 }
5488
Avi Kivitye00c8cf2007-10-21 11:00:39 +02005489 return 0;
5490}
5491
Nadav Amitd28bc9d2015-04-13 14:34:08 +03005492static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
Avi Kivitye00c8cf2007-10-21 11:00:39 +02005493{
5494 struct vcpu_vmx *vmx = to_vmx(vcpu);
Jan Kiszka58cb6282014-01-24 16:48:44 +01005495 struct msr_data apic_base_msr;
Nadav Amitd28bc9d2015-04-13 14:34:08 +03005496 u64 cr0;
Avi Kivitye00c8cf2007-10-21 11:00:39 +02005497
Avi Kivity7ffd92c2009-06-09 14:10:45 +03005498 vmx->rmode.vm86_active = 0;
Wanpeng Li7a1eac82018-02-28 14:03:31 +08005499 vcpu->arch.microcode_version = 0x100000000ULL;
KarimAllah Ahmede5a83412018-02-01 22:59:45 +01005500 vmx->spec_ctrl = 0;
Avi Kivitye00c8cf2007-10-21 11:00:39 +02005501
Jan Kiszka3b86cd92008-09-26 09:30:57 +02005502 vmx->soft_vnmi_blocked = 0;
5503
Zhang Xiantaoad312c72007-12-13 23:50:52 +08005504 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
Nadav Amitd28bc9d2015-04-13 14:34:08 +03005505 kvm_set_cr8(vcpu, 0);
5506
5507 if (!init_event) {
5508 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
5509 MSR_IA32_APICBASE_ENABLE;
5510 if (kvm_vcpu_is_reset_bsp(vcpu))
5511 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
5512 apic_base_msr.host_initiated = true;
5513 kvm_set_apic_base(vcpu, &apic_base_msr);
5514 }
Avi Kivitye00c8cf2007-10-21 11:00:39 +02005515
Avi Kivity2fb92db2011-04-27 19:42:18 +03005516 vmx_segment_cache_clear(vmx);
5517
Avi Kivity5706be02008-08-20 15:07:31 +03005518 seg_setup(VCPU_SREG_CS);
Jan Kiszka66450a22013-03-13 12:42:34 +01005519 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
Paolo Bonzinif3531052015-12-03 15:49:56 +01005520 vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
Avi Kivitye00c8cf2007-10-21 11:00:39 +02005521
5522 seg_setup(VCPU_SREG_DS);
5523 seg_setup(VCPU_SREG_ES);
5524 seg_setup(VCPU_SREG_FS);
5525 seg_setup(VCPU_SREG_GS);
5526 seg_setup(VCPU_SREG_SS);
5527
5528 vmcs_write16(GUEST_TR_SELECTOR, 0);
5529 vmcs_writel(GUEST_TR_BASE, 0);
5530 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
5531 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
5532
5533 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
5534 vmcs_writel(GUEST_LDTR_BASE, 0);
5535 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
5536 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
5537
Nadav Amitd28bc9d2015-04-13 14:34:08 +03005538 if (!init_event) {
5539 vmcs_write32(GUEST_SYSENTER_CS, 0);
5540 vmcs_writel(GUEST_SYSENTER_ESP, 0);
5541 vmcs_writel(GUEST_SYSENTER_EIP, 0);
5542 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
5543 }
Avi Kivitye00c8cf2007-10-21 11:00:39 +02005544
Wanpeng Li5c0b19b2017-11-20 14:52:21 -08005545 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
Jan Kiszka66450a22013-03-13 12:42:34 +01005546 kvm_rip_write(vcpu, 0xfff0);
Avi Kivitye00c8cf2007-10-21 11:00:39 +02005547
Avi Kivitye00c8cf2007-10-21 11:00:39 +02005548 vmcs_writel(GUEST_GDTR_BASE, 0);
5549 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
5550
5551 vmcs_writel(GUEST_IDTR_BASE, 0);
5552 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
5553
Anthony Liguori443381a2010-12-06 10:53:38 -06005554 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
Avi Kivitye00c8cf2007-10-21 11:00:39 +02005555 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
Paolo Bonzinif3531052015-12-03 15:49:56 +01005556 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
Avi Kivitye00c8cf2007-10-21 11:00:39 +02005557
Avi Kivitye00c8cf2007-10-21 11:00:39 +02005558 setup_msrs(vmx);
5559
Avi Kivity6aa8b732006-12-10 02:21:36 -08005560 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
5561
Nadav Amitd28bc9d2015-04-13 14:34:08 +03005562 if (cpu_has_vmx_tpr_shadow() && !init_event) {
Sheng Yangf78e0e22007-10-29 09:40:42 +08005563 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
Paolo Bonzini35754c92015-07-29 12:05:37 +02005564 if (cpu_need_tpr_shadow(vcpu))
Sheng Yangf78e0e22007-10-29 09:40:42 +08005565 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
Nadav Amitd28bc9d2015-04-13 14:34:08 +03005566 __pa(vcpu->arch.apic->regs));
Sheng Yangf78e0e22007-10-29 09:40:42 +08005567 vmcs_write32(TPR_THRESHOLD, 0);
5568 }
5569
Paolo Bonzinia73896c2014-11-02 07:54:30 +01005570 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
Avi Kivity6aa8b732006-12-10 02:21:36 -08005571
Andrey Smetanind62caab2015-11-10 15:36:33 +03005572 if (kvm_vcpu_apicv_active(vcpu))
Yang Zhang01e439b2013-04-11 19:25:12 +08005573 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
5574
Sheng Yang2384d2b2008-01-17 15:14:33 +08005575 if (vmx->vpid != 0)
5576 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
5577
Nadav Amitd28bc9d2015-04-13 14:34:08 +03005578 cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
Nadav Amitd28bc9d2015-04-13 14:34:08 +03005579 vmx->vcpu.arch.cr0 = cr0;
Bruce Rogersf2463242016-04-28 14:49:21 -06005580 vmx_set_cr0(vcpu, cr0); /* enter rmode */
Nadav Amitd28bc9d2015-04-13 14:34:08 +03005581 vmx_set_cr4(vcpu, 0);
Paolo Bonzini56908912015-10-19 11:30:19 +02005582 vmx_set_efer(vcpu, 0);
Nadav Amitd28bc9d2015-04-13 14:34:08 +03005583 vmx_fpu_activate(vcpu);
5584 update_exception_bitmap(vcpu);
Avi Kivity6aa8b732006-12-10 02:21:36 -08005585
Wanpeng Lidd5f5342015-09-23 18:26:57 +08005586 vpid_sync_context(vmx->vpid);
Avi Kivity6aa8b732006-12-10 02:21:36 -08005587}
5588
Nadav Har'Elb6f12502011-05-25 23:13:06 +03005589/*
5590 * In nested virtualization, check if L1 asked to exit on external interrupts.
5591 * For most existing hypervisors, this will always return true.
5592 */
5593static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
5594{
5595 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5596 PIN_BASED_EXT_INTR_MASK;
5597}
5598
Bandan Das77b0f5d2014-04-19 18:17:45 -04005599/*
5600 * In nested virtualization, check if L1 has set
5601 * VM_EXIT_ACK_INTR_ON_EXIT
5602 */
5603static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
5604{
5605 return get_vmcs12(vcpu)->vm_exit_controls &
5606 VM_EXIT_ACK_INTR_ON_EXIT;
5607}
5608
Jan Kiszkaea8ceb82013-04-14 21:04:26 +02005609static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
5610{
5611 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5612 PIN_BASED_NMI_EXITING;
5613}
5614
Jan Kiszkac9a79532014-03-07 20:03:15 +01005615static void enable_irq_window(struct kvm_vcpu *vcpu)
Jan Kiszka3b86cd92008-09-26 09:30:57 +02005616{
5617 u32 cpu_based_vm_exec_control;
Jan Kiszka730dca42013-04-28 10:50:52 +02005618
Jan Kiszka3b86cd92008-09-26 09:30:57 +02005619 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5620 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
5621 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5622}
5623
Jan Kiszkac9a79532014-03-07 20:03:15 +01005624static void enable_nmi_window(struct kvm_vcpu *vcpu)
Jan Kiszka3b86cd92008-09-26 09:30:57 +02005625{
5626 u32 cpu_based_vm_exec_control;
5627
Jan Kiszkac9a79532014-03-07 20:03:15 +01005628 if (!cpu_has_virtual_nmis() ||
5629 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
5630 enable_irq_window(vcpu);
5631 return;
5632 }
Jan Kiszka03b28f82013-04-29 16:46:42 +02005633
Jan Kiszka3b86cd92008-09-26 09:30:57 +02005634 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5635 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
5636 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5637}
5638
Gleb Natapov66fd3f72009-05-11 13:35:50 +03005639static void vmx_inject_irq(struct kvm_vcpu *vcpu)
Eddie Dong85f455f2007-07-06 12:20:49 +03005640{
Avi Kivity9c8cba32007-11-22 11:42:59 +02005641 struct vcpu_vmx *vmx = to_vmx(vcpu);
Gleb Natapov66fd3f72009-05-11 13:35:50 +03005642 uint32_t intr;
5643 int irq = vcpu->arch.interrupt.nr;
Avi Kivity9c8cba32007-11-22 11:42:59 +02005644
Marcelo Tosatti229456f2009-06-17 09:22:14 -03005645 trace_kvm_inj_virq(irq);
Feng (Eric) Liu2714d1d2008-04-10 15:31:10 -04005646
Avi Kivityfa89a812008-09-01 15:57:51 +03005647 ++vcpu->stat.irq_injections;
Avi Kivity7ffd92c2009-06-09 14:10:45 +03005648 if (vmx->rmode.vm86_active) {
Serge E. Hallyn71f98332011-04-13 09:12:54 -05005649 int inc_eip = 0;
5650 if (vcpu->arch.interrupt.soft)
5651 inc_eip = vcpu->arch.event_exit_inst_len;
5652 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
Mohammed Gamala92601b2010-09-19 14:34:07 +02005653 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
Eddie Dong85f455f2007-07-06 12:20:49 +03005654 return;
5655 }
Gleb Natapov66fd3f72009-05-11 13:35:50 +03005656 intr = irq | INTR_INFO_VALID_MASK;
5657 if (vcpu->arch.interrupt.soft) {
5658 intr |= INTR_TYPE_SOFT_INTR;
5659 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
5660 vmx->vcpu.arch.event_exit_inst_len);
5661 } else
5662 intr |= INTR_TYPE_EXT_INTR;
5663 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
Eddie Dong85f455f2007-07-06 12:20:49 +03005664}
5665
Sheng Yangf08864b2008-05-15 18:23:25 +08005666static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
5667{
Jan Kiszka66a5a342008-09-26 09:30:51 +02005668 struct vcpu_vmx *vmx = to_vmx(vcpu);
5669
Wanpeng Lic5a6d5f2016-09-22 17:55:54 +08005670 if (!is_guest_mode(vcpu)) {
5671 if (!cpu_has_virtual_nmis()) {
5672 /*
5673 * Tracking the NMI-blocked state in software is built upon
5674 * finding the next open IRQ window. This, in turn, depends on
5675 * well-behaving guests: They have to keep IRQs disabled at
5676 * least as long as the NMI handler runs. Otherwise we may
5677 * cause NMI nesting, maybe breaking the guest. But as this is
5678 * highly unlikely, we can live with the residual risk.
5679 */
5680 vmx->soft_vnmi_blocked = 1;
5681 vmx->vnmi_blocked_time = 0;
5682 }
Nadav Har'El0b6ac342011-05-25 23:13:36 +03005683
Wanpeng Lic5a6d5f2016-09-22 17:55:54 +08005684 ++vcpu->stat.nmi_injections;
5685 vmx->nmi_known_unmasked = false;
Jan Kiszka3b86cd92008-09-26 09:30:57 +02005686 }
5687
Avi Kivity7ffd92c2009-06-09 14:10:45 +03005688 if (vmx->rmode.vm86_active) {
Serge E. Hallyn71f98332011-04-13 09:12:54 -05005689 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
Mohammed Gamala92601b2010-09-19 14:34:07 +02005690 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
Jan Kiszka66a5a342008-09-26 09:30:51 +02005691 return;
5692 }
Wanpeng Lic5a6d5f2016-09-22 17:55:54 +08005693
Sheng Yangf08864b2008-05-15 18:23:25 +08005694 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
5695 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
Sheng Yangf08864b2008-05-15 18:23:25 +08005696}
5697
Jan Kiszka3cfc3092009-11-12 01:04:25 +01005698static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
5699{
5700 if (!cpu_has_virtual_nmis())
5701 return to_vmx(vcpu)->soft_vnmi_blocked;
Avi Kivity9d58b932011-03-07 16:52:07 +02005702 if (to_vmx(vcpu)->nmi_known_unmasked)
5703 return false;
Avi Kivityc332c832010-05-04 12:24:12 +03005704 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
Jan Kiszka3cfc3092009-11-12 01:04:25 +01005705}
5706
5707static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
5708{
5709 struct vcpu_vmx *vmx = to_vmx(vcpu);
5710
5711 if (!cpu_has_virtual_nmis()) {
5712 if (vmx->soft_vnmi_blocked != masked) {
5713 vmx->soft_vnmi_blocked = masked;
5714 vmx->vnmi_blocked_time = 0;
5715 }
5716 } else {
Avi Kivity9d58b932011-03-07 16:52:07 +02005717 vmx->nmi_known_unmasked = !masked;
Jan Kiszka3cfc3092009-11-12 01:04:25 +01005718 if (masked)
5719 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5720 GUEST_INTR_STATE_NMI);
5721 else
5722 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
5723 GUEST_INTR_STATE_NMI);
5724 }
5725}
5726
Jan Kiszka2505dc92013-04-14 12:12:47 +02005727static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
5728{
Jan Kiszkab6b8a142014-03-07 20:03:12 +01005729 if (to_vmx(vcpu)->nested.nested_run_pending)
5730 return 0;
Jan Kiszkaea8ceb82013-04-14 21:04:26 +02005731
Jan Kiszka2505dc92013-04-14 12:12:47 +02005732 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
5733 return 0;
5734
5735 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5736 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
5737 | GUEST_INTR_STATE_NMI));
5738}
5739
Gleb Natapov78646122009-03-23 12:12:11 +02005740static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
5741{
Jan Kiszkab6b8a142014-03-07 20:03:12 +01005742 return (!to_vmx(vcpu)->nested.nested_run_pending &&
5743 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
Gleb Natapovc4282df2009-04-21 17:45:07 +03005744 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5745 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
Gleb Natapov78646122009-03-23 12:12:11 +02005746}
5747
Izik Eiduscbc94022007-10-25 00:29:55 +02005748static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
5749{
5750 int ret;
Izik Eiduscbc94022007-10-25 00:29:55 +02005751
Paolo Bonzini1d8007b2015-10-12 13:38:32 +02005752 ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
5753 PAGE_SIZE * 3);
Izik Eiduscbc94022007-10-25 00:29:55 +02005754 if (ret)
5755 return ret;
Zhang Xiantaobfc6d222007-12-14 10:20:16 +08005756 kvm->arch.tss_addr = addr;
Paolo Bonzini1f755a82014-09-16 13:37:40 +02005757 return init_rmode_tss(kvm);
Izik Eiduscbc94022007-10-25 00:29:55 +02005758}
5759
Gleb Natapov0ca1b4f2012-12-20 16:57:47 +02005760static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
Avi Kivity6aa8b732006-12-10 02:21:36 -08005761{
Jan Kiszka77ab6db2008-07-14 12:28:51 +02005762 switch (vec) {
Jan Kiszka77ab6db2008-07-14 12:28:51 +02005763 case BP_VECTOR:
Jan Kiszkac573cd22010-02-23 17:47:53 +01005764 /*
5765 * Update instruction length as we may reinject the exception
5766 * from user space while in guest debugging mode.
5767 */
5768 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
5769 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
Jan Kiszkad0bfb942008-12-15 13:52:10 +01005770 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
Gleb Natapov0ca1b4f2012-12-20 16:57:47 +02005771 return false;
5772 /* fall through */
5773 case DB_VECTOR:
5774 if (vcpu->guest_debug &
5775 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
5776 return false;
Jan Kiszkad0bfb942008-12-15 13:52:10 +01005777 /* fall through */
5778 case DE_VECTOR:
Jan Kiszka77ab6db2008-07-14 12:28:51 +02005779 case OF_VECTOR:
5780 case BR_VECTOR:
5781 case UD_VECTOR:
5782 case DF_VECTOR:
5783 case SS_VECTOR:
5784 case GP_VECTOR:
5785 case MF_VECTOR:
Gleb Natapov0ca1b4f2012-12-20 16:57:47 +02005786 return true;
5787 break;
Jan Kiszka77ab6db2008-07-14 12:28:51 +02005788 }
Gleb Natapov0ca1b4f2012-12-20 16:57:47 +02005789 return false;
5790}
5791
5792static int handle_rmode_exception(struct kvm_vcpu *vcpu,
5793 int vec, u32 err_code)
5794{
5795 /*
5796 * Instruction with address size override prefix opcode 0x67
5797 * Cause the #SS fault with 0 error code in VM86 mode.
5798 */
5799 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
5800 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
5801 if (vcpu->arch.halt_request) {
5802 vcpu->arch.halt_request = 0;
Joel Schopp5cb56052015-03-02 13:43:31 -06005803 return kvm_vcpu_halt(vcpu);
Gleb Natapov0ca1b4f2012-12-20 16:57:47 +02005804 }
5805 return 1;
5806 }
5807 return 0;
5808 }
5809
5810 /*
5811 * Forward all other exceptions that are valid in real mode.
5812 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5813 * the required debugging infrastructure rework.
5814 */
5815 kvm_queue_exception(vcpu, vec);
5816 return 1;
Avi Kivity6aa8b732006-12-10 02:21:36 -08005817}
5818
Andi Kleena0861c02009-06-08 17:37:09 +08005819/*
5820 * Trigger machine check on the host. We assume all the MSRs are already set up
5821 * by the CPU and that we still run on the same CPU as the MCE occurred on.
5822 * We pass a fake environment to the machine check handler because we want
5823 * the guest to be always treated like user space, no matter what context
5824 * it used internally.
5825 */
5826static void kvm_machine_check(void)
5827{
5828#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5829 struct pt_regs regs = {
5830 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
5831 .flags = X86_EFLAGS_IF,
5832 };
5833
5834 do_machine_check(&regs, 0);
5835#endif
5836}
5837
Avi Kivity851ba692009-08-24 11:10:17 +03005838static int handle_machine_check(struct kvm_vcpu *vcpu)
Andi Kleena0861c02009-06-08 17:37:09 +08005839{
5840 /* already handled by vcpu_run */
5841 return 1;
5842}
5843
Avi Kivity851ba692009-08-24 11:10:17 +03005844static int handle_exception(struct kvm_vcpu *vcpu)
Avi Kivity6aa8b732006-12-10 02:21:36 -08005845{
Avi Kivity1155f762007-11-22 11:30:47 +02005846 struct vcpu_vmx *vmx = to_vmx(vcpu);
Avi Kivity851ba692009-08-24 11:10:17 +03005847 struct kvm_run *kvm_run = vcpu->run;
Jan Kiszkad0bfb942008-12-15 13:52:10 +01005848 u32 intr_info, ex_no, error_code;
Jan Kiszka42dbaa52008-12-15 13:52:10 +01005849 unsigned long cr2, rip, dr6;
Avi Kivity6aa8b732006-12-10 02:21:36 -08005850 u32 vect_info;
5851 enum emulation_result er;
5852
Avi Kivity1155f762007-11-22 11:30:47 +02005853 vect_info = vmx->idt_vectoring_info;
Avi Kivity88786472011-03-07 17:39:45 +02005854 intr_info = vmx->exit_intr_info;
Avi Kivity6aa8b732006-12-10 02:21:36 -08005855
Andi Kleena0861c02009-06-08 17:37:09 +08005856 if (is_machine_check(intr_info))
Avi Kivity851ba692009-08-24 11:10:17 +03005857 return handle_machine_check(vcpu);
Andi Kleena0861c02009-06-08 17:37:09 +08005858
Jim Mattson3f618a02016-12-12 11:01:37 -08005859 if (is_nmi(intr_info))
Avi Kivity1b6269d2007-10-09 12:12:19 +02005860 return 1; /* already handled by vmx_vcpu_run() */
Anthony Liguori2ab455c2007-04-27 09:29:49 +03005861
5862 if (is_no_device(intr_info)) {
Avi Kivity5fd86fc2007-05-02 20:40:00 +03005863 vmx_fpu_activate(vcpu);
Anthony Liguori2ab455c2007-04-27 09:29:49 +03005864 return 1;
5865 }
5866
Anthony Liguori7aa81cc2007-09-17 14:57:50 -05005867 if (is_invalid_opcode(intr_info)) {
Jan Kiszkaae1f5762015-03-09 20:56:43 +01005868 if (is_guest_mode(vcpu)) {
5869 kvm_queue_exception(vcpu, UD_VECTOR);
5870 return 1;
5871 }
Andre Przywara51d8b662010-12-21 11:12:02 +01005872 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
Liran Alonc0a4c222017-11-05 16:56:32 +02005873 if (er == EMULATE_USER_EXIT)
5874 return 0;
Anthony Liguori7aa81cc2007-09-17 14:57:50 -05005875 if (er != EMULATE_DONE)
Avi Kivity7ee5d9402007-11-25 15:22:50 +02005876 kvm_queue_exception(vcpu, UD_VECTOR);
Anthony Liguori7aa81cc2007-09-17 14:57:50 -05005877 return 1;
5878 }
5879
Avi Kivity6aa8b732006-12-10 02:21:36 -08005880 error_code = 0;
Ryan Harper2e113842008-02-11 10:26:38 -06005881 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
Avi Kivity6aa8b732006-12-10 02:21:36 -08005882 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
Xiao Guangrongbf4ca232012-10-17 13:48:06 +08005883
5884 /*
5885 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5886 * MMIO, it is better to report an internal error.
5887 * See the comments in vmx_handle_exit.
5888 */
5889 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
5890 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
5891 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5892 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
Radim Krčmář80f0e952015-04-02 21:11:05 +02005893 vcpu->run->internal.ndata = 3;
Xiao Guangrongbf4ca232012-10-17 13:48:06 +08005894 vcpu->run->internal.data[0] = vect_info;
5895 vcpu->run->internal.data[1] = intr_info;
Radim Krčmář80f0e952015-04-02 21:11:05 +02005896 vcpu->run->internal.data[2] = error_code;
Xiao Guangrongbf4ca232012-10-17 13:48:06 +08005897 return 0;
5898 }
5899
Avi Kivity6aa8b732006-12-10 02:21:36 -08005900 if (is_page_fault(intr_info)) {
Sheng Yang14394422008-04-28 12:24:45 +08005901 /* EPT won't cause page fault directly */
Julia Lawallcf3ace72011-08-02 12:34:57 +02005902 BUG_ON(enable_ept);
Avi Kivity6aa8b732006-12-10 02:21:36 -08005903 cr2 = vmcs_readl(EXIT_QUALIFICATION);
Marcelo Tosatti229456f2009-06-17 09:22:14 -03005904 trace_kvm_page_fault(cr2, error_code);
Paolo Bonzinib3dc63c2018-07-02 13:07:14 +02005905 vcpu->arch.l1tf_flush_l1d = true;
Marcelo Tosatti229456f2009-06-17 09:22:14 -03005906
Gleb Natapov3298b752009-05-11 13:35:46 +03005907 if (kvm_event_needs_reinjection(vcpu))
Avi Kivity577bdc42008-07-19 08:57:05 +03005908 kvm_mmu_unprotect_page_virt(vcpu, cr2);
Andre Przywaradc25e892010-12-21 11:12:07 +01005909 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
Avi Kivity6aa8b732006-12-10 02:21:36 -08005910 }
5911
Jan Kiszkad0bfb942008-12-15 13:52:10 +01005912 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
Gleb Natapov0ca1b4f2012-12-20 16:57:47 +02005913
5914 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
5915 return handle_rmode_exception(vcpu, ex_no, error_code);
5916
Jan Kiszka42dbaa52008-12-15 13:52:10 +01005917 switch (ex_no) {
Eric Northup54a20552015-11-03 18:03:53 +01005918 case AC_VECTOR:
5919 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
5920 return 1;
Jan Kiszka42dbaa52008-12-15 13:52:10 +01005921 case DB_VECTOR:
5922 dr6 = vmcs_readl(EXIT_QUALIFICATION);
5923 if (!(vcpu->guest_debug &
5924 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
Jan Kiszka8246bf52014-01-04 18:47:17 +01005925 vcpu->arch.dr6 &= ~15;
Nadav Amit6f43ed02014-07-15 17:37:46 +03005926 vcpu->arch.dr6 |= dr6 | DR6_RTM;
Linus Torvalds587da2b2018-03-20 12:16:59 -07005927 if (is_icebp(intr_info))
Huw Daviesfd2a4452014-04-16 10:02:51 +01005928 skip_emulated_instruction(vcpu);
5929
Jan Kiszka42dbaa52008-12-15 13:52:10 +01005930 kvm_queue_exception(vcpu, DB_VECTOR);
5931 return 1;
5932 }
5933 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5934 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
5935 /* fall through */
5936 case BP_VECTOR:
Jan Kiszkac573cd22010-02-23 17:47:53 +01005937 /*
5938 * Update instruction length as we may reinject #BP from
5939 * user space while in guest debugging mode. Reading it for
5940 * #DB as well causes no harm, it is not used in that case.
5941 */
5942 vmx->vcpu.arch.event_exit_inst_len =
5943 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
Avi Kivity6aa8b732006-12-10 02:21:36 -08005944 kvm_run->exit_reason = KVM_EXIT_DEBUG;
Avi Kivity0a434bb2011-04-28 15:59:33 +03005945 rip = kvm_rip_read(vcpu);
Jan Kiszkad0bfb942008-12-15 13:52:10 +01005946 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
5947 kvm_run->debug.arch.exception = ex_no;
Jan Kiszka42dbaa52008-12-15 13:52:10 +01005948 break;
5949 default:
Jan Kiszkad0bfb942008-12-15 13:52:10 +01005950 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
5951 kvm_run->ex.exception = ex_no;
5952 kvm_run->ex.error_code = error_code;
Jan Kiszka42dbaa52008-12-15 13:52:10 +01005953 break;
Avi Kivity6aa8b732006-12-10 02:21:36 -08005954 }
Avi Kivity6aa8b732006-12-10 02:21:36 -08005955 return 0;
5956}
5957
Avi Kivity851ba692009-08-24 11:10:17 +03005958static int handle_external_interrupt(struct kvm_vcpu *vcpu)
Avi Kivity6aa8b732006-12-10 02:21:36 -08005959{
Avi Kivity1165f5f2007-04-19 17:27:43 +03005960 ++vcpu->stat.irq_exits;
Avi Kivity6aa8b732006-12-10 02:21:36 -08005961 return 1;
5962}
5963
Avi Kivity851ba692009-08-24 11:10:17 +03005964static int handle_triple_fault(struct kvm_vcpu *vcpu)
Avi Kivity988ad742007-02-12 00:54:36 -08005965{
Avi Kivity851ba692009-08-24 11:10:17 +03005966 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
Avi Kivity988ad742007-02-12 00:54:36 -08005967 return 0;
5968}
Avi Kivity6aa8b732006-12-10 02:21:36 -08005969
Avi Kivity851ba692009-08-24 11:10:17 +03005970static int handle_io(struct kvm_vcpu *vcpu)
Avi Kivity6aa8b732006-12-10 02:21:36 -08005971{
He, Qingbfdaab02007-09-12 14:18:28 +08005972 unsigned long exit_qualification;
Jan Kiszka34c33d12009-02-08 13:28:15 +01005973 int size, in, string;
Avi Kivity039576c2007-03-20 12:46:50 +02005974 unsigned port;
Avi Kivity6aa8b732006-12-10 02:21:36 -08005975
He, Qingbfdaab02007-09-12 14:18:28 +08005976 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
Avi Kivity039576c2007-03-20 12:46:50 +02005977 string = (exit_qualification & 16) != 0;
Laurent Viviere70669a2007-08-05 10:36:40 +03005978 in = (exit_qualification & 8) != 0;
Laurent Viviere70669a2007-08-05 10:36:40 +03005979
Gleb Natapovcf8f70b2010-03-18 15:20:23 +02005980 ++vcpu->stat.io_exits;
5981
5982 if (string || in)
Andre Przywara51d8b662010-12-21 11:12:02 +01005983 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
Gleb Natapovcf8f70b2010-03-18 15:20:23 +02005984
5985 port = exit_qualification >> 16;
5986 size = (exit_qualification & 7) + 1;
Guillaume Thouvenine93f36b2008-10-28 10:51:30 +01005987 skip_emulated_instruction(vcpu);
Gleb Natapovcf8f70b2010-03-18 15:20:23 +02005988
5989 return kvm_fast_pio_out(vcpu, size, port);
Avi Kivity6aa8b732006-12-10 02:21:36 -08005990}
5991
Ingo Molnar102d8322007-02-19 14:37:47 +02005992static void
5993vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5994{
5995 /*
5996 * Patch in the VMCALL instruction:
5997 */
5998 hypercall[0] = 0x0f;
5999 hypercall[1] = 0x01;
6000 hypercall[2] = 0xc1;
Ingo Molnar102d8322007-02-19 14:37:47 +02006001}
6002
Wincy Vanb9c237b2015-02-03 23:56:30 +08006003static bool nested_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
Jan Kiszka92fbc7b2013-08-08 16:26:33 +02006004{
6005 unsigned long always_on = VMXON_CR0_ALWAYSON;
Wincy Vanb9c237b2015-02-03 23:56:30 +08006006 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
Jan Kiszka92fbc7b2013-08-08 16:26:33 +02006007
Wincy Vanb9c237b2015-02-03 23:56:30 +08006008 if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high &
Jan Kiszka92fbc7b2013-08-08 16:26:33 +02006009 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
6010 nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
6011 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
6012 return (val & always_on) == always_on;
6013}
6014
Guo Chao0fa06072012-06-28 15:16:19 +08006015/* called to set cr0 as appropriate for a mov-to-cr0 exit. */
Nadav Har'Eleeadf9e2011-05-25 23:14:38 +03006016static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
6017{
Nadav Har'Eleeadf9e2011-05-25 23:14:38 +03006018 if (is_guest_mode(vcpu)) {
Jan Kiszka1a0d74e2013-03-07 14:08:07 +01006019 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6020 unsigned long orig_val = val;
6021
Nadav Har'Eleeadf9e2011-05-25 23:14:38 +03006022 /*
6023 * We get here when L2 changed cr0 in a way that did not change
6024 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
Jan Kiszka1a0d74e2013-03-07 14:08:07 +01006025 * but did change L0 shadowed bits. So we first calculate the
6026 * effective cr0 value that L1 would like to write into the
6027 * hardware. It consists of the L2-owned bits from the new
6028 * value combined with the L1-owned bits from L1's guest_cr0.
Nadav Har'Eleeadf9e2011-05-25 23:14:38 +03006029 */
Jan Kiszka1a0d74e2013-03-07 14:08:07 +01006030 val = (val & ~vmcs12->cr0_guest_host_mask) |
6031 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
6032
Wincy Vanb9c237b2015-02-03 23:56:30 +08006033 if (!nested_cr0_valid(vcpu, val))
Nadav Har'Eleeadf9e2011-05-25 23:14:38 +03006034 return 1;
Jan Kiszka1a0d74e2013-03-07 14:08:07 +01006035
6036 if (kvm_set_cr0(vcpu, val))
6037 return 1;
6038 vmcs_writel(CR0_READ_SHADOW, orig_val);
Nadav Har'Eleeadf9e2011-05-25 23:14:38 +03006039 return 0;
Jan Kiszka1a0d74e2013-03-07 14:08:07 +01006040 } else {
6041 if (to_vmx(vcpu)->nested.vmxon &&
6042 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
6043 return 1;
Nadav Har'Eleeadf9e2011-05-25 23:14:38 +03006044 return kvm_set_cr0(vcpu, val);
Jan Kiszka1a0d74e2013-03-07 14:08:07 +01006045 }
Nadav Har'Eleeadf9e2011-05-25 23:14:38 +03006046}
6047
6048static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
6049{
6050 if (is_guest_mode(vcpu)) {
Jan Kiszka1a0d74e2013-03-07 14:08:07 +01006051 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6052 unsigned long orig_val = val;
6053
6054 /* analogously to handle_set_cr0 */
6055 val = (val & ~vmcs12->cr4_guest_host_mask) |
6056 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
6057 if (kvm_set_cr4(vcpu, val))
Nadav Har'Eleeadf9e2011-05-25 23:14:38 +03006058 return 1;
Jan Kiszka1a0d74e2013-03-07 14:08:07 +01006059 vmcs_writel(CR4_READ_SHADOW, orig_val);
Nadav Har'Eleeadf9e2011-05-25 23:14:38 +03006060 return 0;
6061 } else
6062 return kvm_set_cr4(vcpu, val);
6063}
6064
Adam Buchbinder6a6256f2016-02-23 15:34:30 -08006065/* called to set cr0 as appropriate for clts instruction exit. */
Nadav Har'Eleeadf9e2011-05-25 23:14:38 +03006066static void handle_clts(struct kvm_vcpu *vcpu)
6067{
6068 if (is_guest_mode(vcpu)) {
6069 /*
6070 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
6071 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
6072 * just pretend it's off (also in arch.cr0 for fpu_activate).
6073 */
6074 vmcs_writel(CR0_READ_SHADOW,
6075 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
6076 vcpu->arch.cr0 &= ~X86_CR0_TS;
6077 } else
6078 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
6079}
6080
Avi Kivity851ba692009-08-24 11:10:17 +03006081static int handle_cr(struct kvm_vcpu *vcpu)
Avi Kivity6aa8b732006-12-10 02:21:36 -08006082{
Marcelo Tosatti229456f2009-06-17 09:22:14 -03006083 unsigned long exit_qualification, val;
Avi Kivity6aa8b732006-12-10 02:21:36 -08006084 int cr;
6085 int reg;
Avi Kivity49a9b072010-06-10 17:02:14 +03006086 int err;
Avi Kivity6aa8b732006-12-10 02:21:36 -08006087
He, Qingbfdaab02007-09-12 14:18:28 +08006088 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
Avi Kivity6aa8b732006-12-10 02:21:36 -08006089 cr = exit_qualification & 15;
6090 reg = (exit_qualification >> 8) & 15;
6091 switch ((exit_qualification >> 4) & 3) {
6092 case 0: /* mov to cr */
Nadav Amit1e32c072014-06-18 17:19:25 +03006093 val = kvm_register_readl(vcpu, reg);
Marcelo Tosatti229456f2009-06-17 09:22:14 -03006094 trace_kvm_cr_write(cr, val);
Avi Kivity6aa8b732006-12-10 02:21:36 -08006095 switch (cr) {
6096 case 0:
Nadav Har'Eleeadf9e2011-05-25 23:14:38 +03006097 err = handle_set_cr0(vcpu, val);
Andre Przywaradb8fcef2010-12-21 11:12:01 +01006098 kvm_complete_insn_gp(vcpu, err);
Avi Kivity6aa8b732006-12-10 02:21:36 -08006099 return 1;
6100 case 3:
Avi Kivity23902182010-06-10 17:02:16 +03006101 err = kvm_set_cr3(vcpu, val);
Andre Przywaradb8fcef2010-12-21 11:12:01 +01006102 kvm_complete_insn_gp(vcpu, err);
Avi Kivity6aa8b732006-12-10 02:21:36 -08006103 return 1;
6104 case 4:
Nadav Har'Eleeadf9e2011-05-25 23:14:38 +03006105 err = handle_set_cr4(vcpu, val);
Andre Przywaradb8fcef2010-12-21 11:12:01 +01006106 kvm_complete_insn_gp(vcpu, err);
Avi Kivity6aa8b732006-12-10 02:21:36 -08006107 return 1;
Gleb Natapov0a5fff192009-04-21 17:45:06 +03006108 case 8: {
6109 u8 cr8_prev = kvm_get_cr8(vcpu);
Nadav Amit1e32c072014-06-18 17:19:25 +03006110 u8 cr8 = (u8)val;
Andre Przywaraeea1cff2010-12-21 11:12:00 +01006111 err = kvm_set_cr8(vcpu, cr8);
Andre Przywaradb8fcef2010-12-21 11:12:01 +01006112 kvm_complete_insn_gp(vcpu, err);
Paolo Bonzini35754c92015-07-29 12:05:37 +02006113 if (lapic_in_kernel(vcpu))
Gleb Natapov0a5fff192009-04-21 17:45:06 +03006114 return 1;
6115 if (cr8_prev <= cr8)
6116 return 1;
Avi Kivity851ba692009-08-24 11:10:17 +03006117 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
Gleb Natapov0a5fff192009-04-21 17:45:06 +03006118 return 0;
6119 }
Peter Senna Tschudin4b8073e2012-09-18 18:36:14 +02006120 }
Avi Kivity6aa8b732006-12-10 02:21:36 -08006121 break;
Anthony Liguori25c4c272007-04-27 09:29:21 +03006122 case 2: /* clts */
Nadav Har'Eleeadf9e2011-05-25 23:14:38 +03006123 handle_clts(vcpu);
Avi Kivity4d4ec082009-12-29 18:07:30 +02006124 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
Anthony Liguori25c4c272007-04-27 09:29:21 +03006125 skip_emulated_instruction(vcpu);
Avi Kivity6b52d182010-01-21 15:31:47 +02006126 vmx_fpu_activate(vcpu);
Anthony Liguori25c4c272007-04-27 09:29:21 +03006127 return 1;
Avi Kivity6aa8b732006-12-10 02:21:36 -08006128 case 1: /*mov from cr*/
6129 switch (cr) {
6130 case 3:
Avi Kivity9f8fe502010-12-05 17:30:00 +02006131 val = kvm_read_cr3(vcpu);
6132 kvm_register_write(vcpu, reg, val);
6133 trace_kvm_cr_read(cr, val);
Avi Kivity6aa8b732006-12-10 02:21:36 -08006134 skip_emulated_instruction(vcpu);
6135 return 1;
6136 case 8:
Marcelo Tosatti229456f2009-06-17 09:22:14 -03006137 val = kvm_get_cr8(vcpu);
6138 kvm_register_write(vcpu, reg, val);
6139 trace_kvm_cr_read(cr, val);
Avi Kivity6aa8b732006-12-10 02:21:36 -08006140 skip_emulated_instruction(vcpu);
6141 return 1;
6142 }
6143 break;
6144 case 3: /* lmsw */
Avi Kivitya1f83a72009-12-29 17:33:58 +02006145 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
Avi Kivity4d4ec082009-12-29 18:07:30 +02006146 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
Avi Kivitya1f83a72009-12-29 17:33:58 +02006147 kvm_lmsw(vcpu, val);
Avi Kivity6aa8b732006-12-10 02:21:36 -08006148
6149 skip_emulated_instruction(vcpu);
6150 return 1;
6151 default:
6152 break;
6153 }
Avi Kivity851ba692009-08-24 11:10:17 +03006154 vcpu->run->exit_reason = 0;
Christoffer Dalla737f252012-06-03 21:17:48 +03006155 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
Avi Kivity6aa8b732006-12-10 02:21:36 -08006156 (int)(exit_qualification >> 4) & 3, cr);
6157 return 0;
6158}
6159
Avi Kivity851ba692009-08-24 11:10:17 +03006160static int handle_dr(struct kvm_vcpu *vcpu)
Avi Kivity6aa8b732006-12-10 02:21:36 -08006161{
He, Qingbfdaab02007-09-12 14:18:28 +08006162 unsigned long exit_qualification;
Nadav Amit16f8a6f2014-10-03 01:10:05 +03006163 int dr, dr7, reg;
6164
6165 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6166 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
6167
6168 /* First, if DR does not exist, trigger UD */
6169 if (!kvm_require_dr(vcpu, dr))
6170 return 1;
Avi Kivity6aa8b732006-12-10 02:21:36 -08006171
Jan Kiszkaf2483412010-01-20 18:20:20 +01006172 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
Avi Kivity0a79b002009-09-01 12:03:25 +03006173 if (!kvm_require_cpl(vcpu, 0))
6174 return 1;
Nadav Amit16f8a6f2014-10-03 01:10:05 +03006175 dr7 = vmcs_readl(GUEST_DR7);
6176 if (dr7 & DR7_GD) {
Jan Kiszka42dbaa52008-12-15 13:52:10 +01006177 /*
6178 * As the vm-exit takes precedence over the debug trap, we
6179 * need to emulate the latter, either for the host or the
6180 * guest debugging itself.
6181 */
6182 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
Avi Kivity851ba692009-08-24 11:10:17 +03006183 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
Nadav Amit16f8a6f2014-10-03 01:10:05 +03006184 vcpu->run->debug.arch.dr7 = dr7;
Nadav Amit82b32772014-11-02 11:54:45 +02006185 vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
Avi Kivity851ba692009-08-24 11:10:17 +03006186 vcpu->run->debug.arch.exception = DB_VECTOR;
6187 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
Jan Kiszka42dbaa52008-12-15 13:52:10 +01006188 return 0;
6189 } else {
Nadav Amit7305eb52014-11-02 11:54:44 +02006190 vcpu->arch.dr6 &= ~15;
Nadav Amit6f43ed02014-07-15 17:37:46 +03006191 vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
Jan Kiszka42dbaa52008-12-15 13:52:10 +01006192 kvm_queue_exception(vcpu, DB_VECTOR);
6193 return 1;
6194 }
6195 }
6196
Paolo Bonzini81908bf2014-02-21 10:32:27 +01006197 if (vcpu->guest_debug == 0) {
Paolo Bonzini8f223722016-02-26 12:09:49 +01006198 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
6199 CPU_BASED_MOV_DR_EXITING);
Paolo Bonzini81908bf2014-02-21 10:32:27 +01006200
6201 /*
6202 * No more DR vmexits; force a reload of the debug registers
6203 * and reenter on this instruction. The next vmexit will
6204 * retrieve the full state of the debug registers.
6205 */
6206 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
6207 return 1;
6208 }
6209
Jan Kiszka42dbaa52008-12-15 13:52:10 +01006210 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
6211 if (exit_qualification & TYPE_MOV_FROM_DR) {
Gleb Natapov020df072010-04-13 10:05:23 +03006212 unsigned long val;
Jan Kiszka4c4d5632013-12-18 19:16:24 +01006213
6214 if (kvm_get_dr(vcpu, dr, &val))
6215 return 1;
6216 kvm_register_write(vcpu, reg, val);
Gleb Natapov020df072010-04-13 10:05:23 +03006217 } else
Nadav Amit57773922014-06-18 17:19:23 +03006218 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
Jan Kiszka4c4d5632013-12-18 19:16:24 +01006219 return 1;
6220
Avi Kivity6aa8b732006-12-10 02:21:36 -08006221 skip_emulated_instruction(vcpu);
6222 return 1;
6223}
6224
Jan Kiszka73aaf249e2014-01-04 18:47:16 +01006225static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
6226{
6227 return vcpu->arch.dr6;
6228}
6229
6230static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
6231{
6232}
6233
Paolo Bonzini81908bf2014-02-21 10:32:27 +01006234static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
6235{
Paolo Bonzini81908bf2014-02-21 10:32:27 +01006236 get_debugreg(vcpu->arch.db[0], 0);
6237 get_debugreg(vcpu->arch.db[1], 1);
6238 get_debugreg(vcpu->arch.db[2], 2);
6239 get_debugreg(vcpu->arch.db[3], 3);
6240 get_debugreg(vcpu->arch.dr6, 6);
6241 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
6242
6243 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
Paolo Bonzini8f223722016-02-26 12:09:49 +01006244 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, CPU_BASED_MOV_DR_EXITING);
Paolo Bonzini81908bf2014-02-21 10:32:27 +01006245}
6246
Gleb Natapov020df072010-04-13 10:05:23 +03006247static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
6248{
6249 vmcs_writel(GUEST_DR7, val);
6250}
6251
Avi Kivity851ba692009-08-24 11:10:17 +03006252static int handle_cpuid(struct kvm_vcpu *vcpu)
Avi Kivity6aa8b732006-12-10 02:21:36 -08006253{
Avi Kivity06465c52007-02-28 20:46:53 +02006254 kvm_emulate_cpuid(vcpu);
6255 return 1;
Avi Kivity6aa8b732006-12-10 02:21:36 -08006256}
6257
Avi Kivity851ba692009-08-24 11:10:17 +03006258static int handle_rdmsr(struct kvm_vcpu *vcpu)
Avi Kivity6aa8b732006-12-10 02:21:36 -08006259{
Zhang Xiantaoad312c72007-12-13 23:50:52 +08006260 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
Paolo Bonzini609e36d2015-04-08 15:30:38 +02006261 struct msr_data msr_info;
Avi Kivity6aa8b732006-12-10 02:21:36 -08006262
Paolo Bonzini609e36d2015-04-08 15:30:38 +02006263 msr_info.index = ecx;
6264 msr_info.host_initiated = false;
6265 if (vmx_get_msr(vcpu, &msr_info)) {
Avi Kivity59200272010-01-25 19:47:02 +02006266 trace_kvm_msr_read_ex(ecx);
Avi Kivityc1a5d4f2007-11-25 14:12:03 +02006267 kvm_inject_gp(vcpu, 0);
Avi Kivity6aa8b732006-12-10 02:21:36 -08006268 return 1;
6269 }
6270
Paolo Bonzini609e36d2015-04-08 15:30:38 +02006271 trace_kvm_msr_read(ecx, msr_info.data);
Feng (Eric) Liu2714d1d2008-04-10 15:31:10 -04006272
Avi Kivity6aa8b732006-12-10 02:21:36 -08006273 /* FIXME: handling of bits 32:63 of rax, rdx */
Paolo Bonzini609e36d2015-04-08 15:30:38 +02006274 vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u;
6275 vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u;
Avi Kivity6aa8b732006-12-10 02:21:36 -08006276 skip_emulated_instruction(vcpu);
6277 return 1;
6278}
6279
Avi Kivity851ba692009-08-24 11:10:17 +03006280static int handle_wrmsr(struct kvm_vcpu *vcpu)
Avi Kivity6aa8b732006-12-10 02:21:36 -08006281{
Will Auld8fe8ab42012-11-29 12:42:12 -08006282 struct msr_data msr;
Zhang Xiantaoad312c72007-12-13 23:50:52 +08006283 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6284 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
6285 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
Avi Kivity6aa8b732006-12-10 02:21:36 -08006286
Will Auld8fe8ab42012-11-29 12:42:12 -08006287 msr.data = data;
6288 msr.index = ecx;
6289 msr.host_initiated = false;
Nadav Amit854e8bb2014-09-16 03:24:05 +03006290 if (kvm_set_msr(vcpu, &msr) != 0) {
Avi Kivity59200272010-01-25 19:47:02 +02006291 trace_kvm_msr_write_ex(ecx, data);
Avi Kivityc1a5d4f2007-11-25 14:12:03 +02006292 kvm_inject_gp(vcpu, 0);
Avi Kivity6aa8b732006-12-10 02:21:36 -08006293 return 1;
6294 }
6295
Avi Kivity59200272010-01-25 19:47:02 +02006296 trace_kvm_msr_write(ecx, data);
Avi Kivity6aa8b732006-12-10 02:21:36 -08006297 skip_emulated_instruction(vcpu);
6298 return 1;
6299}
6300
Avi Kivity851ba692009-08-24 11:10:17 +03006301static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
Yang, Sheng6e5d8652007-09-12 18:03:11 +08006302{
Avi Kivity3842d132010-07-27 12:30:24 +03006303 kvm_make_request(KVM_REQ_EVENT, vcpu);
Yang, Sheng6e5d8652007-09-12 18:03:11 +08006304 return 1;
6305}
6306
Avi Kivity851ba692009-08-24 11:10:17 +03006307static int handle_interrupt_window(struct kvm_vcpu *vcpu)
Avi Kivity6aa8b732006-12-10 02:21:36 -08006308{
Eddie Dong85f455f2007-07-06 12:20:49 +03006309 u32 cpu_based_vm_exec_control;
6310
6311 /* clear pending irq */
6312 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
6313 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
6314 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
Feng (Eric) Liu2714d1d2008-04-10 15:31:10 -04006315
Avi Kivity3842d132010-07-27 12:30:24 +03006316 kvm_make_request(KVM_REQ_EVENT, vcpu);
6317
Jan Kiszkaa26bf122008-09-26 09:30:45 +02006318 ++vcpu->stat.irq_window_exits;
Avi Kivity6aa8b732006-12-10 02:21:36 -08006319 return 1;
6320}
6321
Avi Kivity851ba692009-08-24 11:10:17 +03006322static int handle_halt(struct kvm_vcpu *vcpu)
Avi Kivity6aa8b732006-12-10 02:21:36 -08006323{
Avi Kivityd3bef152007-06-05 15:53:05 +03006324 return kvm_emulate_halt(vcpu);
Avi Kivity6aa8b732006-12-10 02:21:36 -08006325}
6326
Avi Kivity851ba692009-08-24 11:10:17 +03006327static int handle_vmcall(struct kvm_vcpu *vcpu)
Ingo Molnarc21415e2007-02-19 14:37:47 +02006328{
Andrey Smetanin0d9c0552016-02-11 16:44:59 +03006329 return kvm_emulate_hypercall(vcpu);
Ingo Molnarc21415e2007-02-19 14:37:47 +02006330}
6331
Gleb Natapovec25d5e2010-11-01 15:35:01 +02006332static int handle_invd(struct kvm_vcpu *vcpu)
6333{
Andre Przywara51d8b662010-12-21 11:12:02 +01006334 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
Gleb Natapovec25d5e2010-11-01 15:35:01 +02006335}
6336
Avi Kivity851ba692009-08-24 11:10:17 +03006337static int handle_invlpg(struct kvm_vcpu *vcpu)
Marcelo Tosattia7052892008-09-23 13:18:35 -03006338{
Sheng Yangf9c617f2009-03-25 10:08:52 +08006339 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
Marcelo Tosattia7052892008-09-23 13:18:35 -03006340
6341 kvm_mmu_invlpg(vcpu, exit_qualification);
6342 skip_emulated_instruction(vcpu);
6343 return 1;
6344}
6345
Avi Kivityfee84b02011-11-10 14:57:25 +02006346static int handle_rdpmc(struct kvm_vcpu *vcpu)
6347{
6348 int err;
6349
6350 err = kvm_rdpmc(vcpu);
6351 kvm_complete_insn_gp(vcpu, err);
6352
6353 return 1;
6354}
6355
Avi Kivity851ba692009-08-24 11:10:17 +03006356static int handle_wbinvd(struct kvm_vcpu *vcpu)
Eddie Donge5edaa02007-11-11 12:28:35 +02006357{
Sheng Yangf5f48ee2010-06-30 12:25:15 +08006358 kvm_emulate_wbinvd(vcpu);
Eddie Donge5edaa02007-11-11 12:28:35 +02006359 return 1;
6360}
6361
Dexuan Cui2acf9232010-06-10 11:27:12 +08006362static int handle_xsetbv(struct kvm_vcpu *vcpu)
6363{
6364 u64 new_bv = kvm_read_edx_eax(vcpu);
6365 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
6366
6367 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
6368 skip_emulated_instruction(vcpu);
6369 return 1;
6370}
6371
Wanpeng Lif53cd632014-12-02 19:14:58 +08006372static int handle_xsaves(struct kvm_vcpu *vcpu)
6373{
6374 skip_emulated_instruction(vcpu);
6375 WARN(1, "this should never happen\n");
6376 return 1;
6377}
6378
6379static int handle_xrstors(struct kvm_vcpu *vcpu)
6380{
6381 skip_emulated_instruction(vcpu);
6382 WARN(1, "this should never happen\n");
6383 return 1;
6384}
6385
Avi Kivity851ba692009-08-24 11:10:17 +03006386static int handle_apic_access(struct kvm_vcpu *vcpu)
Sheng Yangf78e0e22007-10-29 09:40:42 +08006387{
Kevin Tian58fbbf22011-08-30 13:56:17 +03006388 if (likely(fasteoi)) {
6389 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6390 int access_type, offset;
6391
6392 access_type = exit_qualification & APIC_ACCESS_TYPE;
6393 offset = exit_qualification & APIC_ACCESS_OFFSET;
6394 /*
6395 * Sane guest uses MOV to write EOI, with written value
6396 * not cared. So make a short-circuit here by avoiding
6397 * heavy instruction emulation.
6398 */
6399 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
6400 (offset == APIC_EOI)) {
6401 kvm_lapic_set_eoi(vcpu);
6402 skip_emulated_instruction(vcpu);
6403 return 1;
6404 }
6405 }
Andre Przywara51d8b662010-12-21 11:12:02 +01006406 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
Sheng Yangf78e0e22007-10-29 09:40:42 +08006407}
6408
Yang Zhangc7c9c562013-01-25 10:18:51 +08006409static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
6410{
6411 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6412 int vector = exit_qualification & 0xff;
6413
6414 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
6415 kvm_apic_set_eoi_accelerated(vcpu, vector);
6416 return 1;
6417}
6418
Yang Zhang83d4c282013-01-25 10:18:49 +08006419static int handle_apic_write(struct kvm_vcpu *vcpu)
6420{
6421 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6422 u32 offset = exit_qualification & 0xfff;
6423
6424 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
6425 kvm_apic_write_nodecode(vcpu, offset);
6426 return 1;
6427}
6428
Avi Kivity851ba692009-08-24 11:10:17 +03006429static int handle_task_switch(struct kvm_vcpu *vcpu)
Izik Eidus37817f22008-03-24 23:14:53 +02006430{
Jan Kiszka60637aa2008-09-26 09:30:47 +02006431 struct vcpu_vmx *vmx = to_vmx(vcpu);
Izik Eidus37817f22008-03-24 23:14:53 +02006432 unsigned long exit_qualification;
Jan Kiszkae269fb22010-04-14 15:51:09 +02006433 bool has_error_code = false;
6434 u32 error_code = 0;
Izik Eidus37817f22008-03-24 23:14:53 +02006435 u16 tss_selector;
Kevin Wolf7f3d35f2012-02-08 14:34:38 +01006436 int reason, type, idt_v, idt_index;
Gleb Natapov64a7ec02009-03-30 16:03:29 +03006437
6438 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
Kevin Wolf7f3d35f2012-02-08 14:34:38 +01006439 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
Gleb Natapov64a7ec02009-03-30 16:03:29 +03006440 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
Izik Eidus37817f22008-03-24 23:14:53 +02006441
6442 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6443
6444 reason = (u32)exit_qualification >> 30;
Gleb Natapov64a7ec02009-03-30 16:03:29 +03006445 if (reason == TASK_SWITCH_GATE && idt_v) {
6446 switch (type) {
6447 case INTR_TYPE_NMI_INTR:
6448 vcpu->arch.nmi_injected = false;
Avi Kivity654f06f2011-03-23 15:02:47 +02006449 vmx_set_nmi_mask(vcpu, true);
Gleb Natapov64a7ec02009-03-30 16:03:29 +03006450 break;
6451 case INTR_TYPE_EXT_INTR:
Gleb Natapov66fd3f72009-05-11 13:35:50 +03006452 case INTR_TYPE_SOFT_INTR:
Gleb Natapov64a7ec02009-03-30 16:03:29 +03006453 kvm_clear_interrupt_queue(vcpu);
6454 break;
6455 case INTR_TYPE_HARD_EXCEPTION:
Jan Kiszkae269fb22010-04-14 15:51:09 +02006456 if (vmx->idt_vectoring_info &
6457 VECTORING_INFO_DELIVER_CODE_MASK) {
6458 has_error_code = true;
6459 error_code =
6460 vmcs_read32(IDT_VECTORING_ERROR_CODE);
6461 }
6462 /* fall through */
Gleb Natapov64a7ec02009-03-30 16:03:29 +03006463 case INTR_TYPE_SOFT_EXCEPTION:
6464 kvm_clear_exception_queue(vcpu);
6465 break;
6466 default:
6467 break;
6468 }
Jan Kiszka60637aa2008-09-26 09:30:47 +02006469 }
Izik Eidus37817f22008-03-24 23:14:53 +02006470 tss_selector = exit_qualification;
6471
Gleb Natapov64a7ec02009-03-30 16:03:29 +03006472 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
6473 type != INTR_TYPE_EXT_INTR &&
6474 type != INTR_TYPE_NMI_INTR))
6475 skip_emulated_instruction(vcpu);
6476
Kevin Wolf7f3d35f2012-02-08 14:34:38 +01006477 if (kvm_task_switch(vcpu, tss_selector,
6478 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
6479 has_error_code, error_code) == EMULATE_FAIL) {
Gleb Natapovacb54512010-04-15 21:03:50 +03006480 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6481 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6482 vcpu->run->internal.ndata = 0;
Jan Kiszka42dbaa52008-12-15 13:52:10 +01006483 return 0;
Gleb Natapovacb54512010-04-15 21:03:50 +03006484 }
Jan Kiszka42dbaa52008-12-15 13:52:10 +01006485
Jan Kiszka42dbaa52008-12-15 13:52:10 +01006486 /*
6487 * TODO: What about debug traps on tss switch?
6488 * Are we supposed to inject them and update dr6?
6489 */
6490
6491 return 1;
Izik Eidus37817f22008-03-24 23:14:53 +02006492}
6493
Avi Kivity851ba692009-08-24 11:10:17 +03006494static int handle_ept_violation(struct kvm_vcpu *vcpu)
Sheng Yang14394422008-04-28 12:24:45 +08006495{
Sheng Yangf9c617f2009-03-25 10:08:52 +08006496 unsigned long exit_qualification;
Sheng Yang14394422008-04-28 12:24:45 +08006497 gpa_t gpa;
Xiao Guangrong4f5982a2012-06-20 15:58:04 +08006498 u32 error_code;
Sheng Yang14394422008-04-28 12:24:45 +08006499 int gla_validity;
Sheng Yang14394422008-04-28 12:24:45 +08006500
Sheng Yangf9c617f2009-03-25 10:08:52 +08006501 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
Sheng Yang14394422008-04-28 12:24:45 +08006502
Sheng Yang14394422008-04-28 12:24:45 +08006503 gla_validity = (exit_qualification >> 7) & 0x3;
Liang Li72e0ae52016-08-18 15:49:19 +08006504 if (gla_validity == 0x2) {
Sheng Yang14394422008-04-28 12:24:45 +08006505 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
6506 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
6507 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
Sheng Yangf9c617f2009-03-25 10:08:52 +08006508 vmcs_readl(GUEST_LINEAR_ADDRESS));
Sheng Yang14394422008-04-28 12:24:45 +08006509 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
6510 (long unsigned int)exit_qualification);
Avi Kivity851ba692009-08-24 11:10:17 +03006511 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6512 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
Avi Kivity596ae892009-06-03 14:12:10 +03006513 return 0;
Sheng Yang14394422008-04-28 12:24:45 +08006514 }
6515
Gleb Natapov0be9c7a2013-09-15 11:07:23 +03006516 /*
6517 * EPT violation happened while executing iret from NMI,
6518 * "blocked by NMI" bit has to be set before next VM entry.
6519 * There are errata that may cause this bit to not be set:
6520 * AAK134, BY25.
6521 */
Gleb Natapovbcd1c292013-09-25 10:58:22 +03006522 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
6523 cpu_has_virtual_nmis() &&
6524 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
Gleb Natapov0be9c7a2013-09-15 11:07:23 +03006525 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
6526
Sheng Yang14394422008-04-28 12:24:45 +08006527 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
Marcelo Tosatti229456f2009-06-17 09:22:14 -03006528 trace_kvm_page_fault(gpa, exit_qualification);
Xiao Guangrong4f5982a2012-06-20 15:58:04 +08006529
Bandan Dasd95c5562016-07-12 18:18:51 -04006530 /* it is a read fault? */
6531 error_code = (exit_qualification << 2) & PFERR_USER_MASK;
6532 /* it is a write fault? */
6533 error_code |= exit_qualification & PFERR_WRITE_MASK;
Yang Zhang25d92082013-08-06 12:00:32 +03006534 /* It is a fetch fault? */
Tiejun Chen81ed33e2014-11-18 17:12:56 +08006535 error_code |= (exit_qualification << 2) & PFERR_FETCH_MASK;
Xiao Guangrong4f5982a2012-06-20 15:58:04 +08006536 /* ept page table is present? */
Bandan Dasd95c5562016-07-12 18:18:51 -04006537 error_code |= (exit_qualification & 0x38) != 0;
Xiao Guangrong4f5982a2012-06-20 15:58:04 +08006538
Yang Zhang25d92082013-08-06 12:00:32 +03006539 vcpu->arch.exit_qualification = exit_qualification;
6540
Xiao Guangrong4f5982a2012-06-20 15:58:04 +08006541 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
Sheng Yang14394422008-04-28 12:24:45 +08006542}
6543
Avi Kivity851ba692009-08-24 11:10:17 +03006544static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
Marcelo Tosatti68f89402009-06-11 12:07:43 -03006545{
Xiao Guangrongf735d4a2015-08-05 12:04:27 +08006546 int ret;
Marcelo Tosatti68f89402009-06-11 12:07:43 -03006547 gpa_t gpa;
6548
6549 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
Nikolay Nikolaeve32edf42015-03-26 14:39:28 +00006550 if (!kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
Michael S. Tsirkin68c3b4d2014-03-31 21:50:44 +03006551 skip_emulated_instruction(vcpu);
Jason Wang931c33b2015-09-15 14:41:58 +08006552 trace_kvm_fast_mmio(gpa);
Michael S. Tsirkin68c3b4d2014-03-31 21:50:44 +03006553 return 1;
6554 }
Marcelo Tosatti68f89402009-06-11 12:07:43 -03006555
Paolo Bonzini450869d2015-11-04 13:41:21 +01006556 ret = handle_mmio_page_fault(vcpu, gpa, true);
Xiao Guangrongb37fbea2013-06-07 16:51:25 +08006557 if (likely(ret == RET_MMIO_PF_EMULATE))
Xiao Guangrongce88dec2011-07-12 03:33:44 +08006558 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
6559 EMULATE_DONE;
Xiao Guangrongf8f55942013-06-07 16:51:26 +08006560
6561 if (unlikely(ret == RET_MMIO_PF_INVALID))
6562 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
6563
Xiao Guangrongb37fbea2013-06-07 16:51:25 +08006564 if (unlikely(ret == RET_MMIO_PF_RETRY))
Xiao Guangrongce88dec2011-07-12 03:33:44 +08006565 return 1;
6566
6567 /* It is the real ept misconfig */
Xiao Guangrongf735d4a2015-08-05 12:04:27 +08006568 WARN_ON(1);
Marcelo Tosatti68f89402009-06-11 12:07:43 -03006569
Avi Kivity851ba692009-08-24 11:10:17 +03006570 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6571 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
Marcelo Tosatti68f89402009-06-11 12:07:43 -03006572
6573 return 0;
6574}
6575
Avi Kivity851ba692009-08-24 11:10:17 +03006576static int handle_nmi_window(struct kvm_vcpu *vcpu)
Sheng Yangf08864b2008-05-15 18:23:25 +08006577{
6578 u32 cpu_based_vm_exec_control;
6579
6580 /* clear pending NMI */
6581 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
6582 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
6583 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
6584 ++vcpu->stat.nmi_window_exits;
Avi Kivity3842d132010-07-27 12:30:24 +03006585 kvm_make_request(KVM_REQ_EVENT, vcpu);
Sheng Yangf08864b2008-05-15 18:23:25 +08006586
6587 return 1;
6588}
6589
Mohammed Gamal80ced182009-09-01 12:48:18 +02006590static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
Mohammed Gamalea953ef2008-08-17 16:47:05 +03006591{
Avi Kivity8b3079a2009-01-05 12:10:54 +02006592 struct vcpu_vmx *vmx = to_vmx(vcpu);
6593 enum emulation_result err = EMULATE_DONE;
Mohammed Gamal80ced182009-09-01 12:48:18 +02006594 int ret = 1;
Avi Kivity49e9d552010-09-19 14:34:08 +02006595 u32 cpu_exec_ctrl;
6596 bool intr_window_requested;
Avi Kivityb8405c12012-06-07 17:08:48 +03006597 unsigned count = 130;
Avi Kivity49e9d552010-09-19 14:34:08 +02006598
6599 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
6600 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
Mohammed Gamalea953ef2008-08-17 16:47:05 +03006601
Paolo Bonzini98eb2f82014-03-27 09:51:52 +01006602 while (vmx->emulation_required && count-- != 0) {
Avi Kivitybdea48e2012-06-10 18:07:57 +03006603 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
Avi Kivity49e9d552010-09-19 14:34:08 +02006604 return handle_interrupt_window(&vmx->vcpu);
6605
Avi Kivityde87dcd2012-06-12 20:21:38 +03006606 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
6607 return 1;
6608
Liran Alon114de9b2017-11-05 16:56:34 +02006609 err = emulate_instruction(vcpu, 0);
Mohammed Gamalea953ef2008-08-17 16:47:05 +03006610
Paolo Bonziniac0a48c2013-06-25 18:24:41 +02006611 if (err == EMULATE_USER_EXIT) {
Paolo Bonzini94452b92013-08-27 15:41:42 +02006612 ++vcpu->stat.mmio_exits;
Mohammed Gamal80ced182009-09-01 12:48:18 +02006613 ret = 0;
6614 goto out;
6615 }
Guillaume Thouvenin1d5a4d92008-10-29 09:39:42 +01006616
Sean Christopherson94b4fed2018-03-23 09:34:00 -07006617 if (err != EMULATE_DONE)
6618 goto emulation_error;
6619
6620 if (vmx->emulation_required && !vmx->rmode.vm86_active &&
6621 vcpu->arch.exception.pending)
6622 goto emulation_error;
Mohammed Gamalea953ef2008-08-17 16:47:05 +03006623
Gleb Natapov8d76c492013-05-08 18:38:44 +03006624 if (vcpu->arch.halt_request) {
6625 vcpu->arch.halt_request = 0;
Joel Schopp5cb56052015-03-02 13:43:31 -06006626 ret = kvm_vcpu_halt(vcpu);
Gleb Natapov8d76c492013-05-08 18:38:44 +03006627 goto out;
6628 }
6629
Mohammed Gamalea953ef2008-08-17 16:47:05 +03006630 if (signal_pending(current))
Mohammed Gamal80ced182009-09-01 12:48:18 +02006631 goto out;
Mohammed Gamalea953ef2008-08-17 16:47:05 +03006632 if (need_resched())
6633 schedule();
6634 }
6635
Mohammed Gamal80ced182009-09-01 12:48:18 +02006636out:
6637 return ret;
Sean Christopherson94b4fed2018-03-23 09:34:00 -07006638
6639emulation_error:
6640 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6641 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6642 vcpu->run->internal.ndata = 0;
6643 return 0;
Mohammed Gamalea953ef2008-08-17 16:47:05 +03006644}
6645
Radim Krčmářb4a2d312014-08-21 18:08:08 +02006646static int __grow_ple_window(int val)
6647{
6648 if (ple_window_grow < 1)
6649 return ple_window;
6650
6651 val = min(val, ple_window_actual_max);
6652
6653 if (ple_window_grow < ple_window)
6654 val *= ple_window_grow;
6655 else
6656 val += ple_window_grow;
6657
6658 return val;
6659}
6660
6661static int __shrink_ple_window(int val, int modifier, int minimum)
6662{
6663 if (modifier < 1)
6664 return ple_window;
6665
6666 if (modifier < ple_window)
6667 val /= modifier;
6668 else
6669 val -= modifier;
6670
6671 return max(val, minimum);
6672}
6673
6674static void grow_ple_window(struct kvm_vcpu *vcpu)
6675{
6676 struct vcpu_vmx *vmx = to_vmx(vcpu);
6677 int old = vmx->ple_window;
6678
6679 vmx->ple_window = __grow_ple_window(old);
6680
6681 if (vmx->ple_window != old)
6682 vmx->ple_window_dirty = true;
Radim Krčmář7b462682014-08-21 18:08:09 +02006683
6684 trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
Radim Krčmářb4a2d312014-08-21 18:08:08 +02006685}
6686
6687static void shrink_ple_window(struct kvm_vcpu *vcpu)
6688{
6689 struct vcpu_vmx *vmx = to_vmx(vcpu);
6690 int old = vmx->ple_window;
6691
6692 vmx->ple_window = __shrink_ple_window(old,
6693 ple_window_shrink, ple_window);
6694
6695 if (vmx->ple_window != old)
6696 vmx->ple_window_dirty = true;
Radim Krčmář7b462682014-08-21 18:08:09 +02006697
6698 trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
Radim Krčmářb4a2d312014-08-21 18:08:08 +02006699}
6700
6701/*
6702 * ple_window_actual_max is computed to be one grow_ple_window() below
6703 * ple_window_max. (See __grow_ple_window for the reason.)
6704 * This prevents overflows, because ple_window_max is int.
6705 * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6706 * this process.
6707 * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6708 */
6709static void update_ple_window_actual_max(void)
6710{
6711 ple_window_actual_max =
6712 __shrink_ple_window(max(ple_window_max, ple_window),
6713 ple_window_grow, INT_MIN);
6714}
6715
Feng Wubf9f6ac2015-09-18 22:29:55 +08006716/*
6717 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6718 */
6719static void wakeup_handler(void)
6720{
6721 struct kvm_vcpu *vcpu;
6722 int cpu = smp_processor_id();
6723
6724 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6725 list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
6726 blocked_vcpu_list) {
6727 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
6728
6729 if (pi_test_on(pi_desc) == 1)
6730 kvm_vcpu_kick(vcpu);
6731 }
6732 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6733}
6734
Tiejun Chenf2c76482014-10-28 10:14:47 +08006735static __init int hardware_setup(void)
6736{
Paolo Bonzini6236b782018-01-16 16:51:18 +01006737 int r = -ENOMEM, i;
Tiejun Chen34a1cd62014-10-28 10:14:48 +08006738
6739 rdmsrl_safe(MSR_EFER, &host_efer);
6740
6741 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
6742 kvm_define_shared_msr(i, vmx_msr_index[i]);
6743
6744 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
6745 if (!vmx_io_bitmap_a)
6746 return r;
6747
6748 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
6749 if (!vmx_io_bitmap_b)
6750 goto out;
6751
Tiejun Chen34a1cd62014-10-28 10:14:48 +08006752 vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6753 if (!vmx_vmread_bitmap)
Paolo Bonzini6236b782018-01-16 16:51:18 +01006754 goto out1;
Tiejun Chen34a1cd62014-10-28 10:14:48 +08006755
6756 vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6757 if (!vmx_vmwrite_bitmap)
Paolo Bonzini6236b782018-01-16 16:51:18 +01006758 goto out2;
Tiejun Chen34a1cd62014-10-28 10:14:48 +08006759
6760 memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
6761 memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
6762
Tiejun Chen34a1cd62014-10-28 10:14:48 +08006763 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
Tiejun Chen34a1cd62014-10-28 10:14:48 +08006764
6765 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
6766
Tiejun Chen34a1cd62014-10-28 10:14:48 +08006767 if (setup_vmcs_config(&vmcs_config) < 0) {
6768 r = -EIO;
Paolo Bonzini6236b782018-01-16 16:51:18 +01006769 goto out3;
Tiejun Chenbaa03522014-12-23 16:21:11 +08006770 }
Tiejun Chenf2c76482014-10-28 10:14:47 +08006771
6772 if (boot_cpu_has(X86_FEATURE_NX))
6773 kvm_enable_efer_bits(EFER_NX);
6774
Wanpeng Li2df19692017-03-23 05:30:08 -07006775 if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
6776 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
Tiejun Chenf2c76482014-10-28 10:14:47 +08006777 enable_vpid = 0;
Wanpeng Li2df19692017-03-23 05:30:08 -07006778
Tiejun Chenf2c76482014-10-28 10:14:47 +08006779 if (!cpu_has_vmx_shadow_vmcs())
6780 enable_shadow_vmcs = 0;
6781 if (enable_shadow_vmcs)
6782 init_vmcs_shadow_fields();
6783
6784 if (!cpu_has_vmx_ept() ||
6785 !cpu_has_vmx_ept_4levels()) {
6786 enable_ept = 0;
6787 enable_unrestricted_guest = 0;
6788 enable_ept_ad_bits = 0;
6789 }
6790
6791 if (!cpu_has_vmx_ept_ad_bits())
6792 enable_ept_ad_bits = 0;
6793
6794 if (!cpu_has_vmx_unrestricted_guest())
6795 enable_unrestricted_guest = 0;
6796
Paolo Bonziniad15a292015-01-30 16:18:49 +01006797 if (!cpu_has_vmx_flexpriority())
Tiejun Chenf2c76482014-10-28 10:14:47 +08006798 flexpriority_enabled = 0;
6799
Paolo Bonziniad15a292015-01-30 16:18:49 +01006800 /*
6801 * set_apic_access_page_addr() is used to reload apic access
6802 * page upon invalidation. No need to do anything if not
6803 * using the APIC_ACCESS_ADDR VMCS field.
6804 */
6805 if (!flexpriority_enabled)
Tiejun Chenf2c76482014-10-28 10:14:47 +08006806 kvm_x86_ops->set_apic_access_page_addr = NULL;
Tiejun Chenf2c76482014-10-28 10:14:47 +08006807
6808 if (!cpu_has_vmx_tpr_shadow())
6809 kvm_x86_ops->update_cr8_intercept = NULL;
6810
6811 if (enable_ept && !cpu_has_vmx_ept_2m_page())
6812 kvm_disable_largepages();
6813
6814 if (!cpu_has_vmx_ple())
6815 ple_gap = 0;
6816
6817 if (!cpu_has_vmx_apicv())
6818 enable_apicv = 0;
6819
Haozhong Zhang64903d62015-10-20 15:39:09 +08006820 if (cpu_has_vmx_tsc_scaling()) {
6821 kvm_has_tsc_control = true;
6822 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
6823 kvm_tsc_scaling_ratio_frac_bits = 48;
6824 }
6825
Wanpeng Li04bb92e2015-09-16 19:31:11 +08006826 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
6827
Tiejun Chenbaa03522014-12-23 16:21:11 +08006828 if (enable_ept) {
Bandan Dasd95c5562016-07-12 18:18:51 -04006829 kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK,
Tiejun Chenbaa03522014-12-23 16:21:11 +08006830 (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
6831 (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
Bandan Dasd95c5562016-07-12 18:18:51 -04006832 0ull, VMX_EPT_EXECUTABLE_MASK,
6833 cpu_has_vmx_ept_execute_only() ?
6834 0ull : VMX_EPT_READABLE_MASK);
Tiejun Chenbaa03522014-12-23 16:21:11 +08006835 ept_set_mmio_spte_mask();
6836 kvm_enable_tdp();
6837 } else
6838 kvm_disable_tdp();
6839
6840 update_ple_window_actual_max();
6841
Kai Huang843e4332015-01-28 10:54:28 +08006842 /*
6843 * Only enable PML when hardware supports PML feature, and both EPT
6844 * and EPT A/D bit features are enabled -- PML depends on them to work.
6845 */
6846 if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
6847 enable_pml = 0;
6848
6849 if (!enable_pml) {
6850 kvm_x86_ops->slot_enable_log_dirty = NULL;
6851 kvm_x86_ops->slot_disable_log_dirty = NULL;
6852 kvm_x86_ops->flush_log_dirty = NULL;
6853 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
6854 }
6855
Yunhong Jiang64672c92016-06-13 14:19:59 -07006856 if (cpu_has_vmx_preemption_timer() && enable_preemption_timer) {
6857 u64 vmx_msr;
6858
6859 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
6860 cpu_preemption_timer_multi =
6861 vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
6862 } else {
6863 kvm_x86_ops->set_hv_timer = NULL;
6864 kvm_x86_ops->cancel_hv_timer = NULL;
6865 }
6866
Feng Wubf9f6ac2015-09-18 22:29:55 +08006867 kvm_set_posted_intr_wakeup_handler(wakeup_handler);
6868
Ashok Rajc45dcc72016-06-22 14:59:56 +08006869 kvm_mce_cap_supported |= MCG_LMCE_P;
6870
Tiejun Chenf2c76482014-10-28 10:14:47 +08006871 return alloc_kvm_area();
Tiejun Chen34a1cd62014-10-28 10:14:48 +08006872
Tiejun Chen34a1cd62014-10-28 10:14:48 +08006873out3:
Paolo Bonzini6236b782018-01-16 16:51:18 +01006874 free_page((unsigned long)vmx_vmwrite_bitmap);
Tiejun Chen34a1cd62014-10-28 10:14:48 +08006875out2:
Paolo Bonzini6236b782018-01-16 16:51:18 +01006876 free_page((unsigned long)vmx_vmread_bitmap);
Tiejun Chen34a1cd62014-10-28 10:14:48 +08006877out1:
6878 free_page((unsigned long)vmx_io_bitmap_b);
6879out:
6880 free_page((unsigned long)vmx_io_bitmap_a);
6881
6882 return r;
Tiejun Chenf2c76482014-10-28 10:14:47 +08006883}
6884
6885static __exit void hardware_unsetup(void)
6886{
Tiejun Chen34a1cd62014-10-28 10:14:48 +08006887 free_page((unsigned long)vmx_io_bitmap_b);
6888 free_page((unsigned long)vmx_io_bitmap_a);
6889 free_page((unsigned long)vmx_vmwrite_bitmap);
6890 free_page((unsigned long)vmx_vmread_bitmap);
6891
Tiejun Chenf2c76482014-10-28 10:14:47 +08006892 free_kvm_area();
6893}
6894
Avi Kivity6aa8b732006-12-10 02:21:36 -08006895/*
Zhai, Edwin4b8d54f2009-10-09 18:03:20 +08006896 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6897 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6898 */
Marcelo Tosatti9fb41ba2009-10-12 19:37:31 -03006899static int handle_pause(struct kvm_vcpu *vcpu)
Zhai, Edwin4b8d54f2009-10-09 18:03:20 +08006900{
Radim Krčmářb4a2d312014-08-21 18:08:08 +02006901 if (ple_gap)
6902 grow_ple_window(vcpu);
6903
Zhai, Edwin4b8d54f2009-10-09 18:03:20 +08006904 skip_emulated_instruction(vcpu);
6905 kvm_vcpu_on_spin(vcpu);
6906
6907 return 1;
6908}
6909
Gabriel L. Somlo87c00572014-05-07 16:52:13 -04006910static int handle_nop(struct kvm_vcpu *vcpu)
Sheng Yang59708672009-12-15 13:29:54 +08006911{
Gabriel L. Somlo87c00572014-05-07 16:52:13 -04006912 skip_emulated_instruction(vcpu);
Sheng Yang59708672009-12-15 13:29:54 +08006913 return 1;
6914}
6915
Gabriel L. Somlo87c00572014-05-07 16:52:13 -04006916static int handle_mwait(struct kvm_vcpu *vcpu)
6917{
6918 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
6919 return handle_nop(vcpu);
6920}
6921
Mihai Donțu5f3d45e2015-07-05 20:08:57 +03006922static int handle_monitor_trap(struct kvm_vcpu *vcpu)
6923{
6924 return 1;
6925}
6926
Gabriel L. Somlo87c00572014-05-07 16:52:13 -04006927static int handle_monitor(struct kvm_vcpu *vcpu)
6928{
6929 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
6930 return handle_nop(vcpu);
6931}
6932
Zhai, Edwin4b8d54f2009-10-09 18:03:20 +08006933/*
Arthur Chunqi Li0658fba2013-07-04 15:03:32 +08006934 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6935 * set the success or error code of an emulated VMX instruction, as specified
6936 * by Vol 2B, VMX Instruction Reference, "Conventions".
6937 */
6938static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
6939{
6940 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
6941 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6942 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
6943}
6944
6945static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
6946{
6947 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6948 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
6949 X86_EFLAGS_SF | X86_EFLAGS_OF))
6950 | X86_EFLAGS_CF);
6951}
6952
Abel Gordon145c28d2013-04-18 14:36:55 +03006953static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
Arthur Chunqi Li0658fba2013-07-04 15:03:32 +08006954 u32 vm_instruction_error)
6955{
6956 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
6957 /*
6958 * failValid writes the error number to the current VMCS, which
6959 * can't be done there isn't a current VMCS.
6960 */
6961 nested_vmx_failInvalid(vcpu);
6962 return;
6963 }
6964 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6965 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6966 X86_EFLAGS_SF | X86_EFLAGS_OF))
6967 | X86_EFLAGS_ZF);
6968 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
6969 /*
6970 * We don't need to force a shadow sync because
6971 * VM_INSTRUCTION_ERROR is not shadowed
6972 */
6973}
Abel Gordon145c28d2013-04-18 14:36:55 +03006974
Wincy Vanff651cb2014-12-11 08:52:58 +03006975static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
6976{
6977 /* TODO: not to reset guest simply here. */
6978 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
Paolo Bonzinibbe41b92016-08-19 17:51:20 +02006979 pr_debug_ratelimited("kvm: nested vmx abort, indicator %d\n", indicator);
Wincy Vanff651cb2014-12-11 08:52:58 +03006980}
6981
Jan Kiszkaf4124502014-03-07 20:03:13 +01006982static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
6983{
6984 struct vcpu_vmx *vmx =
6985 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
6986
6987 vmx->nested.preemption_timer_expired = true;
6988 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6989 kvm_vcpu_kick(&vmx->vcpu);
6990
6991 return HRTIMER_NORESTART;
6992}
6993
Nadav Har'Elff2f6fe2011-05-25 23:05:27 +03006994/*
Bandan Das19677e32014-05-06 02:19:15 -04006995 * Decode the memory-address operand of a vmx instruction, as recorded on an
6996 * exit caused by such an instruction (run by a guest hypervisor).
6997 * On success, returns 0. When the operand is invalid, returns 1 and throws
6998 * #UD or #GP.
6999 */
7000static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
7001 unsigned long exit_qualification,
Eugene Korenevskyf9eb4af2015-04-17 02:22:21 +00007002 u32 vmx_instruction_info, bool wr, gva_t *ret)
Bandan Das19677e32014-05-06 02:19:15 -04007003{
Eugene Korenevskyf9eb4af2015-04-17 02:22:21 +00007004 gva_t off;
7005 bool exn;
7006 struct kvm_segment s;
7007
Bandan Das19677e32014-05-06 02:19:15 -04007008 /*
7009 * According to Vol. 3B, "Information for VM Exits Due to Instruction
7010 * Execution", on an exit, vmx_instruction_info holds most of the
7011 * addressing components of the operand. Only the displacement part
7012 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
7013 * For how an actual address is calculated from all these components,
7014 * refer to Vol. 1, "Operand Addressing".
7015 */
7016 int scaling = vmx_instruction_info & 3;
7017 int addr_size = (vmx_instruction_info >> 7) & 7;
7018 bool is_reg = vmx_instruction_info & (1u << 10);
7019 int seg_reg = (vmx_instruction_info >> 15) & 7;
7020 int index_reg = (vmx_instruction_info >> 18) & 0xf;
7021 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
7022 int base_reg = (vmx_instruction_info >> 23) & 0xf;
7023 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
7024
7025 if (is_reg) {
7026 kvm_queue_exception(vcpu, UD_VECTOR);
7027 return 1;
7028 }
7029
7030 /* Addr = segment_base + offset */
7031 /* offset = base + [index * scale] + displacement */
Eugene Korenevskyf9eb4af2015-04-17 02:22:21 +00007032 off = exit_qualification; /* holds the displacement */
Bandan Das19677e32014-05-06 02:19:15 -04007033 if (base_is_valid)
Eugene Korenevskyf9eb4af2015-04-17 02:22:21 +00007034 off += kvm_register_read(vcpu, base_reg);
Bandan Das19677e32014-05-06 02:19:15 -04007035 if (index_is_valid)
Eugene Korenevskyf9eb4af2015-04-17 02:22:21 +00007036 off += kvm_register_read(vcpu, index_reg)<<scaling;
7037 vmx_get_segment(vcpu, &s, seg_reg);
7038 *ret = s.base + off;
Bandan Das19677e32014-05-06 02:19:15 -04007039
7040 if (addr_size == 1) /* 32 bit */
7041 *ret &= 0xffffffff;
7042
Eugene Korenevskyf9eb4af2015-04-17 02:22:21 +00007043 /* Checks for #GP/#SS exceptions. */
7044 exn = false;
Quentin Casasnovasff30ef42016-06-18 11:01:05 +02007045 if (is_long_mode(vcpu)) {
7046 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
7047 * non-canonical form. This is the only check on the memory
7048 * destination for long mode!
7049 */
7050 exn = is_noncanonical_address(*ret);
7051 } else if (is_protmode(vcpu)) {
Eugene Korenevskyf9eb4af2015-04-17 02:22:21 +00007052 /* Protected mode: apply checks for segment validity in the
7053 * following order:
7054 * - segment type check (#GP(0) may be thrown)
7055 * - usability check (#GP(0)/#SS(0))
7056 * - limit check (#GP(0)/#SS(0))
7057 */
7058 if (wr)
7059 /* #GP(0) if the destination operand is located in a
7060 * read-only data segment or any code segment.
7061 */
7062 exn = ((s.type & 0xa) == 0 || (s.type & 8));
7063 else
7064 /* #GP(0) if the source operand is located in an
7065 * execute-only code segment
7066 */
7067 exn = ((s.type & 0xa) == 8);
Quentin Casasnovasff30ef42016-06-18 11:01:05 +02007068 if (exn) {
7069 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
7070 return 1;
7071 }
Eugene Korenevskyf9eb4af2015-04-17 02:22:21 +00007072 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
7073 */
7074 exn = (s.unusable != 0);
7075 /* Protected mode: #GP(0)/#SS(0) if the memory
7076 * operand is outside the segment limit.
7077 */
7078 exn = exn || (off + sizeof(u64) > s.limit);
7079 }
7080 if (exn) {
7081 kvm_queue_exception_e(vcpu,
7082 seg_reg == VCPU_SREG_SS ?
7083 SS_VECTOR : GP_VECTOR,
7084 0);
7085 return 1;
7086 }
7087
Bandan Das19677e32014-05-06 02:19:15 -04007088 return 0;
7089}
7090
7091/*
Bandan Das3573e222014-05-06 02:19:16 -04007092 * This function performs the various checks including
7093 * - if it's 4KB aligned
7094 * - No bits beyond the physical address width are set
7095 * - Returns 0 on success or else 1
Bandan Das4291b582014-05-06 02:19:18 -04007096 * (Intel SDM Section 30.3)
Bandan Das3573e222014-05-06 02:19:16 -04007097 */
Bandan Das4291b582014-05-06 02:19:18 -04007098static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason,
7099 gpa_t *vmpointer)
Bandan Das3573e222014-05-06 02:19:16 -04007100{
7101 gva_t gva;
7102 gpa_t vmptr;
7103 struct x86_exception e;
7104 struct page *page;
7105 struct vcpu_vmx *vmx = to_vmx(vcpu);
7106 int maxphyaddr = cpuid_maxphyaddr(vcpu);
7107
7108 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
Eugene Korenevskyf9eb4af2015-04-17 02:22:21 +00007109 vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva))
Bandan Das3573e222014-05-06 02:19:16 -04007110 return 1;
7111
Paolo Bonzini838b0e92018-06-06 17:37:49 +02007112 if (kvm_read_guest_virt(vcpu, gva, &vmptr, sizeof(vmptr), &e)) {
Bandan Das3573e222014-05-06 02:19:16 -04007113 kvm_inject_page_fault(vcpu, &e);
7114 return 1;
7115 }
7116
7117 switch (exit_reason) {
7118 case EXIT_REASON_VMON:
7119 /*
7120 * SDM 3: 24.11.5
7121 * The first 4 bytes of VMXON region contain the supported
7122 * VMCS revision identifier
7123 *
7124 * Note - IA32_VMX_BASIC[48] will never be 1
7125 * for the nested case;
7126 * which replaces physical address width with 32
7127 *
7128 */
Fabian Frederickbc39c4d2014-06-14 23:44:29 +02007129 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
Bandan Das3573e222014-05-06 02:19:16 -04007130 nested_vmx_failInvalid(vcpu);
7131 skip_emulated_instruction(vcpu);
7132 return 1;
7133 }
7134
7135 page = nested_get_page(vcpu, vmptr);
Paolo Bonzini75465e72017-01-24 11:56:21 +01007136 if (page == NULL) {
Bandan Das3573e222014-05-06 02:19:16 -04007137 nested_vmx_failInvalid(vcpu);
Paolo Bonzini75465e72017-01-24 11:56:21 +01007138 skip_emulated_instruction(vcpu);
7139 return 1;
7140 }
7141 if (*(u32 *)kmap(page) != VMCS12_REVISION) {
Bandan Das3573e222014-05-06 02:19:16 -04007142 kunmap(page);
Paolo Bonzini75465e72017-01-24 11:56:21 +01007143 nested_release_page_clean(page);
7144 nested_vmx_failInvalid(vcpu);
Bandan Das3573e222014-05-06 02:19:16 -04007145 skip_emulated_instruction(vcpu);
7146 return 1;
7147 }
7148 kunmap(page);
Paolo Bonzini75465e72017-01-24 11:56:21 +01007149 nested_release_page_clean(page);
Bandan Das3573e222014-05-06 02:19:16 -04007150 vmx->nested.vmxon_ptr = vmptr;
7151 break;
Bandan Das4291b582014-05-06 02:19:18 -04007152 case EXIT_REASON_VMCLEAR:
Fabian Frederickbc39c4d2014-06-14 23:44:29 +02007153 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
Bandan Das4291b582014-05-06 02:19:18 -04007154 nested_vmx_failValid(vcpu,
7155 VMXERR_VMCLEAR_INVALID_ADDRESS);
7156 skip_emulated_instruction(vcpu);
7157 return 1;
7158 }
Bandan Das3573e222014-05-06 02:19:16 -04007159
Bandan Das4291b582014-05-06 02:19:18 -04007160 if (vmptr == vmx->nested.vmxon_ptr) {
7161 nested_vmx_failValid(vcpu,
7162 VMXERR_VMCLEAR_VMXON_POINTER);
7163 skip_emulated_instruction(vcpu);
7164 return 1;
7165 }
7166 break;
7167 case EXIT_REASON_VMPTRLD:
Fabian Frederickbc39c4d2014-06-14 23:44:29 +02007168 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
Bandan Das4291b582014-05-06 02:19:18 -04007169 nested_vmx_failValid(vcpu,
7170 VMXERR_VMPTRLD_INVALID_ADDRESS);
7171 skip_emulated_instruction(vcpu);
7172 return 1;
7173 }
7174
7175 if (vmptr == vmx->nested.vmxon_ptr) {
7176 nested_vmx_failValid(vcpu,
7177 VMXERR_VMCLEAR_VMXON_POINTER);
7178 skip_emulated_instruction(vcpu);
7179 return 1;
7180 }
7181 break;
Bandan Das3573e222014-05-06 02:19:16 -04007182 default:
7183 return 1; /* shouldn't happen */
7184 }
7185
Bandan Das4291b582014-05-06 02:19:18 -04007186 if (vmpointer)
7187 *vmpointer = vmptr;
Bandan Das3573e222014-05-06 02:19:16 -04007188 return 0;
7189}
7190
7191/*
Nadav Har'Elec378ae2011-05-25 23:02:54 +03007192 * Emulate the VMXON instruction.
7193 * Currently, we just remember that VMX is active, and do not save or even
7194 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
7195 * do not currently need to store anything in that guest-allocated memory
7196 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
7197 * argument is different from the VMXON pointer (which the spec says they do).
7198 */
7199static int handle_vmon(struct kvm_vcpu *vcpu)
7200{
7201 struct kvm_segment cs;
7202 struct vcpu_vmx *vmx = to_vmx(vcpu);
Abel Gordon8de48832013-04-18 14:37:25 +03007203 struct vmcs *shadow_vmcs;
Nadav Har'Elb3897a42013-07-08 19:12:35 +08007204 const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
7205 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
Paolo Bonziniff546f92018-01-11 12:16:15 +01007206 int r;
Nadav Har'Elec378ae2011-05-25 23:02:54 +03007207
7208 /* The Intel VMX Instruction Reference lists a bunch of bits that
7209 * are prerequisite to running VMXON, most notably cr4.VMXE must be
7210 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
7211 * Otherwise, we should fail with #UD. We test these now:
7212 */
7213 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
7214 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
7215 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
7216 kvm_queue_exception(vcpu, UD_VECTOR);
7217 return 1;
7218 }
7219
7220 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
7221 if (is_long_mode(vcpu) && !cs.l) {
7222 kvm_queue_exception(vcpu, UD_VECTOR);
7223 return 1;
7224 }
7225
7226 if (vmx_get_cpl(vcpu)) {
7227 kvm_inject_gp(vcpu, 0);
7228 return 1;
7229 }
Bandan Das3573e222014-05-06 02:19:16 -04007230
Bandan Das4291b582014-05-06 02:19:18 -04007231 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL))
Bandan Das3573e222014-05-06 02:19:16 -04007232 return 1;
7233
Abel Gordon145c28d2013-04-18 14:36:55 +03007234 if (vmx->nested.vmxon) {
7235 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
7236 skip_emulated_instruction(vcpu);
7237 return 1;
7238 }
Nadav Har'Elb3897a42013-07-08 19:12:35 +08007239
Haozhong Zhang3b840802016-06-22 14:59:54 +08007240 if ((vmx->msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
Nadav Har'Elb3897a42013-07-08 19:12:35 +08007241 != VMXON_NEEDED_FEATURES) {
7242 kvm_inject_gp(vcpu, 0);
7243 return 1;
7244 }
7245
Paolo Bonziniff546f92018-01-11 12:16:15 +01007246 r = alloc_loaded_vmcs(&vmx->nested.vmcs02);
7247 if (r < 0)
Jim Mattson46e24df2017-11-27 17:22:25 -06007248 goto out_vmcs02;
Jim Mattson46e24df2017-11-27 17:22:25 -06007249
David Matlack4f2777b2016-07-13 17:16:37 -07007250 vmx->nested.cached_vmcs12 = kmalloc(VMCS12_SIZE, GFP_KERNEL);
7251 if (!vmx->nested.cached_vmcs12)
Radim Krčmářd048c092016-08-08 20:16:22 +02007252 goto out_cached_vmcs12;
David Matlack4f2777b2016-07-13 17:16:37 -07007253
Abel Gordon8de48832013-04-18 14:37:25 +03007254 if (enable_shadow_vmcs) {
7255 shadow_vmcs = alloc_vmcs();
Radim Krčmářd048c092016-08-08 20:16:22 +02007256 if (!shadow_vmcs)
7257 goto out_shadow_vmcs;
Abel Gordon8de48832013-04-18 14:37:25 +03007258 /* mark vmcs as shadow */
7259 shadow_vmcs->revision_id |= (1u << 31);
7260 /* init shadow vmcs */
7261 vmcs_clear(shadow_vmcs);
Jim Mattson355f4fb2016-10-28 08:29:39 -07007262 vmx->vmcs01.shadow_vmcs = shadow_vmcs;
Abel Gordon8de48832013-04-18 14:37:25 +03007263 }
Nadav Har'Elec378ae2011-05-25 23:02:54 +03007264
Jan Kiszkaf4124502014-03-07 20:03:13 +01007265 hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
Wanpeng Lif15a75e2016-08-30 16:14:01 +08007266 HRTIMER_MODE_REL_PINNED);
Jan Kiszkaf4124502014-03-07 20:03:13 +01007267 vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
7268
Roman Kagan020a90f2018-07-19 21:59:07 +03007269 vmx->nested.vpid02 = allocate_vpid();
7270
Nadav Har'Elec378ae2011-05-25 23:02:54 +03007271 vmx->nested.vmxon = true;
7272
7273 skip_emulated_instruction(vcpu);
Arthur Chunqi Lia25eb112013-07-04 15:03:33 +08007274 nested_vmx_succeed(vcpu);
Nadav Har'Elec378ae2011-05-25 23:02:54 +03007275 return 1;
Radim Krčmářd048c092016-08-08 20:16:22 +02007276
7277out_shadow_vmcs:
7278 kfree(vmx->nested.cached_vmcs12);
7279
7280out_cached_vmcs12:
Jim Mattson46e24df2017-11-27 17:22:25 -06007281 free_loaded_vmcs(&vmx->nested.vmcs02);
7282
7283out_vmcs02:
Radim Krčmářd048c092016-08-08 20:16:22 +02007284 return -ENOMEM;
Nadav Har'Elec378ae2011-05-25 23:02:54 +03007285}
7286
7287/*
7288 * Intel's VMX Instruction Reference specifies a common set of prerequisites
7289 * for running VMX instructions (except VMXON, whose prerequisites are
7290 * slightly different). It also specifies what exception to inject otherwise.
7291 */
7292static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
7293{
7294 struct kvm_segment cs;
7295 struct vcpu_vmx *vmx = to_vmx(vcpu);
7296
7297 if (!vmx->nested.vmxon) {
7298 kvm_queue_exception(vcpu, UD_VECTOR);
7299 return 0;
7300 }
7301
7302 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
7303 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
7304 (is_long_mode(vcpu) && !cs.l)) {
7305 kvm_queue_exception(vcpu, UD_VECTOR);
7306 return 0;
7307 }
7308
7309 if (vmx_get_cpl(vcpu)) {
7310 kvm_inject_gp(vcpu, 0);
7311 return 0;
7312 }
7313
7314 return 1;
7315}
7316
Abel Gordone7953d72013-04-18 14:37:55 +03007317static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
7318{
Paolo Bonzini9a2a05b2014-07-17 11:55:46 +02007319 if (vmx->nested.current_vmptr == -1ull)
7320 return;
7321
7322 /* current_vmptr and current_vmcs12 are always set/reset together */
7323 if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
7324 return;
7325
Abel Gordon012f83c2013-04-18 14:39:25 +03007326 if (enable_shadow_vmcs) {
Paolo Bonzini9a2a05b2014-07-17 11:55:46 +02007327 /* copy to memory all shadowed fields in case
7328 they were modified */
7329 copy_shadow_to_vmcs12(vmx);
7330 vmx->nested.sync_shadow_vmcs = false;
Xiao Guangrong7ec36292015-09-09 14:05:56 +08007331 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
7332 SECONDARY_EXEC_SHADOW_VMCS);
Paolo Bonzini9a2a05b2014-07-17 11:55:46 +02007333 vmcs_write64(VMCS_LINK_POINTER, -1ull);
Abel Gordon012f83c2013-04-18 14:39:25 +03007334 }
Wincy Van705699a2015-02-03 23:58:17 +08007335 vmx->nested.posted_intr_nv = -1;
David Matlack4f2777b2016-07-13 17:16:37 -07007336
7337 /* Flush VMCS12 to guest memory */
7338 memcpy(vmx->nested.current_vmcs12, vmx->nested.cached_vmcs12,
7339 VMCS12_SIZE);
7340
Abel Gordone7953d72013-04-18 14:37:55 +03007341 kunmap(vmx->nested.current_vmcs12_page);
7342 nested_release_page(vmx->nested.current_vmcs12_page);
Paolo Bonzini9a2a05b2014-07-17 11:55:46 +02007343 vmx->nested.current_vmptr = -1ull;
7344 vmx->nested.current_vmcs12 = NULL;
Abel Gordone7953d72013-04-18 14:37:55 +03007345}
7346
Nadav Har'Elec378ae2011-05-25 23:02:54 +03007347/*
7348 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
7349 * just stops using VMX.
7350 */
7351static void free_nested(struct vcpu_vmx *vmx)
7352{
7353 if (!vmx->nested.vmxon)
7354 return;
Paolo Bonzini9a2a05b2014-07-17 11:55:46 +02007355
Nadav Har'Elec378ae2011-05-25 23:02:54 +03007356 vmx->nested.vmxon = false;
Wanpeng Li5c614b32015-10-13 09:18:36 -07007357 free_vpid(vmx->nested.vpid02);
Paolo Bonzini9a2a05b2014-07-17 11:55:46 +02007358 nested_release_vmcs12(vmx);
Jim Mattson355f4fb2016-10-28 08:29:39 -07007359 if (enable_shadow_vmcs) {
7360 vmcs_clear(vmx->vmcs01.shadow_vmcs);
7361 free_vmcs(vmx->vmcs01.shadow_vmcs);
7362 vmx->vmcs01.shadow_vmcs = NULL;
7363 }
David Matlack4f2777b2016-07-13 17:16:37 -07007364 kfree(vmx->nested.cached_vmcs12);
Jim Mattson46e24df2017-11-27 17:22:25 -06007365 /* Unpin physical memory we referred to in the vmcs02 */
Nadav Har'Elfe3ef052011-05-25 23:10:02 +03007366 if (vmx->nested.apic_access_page) {
7367 nested_release_page(vmx->nested.apic_access_page);
Paolo Bonzini48d89b92014-08-26 13:27:46 +02007368 vmx->nested.apic_access_page = NULL;
Nadav Har'Elfe3ef052011-05-25 23:10:02 +03007369 }
Wanpeng Lia7c0b072014-08-21 19:46:50 +08007370 if (vmx->nested.virtual_apic_page) {
7371 nested_release_page(vmx->nested.virtual_apic_page);
Paolo Bonzini48d89b92014-08-26 13:27:46 +02007372 vmx->nested.virtual_apic_page = NULL;
Wanpeng Lia7c0b072014-08-21 19:46:50 +08007373 }
Wincy Van705699a2015-02-03 23:58:17 +08007374 if (vmx->nested.pi_desc_page) {
7375 kunmap(vmx->nested.pi_desc_page);
7376 nested_release_page(vmx->nested.pi_desc_page);
7377 vmx->nested.pi_desc_page = NULL;
7378 vmx->nested.pi_desc = NULL;
7379 }
Nadav Har'Elff2f6fe2011-05-25 23:05:27 +03007380
Jim Mattson46e24df2017-11-27 17:22:25 -06007381 free_loaded_vmcs(&vmx->nested.vmcs02);
Nadav Har'Elec378ae2011-05-25 23:02:54 +03007382}
7383
7384/* Emulate the VMXOFF instruction */
7385static int handle_vmoff(struct kvm_vcpu *vcpu)
7386{
7387 if (!nested_vmx_check_permission(vcpu))
7388 return 1;
7389 free_nested(to_vmx(vcpu));
7390 skip_emulated_instruction(vcpu);
Arthur Chunqi Lia25eb112013-07-04 15:03:33 +08007391 nested_vmx_succeed(vcpu);
Nadav Har'Elec378ae2011-05-25 23:02:54 +03007392 return 1;
7393}
7394
Nadav Har'El27d6c862011-05-25 23:06:59 +03007395/* Emulate the VMCLEAR instruction */
7396static int handle_vmclear(struct kvm_vcpu *vcpu)
7397{
7398 struct vcpu_vmx *vmx = to_vmx(vcpu);
Jim Mattson29deec42017-03-02 12:41:48 -08007399 u32 zero = 0;
Nadav Har'El27d6c862011-05-25 23:06:59 +03007400 gpa_t vmptr;
Nadav Har'El27d6c862011-05-25 23:06:59 +03007401
7402 if (!nested_vmx_check_permission(vcpu))
7403 return 1;
7404
Bandan Das4291b582014-05-06 02:19:18 -04007405 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr))
Nadav Har'El27d6c862011-05-25 23:06:59 +03007406 return 1;
7407
Paolo Bonzini9a2a05b2014-07-17 11:55:46 +02007408 if (vmptr == vmx->nested.current_vmptr)
Abel Gordone7953d72013-04-18 14:37:55 +03007409 nested_release_vmcs12(vmx);
Nadav Har'El27d6c862011-05-25 23:06:59 +03007410
Jim Mattson29deec42017-03-02 12:41:48 -08007411 kvm_vcpu_write_guest(vcpu,
7412 vmptr + offsetof(struct vmcs12, launch_state),
7413 &zero, sizeof(zero));
Nadav Har'El27d6c862011-05-25 23:06:59 +03007414
Nadav Har'El27d6c862011-05-25 23:06:59 +03007415 skip_emulated_instruction(vcpu);
7416 nested_vmx_succeed(vcpu);
7417 return 1;
7418}
7419
Nadav Har'Elcd232ad2011-05-25 23:10:33 +03007420static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
7421
7422/* Emulate the VMLAUNCH instruction */
7423static int handle_vmlaunch(struct kvm_vcpu *vcpu)
7424{
7425 return nested_vmx_run(vcpu, true);
7426}
7427
7428/* Emulate the VMRESUME instruction */
7429static int handle_vmresume(struct kvm_vcpu *vcpu)
7430{
7431
7432 return nested_vmx_run(vcpu, false);
7433}
7434
Nadav Har'El49f705c2011-05-25 23:08:30 +03007435enum vmcs_field_type {
7436 VMCS_FIELD_TYPE_U16 = 0,
7437 VMCS_FIELD_TYPE_U64 = 1,
7438 VMCS_FIELD_TYPE_U32 = 2,
7439 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
7440};
7441
7442static inline int vmcs_field_type(unsigned long field)
7443{
7444 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
7445 return VMCS_FIELD_TYPE_U32;
7446 return (field >> 13) & 0x3 ;
7447}
7448
7449static inline int vmcs_field_readonly(unsigned long field)
7450{
7451 return (((field >> 10) & 0x3) == 1);
7452}
7453
7454/*
7455 * Read a vmcs12 field. Since these can have varying lengths and we return
7456 * one type, we chose the biggest type (u64) and zero-extend the return value
7457 * to that size. Note that the caller, handle_vmread, might need to use only
7458 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
7459 * 64-bit fields are to be returned).
7460 */
Paolo Bonzinia2ae9df2014-11-04 18:31:19 +01007461static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
7462 unsigned long field, u64 *ret)
Nadav Har'El49f705c2011-05-25 23:08:30 +03007463{
7464 short offset = vmcs_field_to_offset(field);
7465 char *p;
7466
7467 if (offset < 0)
Paolo Bonzinia2ae9df2014-11-04 18:31:19 +01007468 return offset;
Nadav Har'El49f705c2011-05-25 23:08:30 +03007469
7470 p = ((char *)(get_vmcs12(vcpu))) + offset;
7471
7472 switch (vmcs_field_type(field)) {
7473 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7474 *ret = *((natural_width *)p);
Paolo Bonzinia2ae9df2014-11-04 18:31:19 +01007475 return 0;
Nadav Har'El49f705c2011-05-25 23:08:30 +03007476 case VMCS_FIELD_TYPE_U16:
7477 *ret = *((u16 *)p);
Paolo Bonzinia2ae9df2014-11-04 18:31:19 +01007478 return 0;
Nadav Har'El49f705c2011-05-25 23:08:30 +03007479 case VMCS_FIELD_TYPE_U32:
7480 *ret = *((u32 *)p);
Paolo Bonzinia2ae9df2014-11-04 18:31:19 +01007481 return 0;
Nadav Har'El49f705c2011-05-25 23:08:30 +03007482 case VMCS_FIELD_TYPE_U64:
7483 *ret = *((u64 *)p);
Paolo Bonzinia2ae9df2014-11-04 18:31:19 +01007484 return 0;
Nadav Har'El49f705c2011-05-25 23:08:30 +03007485 default:
Paolo Bonzinia2ae9df2014-11-04 18:31:19 +01007486 WARN_ON(1);
7487 return -ENOENT;
Nadav Har'El49f705c2011-05-25 23:08:30 +03007488 }
7489}
7490
Abel Gordon20b97fe2013-04-18 14:36:25 +03007491
Paolo Bonzinia2ae9df2014-11-04 18:31:19 +01007492static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
7493 unsigned long field, u64 field_value){
Abel Gordon20b97fe2013-04-18 14:36:25 +03007494 short offset = vmcs_field_to_offset(field);
7495 char *p = ((char *) get_vmcs12(vcpu)) + offset;
7496 if (offset < 0)
Paolo Bonzinia2ae9df2014-11-04 18:31:19 +01007497 return offset;
Abel Gordon20b97fe2013-04-18 14:36:25 +03007498
7499 switch (vmcs_field_type(field)) {
7500 case VMCS_FIELD_TYPE_U16:
7501 *(u16 *)p = field_value;
Paolo Bonzinia2ae9df2014-11-04 18:31:19 +01007502 return 0;
Abel Gordon20b97fe2013-04-18 14:36:25 +03007503 case VMCS_FIELD_TYPE_U32:
7504 *(u32 *)p = field_value;
Paolo Bonzinia2ae9df2014-11-04 18:31:19 +01007505 return 0;
Abel Gordon20b97fe2013-04-18 14:36:25 +03007506 case VMCS_FIELD_TYPE_U64:
7507 *(u64 *)p = field_value;
Paolo Bonzinia2ae9df2014-11-04 18:31:19 +01007508 return 0;
Abel Gordon20b97fe2013-04-18 14:36:25 +03007509 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7510 *(natural_width *)p = field_value;
Paolo Bonzinia2ae9df2014-11-04 18:31:19 +01007511 return 0;
Abel Gordon20b97fe2013-04-18 14:36:25 +03007512 default:
Paolo Bonzinia2ae9df2014-11-04 18:31:19 +01007513 WARN_ON(1);
7514 return -ENOENT;
Abel Gordon20b97fe2013-04-18 14:36:25 +03007515 }
7516
7517}
7518
Abel Gordon16f5b902013-04-18 14:38:25 +03007519static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
7520{
7521 int i;
7522 unsigned long field;
7523 u64 field_value;
Jim Mattson355f4fb2016-10-28 08:29:39 -07007524 struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
Mathias Krausec2bae892013-06-26 20:36:21 +02007525 const unsigned long *fields = shadow_read_write_fields;
7526 const int num_fields = max_shadow_read_write_fields;
Abel Gordon16f5b902013-04-18 14:38:25 +03007527
Jan Kiszka282da872014-10-08 18:05:39 +02007528 preempt_disable();
7529
Abel Gordon16f5b902013-04-18 14:38:25 +03007530 vmcs_load(shadow_vmcs);
7531
7532 for (i = 0; i < num_fields; i++) {
7533 field = fields[i];
7534 switch (vmcs_field_type(field)) {
7535 case VMCS_FIELD_TYPE_U16:
7536 field_value = vmcs_read16(field);
7537 break;
7538 case VMCS_FIELD_TYPE_U32:
7539 field_value = vmcs_read32(field);
7540 break;
7541 case VMCS_FIELD_TYPE_U64:
7542 field_value = vmcs_read64(field);
7543 break;
7544 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7545 field_value = vmcs_readl(field);
7546 break;
Paolo Bonzinia2ae9df2014-11-04 18:31:19 +01007547 default:
7548 WARN_ON(1);
7549 continue;
Abel Gordon16f5b902013-04-18 14:38:25 +03007550 }
7551 vmcs12_write_any(&vmx->vcpu, field, field_value);
7552 }
7553
7554 vmcs_clear(shadow_vmcs);
7555 vmcs_load(vmx->loaded_vmcs->vmcs);
Jan Kiszka282da872014-10-08 18:05:39 +02007556
7557 preempt_enable();
Abel Gordon16f5b902013-04-18 14:38:25 +03007558}
7559
Abel Gordonc3114422013-04-18 14:38:55 +03007560static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
7561{
Mathias Krausec2bae892013-06-26 20:36:21 +02007562 const unsigned long *fields[] = {
7563 shadow_read_write_fields,
7564 shadow_read_only_fields
Abel Gordonc3114422013-04-18 14:38:55 +03007565 };
Mathias Krausec2bae892013-06-26 20:36:21 +02007566 const int max_fields[] = {
Abel Gordonc3114422013-04-18 14:38:55 +03007567 max_shadow_read_write_fields,
7568 max_shadow_read_only_fields
7569 };
7570 int i, q;
7571 unsigned long field;
7572 u64 field_value = 0;
Jim Mattson355f4fb2016-10-28 08:29:39 -07007573 struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
Abel Gordonc3114422013-04-18 14:38:55 +03007574
7575 vmcs_load(shadow_vmcs);
7576
Mathias Krausec2bae892013-06-26 20:36:21 +02007577 for (q = 0; q < ARRAY_SIZE(fields); q++) {
Abel Gordonc3114422013-04-18 14:38:55 +03007578 for (i = 0; i < max_fields[q]; i++) {
7579 field = fields[q][i];
7580 vmcs12_read_any(&vmx->vcpu, field, &field_value);
7581
7582 switch (vmcs_field_type(field)) {
7583 case VMCS_FIELD_TYPE_U16:
7584 vmcs_write16(field, (u16)field_value);
7585 break;
7586 case VMCS_FIELD_TYPE_U32:
7587 vmcs_write32(field, (u32)field_value);
7588 break;
7589 case VMCS_FIELD_TYPE_U64:
7590 vmcs_write64(field, (u64)field_value);
7591 break;
7592 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7593 vmcs_writel(field, (long)field_value);
7594 break;
Paolo Bonzinia2ae9df2014-11-04 18:31:19 +01007595 default:
7596 WARN_ON(1);
7597 break;
Abel Gordonc3114422013-04-18 14:38:55 +03007598 }
7599 }
7600 }
7601
7602 vmcs_clear(shadow_vmcs);
7603 vmcs_load(vmx->loaded_vmcs->vmcs);
7604}
7605
Nadav Har'El49f705c2011-05-25 23:08:30 +03007606/*
7607 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7608 * used before) all generate the same failure when it is missing.
7609 */
7610static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
7611{
7612 struct vcpu_vmx *vmx = to_vmx(vcpu);
7613 if (vmx->nested.current_vmptr == -1ull) {
7614 nested_vmx_failInvalid(vcpu);
7615 skip_emulated_instruction(vcpu);
7616 return 0;
7617 }
7618 return 1;
7619}
7620
7621static int handle_vmread(struct kvm_vcpu *vcpu)
7622{
7623 unsigned long field;
7624 u64 field_value;
7625 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7626 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7627 gva_t gva = 0;
7628
7629 if (!nested_vmx_check_permission(vcpu) ||
7630 !nested_vmx_check_vmcs12(vcpu))
7631 return 1;
7632
7633 /* Decode instruction info and find the field to read */
Nadav Amit27e6fb52014-06-18 17:19:26 +03007634 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
Nadav Har'El49f705c2011-05-25 23:08:30 +03007635 /* Read the field, zero-extended to a u64 field_value */
Paolo Bonzinia2ae9df2014-11-04 18:31:19 +01007636 if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
Nadav Har'El49f705c2011-05-25 23:08:30 +03007637 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7638 skip_emulated_instruction(vcpu);
7639 return 1;
7640 }
7641 /*
7642 * Now copy part of this value to register or memory, as requested.
7643 * Note that the number of bits actually copied is 32 or 64 depending
7644 * on the guest's mode (32 or 64 bit), not on the given field's length.
7645 */
7646 if (vmx_instruction_info & (1u << 10)) {
Nadav Amit27e6fb52014-06-18 17:19:26 +03007647 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
Nadav Har'El49f705c2011-05-25 23:08:30 +03007648 field_value);
7649 } else {
7650 if (get_vmx_mem_address(vcpu, exit_qualification,
Eugene Korenevskyf9eb4af2015-04-17 02:22:21 +00007651 vmx_instruction_info, true, &gva))
Nadav Har'El49f705c2011-05-25 23:08:30 +03007652 return 1;
7653 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
Paolo Bonzini838b0e92018-06-06 17:37:49 +02007654 kvm_write_guest_virt_system(vcpu, gva, &field_value,
7655 (is_long_mode(vcpu) ? 8 : 4), NULL);
Nadav Har'El49f705c2011-05-25 23:08:30 +03007656 }
7657
7658 nested_vmx_succeed(vcpu);
7659 skip_emulated_instruction(vcpu);
7660 return 1;
7661}
7662
7663
7664static int handle_vmwrite(struct kvm_vcpu *vcpu)
7665{
7666 unsigned long field;
7667 gva_t gva;
7668 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7669 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
Nadav Har'El49f705c2011-05-25 23:08:30 +03007670 /* The value to write might be 32 or 64 bits, depending on L1's long
7671 * mode, and eventually we need to write that into a field of several
7672 * possible lengths. The code below first zero-extends the value to 64
Adam Buchbinder6a6256f2016-02-23 15:34:30 -08007673 * bit (field_value), and then copies only the appropriate number of
Nadav Har'El49f705c2011-05-25 23:08:30 +03007674 * bits into the vmcs12 field.
7675 */
7676 u64 field_value = 0;
7677 struct x86_exception e;
7678
7679 if (!nested_vmx_check_permission(vcpu) ||
7680 !nested_vmx_check_vmcs12(vcpu))
7681 return 1;
7682
7683 if (vmx_instruction_info & (1u << 10))
Nadav Amit27e6fb52014-06-18 17:19:26 +03007684 field_value = kvm_register_readl(vcpu,
Nadav Har'El49f705c2011-05-25 23:08:30 +03007685 (((vmx_instruction_info) >> 3) & 0xf));
7686 else {
7687 if (get_vmx_mem_address(vcpu, exit_qualification,
Eugene Korenevskyf9eb4af2015-04-17 02:22:21 +00007688 vmx_instruction_info, false, &gva))
Nadav Har'El49f705c2011-05-25 23:08:30 +03007689 return 1;
Paolo Bonzini838b0e92018-06-06 17:37:49 +02007690 if (kvm_read_guest_virt(vcpu, gva, &field_value,
7691 (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
Nadav Har'El49f705c2011-05-25 23:08:30 +03007692 kvm_inject_page_fault(vcpu, &e);
7693 return 1;
7694 }
7695 }
7696
7697
Nadav Amit27e6fb52014-06-18 17:19:26 +03007698 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
Nadav Har'El49f705c2011-05-25 23:08:30 +03007699 if (vmcs_field_readonly(field)) {
7700 nested_vmx_failValid(vcpu,
7701 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
7702 skip_emulated_instruction(vcpu);
7703 return 1;
7704 }
7705
Paolo Bonzinia2ae9df2014-11-04 18:31:19 +01007706 if (vmcs12_write_any(vcpu, field, field_value) < 0) {
Nadav Har'El49f705c2011-05-25 23:08:30 +03007707 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7708 skip_emulated_instruction(vcpu);
7709 return 1;
7710 }
7711
7712 nested_vmx_succeed(vcpu);
7713 skip_emulated_instruction(vcpu);
7714 return 1;
7715}
7716
Nadav Har'El63846662011-05-25 23:07:29 +03007717/* Emulate the VMPTRLD instruction */
7718static int handle_vmptrld(struct kvm_vcpu *vcpu)
7719{
7720 struct vcpu_vmx *vmx = to_vmx(vcpu);
Nadav Har'El63846662011-05-25 23:07:29 +03007721 gpa_t vmptr;
Nadav Har'El63846662011-05-25 23:07:29 +03007722
7723 if (!nested_vmx_check_permission(vcpu))
7724 return 1;
7725
Bandan Das4291b582014-05-06 02:19:18 -04007726 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr))
Nadav Har'El63846662011-05-25 23:07:29 +03007727 return 1;
7728
Nadav Har'El63846662011-05-25 23:07:29 +03007729 if (vmx->nested.current_vmptr != vmptr) {
7730 struct vmcs12 *new_vmcs12;
7731 struct page *page;
7732 page = nested_get_page(vcpu, vmptr);
7733 if (page == NULL) {
7734 nested_vmx_failInvalid(vcpu);
7735 skip_emulated_instruction(vcpu);
7736 return 1;
7737 }
7738 new_vmcs12 = kmap(page);
7739 if (new_vmcs12->revision_id != VMCS12_REVISION) {
7740 kunmap(page);
7741 nested_release_page_clean(page);
7742 nested_vmx_failValid(vcpu,
7743 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
7744 skip_emulated_instruction(vcpu);
7745 return 1;
7746 }
Nadav Har'El63846662011-05-25 23:07:29 +03007747
Paolo Bonzini9a2a05b2014-07-17 11:55:46 +02007748 nested_release_vmcs12(vmx);
Nadav Har'El63846662011-05-25 23:07:29 +03007749 vmx->nested.current_vmptr = vmptr;
7750 vmx->nested.current_vmcs12 = new_vmcs12;
7751 vmx->nested.current_vmcs12_page = page;
David Matlack4f2777b2016-07-13 17:16:37 -07007752 /*
7753 * Load VMCS12 from guest memory since it is not already
7754 * cached.
7755 */
7756 memcpy(vmx->nested.cached_vmcs12,
7757 vmx->nested.current_vmcs12, VMCS12_SIZE);
7758
Abel Gordon012f83c2013-04-18 14:39:25 +03007759 if (enable_shadow_vmcs) {
Xiao Guangrong7ec36292015-09-09 14:05:56 +08007760 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
7761 SECONDARY_EXEC_SHADOW_VMCS);
Abel Gordon8a1b9dd2013-04-18 14:39:55 +03007762 vmcs_write64(VMCS_LINK_POINTER,
Jim Mattson355f4fb2016-10-28 08:29:39 -07007763 __pa(vmx->vmcs01.shadow_vmcs));
Abel Gordon012f83c2013-04-18 14:39:25 +03007764 vmx->nested.sync_shadow_vmcs = true;
7765 }
Nadav Har'El63846662011-05-25 23:07:29 +03007766 }
7767
7768 nested_vmx_succeed(vcpu);
7769 skip_emulated_instruction(vcpu);
7770 return 1;
7771}
7772
Nadav Har'El6a4d7552011-05-25 23:08:00 +03007773/* Emulate the VMPTRST instruction */
7774static int handle_vmptrst(struct kvm_vcpu *vcpu)
7775{
7776 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7777 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7778 gva_t vmcs_gva;
7779 struct x86_exception e;
7780
7781 if (!nested_vmx_check_permission(vcpu))
7782 return 1;
7783
7784 if (get_vmx_mem_address(vcpu, exit_qualification,
Eugene Korenevskyf9eb4af2015-04-17 02:22:21 +00007785 vmx_instruction_info, true, &vmcs_gva))
Nadav Har'El6a4d7552011-05-25 23:08:00 +03007786 return 1;
7787 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
Paolo Bonzini838b0e92018-06-06 17:37:49 +02007788 if (kvm_write_guest_virt_system(vcpu, vmcs_gva,
7789 (void *)&to_vmx(vcpu)->nested.current_vmptr,
7790 sizeof(u64), &e)) {
Nadav Har'El6a4d7552011-05-25 23:08:00 +03007791 kvm_inject_page_fault(vcpu, &e);
7792 return 1;
7793 }
7794 nested_vmx_succeed(vcpu);
7795 skip_emulated_instruction(vcpu);
7796 return 1;
7797}
7798
Nadav Har'Elbfd0a562013-08-05 11:07:17 +03007799/* Emulate the INVEPT instruction */
7800static int handle_invept(struct kvm_vcpu *vcpu)
7801{
Wincy Vanb9c237b2015-02-03 23:56:30 +08007802 struct vcpu_vmx *vmx = to_vmx(vcpu);
Nadav Har'Elbfd0a562013-08-05 11:07:17 +03007803 u32 vmx_instruction_info, types;
7804 unsigned long type;
7805 gva_t gva;
7806 struct x86_exception e;
7807 struct {
7808 u64 eptp, gpa;
7809 } operand;
Nadav Har'Elbfd0a562013-08-05 11:07:17 +03007810
Wincy Vanb9c237b2015-02-03 23:56:30 +08007811 if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7812 SECONDARY_EXEC_ENABLE_EPT) ||
7813 !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
Nadav Har'Elbfd0a562013-08-05 11:07:17 +03007814 kvm_queue_exception(vcpu, UD_VECTOR);
7815 return 1;
7816 }
7817
7818 if (!nested_vmx_check_permission(vcpu))
7819 return 1;
7820
7821 if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
7822 kvm_queue_exception(vcpu, UD_VECTOR);
7823 return 1;
7824 }
7825
7826 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
Nadav Amit27e6fb52014-06-18 17:19:26 +03007827 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
Nadav Har'Elbfd0a562013-08-05 11:07:17 +03007828
Wincy Vanb9c237b2015-02-03 23:56:30 +08007829 types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
Nadav Har'Elbfd0a562013-08-05 11:07:17 +03007830
Jim Mattson85c856b2016-10-26 08:38:38 -07007831 if (type >= 32 || !(types & (1 << type))) {
Nadav Har'Elbfd0a562013-08-05 11:07:17 +03007832 nested_vmx_failValid(vcpu,
7833 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
Paolo Bonzini2849eb42016-03-18 16:53:29 +01007834 skip_emulated_instruction(vcpu);
Nadav Har'Elbfd0a562013-08-05 11:07:17 +03007835 return 1;
7836 }
7837
7838 /* According to the Intel VMX instruction reference, the memory
7839 * operand is read even if it isn't needed (e.g., for type==global)
7840 */
7841 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
Eugene Korenevskyf9eb4af2015-04-17 02:22:21 +00007842 vmx_instruction_info, false, &gva))
Nadav Har'Elbfd0a562013-08-05 11:07:17 +03007843 return 1;
Paolo Bonzini838b0e92018-06-06 17:37:49 +02007844 if (kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e)) {
Nadav Har'Elbfd0a562013-08-05 11:07:17 +03007845 kvm_inject_page_fault(vcpu, &e);
7846 return 1;
7847 }
7848
7849 switch (type) {
Nadav Har'Elbfd0a562013-08-05 11:07:17 +03007850 case VMX_EPT_EXTENT_GLOBAL:
Bandan Das45e11812016-08-02 16:32:36 -04007851 /*
7852 * TODO: track mappings and invalidate
7853 * single context requests appropriately
7854 */
7855 case VMX_EPT_EXTENT_CONTEXT:
Nadav Har'Elbfd0a562013-08-05 11:07:17 +03007856 kvm_mmu_sync_roots(vcpu);
Liang Chen77c39132014-09-18 12:38:37 -04007857 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
Nadav Har'Elbfd0a562013-08-05 11:07:17 +03007858 nested_vmx_succeed(vcpu);
7859 break;
7860 default:
7861 BUG_ON(1);
7862 break;
7863 }
7864
7865 skip_emulated_instruction(vcpu);
7866 return 1;
7867}
7868
Petr Matouseka642fc32014-09-23 20:22:30 +02007869static int handle_invvpid(struct kvm_vcpu *vcpu)
7870{
Wanpeng Li99b83ac2015-10-13 09:12:21 -07007871 struct vcpu_vmx *vmx = to_vmx(vcpu);
7872 u32 vmx_instruction_info;
7873 unsigned long type, types;
7874 gva_t gva;
7875 struct x86_exception e;
7876 int vpid;
7877
7878 if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7879 SECONDARY_EXEC_ENABLE_VPID) ||
7880 !(vmx->nested.nested_vmx_vpid_caps & VMX_VPID_INVVPID_BIT)) {
7881 kvm_queue_exception(vcpu, UD_VECTOR);
7882 return 1;
7883 }
7884
7885 if (!nested_vmx_check_permission(vcpu))
7886 return 1;
7887
7888 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7889 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7890
Jan Dakinevich04c776e2018-02-23 11:42:18 +01007891 types = (vmx->nested.nested_vmx_vpid_caps &
7892 VMX_VPID_EXTENT_SUPPORTED_MASK) >> 8;
Wanpeng Li99b83ac2015-10-13 09:12:21 -07007893
Jim Mattson85c856b2016-10-26 08:38:38 -07007894 if (type >= 32 || !(types & (1 << type))) {
Wanpeng Li99b83ac2015-10-13 09:12:21 -07007895 nested_vmx_failValid(vcpu,
7896 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
Paolo Bonzinif6870ee2016-03-18 16:53:42 +01007897 skip_emulated_instruction(vcpu);
Wanpeng Li99b83ac2015-10-13 09:12:21 -07007898 return 1;
7899 }
7900
7901 /* according to the intel vmx instruction reference, the memory
7902 * operand is read even if it isn't needed (e.g., for type==global)
7903 */
7904 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7905 vmx_instruction_info, false, &gva))
7906 return 1;
Paolo Bonzini838b0e92018-06-06 17:37:49 +02007907 if (kvm_read_guest_virt(vcpu, gva, &vpid, sizeof(u32), &e)) {
Wanpeng Li99b83ac2015-10-13 09:12:21 -07007908 kvm_inject_page_fault(vcpu, &e);
7909 return 1;
7910 }
7911
7912 switch (type) {
Jan Dakinevich04c776e2018-02-23 11:42:18 +01007913 case VMX_VPID_EXTENT_INDIVIDUAL_ADDR:
Paolo Bonzinief697a72016-03-18 16:58:38 +01007914 case VMX_VPID_EXTENT_SINGLE_CONTEXT:
Jan Dakinevich04c776e2018-02-23 11:42:18 +01007915 case VMX_VPID_EXTENT_SINGLE_NON_GLOBAL:
7916 if (!vpid) {
7917 nested_vmx_failValid(vcpu,
7918 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7919 skip_emulated_instruction(vcpu);
7920 return 1;
7921 }
7922 break;
Wanpeng Li99b83ac2015-10-13 09:12:21 -07007923 case VMX_VPID_EXTENT_ALL_CONTEXT:
Wanpeng Li99b83ac2015-10-13 09:12:21 -07007924 break;
7925 default:
Jan Dakinevich04c776e2018-02-23 11:42:18 +01007926 WARN_ON_ONCE(1);
7927 skip_emulated_instruction(vcpu);
7928 return 1;
Wanpeng Li99b83ac2015-10-13 09:12:21 -07007929 }
7930
Jan Dakinevich04c776e2018-02-23 11:42:18 +01007931 __vmx_flush_tlb(vcpu, vmx->nested.vpid02);
7932 nested_vmx_succeed(vcpu);
7933
Wanpeng Li99b83ac2015-10-13 09:12:21 -07007934 skip_emulated_instruction(vcpu);
Petr Matouseka642fc32014-09-23 20:22:30 +02007935 return 1;
7936}
7937
Kai Huang843e4332015-01-28 10:54:28 +08007938static int handle_pml_full(struct kvm_vcpu *vcpu)
7939{
7940 unsigned long exit_qualification;
7941
7942 trace_kvm_pml_full(vcpu->vcpu_id);
7943
7944 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7945
7946 /*
7947 * PML buffer FULL happened while executing iret from NMI,
7948 * "blocked by NMI" bit has to be set before next VM entry.
7949 */
7950 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
7951 cpu_has_virtual_nmis() &&
7952 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7953 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7954 GUEST_INTR_STATE_NMI);
7955
7956 /*
7957 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7958 * here.., and there's no userspace involvement needed for PML.
7959 */
7960 return 1;
7961}
7962
Yunhong Jiang64672c92016-06-13 14:19:59 -07007963static int handle_preemption_timer(struct kvm_vcpu *vcpu)
7964{
7965 kvm_lapic_expired_hv_timer(vcpu);
7966 return 1;
7967}
7968
Nadav Har'El0140cae2011-05-25 23:06:28 +03007969/*
Avi Kivity6aa8b732006-12-10 02:21:36 -08007970 * The exit handlers return 1 if the exit was handled fully and guest execution
7971 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
7972 * to be done to userspace and return 0.
7973 */
Mathias Krause772e0312012-08-30 01:30:19 +02007974static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
Avi Kivity6aa8b732006-12-10 02:21:36 -08007975 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
7976 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
Avi Kivity988ad742007-02-12 00:54:36 -08007977 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
Sheng Yangf08864b2008-05-15 18:23:25 +08007978 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
Avi Kivity6aa8b732006-12-10 02:21:36 -08007979 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
Avi Kivity6aa8b732006-12-10 02:21:36 -08007980 [EXIT_REASON_CR_ACCESS] = handle_cr,
7981 [EXIT_REASON_DR_ACCESS] = handle_dr,
7982 [EXIT_REASON_CPUID] = handle_cpuid,
7983 [EXIT_REASON_MSR_READ] = handle_rdmsr,
7984 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
7985 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
7986 [EXIT_REASON_HLT] = handle_halt,
Gleb Natapovec25d5e2010-11-01 15:35:01 +02007987 [EXIT_REASON_INVD] = handle_invd,
Marcelo Tosattia7052892008-09-23 13:18:35 -03007988 [EXIT_REASON_INVLPG] = handle_invlpg,
Avi Kivityfee84b02011-11-10 14:57:25 +02007989 [EXIT_REASON_RDPMC] = handle_rdpmc,
Ingo Molnarc21415e2007-02-19 14:37:47 +02007990 [EXIT_REASON_VMCALL] = handle_vmcall,
Nadav Har'El27d6c862011-05-25 23:06:59 +03007991 [EXIT_REASON_VMCLEAR] = handle_vmclear,
Nadav Har'Elcd232ad2011-05-25 23:10:33 +03007992 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
Nadav Har'El63846662011-05-25 23:07:29 +03007993 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
Nadav Har'El6a4d7552011-05-25 23:08:00 +03007994 [EXIT_REASON_VMPTRST] = handle_vmptrst,
Nadav Har'El49f705c2011-05-25 23:08:30 +03007995 [EXIT_REASON_VMREAD] = handle_vmread,
Nadav Har'Elcd232ad2011-05-25 23:10:33 +03007996 [EXIT_REASON_VMRESUME] = handle_vmresume,
Nadav Har'El49f705c2011-05-25 23:08:30 +03007997 [EXIT_REASON_VMWRITE] = handle_vmwrite,
Nadav Har'Elec378ae2011-05-25 23:02:54 +03007998 [EXIT_REASON_VMOFF] = handle_vmoff,
7999 [EXIT_REASON_VMON] = handle_vmon,
Sheng Yangf78e0e22007-10-29 09:40:42 +08008000 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
8001 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
Yang Zhang83d4c282013-01-25 10:18:49 +08008002 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
Yang Zhangc7c9c562013-01-25 10:18:51 +08008003 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
Eddie Donge5edaa02007-11-11 12:28:35 +02008004 [EXIT_REASON_WBINVD] = handle_wbinvd,
Dexuan Cui2acf9232010-06-10 11:27:12 +08008005 [EXIT_REASON_XSETBV] = handle_xsetbv,
Izik Eidus37817f22008-03-24 23:14:53 +02008006 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
Andi Kleena0861c02009-06-08 17:37:09 +08008007 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
Marcelo Tosatti68f89402009-06-11 12:07:43 -03008008 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
8009 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
Zhai, Edwin4b8d54f2009-10-09 18:03:20 +08008010 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
Gabriel L. Somlo87c00572014-05-07 16:52:13 -04008011 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait,
Mihai Donțu5f3d45e2015-07-05 20:08:57 +03008012 [EXIT_REASON_MONITOR_TRAP_FLAG] = handle_monitor_trap,
Gabriel L. Somlo87c00572014-05-07 16:52:13 -04008013 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor,
Nadav Har'Elbfd0a562013-08-05 11:07:17 +03008014 [EXIT_REASON_INVEPT] = handle_invept,
Petr Matouseka642fc32014-09-23 20:22:30 +02008015 [EXIT_REASON_INVVPID] = handle_invvpid,
Wanpeng Lif53cd632014-12-02 19:14:58 +08008016 [EXIT_REASON_XSAVES] = handle_xsaves,
8017 [EXIT_REASON_XRSTORS] = handle_xrstors,
Kai Huang843e4332015-01-28 10:54:28 +08008018 [EXIT_REASON_PML_FULL] = handle_pml_full,
Yunhong Jiang64672c92016-06-13 14:19:59 -07008019 [EXIT_REASON_PREEMPTION_TIMER] = handle_preemption_timer,
Avi Kivity6aa8b732006-12-10 02:21:36 -08008020};
8021
8022static const int kvm_vmx_max_exit_handlers =
Robert P. J. Day50a34852007-06-03 13:35:29 -04008023 ARRAY_SIZE(kvm_vmx_exit_handlers);
Avi Kivity6aa8b732006-12-10 02:21:36 -08008024
Jan Kiszka908a7bd2013-02-18 11:21:16 +01008025static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
8026 struct vmcs12 *vmcs12)
8027{
8028 unsigned long exit_qualification;
8029 gpa_t bitmap, last_bitmap;
8030 unsigned int port;
8031 int size;
8032 u8 b;
8033
Jan Kiszka908a7bd2013-02-18 11:21:16 +01008034 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
Zhihui Zhang2f0a6392013-12-30 15:56:29 -05008035 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
Jan Kiszka908a7bd2013-02-18 11:21:16 +01008036
8037 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
8038
8039 port = exit_qualification >> 16;
8040 size = (exit_qualification & 7) + 1;
8041
8042 last_bitmap = (gpa_t)-1;
8043 b = -1;
8044
8045 while (size > 0) {
8046 if (port < 0x8000)
8047 bitmap = vmcs12->io_bitmap_a;
8048 else if (port < 0x10000)
8049 bitmap = vmcs12->io_bitmap_b;
8050 else
Joe Perches1d804d02015-03-30 16:46:09 -07008051 return true;
Jan Kiszka908a7bd2013-02-18 11:21:16 +01008052 bitmap += (port & 0x7fff) / 8;
8053
8054 if (last_bitmap != bitmap)
Paolo Bonzini54bf36a2015-04-08 15:39:23 +02008055 if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1))
Joe Perches1d804d02015-03-30 16:46:09 -07008056 return true;
Jan Kiszka908a7bd2013-02-18 11:21:16 +01008057 if (b & (1 << (port & 7)))
Joe Perches1d804d02015-03-30 16:46:09 -07008058 return true;
Jan Kiszka908a7bd2013-02-18 11:21:16 +01008059
8060 port++;
8061 size--;
8062 last_bitmap = bitmap;
8063 }
8064
Joe Perches1d804d02015-03-30 16:46:09 -07008065 return false;
Jan Kiszka908a7bd2013-02-18 11:21:16 +01008066}
8067
Nadav Har'El644d7112011-05-25 23:12:35 +03008068/*
8069 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
8070 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
8071 * disinterest in the current event (read or write a specific MSR) by using an
8072 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
8073 */
8074static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
8075 struct vmcs12 *vmcs12, u32 exit_reason)
8076{
8077 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
8078 gpa_t bitmap;
8079
Jan Kiszkacbd29cb2013-02-11 12:19:28 +01008080 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
Joe Perches1d804d02015-03-30 16:46:09 -07008081 return true;
Nadav Har'El644d7112011-05-25 23:12:35 +03008082
8083 /*
8084 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
8085 * for the four combinations of read/write and low/high MSR numbers.
8086 * First we need to figure out which of the four to use:
8087 */
8088 bitmap = vmcs12->msr_bitmap;
8089 if (exit_reason == EXIT_REASON_MSR_WRITE)
8090 bitmap += 2048;
8091 if (msr_index >= 0xc0000000) {
8092 msr_index -= 0xc0000000;
8093 bitmap += 1024;
8094 }
8095
8096 /* Then read the msr_index'th bit from this bitmap: */
8097 if (msr_index < 1024*8) {
8098 unsigned char b;
Paolo Bonzini54bf36a2015-04-08 15:39:23 +02008099 if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1))
Joe Perches1d804d02015-03-30 16:46:09 -07008100 return true;
Nadav Har'El644d7112011-05-25 23:12:35 +03008101 return 1 & (b >> (msr_index & 7));
8102 } else
Joe Perches1d804d02015-03-30 16:46:09 -07008103 return true; /* let L1 handle the wrong parameter */
Nadav Har'El644d7112011-05-25 23:12:35 +03008104}
8105
8106/*
8107 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
8108 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
8109 * intercept (via guest_host_mask etc.) the current event.
8110 */
8111static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
8112 struct vmcs12 *vmcs12)
8113{
8114 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
8115 int cr = exit_qualification & 15;
Jan H. Schönherra74bec42017-05-20 13:22:56 +02008116 int reg;
8117 unsigned long val;
Nadav Har'El644d7112011-05-25 23:12:35 +03008118
8119 switch ((exit_qualification >> 4) & 3) {
8120 case 0: /* mov to cr */
Jan H. Schönherra74bec42017-05-20 13:22:56 +02008121 reg = (exit_qualification >> 8) & 15;
8122 val = kvm_register_readl(vcpu, reg);
Nadav Har'El644d7112011-05-25 23:12:35 +03008123 switch (cr) {
8124 case 0:
8125 if (vmcs12->cr0_guest_host_mask &
8126 (val ^ vmcs12->cr0_read_shadow))
Joe Perches1d804d02015-03-30 16:46:09 -07008127 return true;
Nadav Har'El644d7112011-05-25 23:12:35 +03008128 break;
8129 case 3:
8130 if ((vmcs12->cr3_target_count >= 1 &&
8131 vmcs12->cr3_target_value0 == val) ||
8132 (vmcs12->cr3_target_count >= 2 &&
8133 vmcs12->cr3_target_value1 == val) ||
8134 (vmcs12->cr3_target_count >= 3 &&
8135 vmcs12->cr3_target_value2 == val) ||
8136 (vmcs12->cr3_target_count >= 4 &&
8137 vmcs12->cr3_target_value3 == val))
Joe Perches1d804d02015-03-30 16:46:09 -07008138 return false;
Nadav Har'El644d7112011-05-25 23:12:35 +03008139 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
Joe Perches1d804d02015-03-30 16:46:09 -07008140 return true;
Nadav Har'El644d7112011-05-25 23:12:35 +03008141 break;
8142 case 4:
8143 if (vmcs12->cr4_guest_host_mask &
8144 (vmcs12->cr4_read_shadow ^ val))
Joe Perches1d804d02015-03-30 16:46:09 -07008145 return true;
Nadav Har'El644d7112011-05-25 23:12:35 +03008146 break;
8147 case 8:
8148 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
Joe Perches1d804d02015-03-30 16:46:09 -07008149 return true;
Nadav Har'El644d7112011-05-25 23:12:35 +03008150 break;
8151 }
8152 break;
8153 case 2: /* clts */
8154 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
8155 (vmcs12->cr0_read_shadow & X86_CR0_TS))
Joe Perches1d804d02015-03-30 16:46:09 -07008156 return true;
Nadav Har'El644d7112011-05-25 23:12:35 +03008157 break;
8158 case 1: /* mov from cr */
8159 switch (cr) {
8160 case 3:
8161 if (vmcs12->cpu_based_vm_exec_control &
8162 CPU_BASED_CR3_STORE_EXITING)
Joe Perches1d804d02015-03-30 16:46:09 -07008163 return true;
Nadav Har'El644d7112011-05-25 23:12:35 +03008164 break;
8165 case 8:
8166 if (vmcs12->cpu_based_vm_exec_control &
8167 CPU_BASED_CR8_STORE_EXITING)
Joe Perches1d804d02015-03-30 16:46:09 -07008168 return true;
Nadav Har'El644d7112011-05-25 23:12:35 +03008169 break;
8170 }
8171 break;
8172 case 3: /* lmsw */
8173 /*
8174 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
8175 * cr0. Other attempted changes are ignored, with no exit.
8176 */
Jan H. Schönherra74bec42017-05-20 13:22:56 +02008177 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
Nadav Har'El644d7112011-05-25 23:12:35 +03008178 if (vmcs12->cr0_guest_host_mask & 0xe &
8179 (val ^ vmcs12->cr0_read_shadow))
Joe Perches1d804d02015-03-30 16:46:09 -07008180 return true;
Nadav Har'El644d7112011-05-25 23:12:35 +03008181 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
8182 !(vmcs12->cr0_read_shadow & 0x1) &&
8183 (val & 0x1))
Joe Perches1d804d02015-03-30 16:46:09 -07008184 return true;
Nadav Har'El644d7112011-05-25 23:12:35 +03008185 break;
8186 }
Joe Perches1d804d02015-03-30 16:46:09 -07008187 return false;
Nadav Har'El644d7112011-05-25 23:12:35 +03008188}
8189
8190/*
8191 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
8192 * should handle it ourselves in L0 (and then continue L2). Only call this
8193 * when in is_guest_mode (L2).
8194 */
8195static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
8196{
Nadav Har'El644d7112011-05-25 23:12:35 +03008197 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8198 struct vcpu_vmx *vmx = to_vmx(vcpu);
8199 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
Jan Kiszka957c8972013-02-24 14:11:34 +01008200 u32 exit_reason = vmx->exit_reason;
Nadav Har'El644d7112011-05-25 23:12:35 +03008201
Jan Kiszka542060e2014-01-04 18:47:21 +01008202 trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
8203 vmcs_readl(EXIT_QUALIFICATION),
8204 vmx->idt_vectoring_info,
8205 intr_info,
8206 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8207 KVM_ISA_VMX);
8208
David Matlackb7649e12017-08-01 14:00:40 -07008209 /*
8210 * The host physical addresses of some pages of guest memory
Jim Mattson46e24df2017-11-27 17:22:25 -06008211 * are loaded into the vmcs02 (e.g. vmcs12's Virtual APIC
8212 * Page). The CPU may write to these pages via their host
8213 * physical address while L2 is running, bypassing any
8214 * address-translation-based dirty tracking (e.g. EPT write
8215 * protection).
David Matlackb7649e12017-08-01 14:00:40 -07008216 *
8217 * Mark them dirty on every exit from L2 to prevent them from
8218 * getting out of sync with dirty tracking.
8219 */
8220 nested_mark_vmcs12_pages_dirty(vcpu);
8221
Nadav Har'El644d7112011-05-25 23:12:35 +03008222 if (vmx->nested.nested_run_pending)
Joe Perches1d804d02015-03-30 16:46:09 -07008223 return false;
Nadav Har'El644d7112011-05-25 23:12:35 +03008224
8225 if (unlikely(vmx->fail)) {
Jan Kiszkabd801582011-09-12 11:26:22 +02008226 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
8227 vmcs_read32(VM_INSTRUCTION_ERROR));
Joe Perches1d804d02015-03-30 16:46:09 -07008228 return true;
Nadav Har'El644d7112011-05-25 23:12:35 +03008229 }
8230
8231 switch (exit_reason) {
8232 case EXIT_REASON_EXCEPTION_NMI:
Jim Mattson3f618a02016-12-12 11:01:37 -08008233 if (is_nmi(intr_info))
Joe Perches1d804d02015-03-30 16:46:09 -07008234 return false;
Nadav Har'El644d7112011-05-25 23:12:35 +03008235 else if (is_page_fault(intr_info))
8236 return enable_ept;
Anthoine Bourgeoise504c902013-11-13 11:45:37 +01008237 else if (is_no_device(intr_info) &&
Paolo Bonziniccf98442014-02-27 22:54:11 +01008238 !(vmcs12->guest_cr0 & X86_CR0_TS))
Joe Perches1d804d02015-03-30 16:46:09 -07008239 return false;
Jan Kiszka6f054852016-02-09 20:15:18 +01008240 else if (is_debug(intr_info) &&
8241 vcpu->guest_debug &
8242 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
8243 return false;
8244 else if (is_breakpoint(intr_info) &&
8245 vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
8246 return false;
Nadav Har'El644d7112011-05-25 23:12:35 +03008247 return vmcs12->exception_bitmap &
8248 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
8249 case EXIT_REASON_EXTERNAL_INTERRUPT:
Joe Perches1d804d02015-03-30 16:46:09 -07008250 return false;
Nadav Har'El644d7112011-05-25 23:12:35 +03008251 case EXIT_REASON_TRIPLE_FAULT:
Joe Perches1d804d02015-03-30 16:46:09 -07008252 return true;
Nadav Har'El644d7112011-05-25 23:12:35 +03008253 case EXIT_REASON_PENDING_INTERRUPT:
Jan Kiszka3b656cf2013-04-14 12:12:45 +02008254 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
Nadav Har'El644d7112011-05-25 23:12:35 +03008255 case EXIT_REASON_NMI_WINDOW:
Jan Kiszka3b656cf2013-04-14 12:12:45 +02008256 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
Nadav Har'El644d7112011-05-25 23:12:35 +03008257 case EXIT_REASON_TASK_SWITCH:
Joe Perches1d804d02015-03-30 16:46:09 -07008258 return true;
Nadav Har'El644d7112011-05-25 23:12:35 +03008259 case EXIT_REASON_CPUID:
Joe Perches1d804d02015-03-30 16:46:09 -07008260 return true;
Nadav Har'El644d7112011-05-25 23:12:35 +03008261 case EXIT_REASON_HLT:
8262 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
8263 case EXIT_REASON_INVD:
Joe Perches1d804d02015-03-30 16:46:09 -07008264 return true;
Nadav Har'El644d7112011-05-25 23:12:35 +03008265 case EXIT_REASON_INVLPG:
8266 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
8267 case EXIT_REASON_RDPMC:
8268 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
Jan Kiszkab3a2a902015-03-23 19:27:19 +01008269 case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
Nadav Har'El644d7112011-05-25 23:12:35 +03008270 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
8271 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
8272 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
8273 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
8274 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
8275 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
Petr Matouseka642fc32014-09-23 20:22:30 +02008276 case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
Nadav Har'El644d7112011-05-25 23:12:35 +03008277 /*
8278 * VMX instructions trap unconditionally. This allows L1 to
8279 * emulate them for its L2 guest, i.e., allows 3-level nesting!
8280 */
Joe Perches1d804d02015-03-30 16:46:09 -07008281 return true;
Nadav Har'El644d7112011-05-25 23:12:35 +03008282 case EXIT_REASON_CR_ACCESS:
8283 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
8284 case EXIT_REASON_DR_ACCESS:
8285 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
8286 case EXIT_REASON_IO_INSTRUCTION:
Jan Kiszka908a7bd2013-02-18 11:21:16 +01008287 return nested_vmx_exit_handled_io(vcpu, vmcs12);
Nadav Har'El644d7112011-05-25 23:12:35 +03008288 case EXIT_REASON_MSR_READ:
8289 case EXIT_REASON_MSR_WRITE:
8290 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
8291 case EXIT_REASON_INVALID_STATE:
Joe Perches1d804d02015-03-30 16:46:09 -07008292 return true;
Nadav Har'El644d7112011-05-25 23:12:35 +03008293 case EXIT_REASON_MWAIT_INSTRUCTION:
8294 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
Mihai Donțu5f3d45e2015-07-05 20:08:57 +03008295 case EXIT_REASON_MONITOR_TRAP_FLAG:
8296 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG);
Nadav Har'El644d7112011-05-25 23:12:35 +03008297 case EXIT_REASON_MONITOR_INSTRUCTION:
8298 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
8299 case EXIT_REASON_PAUSE_INSTRUCTION:
8300 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
8301 nested_cpu_has2(vmcs12,
8302 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
8303 case EXIT_REASON_MCE_DURING_VMENTRY:
Joe Perches1d804d02015-03-30 16:46:09 -07008304 return false;
Nadav Har'El644d7112011-05-25 23:12:35 +03008305 case EXIT_REASON_TPR_BELOW_THRESHOLD:
Wanpeng Lia7c0b072014-08-21 19:46:50 +08008306 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
Nadav Har'El644d7112011-05-25 23:12:35 +03008307 case EXIT_REASON_APIC_ACCESS:
8308 return nested_cpu_has2(vmcs12,
8309 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
Wincy Van82f0dd42015-02-03 23:57:18 +08008310 case EXIT_REASON_APIC_WRITE:
Wincy Van608406e2015-02-03 23:57:51 +08008311 case EXIT_REASON_EOI_INDUCED:
8312 /* apic_write and eoi_induced should exit unconditionally. */
Joe Perches1d804d02015-03-30 16:46:09 -07008313 return true;
Nadav Har'El644d7112011-05-25 23:12:35 +03008314 case EXIT_REASON_EPT_VIOLATION:
Nadav Har'El2b1be672013-08-05 11:07:19 +03008315 /*
8316 * L0 always deals with the EPT violation. If nested EPT is
8317 * used, and the nested mmu code discovers that the address is
8318 * missing in the guest EPT table (EPT12), the EPT violation
8319 * will be injected with nested_ept_inject_page_fault()
8320 */
Joe Perches1d804d02015-03-30 16:46:09 -07008321 return false;
Nadav Har'El644d7112011-05-25 23:12:35 +03008322 case EXIT_REASON_EPT_MISCONFIG:
Nadav Har'El2b1be672013-08-05 11:07:19 +03008323 /*
8324 * L2 never uses directly L1's EPT, but rather L0's own EPT
8325 * table (shadow on EPT) or a merged EPT table that L0 built
8326 * (EPT on EPT). So any problems with the structure of the
8327 * table is L0's fault.
8328 */
Joe Perches1d804d02015-03-30 16:46:09 -07008329 return false;
Nadav Har'El644d7112011-05-25 23:12:35 +03008330 case EXIT_REASON_WBINVD:
8331 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
8332 case EXIT_REASON_XSETBV:
Joe Perches1d804d02015-03-30 16:46:09 -07008333 return true;
Wanpeng Li81dc01f2014-12-04 19:11:07 +08008334 case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
8335 /*
8336 * This should never happen, since it is not possible to
8337 * set XSS to a non-zero value---neither in L1 nor in L2.
8338 * If if it were, XSS would have to be checked against
8339 * the XSS exit bitmap in vmcs12.
8340 */
8341 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
Wanpeng Li55123e32016-07-06 18:29:58 +08008342 case EXIT_REASON_PREEMPTION_TIMER:
8343 return false;
Ladi Prosekd0ee3632017-03-31 10:19:26 +02008344 case EXIT_REASON_PML_FULL:
8345 /* We don't expose PML support to L1. */
8346 return false;
Nadav Har'El644d7112011-05-25 23:12:35 +03008347 default:
Joe Perches1d804d02015-03-30 16:46:09 -07008348 return true;
Nadav Har'El644d7112011-05-25 23:12:35 +03008349 }
8350}
8351
Avi Kivity586f9602010-11-18 13:09:54 +02008352static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
8353{
8354 *info1 = vmcs_readl(EXIT_QUALIFICATION);
8355 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
8356}
8357
Kai Huanga3eaa862015-11-04 13:46:05 +08008358static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
Kai Huang843e4332015-01-28 10:54:28 +08008359{
Kai Huanga3eaa862015-11-04 13:46:05 +08008360 if (vmx->pml_pg) {
8361 __free_page(vmx->pml_pg);
8362 vmx->pml_pg = NULL;
8363 }
Kai Huang843e4332015-01-28 10:54:28 +08008364}
8365
Paolo Bonzini54bf36a2015-04-08 15:39:23 +02008366static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
Kai Huang843e4332015-01-28 10:54:28 +08008367{
Paolo Bonzini54bf36a2015-04-08 15:39:23 +02008368 struct vcpu_vmx *vmx = to_vmx(vcpu);
Kai Huang843e4332015-01-28 10:54:28 +08008369 u64 *pml_buf;
8370 u16 pml_idx;
8371
8372 pml_idx = vmcs_read16(GUEST_PML_INDEX);
8373
8374 /* Do nothing if PML buffer is empty */
8375 if (pml_idx == (PML_ENTITY_NUM - 1))
8376 return;
8377
8378 /* PML index always points to next available PML buffer entity */
8379 if (pml_idx >= PML_ENTITY_NUM)
8380 pml_idx = 0;
8381 else
8382 pml_idx++;
8383
8384 pml_buf = page_address(vmx->pml_pg);
8385 for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
8386 u64 gpa;
8387
8388 gpa = pml_buf[pml_idx];
8389 WARN_ON(gpa & (PAGE_SIZE - 1));
Paolo Bonzini54bf36a2015-04-08 15:39:23 +02008390 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
Kai Huang843e4332015-01-28 10:54:28 +08008391 }
8392
8393 /* reset PML index */
8394 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
8395}
8396
8397/*
8398 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
8399 * Called before reporting dirty_bitmap to userspace.
8400 */
8401static void kvm_flush_pml_buffers(struct kvm *kvm)
8402{
8403 int i;
8404 struct kvm_vcpu *vcpu;
8405 /*
8406 * We only need to kick vcpu out of guest mode here, as PML buffer
8407 * is flushed at beginning of all VMEXITs, and it's obvious that only
8408 * vcpus running in guest are possible to have unflushed GPAs in PML
8409 * buffer.
8410 */
8411 kvm_for_each_vcpu(i, vcpu, kvm)
8412 kvm_vcpu_kick(vcpu);
8413}
8414
Paolo Bonzini4eb64dc2015-04-30 12:57:28 +02008415static void vmx_dump_sel(char *name, uint32_t sel)
8416{
8417 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
Chao Peng7c3bab12017-02-21 03:50:01 -05008418 name, vmcs_read16(sel),
Paolo Bonzini4eb64dc2015-04-30 12:57:28 +02008419 vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
8420 vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
8421 vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
8422}
8423
8424static void vmx_dump_dtsel(char *name, uint32_t limit)
8425{
8426 pr_err("%s limit=0x%08x, base=0x%016lx\n",
8427 name, vmcs_read32(limit),
8428 vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
8429}
8430
8431static void dump_vmcs(void)
8432{
8433 u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
8434 u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
8435 u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
8436 u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
8437 u32 secondary_exec_control = 0;
8438 unsigned long cr4 = vmcs_readl(GUEST_CR4);
Paolo Bonzinif3531052015-12-03 15:49:56 +01008439 u64 efer = vmcs_read64(GUEST_IA32_EFER);
Paolo Bonzini4eb64dc2015-04-30 12:57:28 +02008440 int i, n;
8441
8442 if (cpu_has_secondary_exec_ctrls())
8443 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8444
8445 pr_err("*** Guest State ***\n");
8446 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8447 vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
8448 vmcs_readl(CR0_GUEST_HOST_MASK));
8449 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8450 cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
8451 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
8452 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
8453 (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
8454 {
Paolo Bonzini845c5b42015-12-03 15:51:00 +01008455 pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n",
8456 vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
8457 pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n",
8458 vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
Paolo Bonzini4eb64dc2015-04-30 12:57:28 +02008459 }
8460 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n",
8461 vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
8462 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n",
8463 vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
8464 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8465 vmcs_readl(GUEST_SYSENTER_ESP),
8466 vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
8467 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR);
8468 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR);
8469 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR);
8470 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR);
8471 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR);
8472 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR);
8473 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
8474 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
8475 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
8476 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR);
8477 if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
8478 (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
Paolo Bonzini845c5b42015-12-03 15:51:00 +01008479 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
8480 efer, vmcs_read64(GUEST_IA32_PAT));
8481 pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n",
8482 vmcs_read64(GUEST_IA32_DEBUGCTL),
Paolo Bonzini4eb64dc2015-04-30 12:57:28 +02008483 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
8484 if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
Paolo Bonzini845c5b42015-12-03 15:51:00 +01008485 pr_err("PerfGlobCtl = 0x%016llx\n",
8486 vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
Paolo Bonzini4eb64dc2015-04-30 12:57:28 +02008487 if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
Paolo Bonzini845c5b42015-12-03 15:51:00 +01008488 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
Paolo Bonzini4eb64dc2015-04-30 12:57:28 +02008489 pr_err("Interruptibility = %08x ActivityState = %08x\n",
8490 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
8491 vmcs_read32(GUEST_ACTIVITY_STATE));
8492 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
8493 pr_err("InterruptStatus = %04x\n",
8494 vmcs_read16(GUEST_INTR_STATUS));
8495
8496 pr_err("*** Host State ***\n");
8497 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n",
8498 vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
8499 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
8500 vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
8501 vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
8502 vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
8503 vmcs_read16(HOST_TR_SELECTOR));
8504 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
8505 vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
8506 vmcs_readl(HOST_TR_BASE));
8507 pr_err("GDTBase=%016lx IDTBase=%016lx\n",
8508 vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
8509 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
8510 vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
8511 vmcs_readl(HOST_CR4));
8512 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8513 vmcs_readl(HOST_IA32_SYSENTER_ESP),
8514 vmcs_read32(HOST_IA32_SYSENTER_CS),
8515 vmcs_readl(HOST_IA32_SYSENTER_EIP));
8516 if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
Paolo Bonzini845c5b42015-12-03 15:51:00 +01008517 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
8518 vmcs_read64(HOST_IA32_EFER),
8519 vmcs_read64(HOST_IA32_PAT));
Paolo Bonzini4eb64dc2015-04-30 12:57:28 +02008520 if (vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
Paolo Bonzini845c5b42015-12-03 15:51:00 +01008521 pr_err("PerfGlobCtl = 0x%016llx\n",
8522 vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
Paolo Bonzini4eb64dc2015-04-30 12:57:28 +02008523
8524 pr_err("*** Control State ***\n");
8525 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
8526 pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
8527 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
8528 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
8529 vmcs_read32(EXCEPTION_BITMAP),
8530 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
8531 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
8532 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
8533 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8534 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
8535 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
8536 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
8537 vmcs_read32(VM_EXIT_INTR_INFO),
8538 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8539 vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
8540 pr_err(" reason=%08x qualification=%016lx\n",
8541 vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
8542 pr_err("IDTVectoring: info=%08x errcode=%08x\n",
8543 vmcs_read32(IDT_VECTORING_INFO_FIELD),
8544 vmcs_read32(IDT_VECTORING_ERROR_CODE));
Paolo Bonzini845c5b42015-12-03 15:51:00 +01008545 pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
Haozhong Zhang8cfe9862015-10-20 15:39:12 +08008546 if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
Paolo Bonzini845c5b42015-12-03 15:51:00 +01008547 pr_err("TSC Multiplier = 0x%016llx\n",
8548 vmcs_read64(TSC_MULTIPLIER));
Paolo Bonzini4eb64dc2015-04-30 12:57:28 +02008549 if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW)
8550 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
8551 if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
8552 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
8553 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
Paolo Bonzini845c5b42015-12-03 15:51:00 +01008554 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
Paolo Bonzini4eb64dc2015-04-30 12:57:28 +02008555 n = vmcs_read32(CR3_TARGET_COUNT);
8556 for (i = 0; i + 1 < n; i += 4)
8557 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
8558 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
8559 i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
8560 if (i < n)
8561 pr_err("CR3 target%u=%016lx\n",
8562 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
8563 if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
8564 pr_err("PLE Gap=%08x Window=%08x\n",
8565 vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
8566 if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
8567 pr_err("Virtual processor ID = 0x%04x\n",
8568 vmcs_read16(VIRTUAL_PROCESSOR_ID));
8569}
8570
Avi Kivity6aa8b732006-12-10 02:21:36 -08008571/*
8572 * The guest has exited. See if we can fix it or if we need userspace
8573 * assistance.
8574 */
Avi Kivity851ba692009-08-24 11:10:17 +03008575static int vmx_handle_exit(struct kvm_vcpu *vcpu)
Avi Kivity6aa8b732006-12-10 02:21:36 -08008576{
Avi Kivity29bd8a72007-09-10 17:27:03 +03008577 struct vcpu_vmx *vmx = to_vmx(vcpu);
Andi Kleena0861c02009-06-08 17:37:09 +08008578 u32 exit_reason = vmx->exit_reason;
Avi Kivity1155f762007-11-22 11:30:47 +02008579 u32 vectoring_info = vmx->idt_vectoring_info;
Avi Kivity29bd8a72007-09-10 17:27:03 +03008580
Paolo Bonzini8b89fe12015-12-10 18:37:32 +01008581 trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
8582
Kai Huang843e4332015-01-28 10:54:28 +08008583 /*
8584 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
8585 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
8586 * querying dirty_bitmap, we only need to kick all vcpus out of guest
8587 * mode as if vcpus is in root mode, the PML buffer must has been
8588 * flushed already.
8589 */
8590 if (enable_pml)
Paolo Bonzini54bf36a2015-04-08 15:39:23 +02008591 vmx_flush_pml_buffer(vcpu);
Kai Huang843e4332015-01-28 10:54:28 +08008592
Mohammed Gamal80ced182009-09-01 12:48:18 +02008593 /* If guest state is invalid, start emulating */
Gleb Natapov14168782013-01-21 15:36:49 +02008594 if (vmx->emulation_required)
Mohammed Gamal80ced182009-09-01 12:48:18 +02008595 return handle_invalid_guest_state(vcpu);
Guillaume Thouvenin1d5a4d92008-10-29 09:39:42 +01008596
Nadav Har'El644d7112011-05-25 23:12:35 +03008597 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
Jan Kiszka533558b2014-01-04 18:47:20 +01008598 nested_vmx_vmexit(vcpu, exit_reason,
8599 vmcs_read32(VM_EXIT_INTR_INFO),
8600 vmcs_readl(EXIT_QUALIFICATION));
Nadav Har'El644d7112011-05-25 23:12:35 +03008601 return 1;
8602 }
8603
Mohammed Gamal51207022010-05-31 22:40:54 +03008604 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
Paolo Bonzini4eb64dc2015-04-30 12:57:28 +02008605 dump_vmcs();
Mohammed Gamal51207022010-05-31 22:40:54 +03008606 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8607 vcpu->run->fail_entry.hardware_entry_failure_reason
8608 = exit_reason;
8609 return 0;
8610 }
8611
Avi Kivity29bd8a72007-09-10 17:27:03 +03008612 if (unlikely(vmx->fail)) {
Avi Kivity851ba692009-08-24 11:10:17 +03008613 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8614 vcpu->run->fail_entry.hardware_entry_failure_reason
Avi Kivity29bd8a72007-09-10 17:27:03 +03008615 = vmcs_read32(VM_INSTRUCTION_ERROR);
8616 return 0;
8617 }
Avi Kivity6aa8b732006-12-10 02:21:36 -08008618
Xiao Guangrongb9bf6882012-10-17 13:46:52 +08008619 /*
8620 * Note:
8621 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8622 * delivery event since it indicates guest is accessing MMIO.
8623 * The vm-exit can be triggered again after return to guest that
8624 * will cause infinite loop.
8625 */
Mike Dayd77c26f2007-10-08 09:02:08 -04008626 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
Sheng Yang14394422008-04-28 12:24:45 +08008627 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
Jan Kiszka60637aa2008-09-26 09:30:47 +02008628 exit_reason != EXIT_REASON_EPT_VIOLATION &&
Cao, Leib244c9f2016-07-15 13:54:04 +00008629 exit_reason != EXIT_REASON_PML_FULL &&
Xiao Guangrongb9bf6882012-10-17 13:46:52 +08008630 exit_reason != EXIT_REASON_TASK_SWITCH)) {
8631 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
8632 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
8633 vcpu->run->internal.ndata = 2;
8634 vcpu->run->internal.data[0] = vectoring_info;
8635 vcpu->run->internal.data[1] = exit_reason;
8636 return 0;
8637 }
Jan Kiszka3b86cd92008-09-26 09:30:57 +02008638
Nadav Har'El644d7112011-05-25 23:12:35 +03008639 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
8640 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
Nadav Har'Elf5c43682013-08-05 11:07:20 +03008641 get_vmcs12(vcpu))))) {
Gleb Natapovc4282df2009-04-21 17:45:07 +03008642 if (vmx_interrupt_allowed(vcpu)) {
Jan Kiszka3b86cd92008-09-26 09:30:57 +02008643 vmx->soft_vnmi_blocked = 0;
Jan Kiszka3b86cd92008-09-26 09:30:57 +02008644 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
Jan Kiszka45312202008-12-11 16:54:54 +01008645 vcpu->arch.nmi_pending) {
Jan Kiszka3b86cd92008-09-26 09:30:57 +02008646 /*
8647 * This CPU don't support us in finding the end of an
8648 * NMI-blocked window if the guest runs with IRQs
8649 * disabled. So we pull the trigger after 1 s of
8650 * futile waiting, but inform the user about this.
8651 */
8652 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
8653 "state on VCPU %d after 1 s timeout\n",
8654 __func__, vcpu->vcpu_id);
8655 vmx->soft_vnmi_blocked = 0;
Jan Kiszka3b86cd92008-09-26 09:30:57 +02008656 }
Jan Kiszka3b86cd92008-09-26 09:30:57 +02008657 }
8658
Avi Kivity6aa8b732006-12-10 02:21:36 -08008659 if (exit_reason < kvm_vmx_max_exit_handlers
8660 && kvm_vmx_exit_handlers[exit_reason])
Avi Kivity851ba692009-08-24 11:10:17 +03008661 return kvm_vmx_exit_handlers[exit_reason](vcpu);
Avi Kivity6aa8b732006-12-10 02:21:36 -08008662 else {
Michael S. Tsirkin2bc19dc2014-09-18 16:21:16 +03008663 WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_reason);
8664 kvm_queue_exception(vcpu, UD_VECTOR);
8665 return 1;
Avi Kivity6aa8b732006-12-10 02:21:36 -08008666 }
Avi Kivity6aa8b732006-12-10 02:21:36 -08008667}
8668
Paolo Bonzinib3d648a2018-07-02 12:47:38 +02008669/*
8670 * Software based L1D cache flush which is used when microcode providing
8671 * the cache control MSR is not loaded.
8672 *
8673 * The L1D cache is 32 KiB on Nehalem and later microarchitectures, but to
8674 * flush it is required to read in 64 KiB because the replacement algorithm
8675 * is not exactly LRU. This could be sized at runtime via topology
8676 * information but as all relevant affected CPUs have 32KiB L1D cache size
8677 * there is no point in doing so.
8678 */
Paolo Bonzinib3dc63c2018-07-02 13:07:14 +02008679static void vmx_l1d_flush(struct kvm_vcpu *vcpu)
Paolo Bonzinib3d648a2018-07-02 12:47:38 +02008680{
8681 int size = PAGE_SIZE << L1D_CACHE_ORDER;
Paolo Bonzinib3dc63c2018-07-02 13:07:14 +02008682
8683 /*
Thomas Gleixner31282cf2018-07-13 16:23:17 +02008684 * This code is only executed when the the flush mode is 'cond' or
8685 * 'always'
Paolo Bonzinib3dc63c2018-07-02 13:07:14 +02008686 */
Nicolai Stange936f5662018-07-21 22:25:00 +02008687 if (static_branch_likely(&vmx_l1d_flush_cond)) {
Nicolai Stangee371c922018-07-27 13:22:16 +02008688 bool flush_l1d;
Nicolai Stange90bc3062018-07-21 22:35:28 +02008689
Nicolai Stange698ac1b2018-07-21 22:16:56 +02008690 /*
Nicolai Stangee371c922018-07-27 13:22:16 +02008691 * Clear the per-vcpu flush bit, it gets set again
8692 * either from vcpu_run() or from one of the unsafe
8693 * VMEXIT handlers.
Nicolai Stange698ac1b2018-07-21 22:16:56 +02008694 */
Nicolai Stangee371c922018-07-27 13:22:16 +02008695 flush_l1d = vcpu->arch.l1tf_flush_l1d;
Thomas Gleixnerdff09822018-07-13 16:23:20 +02008696 vcpu->arch.l1tf_flush_l1d = false;
Nicolai Stangee371c922018-07-27 13:22:16 +02008697
8698 /*
8699 * Clear the per-cpu flush bit, it gets set again from
8700 * the interrupt handlers.
8701 */
8702 flush_l1d |= kvm_get_cpu_l1tf_flush_l1d();
8703 kvm_clear_cpu_l1tf_flush_l1d();
8704
Nicolai Stange90bc3062018-07-21 22:35:28 +02008705 if (!flush_l1d)
8706 return;
Nicolai Stange698ac1b2018-07-21 22:16:56 +02008707 }
Paolo Bonzinib3dc63c2018-07-02 13:07:14 +02008708
8709 vcpu->stat.l1d_flush++;
Paolo Bonzinib3d648a2018-07-02 12:47:38 +02008710
Paolo Bonziniacca8a72018-07-02 13:03:48 +02008711 if (static_cpu_has(X86_FEATURE_FLUSH_L1D)) {
8712 wrmsrl(MSR_IA32_FLUSH_CMD, L1D_FLUSH);
8713 return;
8714 }
8715
Paolo Bonzinib3d648a2018-07-02 12:47:38 +02008716 asm volatile(
8717 /* First ensure the pages are in the TLB */
8718 "xorl %%eax, %%eax\n"
8719 ".Lpopulate_tlb:\n\t"
Nicolai Stange587d4992018-07-18 19:07:38 +02008720 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
Paolo Bonzinib3d648a2018-07-02 12:47:38 +02008721 "addl $4096, %%eax\n\t"
8722 "cmpl %%eax, %[size]\n\t"
8723 "jne .Lpopulate_tlb\n\t"
8724 "xorl %%eax, %%eax\n\t"
8725 "cpuid\n\t"
8726 /* Now fill the cache */
8727 "xorl %%eax, %%eax\n"
8728 ".Lfill_cache:\n"
Nicolai Stange587d4992018-07-18 19:07:38 +02008729 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
Paolo Bonzinib3d648a2018-07-02 12:47:38 +02008730 "addl $64, %%eax\n\t"
8731 "cmpl %%eax, %[size]\n\t"
8732 "jne .Lfill_cache\n\t"
8733 "lfence\n"
Nicolai Stange587d4992018-07-18 19:07:38 +02008734 :: [flush_pages] "r" (vmx_l1d_flush_pages),
Paolo Bonzinib3d648a2018-07-02 12:47:38 +02008735 [size] "r" (size)
8736 : "eax", "ebx", "ecx", "edx");
8737}
8738
Gleb Natapov95ba8273132009-04-21 17:45:08 +03008739static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
Yang, Sheng6e5d8652007-09-12 18:03:11 +08008740{
Wanpeng Lia7c0b072014-08-21 19:46:50 +08008741 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8742
8743 if (is_guest_mode(vcpu) &&
8744 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
8745 return;
8746
Gleb Natapov95ba8273132009-04-21 17:45:08 +03008747 if (irr == -1 || tpr < irr) {
Yang, Sheng6e5d8652007-09-12 18:03:11 +08008748 vmcs_write32(TPR_THRESHOLD, 0);
8749 return;
8750 }
8751
Gleb Natapov95ba8273132009-04-21 17:45:08 +03008752 vmcs_write32(TPR_THRESHOLD, irr);
Yang, Sheng6e5d8652007-09-12 18:03:11 +08008753}
8754
Yang Zhang8d146952013-01-25 10:18:50 +08008755static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
8756{
8757 u32 sec_exec_control;
8758
Radim Krčmářdccbfcf2016-08-08 20:16:23 +02008759 /* Postpone execution until vmcs01 is the current VMCS. */
8760 if (is_guest_mode(vcpu)) {
8761 to_vmx(vcpu)->nested.change_vmcs01_virtual_x2apic_mode = true;
8762 return;
8763 }
8764
Wanpeng Lif6e90f92016-09-22 07:43:25 +08008765 if (!cpu_has_vmx_virtualize_x2apic_mode())
Yang Zhang8d146952013-01-25 10:18:50 +08008766 return;
8767
Paolo Bonzini35754c92015-07-29 12:05:37 +02008768 if (!cpu_need_tpr_shadow(vcpu))
Yang Zhang8d146952013-01-25 10:18:50 +08008769 return;
8770
8771 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8772
8773 if (set) {
8774 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8775 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8776 } else {
8777 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8778 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
Jim Mattson8386ff52017-03-16 13:53:59 -07008779 vmx_flush_tlb_ept_only(vcpu);
Yang Zhang8d146952013-01-25 10:18:50 +08008780 }
8781 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
8782
Paolo Bonzini6236b782018-01-16 16:51:18 +01008783 vmx_update_msr_bitmap(vcpu);
Yang Zhang8d146952013-01-25 10:18:50 +08008784}
8785
Tang Chen38b99172014-09-24 15:57:54 +08008786static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
8787{
8788 struct vcpu_vmx *vmx = to_vmx(vcpu);
8789
8790 /*
8791 * Currently we do not handle the nested case where L2 has an
8792 * APIC access page of its own; that page is still pinned.
8793 * Hence, we skip the case where the VCPU is in guest mode _and_
8794 * L1 prepared an APIC access page for L2.
8795 *
8796 * For the case where L1 and L2 share the same APIC access page
8797 * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
8798 * in the vmcs12), this function will only update either the vmcs01
8799 * or the vmcs02. If the former, the vmcs02 will be updated by
8800 * prepare_vmcs02. If the latter, the vmcs01 will be updated in
8801 * the next L2->L1 exit.
8802 */
8803 if (!is_guest_mode(vcpu) ||
David Matlack4f2777b2016-07-13 17:16:37 -07008804 !nested_cpu_has2(get_vmcs12(&vmx->vcpu),
Jim Mattson8386ff52017-03-16 13:53:59 -07008805 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
Tang Chen38b99172014-09-24 15:57:54 +08008806 vmcs_write64(APIC_ACCESS_ADDR, hpa);
Jim Mattson8386ff52017-03-16 13:53:59 -07008807 vmx_flush_tlb_ept_only(vcpu);
8808 }
Tang Chen38b99172014-09-24 15:57:54 +08008809}
8810
Paolo Bonzini67c9ddd2016-05-10 17:01:23 +02008811static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
Yang Zhangc7c9c562013-01-25 10:18:51 +08008812{
8813 u16 status;
8814 u8 old;
8815
Paolo Bonzini67c9ddd2016-05-10 17:01:23 +02008816 if (max_isr == -1)
8817 max_isr = 0;
Yang Zhangc7c9c562013-01-25 10:18:51 +08008818
8819 status = vmcs_read16(GUEST_INTR_STATUS);
8820 old = status >> 8;
Paolo Bonzini67c9ddd2016-05-10 17:01:23 +02008821 if (max_isr != old) {
Yang Zhangc7c9c562013-01-25 10:18:51 +08008822 status &= 0xff;
Paolo Bonzini67c9ddd2016-05-10 17:01:23 +02008823 status |= max_isr << 8;
Yang Zhangc7c9c562013-01-25 10:18:51 +08008824 vmcs_write16(GUEST_INTR_STATUS, status);
8825 }
8826}
8827
8828static void vmx_set_rvi(int vector)
8829{
8830 u16 status;
8831 u8 old;
8832
Wei Wang4114c272014-11-05 10:53:43 +08008833 if (vector == -1)
8834 vector = 0;
8835
Yang Zhangc7c9c562013-01-25 10:18:51 +08008836 status = vmcs_read16(GUEST_INTR_STATUS);
8837 old = (u8)status & 0xff;
8838 if ((u8)vector != old) {
8839 status &= ~0xff;
8840 status |= (u8)vector;
8841 vmcs_write16(GUEST_INTR_STATUS, status);
8842 }
8843}
8844
8845static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
8846{
Wanpeng Li963fee12014-07-17 19:03:00 +08008847 if (!is_guest_mode(vcpu)) {
8848 vmx_set_rvi(max_irr);
8849 return;
8850 }
8851
Wei Wang4114c272014-11-05 10:53:43 +08008852 if (max_irr == -1)
8853 return;
8854
Wanpeng Li963fee12014-07-17 19:03:00 +08008855 /*
Wei Wang4114c272014-11-05 10:53:43 +08008856 * In guest mode. If a vmexit is needed, vmx_check_nested_events
8857 * handles it.
8858 */
8859 if (nested_exit_on_intr(vcpu))
8860 return;
8861
8862 /*
8863 * Else, fall back to pre-APICv interrupt injection since L2
Wanpeng Li963fee12014-07-17 19:03:00 +08008864 * is run without virtual interrupt delivery.
8865 */
8866 if (!kvm_event_needs_reinjection(vcpu) &&
8867 vmx_interrupt_allowed(vcpu)) {
8868 kvm_queue_interrupt(vcpu, max_irr, false);
8869 vmx_inject_irq(vcpu);
8870 }
Yang Zhangc7c9c562013-01-25 10:18:51 +08008871}
8872
Andrey Smetanin63086302015-11-10 15:36:32 +03008873static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
Yang Zhangc7c9c562013-01-25 10:18:51 +08008874{
Andrey Smetanind62caab2015-11-10 15:36:33 +03008875 if (!kvm_vcpu_apicv_active(vcpu))
Yang Zhang3d81bc72013-04-11 19:25:13 +08008876 return;
8877
Yang Zhangc7c9c562013-01-25 10:18:51 +08008878 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
8879 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
8880 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
8881 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
8882}
8883
Avi Kivity51aa01d2010-07-20 14:31:20 +03008884static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
Avi Kivitycf393f72008-07-01 16:20:21 +03008885{
Avi Kivity00eba012011-03-07 17:24:54 +02008886 u32 exit_intr_info;
8887
8888 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
8889 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
8890 return;
8891
Avi Kivityc5ca8e52011-03-07 17:37:37 +02008892 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
Avi Kivity00eba012011-03-07 17:24:54 +02008893 exit_intr_info = vmx->exit_intr_info;
Andi Kleena0861c02009-06-08 17:37:09 +08008894
8895 /* Handle machine checks before interrupts are enabled */
Avi Kivity00eba012011-03-07 17:24:54 +02008896 if (is_machine_check(exit_intr_info))
Andi Kleena0861c02009-06-08 17:37:09 +08008897 kvm_machine_check();
8898
Gleb Natapov20f65982009-05-11 13:35:55 +03008899 /* We need to handle NMIs before interrupts are enabled */
Jim Mattson3f618a02016-12-12 11:01:37 -08008900 if (is_nmi(exit_intr_info)) {
Zhang, Yanminff9d07a2010-04-19 13:32:45 +08008901 kvm_before_handle_nmi(&vmx->vcpu);
Gleb Natapov20f65982009-05-11 13:35:55 +03008902 asm("int $2");
Zhang, Yanminff9d07a2010-04-19 13:32:45 +08008903 kvm_after_handle_nmi(&vmx->vcpu);
8904 }
Avi Kivity51aa01d2010-07-20 14:31:20 +03008905}
Gleb Natapov20f65982009-05-11 13:35:55 +03008906
Yang Zhanga547c6d2013-04-11 19:25:10 +08008907static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
8908{
8909 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
Chris J Arges3f62de52016-01-22 15:44:38 -06008910 register void *__sp asm(_ASM_SP);
Yang Zhanga547c6d2013-04-11 19:25:10 +08008911
8912 /*
8913 * If external interrupt exists, IF bit is set in rflags/eflags on the
8914 * interrupt stack frame, and interrupt will be enabled on a return
8915 * from interrupt handler.
8916 */
8917 if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
8918 == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
8919 unsigned int vector;
8920 unsigned long entry;
8921 gate_desc *desc;
8922 struct vcpu_vmx *vmx = to_vmx(vcpu);
8923#ifdef CONFIG_X86_64
8924 unsigned long tmp;
8925#endif
8926
8927 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8928 desc = (gate_desc *)vmx->host_idt_base + vector;
8929 entry = gate_offset(*desc);
8930 asm volatile(
8931#ifdef CONFIG_X86_64
8932 "mov %%" _ASM_SP ", %[sp]\n\t"
8933 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
8934 "push $%c[ss]\n\t"
8935 "push %[sp]\n\t"
8936#endif
8937 "pushf\n\t"
Yang Zhanga547c6d2013-04-11 19:25:10 +08008938 __ASM_SIZE(push) " $%c[cs]\n\t"
Peter Zijlstraec86a1d2018-01-25 10:58:14 +01008939 CALL_NOSPEC
Yang Zhanga547c6d2013-04-11 19:25:10 +08008940 :
8941#ifdef CONFIG_X86_64
Chris J Arges3f62de52016-01-22 15:44:38 -06008942 [sp]"=&r"(tmp),
Yang Zhanga547c6d2013-04-11 19:25:10 +08008943#endif
Chris J Arges3f62de52016-01-22 15:44:38 -06008944 "+r"(__sp)
Yang Zhanga547c6d2013-04-11 19:25:10 +08008945 :
Peter Zijlstraec86a1d2018-01-25 10:58:14 +01008946 THUNK_TARGET(entry),
Yang Zhanga547c6d2013-04-11 19:25:10 +08008947 [ss]"i"(__KERNEL_DS),
8948 [cs]"i"(__KERNEL_CS)
8949 );
Paolo Bonzinif2485b32016-06-15 15:23:11 +02008950 }
Yang Zhanga547c6d2013-04-11 19:25:10 +08008951}
Josh Poimboeuf935893a2017-06-28 10:11:06 -05008952STACK_FRAME_NON_STANDARD(vmx_handle_external_intr);
Yang Zhanga547c6d2013-04-11 19:25:10 +08008953
Tom Lendackyb9655922018-05-10 22:06:39 +02008954static bool vmx_has_emulated_msr(int index)
Paolo Bonzini6d396b52015-04-01 14:25:33 +02008955{
Tom Lendackyb9655922018-05-10 22:06:39 +02008956 switch (index) {
8957 case MSR_IA32_SMBASE:
8958 /*
8959 * We cannot do SMM unless we can run the guest in big
8960 * real mode.
8961 */
8962 return enable_unrestricted_guest || emulate_invalid_guest_state;
8963 case MSR_AMD64_VIRT_SPEC_CTRL:
8964 /* This is AMD only. */
8965 return false;
8966 default:
8967 return true;
8968 }
Paolo Bonzini6d396b52015-04-01 14:25:33 +02008969}
8970
Liu, Jinsongda8999d2014-02-24 10:55:46 +00008971static bool vmx_mpx_supported(void)
8972{
8973 return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
8974 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
8975}
8976
Wanpeng Li55412b22014-12-02 19:21:30 +08008977static bool vmx_xsaves_supported(void)
8978{
8979 return vmcs_config.cpu_based_2nd_exec_ctrl &
8980 SECONDARY_EXEC_XSAVES;
8981}
8982
Avi Kivity51aa01d2010-07-20 14:31:20 +03008983static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
8984{
Avi Kivityc5ca8e52011-03-07 17:37:37 +02008985 u32 exit_intr_info;
Avi Kivity51aa01d2010-07-20 14:31:20 +03008986 bool unblock_nmi;
8987 u8 vector;
8988 bool idtv_info_valid;
8989
8990 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
Gleb Natapov20f65982009-05-11 13:35:55 +03008991
Avi Kivitycf393f72008-07-01 16:20:21 +03008992 if (cpu_has_virtual_nmis()) {
Avi Kivity9d58b932011-03-07 16:52:07 +02008993 if (vmx->nmi_known_unmasked)
8994 return;
Avi Kivityc5ca8e52011-03-07 17:37:37 +02008995 /*
8996 * Can't use vmx->exit_intr_info since we're not sure what
8997 * the exit reason is.
8998 */
8999 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
Avi Kivitycf393f72008-07-01 16:20:21 +03009000 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
9001 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
9002 /*
Gleb Natapov7b4a25c2009-03-30 16:03:08 +03009003 * SDM 3: 27.7.1.2 (September 2008)
Avi Kivitycf393f72008-07-01 16:20:21 +03009004 * Re-set bit "block by NMI" before VM entry if vmexit caused by
9005 * a guest IRET fault.
Gleb Natapov7b4a25c2009-03-30 16:03:08 +03009006 * SDM 3: 23.2.2 (September 2008)
9007 * Bit 12 is undefined in any of the following cases:
9008 * If the VM exit sets the valid bit in the IDT-vectoring
9009 * information field.
9010 * If the VM exit is due to a double fault.
Avi Kivitycf393f72008-07-01 16:20:21 +03009011 */
Gleb Natapov7b4a25c2009-03-30 16:03:08 +03009012 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
9013 vector != DF_VECTOR && !idtv_info_valid)
Avi Kivitycf393f72008-07-01 16:20:21 +03009014 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
9015 GUEST_INTR_STATE_NMI);
Avi Kivity9d58b932011-03-07 16:52:07 +02009016 else
9017 vmx->nmi_known_unmasked =
9018 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
9019 & GUEST_INTR_STATE_NMI);
Jan Kiszka3b86cd92008-09-26 09:30:57 +02009020 } else if (unlikely(vmx->soft_vnmi_blocked))
9021 vmx->vnmi_blocked_time +=
9022 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
Avi Kivity51aa01d2010-07-20 14:31:20 +03009023}
9024
Jan Kiszka3ab66e82013-02-20 14:03:24 +01009025static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
Avi Kivity83422e12010-07-20 14:43:23 +03009026 u32 idt_vectoring_info,
9027 int instr_len_field,
9028 int error_code_field)
Avi Kivity51aa01d2010-07-20 14:31:20 +03009029{
Avi Kivity51aa01d2010-07-20 14:31:20 +03009030 u8 vector;
9031 int type;
9032 bool idtv_info_valid;
9033
9034 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
Avi Kivity668f6122008-07-02 09:28:55 +03009035
Jan Kiszka3ab66e82013-02-20 14:03:24 +01009036 vcpu->arch.nmi_injected = false;
9037 kvm_clear_exception_queue(vcpu);
9038 kvm_clear_interrupt_queue(vcpu);
Gleb Natapov37b96e92009-03-30 16:03:13 +03009039
9040 if (!idtv_info_valid)
9041 return;
9042
Jan Kiszka3ab66e82013-02-20 14:03:24 +01009043 kvm_make_request(KVM_REQ_EVENT, vcpu);
Avi Kivity3842d132010-07-27 12:30:24 +03009044
Avi Kivity668f6122008-07-02 09:28:55 +03009045 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
9046 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
Gleb Natapov37b96e92009-03-30 16:03:13 +03009047
Gleb Natapov64a7ec02009-03-30 16:03:29 +03009048 switch (type) {
Gleb Natapov37b96e92009-03-30 16:03:13 +03009049 case INTR_TYPE_NMI_INTR:
Jan Kiszka3ab66e82013-02-20 14:03:24 +01009050 vcpu->arch.nmi_injected = true;
Avi Kivity668f6122008-07-02 09:28:55 +03009051 /*
Gleb Natapov7b4a25c2009-03-30 16:03:08 +03009052 * SDM 3: 27.7.1.2 (September 2008)
Gleb Natapov37b96e92009-03-30 16:03:13 +03009053 * Clear bit "block by NMI" before VM entry if a NMI
9054 * delivery faulted.
Avi Kivity668f6122008-07-02 09:28:55 +03009055 */
Jan Kiszka3ab66e82013-02-20 14:03:24 +01009056 vmx_set_nmi_mask(vcpu, false);
Gleb Natapov37b96e92009-03-30 16:03:13 +03009057 break;
Gleb Natapov37b96e92009-03-30 16:03:13 +03009058 case INTR_TYPE_SOFT_EXCEPTION:
Jan Kiszka3ab66e82013-02-20 14:03:24 +01009059 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
Gleb Natapov66fd3f72009-05-11 13:35:50 +03009060 /* fall through */
9061 case INTR_TYPE_HARD_EXCEPTION:
Avi Kivity35920a32008-07-03 14:50:12 +03009062 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
Avi Kivity83422e12010-07-20 14:43:23 +03009063 u32 err = vmcs_read32(error_code_field);
Gleb Natapov851eb6672013-09-25 12:51:34 +03009064 kvm_requeue_exception_e(vcpu, vector, err);
Avi Kivity35920a32008-07-03 14:50:12 +03009065 } else
Gleb Natapov851eb6672013-09-25 12:51:34 +03009066 kvm_requeue_exception(vcpu, vector);
Gleb Natapov37b96e92009-03-30 16:03:13 +03009067 break;
Gleb Natapov66fd3f72009-05-11 13:35:50 +03009068 case INTR_TYPE_SOFT_INTR:
Jan Kiszka3ab66e82013-02-20 14:03:24 +01009069 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
Gleb Natapov66fd3f72009-05-11 13:35:50 +03009070 /* fall through */
Gleb Natapov37b96e92009-03-30 16:03:13 +03009071 case INTR_TYPE_EXT_INTR:
Jan Kiszka3ab66e82013-02-20 14:03:24 +01009072 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
Gleb Natapov37b96e92009-03-30 16:03:13 +03009073 break;
9074 default:
9075 break;
Avi Kivityf7d92382008-07-03 16:14:28 +03009076 }
Avi Kivitycf393f72008-07-01 16:20:21 +03009077}
9078
Avi Kivity83422e12010-07-20 14:43:23 +03009079static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
9080{
Jan Kiszka3ab66e82013-02-20 14:03:24 +01009081 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
Avi Kivity83422e12010-07-20 14:43:23 +03009082 VM_EXIT_INSTRUCTION_LEN,
9083 IDT_VECTORING_ERROR_CODE);
9084}
9085
Avi Kivityb463a6f2010-07-20 15:06:17 +03009086static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
9087{
Jan Kiszka3ab66e82013-02-20 14:03:24 +01009088 __vmx_complete_interrupts(vcpu,
Avi Kivityb463a6f2010-07-20 15:06:17 +03009089 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
9090 VM_ENTRY_INSTRUCTION_LEN,
9091 VM_ENTRY_EXCEPTION_ERROR_CODE);
9092
9093 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
9094}
9095
Gleb Natapovd7cd9792011-10-05 14:01:23 +02009096static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
9097{
9098 int i, nr_msrs;
9099 struct perf_guest_switch_msr *msrs;
9100
9101 msrs = perf_guest_get_msrs(&nr_msrs);
9102
9103 if (!msrs)
9104 return;
9105
9106 for (i = 0; i < nr_msrs; i++)
9107 if (msrs[i].host == msrs[i].guest)
9108 clear_atomic_switch_msr(vmx, msrs[i].msr);
9109 else
9110 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
Konrad Rzeszutek Wilkc45ff812018-06-20 22:01:22 -04009111 msrs[i].host, false);
Gleb Natapovd7cd9792011-10-05 14:01:23 +02009112}
9113
Yunhong Jiang64672c92016-06-13 14:19:59 -07009114void vmx_arm_hv_timer(struct kvm_vcpu *vcpu)
9115{
9116 struct vcpu_vmx *vmx = to_vmx(vcpu);
9117 u64 tscl;
9118 u32 delta_tsc;
9119
9120 if (vmx->hv_deadline_tsc == -1)
9121 return;
9122
9123 tscl = rdtsc();
9124 if (vmx->hv_deadline_tsc > tscl)
9125 /* sure to be 32 bit only because checked on set_hv_timer */
9126 delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
9127 cpu_preemption_timer_multi);
9128 else
9129 delta_tsc = 0;
9130
9131 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc);
9132}
9133
Lai Jiangshana3b5ba42011-02-11 14:29:40 +08009134static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
Avi Kivity6aa8b732006-12-10 02:21:36 -08009135{
Gregory Haskinsa2fa3e92007-07-27 08:13:10 -04009136 struct vcpu_vmx *vmx = to_vmx(vcpu);
Andy Lutomirskid974baa2014-10-08 09:02:13 -07009137 unsigned long debugctlmsr, cr4;
Avi Kivity104f2262010-11-18 13:12:52 +02009138
9139 /* Record the guest's net vcpu time for enforced NMI injections. */
9140 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
9141 vmx->entry_time = ktime_get();
9142
9143 /* Don't enter VMX if guest state is invalid, let the exit handler
9144 start emulation until we arrive back to a valid state */
Gleb Natapov14168782013-01-21 15:36:49 +02009145 if (vmx->emulation_required)
Avi Kivity104f2262010-11-18 13:12:52 +02009146 return;
9147
Radim Krčmářa7653ec2014-08-21 18:08:07 +02009148 if (vmx->ple_window_dirty) {
9149 vmx->ple_window_dirty = false;
9150 vmcs_write32(PLE_WINDOW, vmx->ple_window);
9151 }
9152
Abel Gordon012f83c2013-04-18 14:39:25 +03009153 if (vmx->nested.sync_shadow_vmcs) {
9154 copy_vmcs12_to_shadow(vmx);
9155 vmx->nested.sync_shadow_vmcs = false;
9156 }
9157
Avi Kivity104f2262010-11-18 13:12:52 +02009158 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
9159 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
9160 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
9161 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
9162
Andy Lutomirski1e02ce42014-10-24 15:58:08 -07009163 cr4 = cr4_read_shadow();
Andy Lutomirskid974baa2014-10-08 09:02:13 -07009164 if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) {
9165 vmcs_writel(HOST_CR4, cr4);
9166 vmx->host_state.vmcs_host_cr4 = cr4;
9167 }
9168
Avi Kivity104f2262010-11-18 13:12:52 +02009169 /* When single-stepping over STI and MOV SS, we must clear the
9170 * corresponding interruptibility bits in the guest state. Otherwise
9171 * vmentry fails as it then expects bit 14 (BS) in pending debug
9172 * exceptions being set, but that's not correct for the guest debugging
9173 * case. */
9174 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
9175 vmx_set_interrupt_shadow(vcpu, 0);
9176
Xiao Guangrong1be0e612016-03-22 16:51:18 +08009177 if (vmx->guest_pkru_valid)
9178 __write_pkru(vmx->guest_pkru);
9179
Gleb Natapovd7cd9792011-10-05 14:01:23 +02009180 atomic_switch_perf_msrs(vmx);
Gleb Natapov2a7921b2012-08-12 16:12:29 +03009181 debugctlmsr = get_debugctlmsr();
Gleb Natapovd7cd9792011-10-05 14:01:23 +02009182
Yunhong Jiang64672c92016-06-13 14:19:59 -07009183 vmx_arm_hv_timer(vcpu);
9184
KarimAllah Ahmede5a83412018-02-01 22:59:45 +01009185 /*
9186 * If this vCPU has touched SPEC_CTRL, restore the guest's value if
9187 * it's non-zero. Since vmentry is serialising on affected CPUs, there
9188 * is no need to worry about the conditional branch over the wrmsr
9189 * being speculatively taken.
9190 */
Thomas Gleixner1189cbf2018-05-09 23:01:01 +02009191 x86_spec_ctrl_set_guest(vmx->spec_ctrl, 0);
KarimAllah Ahmede5a83412018-02-01 22:59:45 +01009192
Nadav Har'Eld462b812011-05-24 15:26:10 +03009193 vmx->__launched = vmx->loaded_vmcs->launched;
Thomas Gleixner1189cbf2018-05-09 23:01:01 +02009194
Nicolai Stange90bc3062018-07-21 22:35:28 +02009195 if (static_branch_unlikely(&vmx_l1d_should_flush))
9196 vmx_l1d_flush(vcpu);
Paolo Bonzinib3dc63c2018-07-02 13:07:14 +02009197
Avi Kivity104f2262010-11-18 13:12:52 +02009198 asm(
Avi Kivity6aa8b732006-12-10 02:21:36 -08009199 /* Store host registers */
Avi Kivityb188c81f2012-09-16 15:10:58 +03009200 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
9201 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
9202 "push %%" _ASM_CX " \n\t"
9203 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
Avi Kivity313dbd42008-07-17 18:04:30 +03009204 "je 1f \n\t"
Avi Kivityb188c81f2012-09-16 15:10:58 +03009205 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
Avi Kivity4ecac3f2008-05-13 13:23:38 +03009206 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
Avi Kivity313dbd42008-07-17 18:04:30 +03009207 "1: \n\t"
Avi Kivityd3edefc2009-06-16 12:33:56 +03009208 /* Reload cr2 if changed */
Avi Kivityb188c81f2012-09-16 15:10:58 +03009209 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
9210 "mov %%cr2, %%" _ASM_DX " \n\t"
9211 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
Avi Kivityd3edefc2009-06-16 12:33:56 +03009212 "je 2f \n\t"
Avi Kivityb188c81f2012-09-16 15:10:58 +03009213 "mov %%" _ASM_AX", %%cr2 \n\t"
Avi Kivityd3edefc2009-06-16 12:33:56 +03009214 "2: \n\t"
Avi Kivity6aa8b732006-12-10 02:21:36 -08009215 /* Check if vmlaunch of vmresume is needed */
Avi Kivitye08aa782007-11-15 18:06:18 +02009216 "cmpl $0, %c[launched](%0) \n\t"
Avi Kivity6aa8b732006-12-10 02:21:36 -08009217 /* Load guest registers. Don't clobber flags. */
Avi Kivityb188c81f2012-09-16 15:10:58 +03009218 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
9219 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
9220 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
9221 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
9222 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
9223 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
Avi Kivity05b3e0c2006-12-13 00:33:45 -08009224#ifdef CONFIG_X86_64
Avi Kivitye08aa782007-11-15 18:06:18 +02009225 "mov %c[r8](%0), %%r8 \n\t"
9226 "mov %c[r9](%0), %%r9 \n\t"
9227 "mov %c[r10](%0), %%r10 \n\t"
9228 "mov %c[r11](%0), %%r11 \n\t"
9229 "mov %c[r12](%0), %%r12 \n\t"
9230 "mov %c[r13](%0), %%r13 \n\t"
9231 "mov %c[r14](%0), %%r14 \n\t"
9232 "mov %c[r15](%0), %%r15 \n\t"
Avi Kivity6aa8b732006-12-10 02:21:36 -08009233#endif
Avi Kivityb188c81f2012-09-16 15:10:58 +03009234 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
Avi Kivityc8019492008-07-14 14:44:59 +03009235
Avi Kivity6aa8b732006-12-10 02:21:36 -08009236 /* Enter guest mode */
Avi Kivity83287ea422012-09-16 15:10:57 +03009237 "jne 1f \n\t"
Avi Kivity4ecac3f2008-05-13 13:23:38 +03009238 __ex(ASM_VMX_VMLAUNCH) "\n\t"
Avi Kivity83287ea422012-09-16 15:10:57 +03009239 "jmp 2f \n\t"
9240 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
9241 "2: "
Avi Kivity6aa8b732006-12-10 02:21:36 -08009242 /* Save guest registers, load host registers, keep flags */
Avi Kivityb188c81f2012-09-16 15:10:58 +03009243 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
Avi Kivity40712fa2011-01-06 18:09:12 +02009244 "pop %0 \n\t"
Jim Mattson491c0ca2018-01-03 14:31:38 -08009245 "setbe %c[fail](%0)\n\t"
Avi Kivityb188c81f2012-09-16 15:10:58 +03009246 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
9247 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
9248 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
9249 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
9250 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
9251 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
9252 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
Avi Kivity05b3e0c2006-12-13 00:33:45 -08009253#ifdef CONFIG_X86_64
Avi Kivitye08aa782007-11-15 18:06:18 +02009254 "mov %%r8, %c[r8](%0) \n\t"
9255 "mov %%r9, %c[r9](%0) \n\t"
9256 "mov %%r10, %c[r10](%0) \n\t"
9257 "mov %%r11, %c[r11](%0) \n\t"
9258 "mov %%r12, %c[r12](%0) \n\t"
9259 "mov %%r13, %c[r13](%0) \n\t"
9260 "mov %%r14, %c[r14](%0) \n\t"
9261 "mov %%r15, %c[r15](%0) \n\t"
Jim Mattson491c0ca2018-01-03 14:31:38 -08009262 "xor %%r8d, %%r8d \n\t"
9263 "xor %%r9d, %%r9d \n\t"
9264 "xor %%r10d, %%r10d \n\t"
9265 "xor %%r11d, %%r11d \n\t"
9266 "xor %%r12d, %%r12d \n\t"
9267 "xor %%r13d, %%r13d \n\t"
9268 "xor %%r14d, %%r14d \n\t"
9269 "xor %%r15d, %%r15d \n\t"
Avi Kivity6aa8b732006-12-10 02:21:36 -08009270#endif
Avi Kivityb188c81f2012-09-16 15:10:58 +03009271 "mov %%cr2, %%" _ASM_AX " \n\t"
9272 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
Avi Kivityc8019492008-07-14 14:44:59 +03009273
Jim Mattson491c0ca2018-01-03 14:31:38 -08009274 "xor %%eax, %%eax \n\t"
9275 "xor %%ebx, %%ebx \n\t"
9276 "xor %%esi, %%esi \n\t"
9277 "xor %%edi, %%edi \n\t"
Avi Kivityb188c81f2012-09-16 15:10:58 +03009278 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
Avi Kivity83287ea422012-09-16 15:10:57 +03009279 ".pushsection .rodata \n\t"
9280 ".global vmx_return \n\t"
9281 "vmx_return: " _ASM_PTR " 2b \n\t"
9282 ".popsection"
Avi Kivitye08aa782007-11-15 18:06:18 +02009283 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
Nadav Har'Eld462b812011-05-24 15:26:10 +03009284 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
Avi Kivitye08aa782007-11-15 18:06:18 +02009285 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
Avi Kivity313dbd42008-07-17 18:04:30 +03009286 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
Zhang Xiantaoad312c72007-12-13 23:50:52 +08009287 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
9288 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
9289 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
9290 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
9291 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
9292 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
9293 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
Avi Kivity05b3e0c2006-12-13 00:33:45 -08009294#ifdef CONFIG_X86_64
Zhang Xiantaoad312c72007-12-13 23:50:52 +08009295 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
9296 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
9297 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
9298 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
9299 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
9300 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
9301 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
9302 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
Avi Kivity6aa8b732006-12-10 02:21:36 -08009303#endif
Avi Kivity40712fa2011-01-06 18:09:12 +02009304 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
9305 [wordsize]"i"(sizeof(ulong))
Laurent Vivierc2036302007-10-25 14:18:52 +02009306 : "cc", "memory"
9307#ifdef CONFIG_X86_64
Avi Kivityb188c81f2012-09-16 15:10:58 +03009308 , "rax", "rbx", "rdi", "rsi"
Laurent Vivierc2036302007-10-25 14:18:52 +02009309 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
Avi Kivityb188c81f2012-09-16 15:10:58 +03009310#else
9311 , "eax", "ebx", "edi", "esi"
Laurent Vivierc2036302007-10-25 14:18:52 +02009312#endif
9313 );
Avi Kivity6aa8b732006-12-10 02:21:36 -08009314
KarimAllah Ahmede5a83412018-02-01 22:59:45 +01009315 /*
9316 * We do not use IBRS in the kernel. If this vCPU has used the
9317 * SPEC_CTRL MSR it may have left it on; save the value and
9318 * turn it off. This is much more efficient than blindly adding
9319 * it to the atomic save/restore list. Especially as the former
9320 * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
9321 *
9322 * For non-nested case:
9323 * If the L01 MSR bitmap does not intercept the MSR, then we need to
9324 * save it.
9325 *
9326 * For nested case:
9327 * If the L02 MSR bitmap does not intercept the MSR, then we need to
9328 * save it.
9329 */
Paolo Bonzinif750e152018-02-22 16:43:18 +01009330 if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
Paolo Bonzinia175d512018-02-22 16:43:17 +01009331 vmx->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
KarimAllah Ahmede5a83412018-02-01 22:59:45 +01009332
Thomas Gleixner1189cbf2018-05-09 23:01:01 +02009333 x86_spec_ctrl_restore_host(vmx->spec_ctrl, 0);
KarimAllah Ahmede5a83412018-02-01 22:59:45 +01009334
David Woodhousec1ddd992018-01-12 11:11:27 +00009335 /* Eliminate branch target predictions from guest mode */
9336 vmexit_fill_RSB();
9337
Gleb Natapov2a7921b2012-08-12 16:12:29 +03009338 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
9339 if (debugctlmsr)
9340 update_debugctlmsr(debugctlmsr);
9341
Avi Kivityaa67f602012-08-01 16:48:03 +03009342#ifndef CONFIG_X86_64
9343 /*
9344 * The sysexit path does not restore ds/es, so we must set them to
9345 * a reasonable value ourselves.
9346 *
9347 * We can't defer this to vmx_load_host_state() since that function
9348 * may be executed in interrupt context, which saves and restore segments
9349 * around it, nullifying its effect.
9350 */
9351 loadsegment(ds, __USER_DS);
9352 loadsegment(es, __USER_DS);
9353#endif
9354
Avi Kivity6de4f3a2009-05-31 22:58:47 +03009355 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
Avi Kivity6de12732011-03-07 12:51:22 +02009356 | (1 << VCPU_EXREG_RFLAGS)
Avi Kivityaff48ba2010-12-05 18:56:11 +02009357 | (1 << VCPU_EXREG_PDPTR)
Avi Kivity2fb92db2011-04-27 19:42:18 +03009358 | (1 << VCPU_EXREG_SEGMENTS)
Avi Kivityaff48ba2010-12-05 18:56:11 +02009359 | (1 << VCPU_EXREG_CR3));
Marcelo Tosatti5fdbf972008-06-27 14:58:02 -03009360 vcpu->arch.regs_dirty = 0;
9361
Avi Kivity1155f762007-11-22 11:30:47 +02009362 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
9363
Nadav Har'Eld462b812011-05-24 15:26:10 +03009364 vmx->loaded_vmcs->launched = 1;
Avi Kivity1b6269d2007-10-09 12:12:19 +02009365
Avi Kivity51aa01d2010-07-20 14:31:20 +03009366 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
Avi Kivity51aa01d2010-07-20 14:31:20 +03009367
Gleb Natapove0b890d2013-09-25 12:51:33 +03009368 /*
Xiao Guangrong1be0e612016-03-22 16:51:18 +08009369 * eager fpu is enabled if PKEY is supported and CR4 is switched
9370 * back on host, so it is safe to read guest PKRU from current
9371 * XSAVE.
9372 */
9373 if (boot_cpu_has(X86_FEATURE_OSPKE)) {
9374 vmx->guest_pkru = __read_pkru();
9375 if (vmx->guest_pkru != vmx->host_pkru) {
9376 vmx->guest_pkru_valid = true;
9377 __write_pkru(vmx->host_pkru);
9378 } else
9379 vmx->guest_pkru_valid = false;
9380 }
9381
9382 /*
Gleb Natapove0b890d2013-09-25 12:51:33 +03009383 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
9384 * we did not inject a still-pending event to L1 now because of
9385 * nested_run_pending, we need to re-enable this bit.
9386 */
9387 if (vmx->nested.nested_run_pending)
9388 kvm_make_request(KVM_REQ_EVENT, vcpu);
9389
9390 vmx->nested.nested_run_pending = 0;
9391
Avi Kivity51aa01d2010-07-20 14:31:20 +03009392 vmx_complete_atomic_exit(vmx);
9393 vmx_recover_nmi_blocking(vmx);
Avi Kivitycf393f72008-07-01 16:20:21 +03009394 vmx_complete_interrupts(vmx);
Avi Kivity6aa8b732006-12-10 02:21:36 -08009395}
Josh Poimboeuf935893a2017-06-28 10:11:06 -05009396STACK_FRAME_NON_STANDARD(vmx_vcpu_run);
Avi Kivity6aa8b732006-12-10 02:21:36 -08009397
Paolo Bonzini4fa77342014-07-17 12:25:16 +02009398static void vmx_load_vmcs01(struct kvm_vcpu *vcpu)
9399{
9400 struct vcpu_vmx *vmx = to_vmx(vcpu);
9401 int cpu;
9402
9403 if (vmx->loaded_vmcs == &vmx->vmcs01)
9404 return;
9405
9406 cpu = get_cpu();
9407 vmx->loaded_vmcs = &vmx->vmcs01;
9408 vmx_vcpu_put(vcpu);
9409 vmx_vcpu_load(vcpu, cpu);
9410 vcpu->cpu = cpu;
9411 put_cpu();
9412}
9413
Jim Mattson2f1fe812016-07-08 15:36:06 -07009414/*
9415 * Ensure that the current vmcs of the logical processor is the
9416 * vmcs01 of the vcpu before calling free_nested().
9417 */
9418static void vmx_free_vcpu_nested(struct kvm_vcpu *vcpu)
9419{
9420 struct vcpu_vmx *vmx = to_vmx(vcpu);
9421 int r;
9422
9423 r = vcpu_load(vcpu);
9424 BUG_ON(r);
9425 vmx_load_vmcs01(vcpu);
9426 free_nested(vmx);
9427 vcpu_put(vcpu);
9428}
9429
Avi Kivity6aa8b732006-12-10 02:21:36 -08009430static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
9431{
Rusty Russellfb3f0f52007-07-27 17:16:56 +10009432 struct vcpu_vmx *vmx = to_vmx(vcpu);
9433
Kai Huang843e4332015-01-28 10:54:28 +08009434 if (enable_pml)
Kai Huanga3eaa862015-11-04 13:46:05 +08009435 vmx_destroy_pml_buffer(vmx);
Wanpeng Li991e7a02015-09-16 17:30:05 +08009436 free_vpid(vmx->vpid);
Paolo Bonzini4fa77342014-07-17 12:25:16 +02009437 leave_guest_mode(vcpu);
Jim Mattson2f1fe812016-07-08 15:36:06 -07009438 vmx_free_vcpu_nested(vcpu);
Paolo Bonzini4fa77342014-07-17 12:25:16 +02009439 free_loaded_vmcs(vmx->loaded_vmcs);
Rusty Russellfb3f0f52007-07-27 17:16:56 +10009440 kfree(vmx->guest_msrs);
9441 kvm_vcpu_uninit(vcpu);
Rusty Russella4770342007-08-01 14:46:11 +10009442 kmem_cache_free(kvm_vcpu_cache, vmx);
Avi Kivity6aa8b732006-12-10 02:21:36 -08009443}
9444
Rusty Russellfb3f0f52007-07-27 17:16:56 +10009445static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
Avi Kivity6aa8b732006-12-10 02:21:36 -08009446{
Rusty Russellfb3f0f52007-07-27 17:16:56 +10009447 int err;
Rusty Russellc16f8622007-07-30 21:12:19 +10009448 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
Paolo Bonzini6236b782018-01-16 16:51:18 +01009449 unsigned long *msr_bitmap;
Avi Kivity15ad7142007-07-11 18:17:21 +03009450 int cpu;
Avi Kivity6aa8b732006-12-10 02:21:36 -08009451
Gregory Haskinsa2fa3e92007-07-27 08:13:10 -04009452 if (!vmx)
Rusty Russellfb3f0f52007-07-27 17:16:56 +10009453 return ERR_PTR(-ENOMEM);
9454
Wanpeng Li991e7a02015-09-16 17:30:05 +08009455 vmx->vpid = allocate_vpid();
Sheng Yang2384d2b2008-01-17 15:14:33 +08009456
Rusty Russellfb3f0f52007-07-27 17:16:56 +10009457 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
9458 if (err)
9459 goto free_vcpu;
Ingo Molnar965b58a2007-01-05 16:36:23 -08009460
Peter Feiner4e595162016-07-07 14:49:58 -07009461 err = -ENOMEM;
9462
9463 /*
9464 * If PML is turned on, failure on enabling PML just results in failure
9465 * of creating the vcpu, therefore we can simplify PML logic (by
9466 * avoiding dealing with cases, such as enabling PML partially on vcpus
9467 * for the guest, etc.
9468 */
9469 if (enable_pml) {
9470 vmx->pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
9471 if (!vmx->pml_pg)
9472 goto uninit_vcpu;
9473 }
9474
Gregory Haskinsa2fa3e92007-07-27 08:13:10 -04009475 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
Paolo Bonzini03916db2014-07-24 14:21:57 +02009476 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
9477 > PAGE_SIZE);
Nadav Amit0123be42014-07-24 15:06:56 +03009478
Peter Feiner4e595162016-07-07 14:49:58 -07009479 if (!vmx->guest_msrs)
9480 goto free_pml;
Ingo Molnar965b58a2007-01-05 16:36:23 -08009481
Nadav Har'Eld462b812011-05-24 15:26:10 +03009482 if (!vmm_exclusive)
9483 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
Paolo Bonziniff546f92018-01-11 12:16:15 +01009484 err = alloc_loaded_vmcs(&vmx->vmcs01);
Nadav Har'Eld462b812011-05-24 15:26:10 +03009485 if (!vmm_exclusive)
9486 kvm_cpu_vmxoff();
Paolo Bonziniff546f92018-01-11 12:16:15 +01009487 if (err < 0)
9488 goto free_msrs;
Gregory Haskinsa2fa3e92007-07-27 08:13:10 -04009489
Paolo Bonzini6236b782018-01-16 16:51:18 +01009490 msr_bitmap = vmx->vmcs01.msr_bitmap;
9491 vmx_disable_intercept_for_msr(msr_bitmap, MSR_FS_BASE, MSR_TYPE_RW);
9492 vmx_disable_intercept_for_msr(msr_bitmap, MSR_GS_BASE, MSR_TYPE_RW);
9493 vmx_disable_intercept_for_msr(msr_bitmap, MSR_KERNEL_GS_BASE, MSR_TYPE_RW);
9494 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_CS, MSR_TYPE_RW);
9495 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_ESP, MSR_TYPE_RW);
9496 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_EIP, MSR_TYPE_RW);
9497 vmx->msr_bitmap_mode = 0;
9498
Paolo Bonziniff546f92018-01-11 12:16:15 +01009499 vmx->loaded_vmcs = &vmx->vmcs01;
Avi Kivity15ad7142007-07-11 18:17:21 +03009500 cpu = get_cpu();
9501 vmx_vcpu_load(&vmx->vcpu, cpu);
Zachary Amsdene48672f2010-08-19 22:07:23 -10009502 vmx->vcpu.cpu = cpu;
Rusty Russell8b9cf982007-07-30 16:31:43 +10009503 err = vmx_vcpu_setup(vmx);
Rusty Russellfb3f0f52007-07-27 17:16:56 +10009504 vmx_vcpu_put(&vmx->vcpu);
Avi Kivity15ad7142007-07-11 18:17:21 +03009505 put_cpu();
Rusty Russellfb3f0f52007-07-27 17:16:56 +10009506 if (err)
9507 goto free_vmcs;
Paolo Bonzini35754c92015-07-29 12:05:37 +02009508 if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
Jan Kiszkabe6d05c2011-04-13 01:27:55 +02009509 err = alloc_apic_access_page(kvm);
9510 if (err)
Marcelo Tosatti5e4a0b32008-02-14 21:21:43 -02009511 goto free_vmcs;
Jan Kiszkaa63cb562013-04-08 11:07:46 +02009512 }
Ingo Molnar965b58a2007-01-05 16:36:23 -08009513
Sheng Yangb927a3c2009-07-21 10:42:48 +08009514 if (enable_ept) {
9515 if (!kvm->arch.ept_identity_map_addr)
9516 kvm->arch.ept_identity_map_addr =
9517 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
Tang Chenf51770e2014-09-16 18:41:59 +08009518 err = init_rmode_identity_map(kvm);
9519 if (err)
Gleb Natapov93ea5382011-02-21 12:07:59 +02009520 goto free_vmcs;
Sheng Yangb927a3c2009-07-21 10:42:48 +08009521 }
Sheng Yangb7ebfb02008-04-25 21:44:52 +08009522
Roman Kagan020a90f2018-07-19 21:59:07 +03009523 if (nested)
Wincy Vanb9c237b2015-02-03 23:56:30 +08009524 nested_vmx_setup_ctls_msrs(vmx);
9525
Wincy Van705699a2015-02-03 23:58:17 +08009526 vmx->nested.posted_intr_nv = -1;
Nadav Har'Ela9d30f32011-05-25 23:03:55 +03009527 vmx->nested.current_vmptr = -1ull;
9528 vmx->nested.current_vmcs12 = NULL;
9529
Haozhong Zhang37e4c992016-06-22 14:59:55 +08009530 vmx->msr_ia32_feature_control_valid_bits = FEATURE_CONTROL_LOCKED;
9531
Paolo Bonzini58d2fb12017-06-06 12:57:06 +02009532 /*
9533 * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR
9534 * or POSTED_INTR_WAKEUP_VECTOR.
9535 */
9536 vmx->pi_desc.nv = POSTED_INTR_VECTOR;
9537 vmx->pi_desc.sn = 1;
9538
Rusty Russellfb3f0f52007-07-27 17:16:56 +10009539 return &vmx->vcpu;
Ingo Molnar965b58a2007-01-05 16:36:23 -08009540
Rusty Russellfb3f0f52007-07-27 17:16:56 +10009541free_vmcs:
Xiao Guangrong5f3fbc32012-05-14 14:58:58 +08009542 free_loaded_vmcs(vmx->loaded_vmcs);
Rusty Russellfb3f0f52007-07-27 17:16:56 +10009543free_msrs:
Rusty Russellfb3f0f52007-07-27 17:16:56 +10009544 kfree(vmx->guest_msrs);
Peter Feiner4e595162016-07-07 14:49:58 -07009545free_pml:
9546 vmx_destroy_pml_buffer(vmx);
Rusty Russellfb3f0f52007-07-27 17:16:56 +10009547uninit_vcpu:
9548 kvm_vcpu_uninit(&vmx->vcpu);
9549free_vcpu:
Wanpeng Li991e7a02015-09-16 17:30:05 +08009550 free_vpid(vmx->vpid);
Rusty Russella4770342007-08-01 14:46:11 +10009551 kmem_cache_free(kvm_vcpu_cache, vmx);
Rusty Russellfb3f0f52007-07-27 17:16:56 +10009552 return ERR_PTR(err);
Avi Kivity6aa8b732006-12-10 02:21:36 -08009553}
9554
Jiri Kosina2decbf52018-07-13 16:23:25 +02009555#define L1TF_MSG_SMT "L1TF CPU bug present and SMT on, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/l1tf.html for details.\n"
9556#define L1TF_MSG_L1D "L1TF CPU bug present and virtualization mitigation disabled, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/l1tf.html for details.\n"
Konrad Rzeszutek Wilka0695af2018-06-20 11:29:53 -04009557
9558static int vmx_vm_init(struct kvm *kvm)
9559{
Jiri Kosina2decbf52018-07-13 16:23:25 +02009560 if (boot_cpu_has(X86_BUG_L1TF) && enable_ept) {
9561 switch (l1tf_mitigation) {
9562 case L1TF_MITIGATION_OFF:
9563 case L1TF_MITIGATION_FLUSH_NOWARN:
9564 /* 'I explicitly don't care' is set */
9565 break;
9566 case L1TF_MITIGATION_FLUSH:
9567 case L1TF_MITIGATION_FLUSH_NOSMT:
9568 case L1TF_MITIGATION_FULL:
9569 /*
9570 * Warn upon starting the first VM in a potentially
9571 * insecure environment.
9572 */
9573 if (cpu_smt_control == CPU_SMT_ENABLED)
9574 pr_warn_once(L1TF_MSG_SMT);
9575 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER)
9576 pr_warn_once(L1TF_MSG_L1D);
9577 break;
9578 case L1TF_MITIGATION_FULL_FORCE:
9579 /* Flush is enforced */
9580 break;
Konrad Rzeszutek Wilka0695af2018-06-20 11:29:53 -04009581 }
Konrad Rzeszutek Wilka0695af2018-06-20 11:29:53 -04009582 }
9583 return 0;
9584}
9585
Yang, Sheng002c7f72007-07-31 14:23:01 +03009586static void __init vmx_check_processor_compat(void *rtn)
9587{
9588 struct vmcs_config vmcs_conf;
9589
9590 *(int *)rtn = 0;
9591 if (setup_vmcs_config(&vmcs_conf) < 0)
9592 *(int *)rtn = -EIO;
9593 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
9594 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
9595 smp_processor_id());
9596 *(int *)rtn = -EIO;
9597 }
9598}
9599
Sheng Yang67253af2008-04-25 10:20:22 +08009600static int get_ept_level(void)
9601{
9602 return VMX_EPT_DEFAULT_GAW + 1;
9603}
9604
Sheng Yang4b12f0d2009-04-27 20:35:42 +08009605static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
Sheng Yang64d4d522008-10-09 16:01:57 +08009606{
Xiao Guangrongb18d5432015-06-15 16:55:21 +08009607 u8 cache;
9608 u64 ipat = 0;
Sheng Yang4b12f0d2009-04-27 20:35:42 +08009609
Sheng Yang522c68c2009-04-27 20:35:43 +08009610 /* For VT-d and EPT combination
Paolo Bonzini606decd2015-10-01 13:12:47 +02009611 * 1. MMIO: always map as UC
Sheng Yang522c68c2009-04-27 20:35:43 +08009612 * 2. EPT with VT-d:
9613 * a. VT-d without snooping control feature: can't guarantee the
Paolo Bonzini606decd2015-10-01 13:12:47 +02009614 * result, try to trust guest.
Sheng Yang522c68c2009-04-27 20:35:43 +08009615 * b. VT-d with snooping control feature: snooping control feature of
9616 * VT-d engine can guarantee the cache correctness. Just set it
9617 * to WB to keep consistent with host. So the same as item 3.
Sheng Yanga19a6d12010-02-09 16:41:53 +08009618 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
Sheng Yang522c68c2009-04-27 20:35:43 +08009619 * consistent with host MTRR
9620 */
Paolo Bonzini606decd2015-10-01 13:12:47 +02009621 if (is_mmio) {
9622 cache = MTRR_TYPE_UNCACHABLE;
9623 goto exit;
9624 }
9625
9626 if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
Xiao Guangrongb18d5432015-06-15 16:55:21 +08009627 ipat = VMX_EPT_IPAT_BIT;
9628 cache = MTRR_TYPE_WRBACK;
9629 goto exit;
9630 }
9631
9632 if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
9633 ipat = VMX_EPT_IPAT_BIT;
Paolo Bonzini0da029e2015-07-23 08:24:42 +02009634 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
Xiao Guangrongfb2799502015-07-16 03:25:56 +08009635 cache = MTRR_TYPE_WRBACK;
9636 else
9637 cache = MTRR_TYPE_UNCACHABLE;
Xiao Guangrongb18d5432015-06-15 16:55:21 +08009638 goto exit;
9639 }
9640
Xiao Guangrongff536042015-06-15 16:55:22 +08009641 cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
Xiao Guangrongb18d5432015-06-15 16:55:21 +08009642
9643exit:
9644 return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
Sheng Yang64d4d522008-10-09 16:01:57 +08009645}
9646
Sheng Yang17cc3932010-01-05 19:02:27 +08009647static int vmx_get_lpage_level(void)
Joerg Roedel344f4142009-07-27 16:30:48 +02009648{
Sheng Yang878403b2010-01-05 19:02:29 +08009649 if (enable_ept && !cpu_has_vmx_ept_1g_page())
9650 return PT_DIRECTORY_LEVEL;
9651 else
9652 /* For shadow and EPT supported 1GB page */
9653 return PT_PDPE_LEVEL;
Joerg Roedel344f4142009-07-27 16:30:48 +02009654}
9655
Xiao Guangrongfeda8052015-09-09 14:05:55 +08009656static void vmcs_set_secondary_exec_control(u32 new_ctl)
9657{
9658 /*
9659 * These bits in the secondary execution controls field
9660 * are dynamic, the others are mostly based on the hypervisor
9661 * architecture and the guest's CPUID. Do not touch the
9662 * dynamic bits.
9663 */
9664 u32 mask =
9665 SECONDARY_EXEC_SHADOW_VMCS |
9666 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
9667 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9668
9669 u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
9670
9671 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
9672 (new_ctl & ~mask) | (cur_ctl & mask));
9673}
9674
Sheng Yang0e851882009-12-18 16:48:46 +08009675static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
9676{
Sheng Yang4e47c7a2009-12-18 16:48:47 +08009677 struct kvm_cpuid_entry2 *best;
9678 struct vcpu_vmx *vmx = to_vmx(vcpu);
Xiao Guangrongfeda8052015-09-09 14:05:55 +08009679 u32 secondary_exec_ctl = vmx_secondary_exec_control(vmx);
Sheng Yang4e47c7a2009-12-18 16:48:47 +08009680
Sheng Yang4e47c7a2009-12-18 16:48:47 +08009681 if (vmx_rdtscp_supported()) {
Xiao Guangrong1cea0ce2015-09-09 14:05:57 +08009682 bool rdtscp_enabled = guest_cpuid_has_rdtscp(vcpu);
9683 if (!rdtscp_enabled)
Xiao Guangrongfeda8052015-09-09 14:05:55 +08009684 secondary_exec_ctl &= ~SECONDARY_EXEC_RDTSCP;
Xiao Guangrongf36201e2015-09-09 14:05:53 +08009685
Paolo Bonzini8b972652015-09-15 17:34:42 +02009686 if (nested) {
Xiao Guangrong1cea0ce2015-09-09 14:05:57 +08009687 if (rdtscp_enabled)
Paolo Bonzini8b972652015-09-15 17:34:42 +02009688 vmx->nested.nested_vmx_secondary_ctls_high |=
9689 SECONDARY_EXEC_RDTSCP;
9690 else
9691 vmx->nested.nested_vmx_secondary_ctls_high &=
9692 ~SECONDARY_EXEC_RDTSCP;
9693 }
Sheng Yang4e47c7a2009-12-18 16:48:47 +08009694 }
Mao, Junjiead756a12012-07-02 01:18:48 +00009695
Mao, Junjiead756a12012-07-02 01:18:48 +00009696 /* Exposing INVPCID only when PCID is exposed */
9697 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
9698 if (vmx_invpcid_supported() &&
Xiao Guangrong29541bb2015-09-09 14:05:54 +08009699 (!best || !(best->ebx & bit(X86_FEATURE_INVPCID)) ||
9700 !guest_cpuid_has_pcid(vcpu))) {
Xiao Guangrongfeda8052015-09-09 14:05:55 +08009701 secondary_exec_ctl &= ~SECONDARY_EXEC_ENABLE_INVPCID;
Xiao Guangrong29541bb2015-09-09 14:05:54 +08009702
Mao, Junjiead756a12012-07-02 01:18:48 +00009703 if (best)
Ren, Yongjie4f977042012-09-07 07:36:59 +00009704 best->ebx &= ~bit(X86_FEATURE_INVPCID);
Mao, Junjiead756a12012-07-02 01:18:48 +00009705 }
Xiao Guangrong8b3e34e2015-09-09 14:05:51 +08009706
Huaitong Han45bdbcf2016-01-12 16:04:20 +08009707 if (cpu_has_secondary_exec_ctrls())
9708 vmcs_set_secondary_exec_control(secondary_exec_ctl);
Xiao Guangrongfeda8052015-09-09 14:05:55 +08009709
Haozhong Zhang37e4c992016-06-22 14:59:55 +08009710 if (nested_vmx_allowed(vcpu))
9711 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
9712 FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
9713 else
9714 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
9715 ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
Sheng Yang0e851882009-12-18 16:48:46 +08009716}
9717
Joerg Roedeld4330ef2010-04-22 12:33:11 +02009718static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
9719{
Nadav Har'El7b8050f2011-05-25 23:16:10 +03009720 if (func == 1 && nested)
9721 entry->ecx |= bit(X86_FEATURE_VMX);
Joerg Roedeld4330ef2010-04-22 12:33:11 +02009722}
9723
Yang Zhang25d92082013-08-06 12:00:32 +03009724static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
9725 struct x86_exception *fault)
9726{
Jan Kiszka533558b2014-01-04 18:47:20 +01009727 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9728 u32 exit_reason;
Yang Zhang25d92082013-08-06 12:00:32 +03009729
9730 if (fault->error_code & PFERR_RSVD_MASK)
Jan Kiszka533558b2014-01-04 18:47:20 +01009731 exit_reason = EXIT_REASON_EPT_MISCONFIG;
Yang Zhang25d92082013-08-06 12:00:32 +03009732 else
Jan Kiszka533558b2014-01-04 18:47:20 +01009733 exit_reason = EXIT_REASON_EPT_VIOLATION;
9734 nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
Yang Zhang25d92082013-08-06 12:00:32 +03009735 vmcs12->guest_physical_address = fault->address;
9736}
9737
Nadav Har'El155a97a2013-08-05 11:07:16 +03009738/* Callbacks for nested_ept_init_mmu_context: */
9739
9740static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
9741{
9742 /* return the page table to be shadowed - in our case, EPT12 */
9743 return get_vmcs12(vcpu)->ept_pointer;
9744}
9745
Paolo Bonzini8a3c1a332013-10-02 16:56:13 +02009746static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
Nadav Har'El155a97a2013-08-05 11:07:16 +03009747{
Paolo Bonziniad896af2013-10-02 16:56:14 +02009748 WARN_ON(mmu_is_nested(vcpu));
9749 kvm_init_shadow_ept_mmu(vcpu,
Wincy Vanb9c237b2015-02-03 23:56:30 +08009750 to_vmx(vcpu)->nested.nested_vmx_ept_caps &
9751 VMX_EPT_EXECUTE_ONLY_BIT);
Nadav Har'El155a97a2013-08-05 11:07:16 +03009752 vcpu->arch.mmu.set_cr3 = vmx_set_cr3;
9753 vcpu->arch.mmu.get_cr3 = nested_ept_get_cr3;
9754 vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
9755
9756 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
Nadav Har'El155a97a2013-08-05 11:07:16 +03009757}
9758
9759static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
9760{
9761 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
9762}
9763
Eugene Korenevsky19d5f102014-12-16 22:35:53 +03009764static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
9765 u16 error_code)
9766{
9767 bool inequality, bit;
9768
9769 bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
9770 inequality =
9771 (error_code & vmcs12->page_fault_error_code_mask) !=
9772 vmcs12->page_fault_error_code_match;
9773 return inequality ^ bit;
9774}
9775
Gleb Natapovfeaf0c7d2013-09-25 12:51:36 +03009776static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
9777 struct x86_exception *fault)
9778{
9779 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9780
9781 WARN_ON(!is_guest_mode(vcpu));
9782
Eugene Korenevsky19d5f102014-12-16 22:35:53 +03009783 if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code))
Jan Kiszka533558b2014-01-04 18:47:20 +01009784 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
9785 vmcs_read32(VM_EXIT_INTR_INFO),
9786 vmcs_readl(EXIT_QUALIFICATION));
Gleb Natapovfeaf0c7d2013-09-25 12:51:36 +03009787 else
9788 kvm_inject_page_fault(vcpu, fault);
9789}
9790
Wanpeng Lia2bcba52014-08-21 19:46:49 +08009791static bool nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
9792 struct vmcs12 *vmcs12)
9793{
9794 struct vcpu_vmx *vmx = to_vmx(vcpu);
Eugene Korenevsky90904222015-03-29 23:56:27 +03009795 int maxphyaddr = cpuid_maxphyaddr(vcpu);
Wanpeng Lia2bcba52014-08-21 19:46:49 +08009796
9797 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
Eugene Korenevsky90904222015-03-29 23:56:27 +03009798 if (!PAGE_ALIGNED(vmcs12->apic_access_addr) ||
9799 vmcs12->apic_access_addr >> maxphyaddr)
Wanpeng Lia2bcba52014-08-21 19:46:49 +08009800 return false;
9801
9802 /*
9803 * Translate L1 physical address to host physical
9804 * address for vmcs02. Keep the page pinned, so this
9805 * physical address remains valid. We keep a reference
9806 * to it so we can release it later.
9807 */
9808 if (vmx->nested.apic_access_page) /* shouldn't happen */
9809 nested_release_page(vmx->nested.apic_access_page);
9810 vmx->nested.apic_access_page =
9811 nested_get_page(vcpu, vmcs12->apic_access_addr);
9812 }
Wanpeng Lia7c0b072014-08-21 19:46:50 +08009813
9814 if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
Eugene Korenevsky90904222015-03-29 23:56:27 +03009815 if (!PAGE_ALIGNED(vmcs12->virtual_apic_page_addr) ||
9816 vmcs12->virtual_apic_page_addr >> maxphyaddr)
Wanpeng Lia7c0b072014-08-21 19:46:50 +08009817 return false;
9818
9819 if (vmx->nested.virtual_apic_page) /* shouldn't happen */
9820 nested_release_page(vmx->nested.virtual_apic_page);
9821 vmx->nested.virtual_apic_page =
9822 nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
9823
9824 /*
9825 * Failing the vm entry is _not_ what the processor does
9826 * but it's basically the only possibility we have.
9827 * We could still enter the guest if CR8 load exits are
9828 * enabled, CR8 store exits are enabled, and virtualize APIC
9829 * access is disabled; in this case the processor would never
9830 * use the TPR shadow and we could simply clear the bit from
9831 * the execution control. But such a configuration is useless,
9832 * so let's keep the code simple.
9833 */
9834 if (!vmx->nested.virtual_apic_page)
9835 return false;
9836 }
9837
Wincy Van705699a2015-02-03 23:58:17 +08009838 if (nested_cpu_has_posted_intr(vmcs12)) {
Eugene Korenevsky90904222015-03-29 23:56:27 +03009839 if (!IS_ALIGNED(vmcs12->posted_intr_desc_addr, 64) ||
9840 vmcs12->posted_intr_desc_addr >> maxphyaddr)
Wincy Van705699a2015-02-03 23:58:17 +08009841 return false;
9842
9843 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
9844 kunmap(vmx->nested.pi_desc_page);
9845 nested_release_page(vmx->nested.pi_desc_page);
9846 }
9847 vmx->nested.pi_desc_page =
9848 nested_get_page(vcpu, vmcs12->posted_intr_desc_addr);
9849 if (!vmx->nested.pi_desc_page)
9850 return false;
9851
9852 vmx->nested.pi_desc =
9853 (struct pi_desc *)kmap(vmx->nested.pi_desc_page);
9854 if (!vmx->nested.pi_desc) {
9855 nested_release_page_clean(vmx->nested.pi_desc_page);
9856 return false;
9857 }
9858 vmx->nested.pi_desc =
9859 (struct pi_desc *)((void *)vmx->nested.pi_desc +
9860 (unsigned long)(vmcs12->posted_intr_desc_addr &
9861 (PAGE_SIZE - 1)));
9862 }
9863
Wanpeng Lia2bcba52014-08-21 19:46:49 +08009864 return true;
9865}
9866
Jan Kiszkaf4124502014-03-07 20:03:13 +01009867static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
9868{
9869 u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
9870 struct vcpu_vmx *vmx = to_vmx(vcpu);
9871
9872 if (vcpu->arch.virtual_tsc_khz == 0)
9873 return;
9874
9875 /* Make sure short timeouts reliably trigger an immediate vmexit.
9876 * hrtimer_start does not guarantee this. */
9877 if (preemption_timeout <= 1) {
9878 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
9879 return;
9880 }
9881
9882 preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
9883 preemption_timeout *= 1000000;
9884 do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
9885 hrtimer_start(&vmx->nested.preemption_timer,
9886 ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
9887}
9888
Wincy Van3af18d92015-02-03 23:49:31 +08009889static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
9890 struct vmcs12 *vmcs12)
9891{
9892 int maxphyaddr;
9893 u64 addr;
9894
9895 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
9896 return 0;
9897
9898 if (vmcs12_read_any(vcpu, MSR_BITMAP, &addr)) {
9899 WARN_ON(1);
9900 return -EINVAL;
9901 }
9902 maxphyaddr = cpuid_maxphyaddr(vcpu);
9903
9904 if (!PAGE_ALIGNED(vmcs12->msr_bitmap) ||
9905 ((addr + PAGE_SIZE) >> maxphyaddr))
9906 return -EINVAL;
9907
9908 return 0;
9909}
9910
9911/*
9912 * Merge L0's and L1's MSR bitmap, return false to indicate that
9913 * we do not use the hardware.
9914 */
9915static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
9916 struct vmcs12 *vmcs12)
9917{
Wincy Van82f0dd42015-02-03 23:57:18 +08009918 int msr;
Wincy Vanf2b93282015-02-03 23:56:03 +08009919 struct page *page;
Radim Krčmářd048c092016-08-08 20:16:22 +02009920 unsigned long *msr_bitmap_l1;
Paolo Bonzini6236b782018-01-16 16:51:18 +01009921 unsigned long *msr_bitmap_l0 = to_vmx(vcpu)->nested.vmcs02.msr_bitmap;
Ashok Raj70131292018-02-01 22:59:43 +01009922 /*
KarimAllah Ahmede5a83412018-02-01 22:59:45 +01009923 * pred_cmd & spec_ctrl are trying to verify two things:
Ashok Raj70131292018-02-01 22:59:43 +01009924 *
9925 * 1. L0 gave a permission to L1 to actually passthrough the MSR. This
9926 * ensures that we do not accidentally generate an L02 MSR bitmap
9927 * from the L12 MSR bitmap that is too permissive.
9928 * 2. That L1 or L2s have actually used the MSR. This avoids
9929 * unnecessarily merging of the bitmap if the MSR is unused. This
9930 * works properly because we only update the L01 MSR bitmap lazily.
9931 * So even if L0 should pass L1 these MSRs, the L01 bitmap is only
9932 * updated to reflect this when L1 (or its L2s) actually write to
9933 * the MSR.
9934 */
KarimAllah Ahmed96652962018-02-10 23:39:25 +00009935 bool pred_cmd = !msr_write_intercepted_l01(vcpu, MSR_IA32_PRED_CMD);
9936 bool spec_ctrl = !msr_write_intercepted_l01(vcpu, MSR_IA32_SPEC_CTRL);
Wincy Vanf2b93282015-02-03 23:56:03 +08009937
Ashok Raj70131292018-02-01 22:59:43 +01009938 if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
KarimAllah Ahmede5a83412018-02-01 22:59:45 +01009939 !pred_cmd && !spec_ctrl)
Wincy Vanf2b93282015-02-03 23:56:03 +08009940 return false;
9941
9942 page = nested_get_page(vcpu, vmcs12->msr_bitmap);
Radim Krčmář215df1f2017-03-07 17:51:49 +01009943 if (!page)
Wincy Vanf2b93282015-02-03 23:56:03 +08009944 return false;
Radim Krčmářd048c092016-08-08 20:16:22 +02009945 msr_bitmap_l1 = (unsigned long *)kmap(page);
Wincy Vanf2b93282015-02-03 23:56:03 +08009946
Radim Krčmářd048c092016-08-08 20:16:22 +02009947 memset(msr_bitmap_l0, 0xff, PAGE_SIZE);
9948
Wincy Vanf2b93282015-02-03 23:56:03 +08009949 if (nested_cpu_has_virt_x2apic_mode(vmcs12)) {
Wincy Van82f0dd42015-02-03 23:57:18 +08009950 if (nested_cpu_has_apic_reg_virt(vmcs12))
9951 for (msr = 0x800; msr <= 0x8ff; msr++)
9952 nested_vmx_disable_intercept_for_msr(
Radim Krčmářd048c092016-08-08 20:16:22 +02009953 msr_bitmap_l1, msr_bitmap_l0,
Wincy Van82f0dd42015-02-03 23:57:18 +08009954 msr, MSR_TYPE_R);
Radim Krčmářd048c092016-08-08 20:16:22 +02009955
9956 nested_vmx_disable_intercept_for_msr(
9957 msr_bitmap_l1, msr_bitmap_l0,
Wincy Vanf2b93282015-02-03 23:56:03 +08009958 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
9959 MSR_TYPE_R | MSR_TYPE_W);
Radim Krčmářd048c092016-08-08 20:16:22 +02009960
Wincy Van608406e2015-02-03 23:57:51 +08009961 if (nested_cpu_has_vid(vmcs12)) {
Wincy Van608406e2015-02-03 23:57:51 +08009962 nested_vmx_disable_intercept_for_msr(
Radim Krčmářd048c092016-08-08 20:16:22 +02009963 msr_bitmap_l1, msr_bitmap_l0,
Wincy Van608406e2015-02-03 23:57:51 +08009964 APIC_BASE_MSR + (APIC_EOI >> 4),
9965 MSR_TYPE_W);
9966 nested_vmx_disable_intercept_for_msr(
Radim Krčmářd048c092016-08-08 20:16:22 +02009967 msr_bitmap_l1, msr_bitmap_l0,
Wincy Van608406e2015-02-03 23:57:51 +08009968 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
9969 MSR_TYPE_W);
9970 }
Wincy Van82f0dd42015-02-03 23:57:18 +08009971 }
Ashok Raj70131292018-02-01 22:59:43 +01009972
KarimAllah Ahmede5a83412018-02-01 22:59:45 +01009973 if (spec_ctrl)
9974 nested_vmx_disable_intercept_for_msr(
9975 msr_bitmap_l1, msr_bitmap_l0,
9976 MSR_IA32_SPEC_CTRL,
9977 MSR_TYPE_R | MSR_TYPE_W);
9978
Ashok Raj70131292018-02-01 22:59:43 +01009979 if (pred_cmd)
9980 nested_vmx_disable_intercept_for_msr(
9981 msr_bitmap_l1, msr_bitmap_l0,
9982 MSR_IA32_PRED_CMD,
9983 MSR_TYPE_W);
9984
Wincy Vanf2b93282015-02-03 23:56:03 +08009985 kunmap(page);
9986 nested_release_page_clean(page);
9987
9988 return true;
9989}
9990
9991static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
9992 struct vmcs12 *vmcs12)
9993{
Wincy Van82f0dd42015-02-03 23:57:18 +08009994 if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
Wincy Van608406e2015-02-03 23:57:51 +08009995 !nested_cpu_has_apic_reg_virt(vmcs12) &&
Wincy Van705699a2015-02-03 23:58:17 +08009996 !nested_cpu_has_vid(vmcs12) &&
9997 !nested_cpu_has_posted_intr(vmcs12))
Wincy Vanf2b93282015-02-03 23:56:03 +08009998 return 0;
9999
10000 /*
10001 * If virtualize x2apic mode is enabled,
10002 * virtualize apic access must be disabled.
10003 */
Wincy Van82f0dd42015-02-03 23:57:18 +080010004 if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
10005 nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
Wincy Vanf2b93282015-02-03 23:56:03 +080010006 return -EINVAL;
10007
Wincy Van608406e2015-02-03 23:57:51 +080010008 /*
10009 * If virtual interrupt delivery is enabled,
10010 * we must exit on external interrupts.
10011 */
10012 if (nested_cpu_has_vid(vmcs12) &&
10013 !nested_exit_on_intr(vcpu))
10014 return -EINVAL;
10015
Wincy Van705699a2015-02-03 23:58:17 +080010016 /*
10017 * bits 15:8 should be zero in posted_intr_nv,
10018 * the descriptor address has been already checked
10019 * in nested_get_vmcs12_pages.
10020 */
10021 if (nested_cpu_has_posted_intr(vmcs12) &&
10022 (!nested_cpu_has_vid(vmcs12) ||
10023 !nested_exit_intr_ack_set(vcpu) ||
10024 vmcs12->posted_intr_nv & 0xff00))
10025 return -EINVAL;
10026
Wincy Vanf2b93282015-02-03 23:56:03 +080010027 /* tpr shadow is needed by all apicv features. */
10028 if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
10029 return -EINVAL;
10030
10031 return 0;
Wincy Van3af18d92015-02-03 23:49:31 +080010032}
10033
Eugene Korenevskye9ac0332014-12-11 08:53:27 +030010034static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
10035 unsigned long count_field,
Eugene Korenevsky92d71bc2015-03-29 23:56:44 +030010036 unsigned long addr_field)
Wincy Vanff651cb2014-12-11 08:52:58 +030010037{
Eugene Korenevsky92d71bc2015-03-29 23:56:44 +030010038 int maxphyaddr;
Eugene Korenevskye9ac0332014-12-11 08:53:27 +030010039 u64 count, addr;
10040
10041 if (vmcs12_read_any(vcpu, count_field, &count) ||
10042 vmcs12_read_any(vcpu, addr_field, &addr)) {
10043 WARN_ON(1);
10044 return -EINVAL;
10045 }
10046 if (count == 0)
10047 return 0;
Eugene Korenevsky92d71bc2015-03-29 23:56:44 +030010048 maxphyaddr = cpuid_maxphyaddr(vcpu);
Eugene Korenevskye9ac0332014-12-11 08:53:27 +030010049 if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
10050 (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
Paolo Bonzinibbe41b92016-08-19 17:51:20 +020010051 pr_debug_ratelimited(
Eugene Korenevskye9ac0332014-12-11 08:53:27 +030010052 "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
10053 addr_field, maxphyaddr, count, addr);
10054 return -EINVAL;
10055 }
10056 return 0;
10057}
10058
10059static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
10060 struct vmcs12 *vmcs12)
10061{
Eugene Korenevskye9ac0332014-12-11 08:53:27 +030010062 if (vmcs12->vm_exit_msr_load_count == 0 &&
10063 vmcs12->vm_exit_msr_store_count == 0 &&
10064 vmcs12->vm_entry_msr_load_count == 0)
10065 return 0; /* Fast path */
Eugene Korenevskye9ac0332014-12-11 08:53:27 +030010066 if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
Eugene Korenevsky92d71bc2015-03-29 23:56:44 +030010067 VM_EXIT_MSR_LOAD_ADDR) ||
Eugene Korenevskye9ac0332014-12-11 08:53:27 +030010068 nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
Eugene Korenevsky92d71bc2015-03-29 23:56:44 +030010069 VM_EXIT_MSR_STORE_ADDR) ||
Eugene Korenevskye9ac0332014-12-11 08:53:27 +030010070 nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
Eugene Korenevsky92d71bc2015-03-29 23:56:44 +030010071 VM_ENTRY_MSR_LOAD_ADDR))
Wincy Vanff651cb2014-12-11 08:52:58 +030010072 return -EINVAL;
10073 return 0;
10074}
10075
Eugene Korenevskye9ac0332014-12-11 08:53:27 +030010076static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
10077 struct vmx_msr_entry *e)
10078{
10079 /* x2APIC MSR accesses are not allowed */
Jan Kiszka8a9781f2015-05-04 08:32:32 +020010080 if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8)
Eugene Korenevskye9ac0332014-12-11 08:53:27 +030010081 return -EINVAL;
10082 if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
10083 e->index == MSR_IA32_UCODE_REV)
10084 return -EINVAL;
10085 if (e->reserved != 0)
10086 return -EINVAL;
10087 return 0;
10088}
10089
10090static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
10091 struct vmx_msr_entry *e)
Wincy Vanff651cb2014-12-11 08:52:58 +030010092{
10093 if (e->index == MSR_FS_BASE ||
10094 e->index == MSR_GS_BASE ||
Eugene Korenevskye9ac0332014-12-11 08:53:27 +030010095 e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
10096 nested_vmx_msr_check_common(vcpu, e))
10097 return -EINVAL;
10098 return 0;
10099}
10100
10101static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
10102 struct vmx_msr_entry *e)
10103{
10104 if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
10105 nested_vmx_msr_check_common(vcpu, e))
Wincy Vanff651cb2014-12-11 08:52:58 +030010106 return -EINVAL;
10107 return 0;
10108}
10109
10110/*
10111 * Load guest's/host's msr at nested entry/exit.
10112 * return 0 for success, entry index for failure.
10113 */
10114static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
10115{
10116 u32 i;
10117 struct vmx_msr_entry e;
10118 struct msr_data msr;
10119
10120 msr.host_initiated = false;
10121 for (i = 0; i < count; i++) {
Paolo Bonzini54bf36a2015-04-08 15:39:23 +020010122 if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e),
10123 &e, sizeof(e))) {
Paolo Bonzinibbe41b92016-08-19 17:51:20 +020010124 pr_debug_ratelimited(
Eugene Korenevskye9ac0332014-12-11 08:53:27 +030010125 "%s cannot read MSR entry (%u, 0x%08llx)\n",
10126 __func__, i, gpa + i * sizeof(e));
Wincy Vanff651cb2014-12-11 08:52:58 +030010127 goto fail;
Eugene Korenevskye9ac0332014-12-11 08:53:27 +030010128 }
10129 if (nested_vmx_load_msr_check(vcpu, &e)) {
Paolo Bonzinibbe41b92016-08-19 17:51:20 +020010130 pr_debug_ratelimited(
Eugene Korenevskye9ac0332014-12-11 08:53:27 +030010131 "%s check failed (%u, 0x%x, 0x%x)\n",
10132 __func__, i, e.index, e.reserved);
10133 goto fail;
10134 }
Wincy Vanff651cb2014-12-11 08:52:58 +030010135 msr.index = e.index;
10136 msr.data = e.value;
Eugene Korenevskye9ac0332014-12-11 08:53:27 +030010137 if (kvm_set_msr(vcpu, &msr)) {
Paolo Bonzinibbe41b92016-08-19 17:51:20 +020010138 pr_debug_ratelimited(
Eugene Korenevskye9ac0332014-12-11 08:53:27 +030010139 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
10140 __func__, i, e.index, e.value);
Wincy Vanff651cb2014-12-11 08:52:58 +030010141 goto fail;
Eugene Korenevskye9ac0332014-12-11 08:53:27 +030010142 }
Wincy Vanff651cb2014-12-11 08:52:58 +030010143 }
10144 return 0;
10145fail:
10146 return i + 1;
10147}
10148
10149static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
10150{
10151 u32 i;
10152 struct vmx_msr_entry e;
10153
10154 for (i = 0; i < count; i++) {
Paolo Bonzini609e36d2015-04-08 15:30:38 +020010155 struct msr_data msr_info;
Paolo Bonzini54bf36a2015-04-08 15:39:23 +020010156 if (kvm_vcpu_read_guest(vcpu,
10157 gpa + i * sizeof(e),
10158 &e, 2 * sizeof(u32))) {
Paolo Bonzinibbe41b92016-08-19 17:51:20 +020010159 pr_debug_ratelimited(
Eugene Korenevskye9ac0332014-12-11 08:53:27 +030010160 "%s cannot read MSR entry (%u, 0x%08llx)\n",
10161 __func__, i, gpa + i * sizeof(e));
Wincy Vanff651cb2014-12-11 08:52:58 +030010162 return -EINVAL;
Eugene Korenevskye9ac0332014-12-11 08:53:27 +030010163 }
10164 if (nested_vmx_store_msr_check(vcpu, &e)) {
Paolo Bonzinibbe41b92016-08-19 17:51:20 +020010165 pr_debug_ratelimited(
Eugene Korenevskye9ac0332014-12-11 08:53:27 +030010166 "%s check failed (%u, 0x%x, 0x%x)\n",
10167 __func__, i, e.index, e.reserved);
Wincy Vanff651cb2014-12-11 08:52:58 +030010168 return -EINVAL;
Eugene Korenevskye9ac0332014-12-11 08:53:27 +030010169 }
Paolo Bonzini609e36d2015-04-08 15:30:38 +020010170 msr_info.host_initiated = false;
10171 msr_info.index = e.index;
10172 if (kvm_get_msr(vcpu, &msr_info)) {
Paolo Bonzinibbe41b92016-08-19 17:51:20 +020010173 pr_debug_ratelimited(
Eugene Korenevskye9ac0332014-12-11 08:53:27 +030010174 "%s cannot read MSR (%u, 0x%x)\n",
10175 __func__, i, e.index);
10176 return -EINVAL;
10177 }
Paolo Bonzini54bf36a2015-04-08 15:39:23 +020010178 if (kvm_vcpu_write_guest(vcpu,
10179 gpa + i * sizeof(e) +
10180 offsetof(struct vmx_msr_entry, value),
10181 &msr_info.data, sizeof(msr_info.data))) {
Paolo Bonzinibbe41b92016-08-19 17:51:20 +020010182 pr_debug_ratelimited(
Eugene Korenevskye9ac0332014-12-11 08:53:27 +030010183 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
Paolo Bonzini609e36d2015-04-08 15:30:38 +020010184 __func__, i, e.index, msr_info.data);
Eugene Korenevskye9ac0332014-12-11 08:53:27 +030010185 return -EINVAL;
10186 }
Wincy Vanff651cb2014-12-11 08:52:58 +030010187 }
10188 return 0;
10189}
10190
Nadav Har'Elfe3ef052011-05-25 23:10:02 +030010191/*
10192 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
10193 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
Tiejun Chenb4619662014-09-22 10:31:38 +080010194 * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
Nadav Har'Elfe3ef052011-05-25 23:10:02 +030010195 * guest in a way that will both be appropriate to L1's requests, and our
10196 * needs. In addition to modifying the active vmcs (which is vmcs02), this
10197 * function also has additional necessary side-effects, like setting various
10198 * vcpu->arch fields.
10199 */
10200static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10201{
10202 struct vcpu_vmx *vmx = to_vmx(vcpu);
10203 u32 exec_control;
10204
10205 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
10206 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
10207 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
10208 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
10209 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
10210 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
10211 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
10212 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
10213 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
10214 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
10215 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
10216 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
10217 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
10218 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
10219 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
10220 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
10221 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
10222 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
10223 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
10224 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
10225 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
10226 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
10227 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
10228 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
10229 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
10230 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
10231 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
10232 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
10233 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
10234 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
10235 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
10236 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
10237 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
10238 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
10239 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
10240 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
10241
Jan Kiszka2996fca2014-06-16 13:59:43 +020010242 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) {
10243 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
10244 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
10245 } else {
10246 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
10247 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
10248 }
Nadav Har'Elfe3ef052011-05-25 23:10:02 +030010249 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
10250 vmcs12->vm_entry_intr_info_field);
10251 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
10252 vmcs12->vm_entry_exception_error_code);
10253 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
10254 vmcs12->vm_entry_instruction_len);
10255 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
10256 vmcs12->guest_interruptibility_info);
Nadav Har'Elfe3ef052011-05-25 23:10:02 +030010257 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
Gleb Natapov63fbf592013-07-28 18:31:06 +030010258 vmx_set_rflags(vcpu, vmcs12->guest_rflags);
Nadav Har'Elfe3ef052011-05-25 23:10:02 +030010259 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
10260 vmcs12->guest_pending_dbg_exceptions);
10261 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
10262 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
10263
Wanpeng Li81dc01f2014-12-04 19:11:07 +080010264 if (nested_cpu_has_xsaves(vmcs12))
10265 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
Nadav Har'Elfe3ef052011-05-25 23:10:02 +030010266 vmcs_write64(VMCS_LINK_POINTER, -1ull);
10267
Jan Kiszkaf4124502014-03-07 20:03:13 +010010268 exec_control = vmcs12->pin_based_vm_exec_control;
Wincy Van705699a2015-02-03 23:58:17 +080010269
Paolo Bonzini93140062016-07-06 13:23:51 +020010270 /* Preemption timer setting is only taken from vmcs01. */
10271 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
10272 exec_control |= vmcs_config.pin_based_exec_ctrl;
10273 if (vmx->hv_deadline_tsc == -1)
10274 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
10275
10276 /* Posted interrupts setting is only taken from vmcs12. */
Wincy Van705699a2015-02-03 23:58:17 +080010277 if (nested_cpu_has_posted_intr(vmcs12)) {
10278 /*
10279 * Note that we use L0's vector here and in
10280 * vmx_deliver_nested_posted_interrupt.
10281 */
10282 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
10283 vmx->nested.pi_pending = false;
Li RongQing0bcf2612015-12-03 13:29:34 +080010284 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
Wincy Van705699a2015-02-03 23:58:17 +080010285 vmcs_write64(POSTED_INTR_DESC_ADDR,
10286 page_to_phys(vmx->nested.pi_desc_page) +
10287 (unsigned long)(vmcs12->posted_intr_desc_addr &
10288 (PAGE_SIZE - 1)));
10289 } else
10290 exec_control &= ~PIN_BASED_POSTED_INTR;
10291
Jan Kiszkaf4124502014-03-07 20:03:13 +010010292 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
Nadav Har'Elfe3ef052011-05-25 23:10:02 +030010293
Jan Kiszkaf4124502014-03-07 20:03:13 +010010294 vmx->nested.preemption_timer_expired = false;
10295 if (nested_cpu_has_preemption_timer(vmcs12))
10296 vmx_start_preemption_timer(vcpu);
Jan Kiszka0238ea92013-03-13 11:31:24 +010010297
Nadav Har'Elfe3ef052011-05-25 23:10:02 +030010298 /*
10299 * Whether page-faults are trapped is determined by a combination of
10300 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
10301 * If enable_ept, L0 doesn't care about page faults and we should
10302 * set all of these to L1's desires. However, if !enable_ept, L0 does
10303 * care about (at least some) page faults, and because it is not easy
10304 * (if at all possible?) to merge L0 and L1's desires, we simply ask
10305 * to exit on each and every L2 page fault. This is done by setting
10306 * MASK=MATCH=0 and (see below) EB.PF=1.
10307 * Note that below we don't need special code to set EB.PF beyond the
10308 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
10309 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
10310 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
10311 *
10312 * A problem with this approach (when !enable_ept) is that L1 may be
10313 * injected with more page faults than it asked for. This could have
10314 * caused problems, but in practice existing hypervisors don't care.
10315 * To fix this, we will need to emulate the PFEC checking (on the L1
10316 * page tables), using walk_addr(), when injecting PFs to L1.
10317 */
10318 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
10319 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
10320 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
10321 enable_ept ? vmcs12->page_fault_error_code_match : 0);
10322
10323 if (cpu_has_secondary_exec_ctrls()) {
Jan Kiszkaf4124502014-03-07 20:03:13 +010010324 exec_control = vmx_secondary_exec_control(vmx);
Xiao Guangronge2821622015-09-09 14:05:52 +080010325
Nadav Har'Elfe3ef052011-05-25 23:10:02 +030010326 /* Take the following fields only from vmcs12 */
Paolo Bonzini696dfd92014-05-07 11:20:54 +020010327 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
Jan Kiszkab3a2a902015-03-23 19:27:19 +010010328 SECONDARY_EXEC_RDTSCP |
Paolo Bonzini696dfd92014-05-07 11:20:54 +020010329 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
Dan Williamsdfa169b2016-06-02 11:17:24 -070010330 SECONDARY_EXEC_APIC_REGISTER_VIRT);
Nadav Har'Elfe3ef052011-05-25 23:10:02 +030010331 if (nested_cpu_has(vmcs12,
10332 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
10333 exec_control |= vmcs12->secondary_vm_exec_control;
10334
10335 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
10336 /*
Nadav Har'Elfe3ef052011-05-25 23:10:02 +030010337 * If translation failed, no matter: This feature asks
10338 * to exit when accessing the given address, and if it
10339 * can never be accessed, this feature won't do
10340 * anything anyway.
10341 */
10342 if (!vmx->nested.apic_access_page)
10343 exec_control &=
10344 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
10345 else
10346 vmcs_write64(APIC_ACCESS_ADDR,
10347 page_to_phys(vmx->nested.apic_access_page));
Wincy Vanf2b93282015-02-03 23:56:03 +080010348 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) &&
Paolo Bonzini35754c92015-07-29 12:05:37 +020010349 cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
Jan Kiszkaca3f2572013-12-16 12:55:46 +010010350 exec_control |=
10351 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
Tang Chen38b99172014-09-24 15:57:54 +080010352 kvm_vcpu_reload_apic_access_page(vcpu);
Nadav Har'Elfe3ef052011-05-25 23:10:02 +030010353 }
10354
Wincy Van608406e2015-02-03 23:57:51 +080010355 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
10356 vmcs_write64(EOI_EXIT_BITMAP0,
10357 vmcs12->eoi_exit_bitmap0);
10358 vmcs_write64(EOI_EXIT_BITMAP1,
10359 vmcs12->eoi_exit_bitmap1);
10360 vmcs_write64(EOI_EXIT_BITMAP2,
10361 vmcs12->eoi_exit_bitmap2);
10362 vmcs_write64(EOI_EXIT_BITMAP3,
10363 vmcs12->eoi_exit_bitmap3);
10364 vmcs_write16(GUEST_INTR_STATUS,
10365 vmcs12->guest_intr_status);
10366 }
10367
Nadav Har'Elfe3ef052011-05-25 23:10:02 +030010368 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
10369 }
10370
10371
10372 /*
10373 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
10374 * Some constant fields are set here by vmx_set_constant_host_state().
10375 * Other fields are different per CPU, and will be set later when
10376 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
10377 */
Yang Zhanga547c6d2013-04-11 19:25:10 +080010378 vmx_set_constant_host_state(vmx);
Nadav Har'Elfe3ef052011-05-25 23:10:02 +030010379
10380 /*
Jim Mattson69c25252016-10-04 10:48:38 -070010381 * Set the MSR load/store lists to match L0's settings.
10382 */
10383 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
Konrad Rzeszutek Wilk57e3ada2018-06-20 13:58:37 -040010384 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.host.nr);
10385 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host.val));
10386 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.guest.nr);
10387 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest.val));
Jim Mattson69c25252016-10-04 10:48:38 -070010388
10389 /*
Nadav Har'Elfe3ef052011-05-25 23:10:02 +030010390 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
10391 * entry, but only if the current (host) sp changed from the value
10392 * we wrote last (vmx->host_rsp). This cache is no longer relevant
10393 * if we switch vmcs, and rather than hold a separate cache per vmcs,
10394 * here we just force the write to happen on entry.
10395 */
10396 vmx->host_rsp = 0;
10397
10398 exec_control = vmx_exec_control(vmx); /* L0's desires */
10399 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
10400 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
10401 exec_control &= ~CPU_BASED_TPR_SHADOW;
10402 exec_control |= vmcs12->cpu_based_vm_exec_control;
Wanpeng Lia7c0b072014-08-21 19:46:50 +080010403
10404 if (exec_control & CPU_BASED_TPR_SHADOW) {
10405 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
10406 page_to_phys(vmx->nested.virtual_apic_page));
10407 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
Jim Mattson86ef97b2017-09-12 13:02:54 -070010408 } else {
10409#ifdef CONFIG_X86_64
10410 exec_control |= CPU_BASED_CR8_LOAD_EXITING |
10411 CPU_BASED_CR8_STORE_EXITING;
10412#endif
Wanpeng Lia7c0b072014-08-21 19:46:50 +080010413 }
10414
Wincy Van3af18d92015-02-03 23:49:31 +080010415 if (cpu_has_vmx_msr_bitmap() &&
Radim Krčmářd048c092016-08-08 20:16:22 +020010416 exec_control & CPU_BASED_USE_MSR_BITMAPS &&
10417 nested_vmx_merge_msr_bitmap(vcpu, vmcs12))
10418 ; /* MSR_BITMAP will be set by following vmx_set_efer. */
10419 else
Wincy Van3af18d92015-02-03 23:49:31 +080010420 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
10421
Nadav Har'Elfe3ef052011-05-25 23:10:02 +030010422 /*
Wincy Van3af18d92015-02-03 23:49:31 +080010423 * Merging of IO bitmap not currently supported.
Nadav Har'Elfe3ef052011-05-25 23:10:02 +030010424 * Rather, exit every time.
10425 */
Nadav Har'Elfe3ef052011-05-25 23:10:02 +030010426 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
10427 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
10428
10429 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
10430
10431 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
10432 * bitwise-or of what L1 wants to trap for L2, and what we want to
10433 * trap. Note that CR0.TS also needs updating - we do this later.
10434 */
10435 update_exception_bitmap(vcpu);
10436 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
10437 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
10438
Nadav Har'El8049d652013-08-05 11:07:06 +030010439 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
10440 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
10441 * bits are further modified by vmx_set_efer() below.
10442 */
Jan Kiszkaf4124502014-03-07 20:03:13 +010010443 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
Nadav Har'El8049d652013-08-05 11:07:06 +030010444
10445 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
10446 * emulated by vmx_set_efer(), below.
10447 */
Gleb Natapov2961e8762013-11-25 15:37:13 +020010448 vm_entry_controls_init(vmx,
Nadav Har'El8049d652013-08-05 11:07:06 +030010449 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
10450 ~VM_ENTRY_IA32E_MODE) |
Nadav Har'Elfe3ef052011-05-25 23:10:02 +030010451 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
10452
Jan Kiszka44811c02013-08-04 17:17:27 +020010453 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
Nadav Har'Elfe3ef052011-05-25 23:10:02 +030010454 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
Jan Kiszka44811c02013-08-04 17:17:27 +020010455 vcpu->arch.pat = vmcs12->guest_ia32_pat;
10456 } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
Nadav Har'Elfe3ef052011-05-25 23:10:02 +030010457 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
10458
10459
10460 set_cr4_guest_host_mask(vmx);
10461
Paolo Bonzini36be0b92014-02-24 12:30:04 +010010462 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
10463 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
10464
Nadav Har'El27fc51b2011-08-02 15:54:52 +030010465 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
10466 vmcs_write64(TSC_OFFSET,
Paolo Bonziniea26e4e2016-11-01 00:39:48 +010010467 vcpu->arch.tsc_offset + vmcs12->tsc_offset);
Nadav Har'El27fc51b2011-08-02 15:54:52 +030010468 else
Paolo Bonziniea26e4e2016-11-01 00:39:48 +010010469 vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
Peter Feinerc95ba922016-08-17 09:36:47 -070010470 if (kvm_has_tsc_control)
10471 decache_tsc_multiplier(vmx);
Nadav Har'Elfe3ef052011-05-25 23:10:02 +030010472
Paolo Bonzini6236b782018-01-16 16:51:18 +010010473 if (cpu_has_vmx_msr_bitmap())
10474 vmcs_write64(MSR_BITMAP, __pa(vmx->nested.vmcs02.msr_bitmap));
10475
Nadav Har'Elfe3ef052011-05-25 23:10:02 +030010476 if (enable_vpid) {
10477 /*
Wanpeng Li5c614b32015-10-13 09:18:36 -070010478 * There is no direct mapping between vpid02 and vpid12, the
10479 * vpid02 is per-vCPU for L0 and reused while the value of
10480 * vpid12 is changed w/ one invvpid during nested vmentry.
10481 * The vpid12 is allocated by L1 for L2, so it will not
10482 * influence global bitmap(for vpid01 and vpid02 allocation)
10483 * even if spawn a lot of nested vCPUs.
Nadav Har'Elfe3ef052011-05-25 23:10:02 +030010484 */
Wanpeng Li5c614b32015-10-13 09:18:36 -070010485 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02) {
10486 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02);
10487 if (vmcs12->virtual_processor_id != vmx->nested.last_vpid) {
10488 vmx->nested.last_vpid = vmcs12->virtual_processor_id;
10489 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02);
10490 }
10491 } else {
10492 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
10493 vmx_flush_tlb(vcpu);
10494 }
10495
Nadav Har'Elfe3ef052011-05-25 23:10:02 +030010496 }
10497
Ladi Prosek560a9792017-04-04 14:18:53 +020010498 if (enable_pml) {
10499 /*
10500 * Conceptually we want to copy the PML address and index from
10501 * vmcs01 here, and then back to vmcs01 on nested vmexit. But,
10502 * since we always flush the log on each vmexit, this happens
10503 * to be equivalent to simply resetting the fields in vmcs02.
10504 */
10505 ASSERT(vmx->pml_pg);
10506 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
10507 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
10508 }
10509
Nadav Har'El155a97a2013-08-05 11:07:16 +030010510 if (nested_cpu_has_ept(vmcs12)) {
10511 kvm_mmu_unload(vcpu);
10512 nested_ept_init_mmu_context(vcpu);
Jim Mattson8386ff52017-03-16 13:53:59 -070010513 } else if (nested_cpu_has2(vmcs12,
10514 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
10515 vmx_flush_tlb_ept_only(vcpu);
Nadav Har'El155a97a2013-08-05 11:07:16 +030010516 }
10517
Nadav Har'Elfe3ef052011-05-25 23:10:02 +030010518 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
10519 vcpu->arch.efer = vmcs12->guest_ia32_efer;
Jan Kiszkad1fa0352013-04-14 12:44:54 +020010520 else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
Nadav Har'Elfe3ef052011-05-25 23:10:02 +030010521 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10522 else
10523 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10524 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
10525 vmx_set_efer(vcpu, vcpu->arch.efer);
10526
10527 /*
10528 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
10529 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
10530 * The CR0_READ_SHADOW is what L2 should have expected to read given
10531 * the specifications by L1; It's not enough to take
10532 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
10533 * have more bits than L1 expected.
10534 */
10535 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
10536 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
10537
10538 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
10539 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
10540
10541 /* shadow page tables on either EPT or shadow page tables */
10542 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
10543 kvm_mmu_reset_context(vcpu);
10544
Gleb Natapovfeaf0c7d2013-09-25 12:51:36 +030010545 if (!enable_ept)
10546 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
10547
Nadav Har'El3633cfc2013-08-05 11:07:07 +030010548 /*
10549 * L1 may access the L2's PDPTR, so save them to construct vmcs12
10550 */
10551 if (enable_ept) {
10552 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
10553 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
10554 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
10555 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
10556 }
10557
Nadav Har'Elfe3ef052011-05-25 23:10:02 +030010558 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
10559 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
10560}
10561
Nadav Har'Elcd232ad2011-05-25 23:10:33 +030010562/*
10563 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
10564 * for running an L2 nested guest.
10565 */
10566static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
10567{
10568 struct vmcs12 *vmcs12;
10569 struct vcpu_vmx *vmx = to_vmx(vcpu);
10570 int cpu;
Jan Kiszka384bb782013-04-20 10:52:36 +020010571 bool ia32e;
Wincy Vanff651cb2014-12-11 08:52:58 +030010572 u32 msr_entry_idx;
Nadav Har'Elcd232ad2011-05-25 23:10:33 +030010573
10574 if (!nested_vmx_check_permission(vcpu) ||
10575 !nested_vmx_check_vmcs12(vcpu))
10576 return 1;
10577
10578 skip_emulated_instruction(vcpu);
10579 vmcs12 = get_vmcs12(vcpu);
10580
Abel Gordon012f83c2013-04-18 14:39:25 +030010581 if (enable_shadow_vmcs)
10582 copy_shadow_to_vmcs12(vmx);
10583
Nadav Har'El7c177932011-05-25 23:12:04 +030010584 /*
10585 * The nested entry process starts with enforcing various prerequisites
10586 * on vmcs12 as required by the Intel SDM, and act appropriately when
10587 * they fail: As the SDM explains, some conditions should cause the
10588 * instruction to fail, while others will cause the instruction to seem
10589 * to succeed, but return an EXIT_REASON_INVALID_STATE.
10590 * To speed up the normal (success) code path, we should avoid checking
10591 * for misconfigurations which will anyway be caught by the processor
10592 * when using the merged vmcs02.
10593 */
10594 if (vmcs12->launch_state == launch) {
10595 nested_vmx_failValid(vcpu,
10596 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
10597 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
10598 return 1;
10599 }
10600
Jan Kiszka6dfacad2013-12-04 08:58:54 +010010601 if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
10602 vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
Paolo Bonzini26539bd2013-04-15 15:00:27 +020010603 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
10604 return 1;
10605 }
10606
Wincy Van3af18d92015-02-03 23:49:31 +080010607 if (!nested_get_vmcs12_pages(vcpu, vmcs12)) {
Nadav Har'El7c177932011-05-25 23:12:04 +030010608 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
10609 return 1;
10610 }
10611
Wincy Van3af18d92015-02-03 23:49:31 +080010612 if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12)) {
Nadav Har'El7c177932011-05-25 23:12:04 +030010613 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
10614 return 1;
10615 }
10616
Wincy Vanf2b93282015-02-03 23:56:03 +080010617 if (nested_vmx_check_apicv_controls(vcpu, vmcs12)) {
10618 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
10619 return 1;
10620 }
10621
Eugene Korenevskye9ac0332014-12-11 08:53:27 +030010622 if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12)) {
10623 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
10624 return 1;
10625 }
10626
Nadav Har'El7c177932011-05-25 23:12:04 +030010627 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
Wincy Vanb9c237b2015-02-03 23:56:30 +080010628 vmx->nested.nested_vmx_true_procbased_ctls_low,
10629 vmx->nested.nested_vmx_procbased_ctls_high) ||
Nadav Har'El7c177932011-05-25 23:12:04 +030010630 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
Wincy Vanb9c237b2015-02-03 23:56:30 +080010631 vmx->nested.nested_vmx_secondary_ctls_low,
10632 vmx->nested.nested_vmx_secondary_ctls_high) ||
Nadav Har'El7c177932011-05-25 23:12:04 +030010633 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
Wincy Vanb9c237b2015-02-03 23:56:30 +080010634 vmx->nested.nested_vmx_pinbased_ctls_low,
10635 vmx->nested.nested_vmx_pinbased_ctls_high) ||
Nadav Har'El7c177932011-05-25 23:12:04 +030010636 !vmx_control_verify(vmcs12->vm_exit_controls,
Wincy Vanb9c237b2015-02-03 23:56:30 +080010637 vmx->nested.nested_vmx_true_exit_ctls_low,
10638 vmx->nested.nested_vmx_exit_ctls_high) ||
Nadav Har'El7c177932011-05-25 23:12:04 +030010639 !vmx_control_verify(vmcs12->vm_entry_controls,
Wincy Vanb9c237b2015-02-03 23:56:30 +080010640 vmx->nested.nested_vmx_true_entry_ctls_low,
10641 vmx->nested.nested_vmx_entry_ctls_high))
Nadav Har'El7c177932011-05-25 23:12:04 +030010642 {
10643 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
10644 return 1;
10645 }
10646
10647 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
10648 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
10649 nested_vmx_failValid(vcpu,
10650 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
10651 return 1;
10652 }
10653
Wincy Vanb9c237b2015-02-03 23:56:30 +080010654 if (!nested_cr0_valid(vcpu, vmcs12->guest_cr0) ||
Nadav Har'El7c177932011-05-25 23:12:04 +030010655 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
10656 nested_vmx_entry_failure(vcpu, vmcs12,
10657 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
10658 return 1;
10659 }
10660 if (vmcs12->vmcs_link_pointer != -1ull) {
10661 nested_vmx_entry_failure(vcpu, vmcs12,
10662 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
10663 return 1;
10664 }
10665
10666 /*
Jan Kiszkacb0c8cda2013-04-27 12:58:00 +020010667 * If the load IA32_EFER VM-entry control is 1, the following checks
Jan Kiszka384bb782013-04-20 10:52:36 +020010668 * are performed on the field for the IA32_EFER MSR:
10669 * - Bits reserved in the IA32_EFER MSR must be 0.
10670 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
10671 * the IA-32e mode guest VM-exit control. It must also be identical
10672 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
10673 * CR0.PG) is 1.
10674 */
10675 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
10676 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
10677 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
10678 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
10679 ((vmcs12->guest_cr0 & X86_CR0_PG) &&
10680 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
10681 nested_vmx_entry_failure(vcpu, vmcs12,
10682 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
10683 return 1;
10684 }
10685 }
10686
10687 /*
10688 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
10689 * IA32_EFER MSR must be 0 in the field for that register. In addition,
10690 * the values of the LMA and LME bits in the field must each be that of
10691 * the host address-space size VM-exit control.
10692 */
10693 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
10694 ia32e = (vmcs12->vm_exit_controls &
10695 VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
10696 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
10697 ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
10698 ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
10699 nested_vmx_entry_failure(vcpu, vmcs12,
10700 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
10701 return 1;
10702 }
10703 }
10704
10705 /*
Nadav Har'El7c177932011-05-25 23:12:04 +030010706 * We're finally done with prerequisite checking, and can start with
10707 * the nested entry.
10708 */
10709
Nadav Har'Elcd232ad2011-05-25 23:10:33 +030010710 enter_guest_mode(vcpu);
10711
Jan Kiszka2996fca2014-06-16 13:59:43 +020010712 if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
10713 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10714
Nadav Har'Elcd232ad2011-05-25 23:10:33 +030010715 cpu = get_cpu();
Jim Mattson46e24df2017-11-27 17:22:25 -060010716 vmx->loaded_vmcs = &vmx->nested.vmcs02;
Nadav Har'Elcd232ad2011-05-25 23:10:33 +030010717 vmx_vcpu_put(vcpu);
10718 vmx_vcpu_load(vcpu, cpu);
10719 vcpu->cpu = cpu;
10720 put_cpu();
10721
Jan Kiszka36c3cc42013-02-23 22:35:37 +010010722 vmx_segment_cache_clear(vmx);
10723
Nadav Har'Elcd232ad2011-05-25 23:10:33 +030010724 prepare_vmcs02(vcpu, vmcs12);
10725
Wincy Vanff651cb2014-12-11 08:52:58 +030010726 msr_entry_idx = nested_vmx_load_msr(vcpu,
10727 vmcs12->vm_entry_msr_load_addr,
10728 vmcs12->vm_entry_msr_load_count);
10729 if (msr_entry_idx) {
10730 leave_guest_mode(vcpu);
10731 vmx_load_vmcs01(vcpu);
10732 nested_vmx_entry_failure(vcpu, vmcs12,
10733 EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx);
10734 return 1;
10735 }
10736
10737 vmcs12->launch_state = 1;
10738
Paolo Bonzinib3dc63c2018-07-02 13:07:14 +020010739 /* Hide L1D cache contents from the nested guest. */
10740 vmx->vcpu.arch.l1tf_flush_l1d = true;
10741
Jan Kiszka6dfacad2013-12-04 08:58:54 +010010742 if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
Joel Schopp5cb56052015-03-02 13:43:31 -060010743 return kvm_vcpu_halt(vcpu);
Jan Kiszka6dfacad2013-12-04 08:58:54 +010010744
Jan Kiszka7af40ad32014-01-04 18:47:23 +010010745 vmx->nested.nested_run_pending = 1;
10746
Nadav Har'Elcd232ad2011-05-25 23:10:33 +030010747 /*
10748 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
10749 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
10750 * returned as far as L1 is concerned. It will only return (and set
10751 * the success flag) when L2 exits (see nested_vmx_vmexit()).
10752 */
10753 return 1;
10754}
10755
Nadav Har'El4704d0b2011-05-25 23:11:34 +030010756/*
10757 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
10758 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
10759 * This function returns the new value we should put in vmcs12.guest_cr0.
10760 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
10761 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
10762 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
10763 * didn't trap the bit, because if L1 did, so would L0).
10764 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
10765 * been modified by L2, and L1 knows it. So just leave the old value of
10766 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
10767 * isn't relevant, because if L0 traps this bit it can set it to anything.
10768 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
10769 * changed these bits, and therefore they need to be updated, but L0
10770 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
10771 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
10772 */
10773static inline unsigned long
10774vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10775{
10776 return
10777 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
10778 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
10779 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
10780 vcpu->arch.cr0_guest_owned_bits));
10781}
10782
10783static inline unsigned long
10784vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10785{
10786 return
10787 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
10788 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
10789 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
10790 vcpu->arch.cr4_guest_owned_bits));
10791}
10792
Jan Kiszka5f3d5792013-04-14 12:12:46 +020010793static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
10794 struct vmcs12 *vmcs12)
10795{
10796 u32 idt_vectoring;
10797 unsigned int nr;
10798
Gleb Natapov851eb6672013-09-25 12:51:34 +030010799 if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
Jan Kiszka5f3d5792013-04-14 12:12:46 +020010800 nr = vcpu->arch.exception.nr;
10801 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10802
10803 if (kvm_exception_is_soft(nr)) {
10804 vmcs12->vm_exit_instruction_len =
10805 vcpu->arch.event_exit_inst_len;
10806 idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
10807 } else
10808 idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
10809
10810 if (vcpu->arch.exception.has_error_code) {
10811 idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
10812 vmcs12->idt_vectoring_error_code =
10813 vcpu->arch.exception.error_code;
10814 }
10815
10816 vmcs12->idt_vectoring_info_field = idt_vectoring;
Jan Kiszkacd2633c2013-10-23 17:42:15 +010010817 } else if (vcpu->arch.nmi_injected) {
Jan Kiszka5f3d5792013-04-14 12:12:46 +020010818 vmcs12->idt_vectoring_info_field =
10819 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
10820 } else if (vcpu->arch.interrupt.pending) {
10821 nr = vcpu->arch.interrupt.nr;
10822 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10823
10824 if (vcpu->arch.interrupt.soft) {
10825 idt_vectoring |= INTR_TYPE_SOFT_INTR;
10826 vmcs12->vm_entry_instruction_len =
10827 vcpu->arch.event_exit_inst_len;
10828 } else
10829 idt_vectoring |= INTR_TYPE_EXT_INTR;
10830
10831 vmcs12->idt_vectoring_info_field = idt_vectoring;
10832 }
10833}
10834
Jan Kiszkab6b8a142014-03-07 20:03:12 +010010835static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
10836{
10837 struct vcpu_vmx *vmx = to_vmx(vcpu);
10838
Jan Kiszkaf4124502014-03-07 20:03:13 +010010839 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
10840 vmx->nested.preemption_timer_expired) {
10841 if (vmx->nested.nested_run_pending)
10842 return -EBUSY;
10843 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
10844 return 0;
10845 }
10846
Jan Kiszkab6b8a142014-03-07 20:03:12 +010010847 if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
Jan Kiszka220c5672014-03-07 20:03:14 +010010848 if (vmx->nested.nested_run_pending ||
10849 vcpu->arch.interrupt.pending)
Jan Kiszkab6b8a142014-03-07 20:03:12 +010010850 return -EBUSY;
10851 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
10852 NMI_VECTOR | INTR_TYPE_NMI_INTR |
10853 INTR_INFO_VALID_MASK, 0);
10854 /*
10855 * The NMI-triggered VM exit counts as injection:
10856 * clear this one and block further NMIs.
10857 */
10858 vcpu->arch.nmi_pending = 0;
10859 vmx_set_nmi_mask(vcpu, true);
10860 return 0;
10861 }
10862
10863 if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
10864 nested_exit_on_intr(vcpu)) {
10865 if (vmx->nested.nested_run_pending)
10866 return -EBUSY;
10867 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
Wincy Van705699a2015-02-03 23:58:17 +080010868 return 0;
Jan Kiszkab6b8a142014-03-07 20:03:12 +010010869 }
10870
David Hildenbrand1edccf22017-01-25 11:58:58 +010010871 vmx_complete_nested_posted_interrupt(vcpu);
10872 return 0;
Jan Kiszkab6b8a142014-03-07 20:03:12 +010010873}
10874
Jan Kiszkaf4124502014-03-07 20:03:13 +010010875static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
10876{
10877 ktime_t remaining =
10878 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
10879 u64 value;
10880
10881 if (ktime_to_ns(remaining) <= 0)
10882 return 0;
10883
10884 value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
10885 do_div(value, 1000000);
10886 return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
10887}
10888
Nadav Har'El4704d0b2011-05-25 23:11:34 +030010889/*
10890 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
10891 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
10892 * and this function updates it to reflect the changes to the guest state while
10893 * L2 was running (and perhaps made some exits which were handled directly by L0
10894 * without going back to L1), and to reflect the exit reason.
10895 * Note that we do not have to copy here all VMCS fields, just those that
10896 * could have changed by the L2 guest or the exit - i.e., the guest-state and
10897 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
10898 * which already writes to vmcs12 directly.
10899 */
Jan Kiszka533558b2014-01-04 18:47:20 +010010900static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10901 u32 exit_reason, u32 exit_intr_info,
10902 unsigned long exit_qualification)
Nadav Har'El4704d0b2011-05-25 23:11:34 +030010903{
10904 /* update guest state fields: */
10905 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
10906 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
10907
Nadav Har'El4704d0b2011-05-25 23:11:34 +030010908 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
10909 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
10910 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
10911
10912 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
10913 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
10914 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
10915 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
10916 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
10917 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
10918 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
10919 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
10920 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
10921 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
10922 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
10923 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
10924 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
10925 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
10926 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
10927 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
10928 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
10929 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
10930 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
10931 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
10932 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
10933 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
10934 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
10935 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
10936 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
10937 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
10938 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
10939 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
10940 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
10941 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
10942 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
10943 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
10944 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
10945 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
10946 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
10947 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
10948
Nadav Har'El4704d0b2011-05-25 23:11:34 +030010949 vmcs12->guest_interruptibility_info =
10950 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
10951 vmcs12->guest_pending_dbg_exceptions =
10952 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
Jan Kiszka3edf1e62014-01-04 18:47:24 +010010953 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
10954 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
10955 else
10956 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
Nadav Har'El4704d0b2011-05-25 23:11:34 +030010957
Jan Kiszkaf4124502014-03-07 20:03:13 +010010958 if (nested_cpu_has_preemption_timer(vmcs12)) {
10959 if (vmcs12->vm_exit_controls &
10960 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
10961 vmcs12->vmx_preemption_timer_value =
10962 vmx_get_preemption_timer_value(vcpu);
10963 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
10964 }
Arthur Chunqi Li7854cbc2013-09-16 16:11:44 +080010965
Nadav Har'El3633cfc2013-08-05 11:07:07 +030010966 /*
10967 * In some cases (usually, nested EPT), L2 is allowed to change its
10968 * own CR3 without exiting. If it has changed it, we must keep it.
10969 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
10970 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
10971 *
10972 * Additionally, restore L2's PDPTR to vmcs12.
10973 */
10974 if (enable_ept) {
Paolo Bonzinif3531052015-12-03 15:49:56 +010010975 vmcs12->guest_cr3 = vmcs_readl(GUEST_CR3);
Nadav Har'El3633cfc2013-08-05 11:07:07 +030010976 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
10977 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
10978 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
10979 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
10980 }
10981
Jim Mattson4933e9f2017-06-01 12:44:46 -070010982 vmcs12->guest_linear_address = vmcs_readl(GUEST_LINEAR_ADDRESS);
Jan Dakinevich119a9c02016-09-04 21:22:47 +030010983
Wincy Van608406e2015-02-03 23:57:51 +080010984 if (nested_cpu_has_vid(vmcs12))
10985 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
10986
Jan Kiszkac18911a2013-03-13 16:06:41 +010010987 vmcs12->vm_entry_controls =
10988 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
Gleb Natapov2961e8762013-11-25 15:37:13 +020010989 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
Jan Kiszkac18911a2013-03-13 16:06:41 +010010990
Jan Kiszka2996fca2014-06-16 13:59:43 +020010991 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
10992 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
10993 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10994 }
10995
Nadav Har'El4704d0b2011-05-25 23:11:34 +030010996 /* TODO: These cannot have changed unless we have MSR bitmaps and
10997 * the relevant bit asks not to trap the change */
Jan Kiszkab8c07d52013-04-06 13:51:21 +020010998 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
Nadav Har'El4704d0b2011-05-25 23:11:34 +030010999 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
Jan Kiszka10ba54a2013-08-08 16:26:31 +020011000 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
11001 vmcs12->guest_ia32_efer = vcpu->arch.efer;
Nadav Har'El4704d0b2011-05-25 23:11:34 +030011002 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
11003 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
11004 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
Paolo Bonzinia87036a2016-03-08 09:52:13 +010011005 if (kvm_mpx_supported())
Paolo Bonzini36be0b92014-02-24 12:30:04 +010011006 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
Wanpeng Li81dc01f2014-12-04 19:11:07 +080011007 if (nested_cpu_has_xsaves(vmcs12))
11008 vmcs12->xss_exit_bitmap = vmcs_read64(XSS_EXIT_BITMAP);
Nadav Har'El4704d0b2011-05-25 23:11:34 +030011009
11010 /* update exit information fields: */
11011
Jan Kiszka533558b2014-01-04 18:47:20 +010011012 vmcs12->vm_exit_reason = exit_reason;
11013 vmcs12->exit_qualification = exit_qualification;
Nadav Har'El4704d0b2011-05-25 23:11:34 +030011014
Jan Kiszka533558b2014-01-04 18:47:20 +010011015 vmcs12->vm_exit_intr_info = exit_intr_info;
Jan Kiszkac0d1c772013-04-14 12:12:50 +020011016 if ((vmcs12->vm_exit_intr_info &
11017 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
11018 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
11019 vmcs12->vm_exit_intr_error_code =
11020 vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
Jan Kiszka5f3d5792013-04-14 12:12:46 +020011021 vmcs12->idt_vectoring_info_field = 0;
Nadav Har'El4704d0b2011-05-25 23:11:34 +030011022 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
11023 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
11024
Jan Kiszka5f3d5792013-04-14 12:12:46 +020011025 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
11026 /* vm_entry_intr_info_field is cleared on exit. Emulate this
11027 * instead of reading the real value. */
Nadav Har'El4704d0b2011-05-25 23:11:34 +030011028 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
Jan Kiszka5f3d5792013-04-14 12:12:46 +020011029
11030 /*
11031 * Transfer the event that L0 or L1 may wanted to inject into
11032 * L2 to IDT_VECTORING_INFO_FIELD.
11033 */
11034 vmcs12_save_pending_event(vcpu, vmcs12);
11035 }
11036
11037 /*
11038 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
11039 * preserved above and would only end up incorrectly in L1.
11040 */
11041 vcpu->arch.nmi_injected = false;
11042 kvm_clear_exception_queue(vcpu);
11043 kvm_clear_interrupt_queue(vcpu);
Nadav Har'El4704d0b2011-05-25 23:11:34 +030011044}
11045
11046/*
11047 * A part of what we need to when the nested L2 guest exits and we want to
11048 * run its L1 parent, is to reset L1's guest state to the host state specified
11049 * in vmcs12.
11050 * This function is to be called not only on normal nested exit, but also on
11051 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
11052 * Failures During or After Loading Guest State").
11053 * This function should be called when the active VMCS is L1's (vmcs01).
11054 */
Jan Kiszka733568f2013-02-23 15:07:47 +010011055static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
11056 struct vmcs12 *vmcs12)
Nadav Har'El4704d0b2011-05-25 23:11:34 +030011057{
Arthur Chunqi Li21feb4e2013-07-15 16:04:08 +080011058 struct kvm_segment seg;
11059
Nadav Har'El4704d0b2011-05-25 23:11:34 +030011060 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
11061 vcpu->arch.efer = vmcs12->host_ia32_efer;
Jan Kiszkad1fa0352013-04-14 12:44:54 +020011062 else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
Nadav Har'El4704d0b2011-05-25 23:11:34 +030011063 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
11064 else
11065 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
11066 vmx_set_efer(vcpu, vcpu->arch.efer);
11067
11068 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
11069 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
H. Peter Anvin1adfa762013-04-27 16:10:11 -070011070 vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
Nadav Har'El4704d0b2011-05-25 23:11:34 +030011071 /*
11072 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
11073 * actually changed, because it depends on the current state of
11074 * fpu_active (which may have changed).
11075 * Note that vmx_set_cr0 refers to efer set above.
11076 */
Jan Kiszka9e3e4db2013-09-03 21:11:45 +020011077 vmx_set_cr0(vcpu, vmcs12->host_cr0);
Nadav Har'El4704d0b2011-05-25 23:11:34 +030011078 /*
11079 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
11080 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
11081 * but we also need to update cr0_guest_host_mask and exception_bitmap.
11082 */
11083 update_exception_bitmap(vcpu);
11084 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
11085 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
11086
11087 /*
11088 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
11089 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
11090 */
11091 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
Haozhong Zhang08e16742017-10-10 15:01:22 +080011092 vmx_set_cr4(vcpu, vmcs12->host_cr4);
Nadav Har'El4704d0b2011-05-25 23:11:34 +030011093
Jan Kiszka29bf08f2013-12-28 16:31:52 +010011094 nested_ept_uninit_mmu_context(vcpu);
Nadav Har'El155a97a2013-08-05 11:07:16 +030011095
Nadav Har'El4704d0b2011-05-25 23:11:34 +030011096 kvm_set_cr3(vcpu, vmcs12->host_cr3);
11097 kvm_mmu_reset_context(vcpu);
11098
Gleb Natapovfeaf0c7d2013-09-25 12:51:36 +030011099 if (!enable_ept)
11100 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
11101
Nadav Har'El4704d0b2011-05-25 23:11:34 +030011102 if (enable_vpid) {
11103 /*
11104 * Trivially support vpid by letting L2s share their parent
11105 * L1's vpid. TODO: move to a more elaborate solution, giving
11106 * each L2 its own vpid and exposing the vpid feature to L1.
11107 */
11108 vmx_flush_tlb(vcpu);
11109 }
11110
11111
11112 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
11113 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
11114 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
11115 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
11116 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
Ladi Prosek1be0c0e2017-10-11 16:54:42 +020011117 vmcs_write32(GUEST_IDTR_LIMIT, 0xFFFF);
11118 vmcs_write32(GUEST_GDTR_LIMIT, 0xFFFF);
Nadav Har'El4704d0b2011-05-25 23:11:34 +030011119
Paolo Bonzini36be0b92014-02-24 12:30:04 +010011120 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
11121 if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
11122 vmcs_write64(GUEST_BNDCFGS, 0);
11123
Jan Kiszka44811c02013-08-04 17:17:27 +020011124 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
Nadav Har'El4704d0b2011-05-25 23:11:34 +030011125 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
Jan Kiszka44811c02013-08-04 17:17:27 +020011126 vcpu->arch.pat = vmcs12->host_ia32_pat;
11127 }
Nadav Har'El4704d0b2011-05-25 23:11:34 +030011128 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
11129 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
11130 vmcs12->host_ia32_perf_global_ctrl);
Jan Kiszka503cd0c2013-03-03 13:05:44 +010011131
Arthur Chunqi Li21feb4e2013-07-15 16:04:08 +080011132 /* Set L1 segment info according to Intel SDM
11133 27.5.2 Loading Host Segment and Descriptor-Table Registers */
11134 seg = (struct kvm_segment) {
11135 .base = 0,
11136 .limit = 0xFFFFFFFF,
11137 .selector = vmcs12->host_cs_selector,
11138 .type = 11,
11139 .present = 1,
11140 .s = 1,
11141 .g = 1
11142 };
11143 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
11144 seg.l = 1;
11145 else
11146 seg.db = 1;
11147 vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
11148 seg = (struct kvm_segment) {
11149 .base = 0,
11150 .limit = 0xFFFFFFFF,
11151 .type = 3,
11152 .present = 1,
11153 .s = 1,
11154 .db = 1,
11155 .g = 1
11156 };
11157 seg.selector = vmcs12->host_ds_selector;
11158 vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
11159 seg.selector = vmcs12->host_es_selector;
11160 vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
11161 seg.selector = vmcs12->host_ss_selector;
11162 vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
11163 seg.selector = vmcs12->host_fs_selector;
11164 seg.base = vmcs12->host_fs_base;
11165 vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
11166 seg.selector = vmcs12->host_gs_selector;
11167 seg.base = vmcs12->host_gs_base;
11168 vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
11169 seg = (struct kvm_segment) {
Gleb Natapov205befd2013-08-04 15:08:06 +030011170 .base = vmcs12->host_tr_base,
Arthur Chunqi Li21feb4e2013-07-15 16:04:08 +080011171 .limit = 0x67,
11172 .selector = vmcs12->host_tr_selector,
11173 .type = 11,
11174 .present = 1
11175 };
11176 vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
11177
Jan Kiszka503cd0c2013-03-03 13:05:44 +010011178 kvm_set_dr(vcpu, 7, 0x400);
11179 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
Wincy Vanff651cb2014-12-11 08:52:58 +030011180
Wincy Van3af18d92015-02-03 23:49:31 +080011181 if (cpu_has_vmx_msr_bitmap())
Paolo Bonzini6236b782018-01-16 16:51:18 +010011182 vmx_update_msr_bitmap(vcpu);
Wincy Van3af18d92015-02-03 23:49:31 +080011183
Wincy Vanff651cb2014-12-11 08:52:58 +030011184 if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
11185 vmcs12->vm_exit_msr_load_count))
11186 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
Nadav Har'El4704d0b2011-05-25 23:11:34 +030011187}
11188
11189/*
11190 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
11191 * and modify vmcs12 to make it see what it would expect to see there if
11192 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
11193 */
Jan Kiszka533558b2014-01-04 18:47:20 +010011194static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
11195 u32 exit_intr_info,
11196 unsigned long exit_qualification)
Nadav Har'El4704d0b2011-05-25 23:11:34 +030011197{
11198 struct vcpu_vmx *vmx = to_vmx(vcpu);
Nadav Har'El4704d0b2011-05-25 23:11:34 +030011199 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
11200
Jan Kiszka5f3d5792013-04-14 12:12:46 +020011201 /* trying to cancel vmlaunch/vmresume is a bug */
11202 WARN_ON_ONCE(vmx->nested.nested_run_pending);
11203
Nadav Har'El4704d0b2011-05-25 23:11:34 +030011204 leave_guest_mode(vcpu);
Jan Kiszka533558b2014-01-04 18:47:20 +010011205 prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
11206 exit_qualification);
Nadav Har'El4704d0b2011-05-25 23:11:34 +030011207
Wincy Vanff651cb2014-12-11 08:52:58 +030011208 if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
11209 vmcs12->vm_exit_msr_store_count))
11210 nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
11211
Wanpeng Lif3380ca2014-08-05 12:42:23 +080011212 vmx_load_vmcs01(vcpu);
11213
Bandan Das77b0f5d2014-04-19 18:17:45 -040011214 if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
11215 && nested_exit_intr_ack_set(vcpu)) {
11216 int irq = kvm_cpu_get_interrupt(vcpu);
11217 WARN_ON(irq < 0);
11218 vmcs12->vm_exit_intr_info = irq |
11219 INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
11220 }
11221
Jan Kiszka542060e2014-01-04 18:47:21 +010011222 trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
11223 vmcs12->exit_qualification,
11224 vmcs12->idt_vectoring_info_field,
11225 vmcs12->vm_exit_intr_info,
11226 vmcs12->vm_exit_intr_error_code,
11227 KVM_ISA_VMX);
Nadav Har'El4704d0b2011-05-25 23:11:34 +030011228
Paolo Bonzini8391ce42016-07-07 14:58:33 +020011229 vm_entry_controls_reset_shadow(vmx);
11230 vm_exit_controls_reset_shadow(vmx);
Jan Kiszka36c3cc42013-02-23 22:35:37 +010011231 vmx_segment_cache_clear(vmx);
11232
Nadav Har'El4704d0b2011-05-25 23:11:34 +030011233 load_vmcs12_host_state(vcpu, vmcs12);
11234
Paolo Bonzini93140062016-07-06 13:23:51 +020011235 /* Update any VMCS fields that might have changed while L2 ran */
Konrad Rzeszutek Wilk57e3ada2018-06-20 13:58:37 -040011236 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.host.nr);
11237 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.guest.nr);
Paolo Bonziniea26e4e2016-11-01 00:39:48 +010011238 vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
Paolo Bonzini93140062016-07-06 13:23:51 +020011239 if (vmx->hv_deadline_tsc == -1)
11240 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
11241 PIN_BASED_VMX_PREEMPTION_TIMER);
11242 else
11243 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
11244 PIN_BASED_VMX_PREEMPTION_TIMER);
Peter Feinerc95ba922016-08-17 09:36:47 -070011245 if (kvm_has_tsc_control)
11246 decache_tsc_multiplier(vmx);
Nadav Har'El4704d0b2011-05-25 23:11:34 +030011247
Radim Krčmářdccbfcf2016-08-08 20:16:23 +020011248 if (vmx->nested.change_vmcs01_virtual_x2apic_mode) {
11249 vmx->nested.change_vmcs01_virtual_x2apic_mode = false;
11250 vmx_set_virtual_x2apic_mode(vcpu,
11251 vcpu->arch.apic_base & X2APIC_ENABLE);
Jim Mattson8386ff52017-03-16 13:53:59 -070011252 } else if (!nested_cpu_has_ept(vmcs12) &&
11253 nested_cpu_has2(vmcs12,
11254 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
11255 vmx_flush_tlb_ept_only(vcpu);
Radim Krčmářdccbfcf2016-08-08 20:16:23 +020011256 }
Nadav Har'El4704d0b2011-05-25 23:11:34 +030011257
11258 /* This is needed for same reason as it was needed in prepare_vmcs02 */
11259 vmx->host_rsp = 0;
11260
11261 /* Unpin physical memory we referred to in vmcs02 */
11262 if (vmx->nested.apic_access_page) {
11263 nested_release_page(vmx->nested.apic_access_page);
Paolo Bonzini48d89b92014-08-26 13:27:46 +020011264 vmx->nested.apic_access_page = NULL;
Nadav Har'El4704d0b2011-05-25 23:11:34 +030011265 }
Wanpeng Lia7c0b072014-08-21 19:46:50 +080011266 if (vmx->nested.virtual_apic_page) {
11267 nested_release_page(vmx->nested.virtual_apic_page);
Paolo Bonzini48d89b92014-08-26 13:27:46 +020011268 vmx->nested.virtual_apic_page = NULL;
Wanpeng Lia7c0b072014-08-21 19:46:50 +080011269 }
Wincy Van705699a2015-02-03 23:58:17 +080011270 if (vmx->nested.pi_desc_page) {
11271 kunmap(vmx->nested.pi_desc_page);
11272 nested_release_page(vmx->nested.pi_desc_page);
11273 vmx->nested.pi_desc_page = NULL;
11274 vmx->nested.pi_desc = NULL;
11275 }
Nadav Har'El4704d0b2011-05-25 23:11:34 +030011276
11277 /*
Tang Chen38b99172014-09-24 15:57:54 +080011278 * We are now running in L2, mmu_notifier will force to reload the
11279 * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
11280 */
Wanpeng Lic83b6d12016-09-06 17:20:33 +080011281 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
Tang Chen38b99172014-09-24 15:57:54 +080011282
11283 /*
Nadav Har'El4704d0b2011-05-25 23:11:34 +030011284 * Exiting from L2 to L1, we're now back to L1 which thinks it just
11285 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
11286 * success or failure flag accordingly.
11287 */
11288 if (unlikely(vmx->fail)) {
11289 vmx->fail = 0;
11290 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
11291 } else
11292 nested_vmx_succeed(vcpu);
Abel Gordon012f83c2013-04-18 14:39:25 +030011293 if (enable_shadow_vmcs)
11294 vmx->nested.sync_shadow_vmcs = true;
Jan Kiszkab6b8a142014-03-07 20:03:12 +010011295
11296 /* in case we halted in L2 */
11297 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
Nadav Har'El4704d0b2011-05-25 23:11:34 +030011298}
11299
Nadav Har'El7c177932011-05-25 23:12:04 +030011300/*
Jan Kiszka42124922014-01-04 18:47:19 +010011301 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
11302 */
11303static void vmx_leave_nested(struct kvm_vcpu *vcpu)
11304{
Wanpeng Lic886f282017-03-06 04:03:28 -080011305 if (is_guest_mode(vcpu)) {
11306 to_vmx(vcpu)->nested.nested_run_pending = 0;
Jan Kiszka533558b2014-01-04 18:47:20 +010011307 nested_vmx_vmexit(vcpu, -1, 0, 0);
Wanpeng Lic886f282017-03-06 04:03:28 -080011308 }
Jan Kiszka42124922014-01-04 18:47:19 +010011309 free_nested(to_vmx(vcpu));
11310}
11311
11312/*
Nadav Har'El7c177932011-05-25 23:12:04 +030011313 * L1's failure to enter L2 is a subset of a normal exit, as explained in
11314 * 23.7 "VM-entry failures during or after loading guest state" (this also
11315 * lists the acceptable exit-reason and exit-qualification parameters).
11316 * It should only be called before L2 actually succeeded to run, and when
11317 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
11318 */
11319static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
11320 struct vmcs12 *vmcs12,
11321 u32 reason, unsigned long qualification)
11322{
11323 load_vmcs12_host_state(vcpu, vmcs12);
11324 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
11325 vmcs12->exit_qualification = qualification;
11326 nested_vmx_succeed(vcpu);
Abel Gordon012f83c2013-04-18 14:39:25 +030011327 if (enable_shadow_vmcs)
11328 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
Nadav Har'El7c177932011-05-25 23:12:04 +030011329}
11330
Joerg Roedel8a76d7f2011-04-04 12:39:27 +020011331static int vmx_check_intercept(struct kvm_vcpu *vcpu,
11332 struct x86_instruction_info *info,
11333 enum x86_intercept_stage stage)
11334{
11335 return X86EMUL_CONTINUE;
11336}
11337
Yunhong Jiang64672c92016-06-13 14:19:59 -070011338#ifdef CONFIG_X86_64
11339/* (a << shift) / divisor, return 1 if overflow otherwise 0 */
11340static inline int u64_shl_div_u64(u64 a, unsigned int shift,
11341 u64 divisor, u64 *result)
11342{
11343 u64 low = a << shift, high = a >> (64 - shift);
11344
11345 /* To avoid the overflow on divq */
11346 if (high >= divisor)
11347 return 1;
11348
11349 /* Low hold the result, high hold rem which is discarded */
11350 asm("divq %2\n\t" : "=a" (low), "=d" (high) :
11351 "rm" (divisor), "0" (low), "1" (high));
11352 *result = low;
11353
11354 return 0;
11355}
11356
11357static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc)
11358{
11359 struct vcpu_vmx *vmx = to_vmx(vcpu);
Paolo Bonzini9175d2e2016-06-27 15:08:01 +020011360 u64 tscl = rdtsc();
11361 u64 guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
11362 u64 delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
Yunhong Jiang64672c92016-06-13 14:19:59 -070011363
11364 /* Convert to host delta tsc if tsc scaling is enabled */
11365 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
11366 u64_shl_div_u64(delta_tsc,
11367 kvm_tsc_scaling_ratio_frac_bits,
11368 vcpu->arch.tsc_scaling_ratio,
11369 &delta_tsc))
11370 return -ERANGE;
11371
11372 /*
11373 * If the delta tsc can't fit in the 32 bit after the multi shift,
11374 * we can't use the preemption timer.
11375 * It's possible that it fits on later vmentries, but checking
11376 * on every vmentry is costly so we just use an hrtimer.
11377 */
11378 if (delta_tsc >> (cpu_preemption_timer_multi + 32))
11379 return -ERANGE;
11380
11381 vmx->hv_deadline_tsc = tscl + delta_tsc;
11382 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
11383 PIN_BASED_VMX_PREEMPTION_TIMER);
11384 return 0;
11385}
11386
11387static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
11388{
11389 struct vcpu_vmx *vmx = to_vmx(vcpu);
11390 vmx->hv_deadline_tsc = -1;
11391 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
11392 PIN_BASED_VMX_PREEMPTION_TIMER);
11393}
11394#endif
11395
Paolo Bonzini48d89b92014-08-26 13:27:46 +020011396static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
Radim Krčmářae97a3b2014-08-21 18:08:06 +020011397{
Radim Krčmářb4a2d312014-08-21 18:08:08 +020011398 if (ple_gap)
11399 shrink_ple_window(vcpu);
Radim Krčmářae97a3b2014-08-21 18:08:06 +020011400}
11401
Kai Huang843e4332015-01-28 10:54:28 +080011402static void vmx_slot_enable_log_dirty(struct kvm *kvm,
11403 struct kvm_memory_slot *slot)
11404{
11405 kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
11406 kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
11407}
11408
11409static void vmx_slot_disable_log_dirty(struct kvm *kvm,
11410 struct kvm_memory_slot *slot)
11411{
11412 kvm_mmu_slot_set_dirty(kvm, slot);
11413}
11414
11415static void vmx_flush_log_dirty(struct kvm *kvm)
11416{
11417 kvm_flush_pml_buffers(kvm);
11418}
11419
11420static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
11421 struct kvm_memory_slot *memslot,
11422 gfn_t offset, unsigned long mask)
11423{
11424 kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
11425}
11426
Paolo Bonzini01c58b02017-06-06 12:57:04 +020011427static void __pi_post_block(struct kvm_vcpu *vcpu)
11428{
11429 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
11430 struct pi_desc old, new;
11431 unsigned int dest;
Paolo Bonzini01c58b02017-06-06 12:57:04 +020011432
11433 do {
11434 old.control = new.control = pi_desc->control;
Paolo Bonziniff5eb8f2017-06-06 12:57:05 +020011435 WARN(old.nv != POSTED_INTR_WAKEUP_VECTOR,
11436 "Wakeup handler not enabled while the VCPU is blocked\n");
Paolo Bonzini01c58b02017-06-06 12:57:04 +020011437
11438 dest = cpu_physical_id(vcpu->cpu);
11439
11440 if (x2apic_enabled())
11441 new.ndst = dest;
11442 else
11443 new.ndst = (dest << 8) & 0xFF00;
11444
Paolo Bonzini01c58b02017-06-06 12:57:04 +020011445 /* set 'NV' to 'notification vector' */
11446 new.nv = POSTED_INTR_VECTOR;
Paolo Bonziniea37f612017-09-28 17:58:41 +020011447 } while (cmpxchg64(&pi_desc->control, old.control,
11448 new.control) != old.control);
Paolo Bonzini01c58b02017-06-06 12:57:04 +020011449
Paolo Bonziniff5eb8f2017-06-06 12:57:05 +020011450 if (!WARN_ON_ONCE(vcpu->pre_pcpu == -1)) {
11451 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
Paolo Bonzini01c58b02017-06-06 12:57:04 +020011452 list_del(&vcpu->blocked_vcpu_list);
Paolo Bonziniff5eb8f2017-06-06 12:57:05 +020011453 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
Paolo Bonzini01c58b02017-06-06 12:57:04 +020011454 vcpu->pre_pcpu = -1;
11455 }
11456}
11457
Feng Wuefc64402015-09-18 22:29:51 +080011458/*
Feng Wubf9f6ac2015-09-18 22:29:55 +080011459 * This routine does the following things for vCPU which is going
11460 * to be blocked if VT-d PI is enabled.
11461 * - Store the vCPU to the wakeup list, so when interrupts happen
11462 * we can find the right vCPU to wake up.
11463 * - Change the Posted-interrupt descriptor as below:
11464 * 'NDST' <-- vcpu->pre_pcpu
11465 * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR
11466 * - If 'ON' is set during this process, which means at least one
11467 * interrupt is posted for this vCPU, we cannot block it, in
11468 * this case, return 1, otherwise, return 0.
11469 *
11470 */
Yunhong Jiangbc225122016-06-13 14:19:58 -070011471static int pi_pre_block(struct kvm_vcpu *vcpu)
Feng Wubf9f6ac2015-09-18 22:29:55 +080011472{
Feng Wubf9f6ac2015-09-18 22:29:55 +080011473 unsigned int dest;
11474 struct pi_desc old, new;
11475 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
11476
11477 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
Yang Zhanga0052192016-06-13 09:56:56 +080011478 !irq_remapping_cap(IRQ_POSTING_CAP) ||
11479 !kvm_vcpu_apicv_active(vcpu))
Feng Wubf9f6ac2015-09-18 22:29:55 +080011480 return 0;
11481
Paolo Bonziniff5eb8f2017-06-06 12:57:05 +020011482 WARN_ON(irqs_disabled());
11483 local_irq_disable();
11484 if (!WARN_ON_ONCE(vcpu->pre_pcpu != -1)) {
11485 vcpu->pre_pcpu = vcpu->cpu;
11486 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
11487 list_add_tail(&vcpu->blocked_vcpu_list,
11488 &per_cpu(blocked_vcpu_on_cpu,
11489 vcpu->pre_pcpu));
11490 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
11491 }
Feng Wubf9f6ac2015-09-18 22:29:55 +080011492
11493 do {
11494 old.control = new.control = pi_desc->control;
11495
Feng Wubf9f6ac2015-09-18 22:29:55 +080011496 WARN((pi_desc->sn == 1),
11497 "Warning: SN field of posted-interrupts "
11498 "is set before blocking\n");
11499
11500 /*
11501 * Since vCPU can be preempted during this process,
11502 * vcpu->cpu could be different with pre_pcpu, we
11503 * need to set pre_pcpu as the destination of wakeup
11504 * notification event, then we can find the right vCPU
11505 * to wakeup in wakeup handler if interrupts happen
11506 * when the vCPU is in blocked state.
11507 */
11508 dest = cpu_physical_id(vcpu->pre_pcpu);
11509
11510 if (x2apic_enabled())
11511 new.ndst = dest;
11512 else
11513 new.ndst = (dest << 8) & 0xFF00;
11514
11515 /* set 'NV' to 'wakeup vector' */
11516 new.nv = POSTED_INTR_WAKEUP_VECTOR;
Paolo Bonziniea37f612017-09-28 17:58:41 +020011517 } while (cmpxchg64(&pi_desc->control, old.control,
11518 new.control) != old.control);
Feng Wubf9f6ac2015-09-18 22:29:55 +080011519
Paolo Bonziniff5eb8f2017-06-06 12:57:05 +020011520 /* We should not block the vCPU if an interrupt is posted for it. */
11521 if (pi_test_on(pi_desc) == 1)
11522 __pi_post_block(vcpu);
11523
11524 local_irq_enable();
11525 return (vcpu->pre_pcpu == -1);
Feng Wubf9f6ac2015-09-18 22:29:55 +080011526}
11527
Yunhong Jiangbc225122016-06-13 14:19:58 -070011528static int vmx_pre_block(struct kvm_vcpu *vcpu)
11529{
11530 if (pi_pre_block(vcpu))
11531 return 1;
11532
Yunhong Jiang64672c92016-06-13 14:19:59 -070011533 if (kvm_lapic_hv_timer_in_use(vcpu))
11534 kvm_lapic_switch_to_sw_timer(vcpu);
11535
Yunhong Jiangbc225122016-06-13 14:19:58 -070011536 return 0;
11537}
11538
11539static void pi_post_block(struct kvm_vcpu *vcpu)
Feng Wubf9f6ac2015-09-18 22:29:55 +080011540{
Paolo Bonziniff5eb8f2017-06-06 12:57:05 +020011541 if (vcpu->pre_pcpu == -1)
Feng Wubf9f6ac2015-09-18 22:29:55 +080011542 return;
11543
Paolo Bonziniff5eb8f2017-06-06 12:57:05 +020011544 WARN_ON(irqs_disabled());
11545 local_irq_disable();
Paolo Bonzini01c58b02017-06-06 12:57:04 +020011546 __pi_post_block(vcpu);
Paolo Bonziniff5eb8f2017-06-06 12:57:05 +020011547 local_irq_enable();
Feng Wubf9f6ac2015-09-18 22:29:55 +080011548}
11549
Yunhong Jiangbc225122016-06-13 14:19:58 -070011550static void vmx_post_block(struct kvm_vcpu *vcpu)
11551{
Yunhong Jiang64672c92016-06-13 14:19:59 -070011552 if (kvm_x86_ops->set_hv_timer)
11553 kvm_lapic_switch_to_hv_timer(vcpu);
11554
Yunhong Jiangbc225122016-06-13 14:19:58 -070011555 pi_post_block(vcpu);
11556}
11557
Feng Wubf9f6ac2015-09-18 22:29:55 +080011558/*
Feng Wuefc64402015-09-18 22:29:51 +080011559 * vmx_update_pi_irte - set IRTE for Posted-Interrupts
11560 *
11561 * @kvm: kvm
11562 * @host_irq: host irq of the interrupt
11563 * @guest_irq: gsi of the interrupt
11564 * @set: set or unset PI
11565 * returns 0 on success, < 0 on failure
11566 */
11567static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
11568 uint32_t guest_irq, bool set)
11569{
11570 struct kvm_kernel_irq_routing_entry *e;
11571 struct kvm_irq_routing_table *irq_rt;
11572 struct kvm_lapic_irq irq;
11573 struct kvm_vcpu *vcpu;
11574 struct vcpu_data vcpu_info;
Jan H. Schönherr3d4213f2017-09-07 19:02:30 +010011575 int idx, ret = 0;
Feng Wuefc64402015-09-18 22:29:51 +080011576
11577 if (!kvm_arch_has_assigned_device(kvm) ||
Yang Zhanga0052192016-06-13 09:56:56 +080011578 !irq_remapping_cap(IRQ_POSTING_CAP) ||
11579 !kvm_vcpu_apicv_active(kvm->vcpus[0]))
Feng Wuefc64402015-09-18 22:29:51 +080011580 return 0;
11581
11582 idx = srcu_read_lock(&kvm->irq_srcu);
11583 irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
Jan H. Schönherr3d4213f2017-09-07 19:02:30 +010011584 if (guest_irq >= irq_rt->nr_rt_entries ||
11585 hlist_empty(&irq_rt->map[guest_irq])) {
11586 pr_warn_once("no route for guest_irq %u/%u (broken user space?)\n",
11587 guest_irq, irq_rt->nr_rt_entries);
11588 goto out;
11589 }
Feng Wuefc64402015-09-18 22:29:51 +080011590
11591 hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
11592 if (e->type != KVM_IRQ_ROUTING_MSI)
11593 continue;
11594 /*
11595 * VT-d PI cannot support posting multicast/broadcast
11596 * interrupts to a vCPU, we still use interrupt remapping
11597 * for these kind of interrupts.
11598 *
11599 * For lowest-priority interrupts, we only support
11600 * those with single CPU as the destination, e.g. user
11601 * configures the interrupts via /proc/irq or uses
11602 * irqbalance to make the interrupts single-CPU.
11603 *
11604 * We will support full lowest-priority interrupt later.
11605 */
11606
Radim Krčmář371313132016-07-12 22:09:27 +020011607 kvm_set_msi_irq(kvm, e, &irq);
Feng Wu23a1c252016-01-25 16:53:32 +080011608 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
11609 /*
11610 * Make sure the IRTE is in remapped mode if
11611 * we don't handle it in posted mode.
11612 */
11613 ret = irq_set_vcpu_affinity(host_irq, NULL);
11614 if (ret < 0) {
11615 printk(KERN_INFO
11616 "failed to back to remapped mode, irq: %u\n",
11617 host_irq);
11618 goto out;
11619 }
11620
Feng Wuefc64402015-09-18 22:29:51 +080011621 continue;
Feng Wu23a1c252016-01-25 16:53:32 +080011622 }
Feng Wuefc64402015-09-18 22:29:51 +080011623
11624 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
11625 vcpu_info.vector = irq.vector;
11626
Feng Wub6ce9782016-01-25 16:53:35 +080011627 trace_kvm_pi_irte_update(vcpu->vcpu_id, host_irq, e->gsi,
Feng Wuefc64402015-09-18 22:29:51 +080011628 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
11629
11630 if (set)
11631 ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
Haozhong Zhang0c4e39c2017-09-18 09:56:49 +080011632 else
Feng Wuefc64402015-09-18 22:29:51 +080011633 ret = irq_set_vcpu_affinity(host_irq, NULL);
Feng Wuefc64402015-09-18 22:29:51 +080011634
11635 if (ret < 0) {
11636 printk(KERN_INFO "%s: failed to update PI IRTE\n",
11637 __func__);
11638 goto out;
11639 }
11640 }
11641
11642 ret = 0;
11643out:
11644 srcu_read_unlock(&kvm->irq_srcu, idx);
11645 return ret;
11646}
11647
Ashok Rajc45dcc72016-06-22 14:59:56 +080011648static void vmx_setup_mce(struct kvm_vcpu *vcpu)
11649{
11650 if (vcpu->arch.mcg_cap & MCG_LMCE_P)
11651 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
11652 FEATURE_CONTROL_LMCE;
11653 else
11654 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
11655 ~FEATURE_CONTROL_LMCE;
11656}
11657
Kees Cook404f6aa2016-08-08 16:29:06 -070011658static struct kvm_x86_ops vmx_x86_ops __ro_after_init = {
Avi Kivity6aa8b732006-12-10 02:21:36 -080011659 .cpu_has_kvm_support = cpu_has_kvm_support,
11660 .disabled_by_bios = vmx_disabled_by_bios,
11661 .hardware_setup = hardware_setup,
11662 .hardware_unsetup = hardware_unsetup,
Yang, Sheng002c7f72007-07-31 14:23:01 +030011663 .check_processor_compatibility = vmx_check_processor_compat,
Avi Kivity6aa8b732006-12-10 02:21:36 -080011664 .hardware_enable = hardware_enable,
11665 .hardware_disable = hardware_disable,
Sheng Yang04547152009-04-01 15:52:31 +080011666 .cpu_has_accelerated_tpr = report_flexpriority,
Tom Lendackyb9655922018-05-10 22:06:39 +020011667 .has_emulated_msr = vmx_has_emulated_msr,
Avi Kivity6aa8b732006-12-10 02:21:36 -080011668
Konrad Rzeszutek Wilka0695af2018-06-20 11:29:53 -040011669 .vm_init = vmx_vm_init,
11670
Avi Kivity6aa8b732006-12-10 02:21:36 -080011671 .vcpu_create = vmx_create_vcpu,
11672 .vcpu_free = vmx_free_vcpu,
Avi Kivity04d2cc72007-09-10 18:10:54 +030011673 .vcpu_reset = vmx_vcpu_reset,
Avi Kivity6aa8b732006-12-10 02:21:36 -080011674
Avi Kivity04d2cc72007-09-10 18:10:54 +030011675 .prepare_guest_switch = vmx_save_host_state,
Avi Kivity6aa8b732006-12-10 02:21:36 -080011676 .vcpu_load = vmx_vcpu_load,
11677 .vcpu_put = vmx_vcpu_put,
11678
Paolo Bonzinia96036b2015-11-10 11:55:36 +010011679 .update_bp_intercept = update_exception_bitmap,
Tom Lendacky62d88fc2018-02-21 13:39:51 -060011680 .get_msr_feature = vmx_get_msr_feature,
Avi Kivity6aa8b732006-12-10 02:21:36 -080011681 .get_msr = vmx_get_msr,
11682 .set_msr = vmx_set_msr,
11683 .get_segment_base = vmx_get_segment_base,
11684 .get_segment = vmx_get_segment,
11685 .set_segment = vmx_set_segment,
Izik Eidus2e4d2652008-03-24 19:38:34 +020011686 .get_cpl = vmx_get_cpl,
Avi Kivity6aa8b732006-12-10 02:21:36 -080011687 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
Avi Kivitye8467fd2009-12-29 18:43:06 +020011688 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
Avi Kivityaff48ba2010-12-05 18:56:11 +020011689 .decache_cr3 = vmx_decache_cr3,
Anthony Liguori25c4c272007-04-27 09:29:21 +030011690 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
Avi Kivity6aa8b732006-12-10 02:21:36 -080011691 .set_cr0 = vmx_set_cr0,
Avi Kivity6aa8b732006-12-10 02:21:36 -080011692 .set_cr3 = vmx_set_cr3,
11693 .set_cr4 = vmx_set_cr4,
Avi Kivity6aa8b732006-12-10 02:21:36 -080011694 .set_efer = vmx_set_efer,
Avi Kivity6aa8b732006-12-10 02:21:36 -080011695 .get_idt = vmx_get_idt,
11696 .set_idt = vmx_set_idt,
11697 .get_gdt = vmx_get_gdt,
11698 .set_gdt = vmx_set_gdt,
Jan Kiszka73aaf249e2014-01-04 18:47:16 +010011699 .get_dr6 = vmx_get_dr6,
11700 .set_dr6 = vmx_set_dr6,
Gleb Natapov020df072010-04-13 10:05:23 +030011701 .set_dr7 = vmx_set_dr7,
Paolo Bonzini81908bf2014-02-21 10:32:27 +010011702 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
Marcelo Tosatti5fdbf972008-06-27 14:58:02 -030011703 .cache_reg = vmx_cache_reg,
Avi Kivity6aa8b732006-12-10 02:21:36 -080011704 .get_rflags = vmx_get_rflags,
11705 .set_rflags = vmx_set_rflags,
Huaitong Hanbe94f6b2016-03-22 16:51:20 +080011706
11707 .get_pkru = vmx_get_pkru,
11708
Paolo Bonzini0fdd74f2015-05-20 11:33:43 +020011709 .fpu_activate = vmx_fpu_activate,
Avi Kivity02daab22009-12-30 12:40:26 +020011710 .fpu_deactivate = vmx_fpu_deactivate,
Avi Kivity6aa8b732006-12-10 02:21:36 -080011711
11712 .tlb_flush = vmx_flush_tlb,
Avi Kivity6aa8b732006-12-10 02:21:36 -080011713
Avi Kivity6aa8b732006-12-10 02:21:36 -080011714 .run = vmx_vcpu_run,
Avi Kivity6062d012009-03-23 17:35:17 +020011715 .handle_exit = vmx_handle_exit,
Avi Kivity6aa8b732006-12-10 02:21:36 -080011716 .skip_emulated_instruction = skip_emulated_instruction,
Glauber Costa2809f5d2009-05-12 16:21:05 -040011717 .set_interrupt_shadow = vmx_set_interrupt_shadow,
11718 .get_interrupt_shadow = vmx_get_interrupt_shadow,
Ingo Molnar102d8322007-02-19 14:37:47 +020011719 .patch_hypercall = vmx_patch_hypercall,
Eddie Dong2a8067f2007-08-06 16:29:07 +030011720 .set_irq = vmx_inject_irq,
Gleb Natapov95ba8273132009-04-21 17:45:08 +030011721 .set_nmi = vmx_inject_nmi,
Avi Kivity298101d2007-11-25 13:41:11 +020011722 .queue_exception = vmx_queue_exception,
Avi Kivityb463a6f2010-07-20 15:06:17 +030011723 .cancel_injection = vmx_cancel_injection,
Gleb Natapov78646122009-03-23 12:12:11 +020011724 .interrupt_allowed = vmx_interrupt_allowed,
Gleb Natapov95ba8273132009-04-21 17:45:08 +030011725 .nmi_allowed = vmx_nmi_allowed,
Jan Kiszka3cfc3092009-11-12 01:04:25 +010011726 .get_nmi_mask = vmx_get_nmi_mask,
11727 .set_nmi_mask = vmx_set_nmi_mask,
Gleb Natapov95ba8273132009-04-21 17:45:08 +030011728 .enable_nmi_window = enable_nmi_window,
11729 .enable_irq_window = enable_irq_window,
11730 .update_cr8_intercept = update_cr8_intercept,
Yang Zhang8d146952013-01-25 10:18:50 +080011731 .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
Tang Chen38b99172014-09-24 15:57:54 +080011732 .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
Andrey Smetanind62caab2015-11-10 15:36:33 +030011733 .get_enable_apicv = vmx_get_enable_apicv,
11734 .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
Yang Zhangc7c9c562013-01-25 10:18:51 +080011735 .load_eoi_exitmap = vmx_load_eoi_exitmap,
11736 .hwapic_irr_update = vmx_hwapic_irr_update,
11737 .hwapic_isr_update = vmx_hwapic_isr_update,
Yang Zhanga20ed542013-04-11 19:25:15 +080011738 .sync_pir_to_irr = vmx_sync_pir_to_irr,
11739 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
Gleb Natapov95ba8273132009-04-21 17:45:08 +030011740
Izik Eiduscbc94022007-10-25 00:29:55 +020011741 .set_tss_addr = vmx_set_tss_addr,
Sheng Yang67253af2008-04-25 10:20:22 +080011742 .get_tdp_level = get_ept_level,
Sheng Yang4b12f0d2009-04-27 20:35:42 +080011743 .get_mt_mask = vmx_get_mt_mask,
Marcelo Tosatti229456f2009-06-17 09:22:14 -030011744
Avi Kivity586f9602010-11-18 13:09:54 +020011745 .get_exit_info = vmx_get_exit_info,
Avi Kivity586f9602010-11-18 13:09:54 +020011746
Sheng Yang17cc3932010-01-05 19:02:27 +080011747 .get_lpage_level = vmx_get_lpage_level,
Sheng Yang0e851882009-12-18 16:48:46 +080011748
11749 .cpuid_update = vmx_cpuid_update,
Sheng Yang4e47c7a2009-12-18 16:48:47 +080011750
11751 .rdtscp_supported = vmx_rdtscp_supported,
Mao, Junjiead756a12012-07-02 01:18:48 +000011752 .invpcid_supported = vmx_invpcid_supported,
Joerg Roedeld4330ef2010-04-22 12:33:11 +020011753
11754 .set_supported_cpuid = vmx_set_supported_cpuid,
Sheng Yangf5f48ee2010-06-30 12:25:15 +080011755
11756 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
Zachary Amsden99e3e302010-08-19 22:07:17 -100011757
11758 .write_tsc_offset = vmx_write_tsc_offset,
Joerg Roedel1c97f0a2010-09-10 17:30:41 +020011759
11760 .set_tdp_cr3 = vmx_set_cr3,
Joerg Roedel8a76d7f2011-04-04 12:39:27 +020011761
11762 .check_intercept = vmx_check_intercept,
Yang Zhanga547c6d2013-04-11 19:25:10 +080011763 .handle_external_intr = vmx_handle_external_intr,
Liu, Jinsongda8999d2014-02-24 10:55:46 +000011764 .mpx_supported = vmx_mpx_supported,
Wanpeng Li55412b22014-12-02 19:21:30 +080011765 .xsaves_supported = vmx_xsaves_supported,
Jan Kiszkab6b8a142014-03-07 20:03:12 +010011766
11767 .check_nested_events = vmx_check_nested_events,
Radim Krčmářae97a3b2014-08-21 18:08:06 +020011768
11769 .sched_in = vmx_sched_in,
Kai Huang843e4332015-01-28 10:54:28 +080011770
11771 .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
11772 .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
11773 .flush_log_dirty = vmx_flush_log_dirty,
11774 .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
Wei Huang25462f72015-06-19 15:45:05 +020011775
Feng Wubf9f6ac2015-09-18 22:29:55 +080011776 .pre_block = vmx_pre_block,
11777 .post_block = vmx_post_block,
11778
Wei Huang25462f72015-06-19 15:45:05 +020011779 .pmu_ops = &intel_pmu_ops,
Feng Wuefc64402015-09-18 22:29:51 +080011780
11781 .update_pi_irte = vmx_update_pi_irte,
Yunhong Jiang64672c92016-06-13 14:19:59 -070011782
11783#ifdef CONFIG_X86_64
11784 .set_hv_timer = vmx_set_hv_timer,
11785 .cancel_hv_timer = vmx_cancel_hv_timer,
11786#endif
Ashok Rajc45dcc72016-06-22 14:59:56 +080011787
11788 .setup_mce = vmx_setup_mce,
Avi Kivity6aa8b732006-12-10 02:21:36 -080011789};
11790
Thomas Gleixner80e55b52018-07-13 16:23:16 +020011791static void vmx_cleanup_l1d_flush(void)
Paolo Bonzinib3d648a2018-07-02 12:47:38 +020011792{
11793 if (vmx_l1d_flush_pages) {
11794 free_pages((unsigned long)vmx_l1d_flush_pages, L1D_CACHE_ORDER);
11795 vmx_l1d_flush_pages = NULL;
11796 }
Thomas Gleixner80e55b52018-07-13 16:23:16 +020011797 /* Restore state so sysfs ignores VMX */
11798 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO;
Konrad Rzeszutek Wilkaf6ce922018-07-02 12:29:30 +020011799}
11800
Konrad Rzeszutek Wilkaf6ce922018-07-02 12:29:30 +020011801
Thomas Gleixner4186ae82018-07-13 16:23:18 +020011802static void vmx_exit(void)
Avi Kivity6aa8b732006-12-10 02:21:36 -080011803{
Dave Young2965faa2015-09-09 15:38:55 -070011804#ifdef CONFIG_KEXEC_CORE
Monam Agarwal3b63a432014-03-22 12:28:10 +053011805 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
Zhang Yanfei8f536b72012-12-06 23:43:34 +080011806 synchronize_rcu();
11807#endif
11808
Zhang Xiantaocb498ea2007-11-14 20:39:31 +080011809 kvm_exit();
Paolo Bonzinib3d648a2018-07-02 12:47:38 +020011810
Thomas Gleixner80e55b52018-07-13 16:23:16 +020011811 vmx_cleanup_l1d_flush();
Avi Kivity6aa8b732006-12-10 02:21:36 -080011812}
Avi Kivity6aa8b732006-12-10 02:21:36 -080011813module_exit(vmx_exit)
Thomas Gleixner4186ae82018-07-13 16:23:18 +020011814
11815static int __init vmx_init(void)
11816{
11817 int r;
11818
11819 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
11820 __alignof__(struct vcpu_vmx), THIS_MODULE);
11821 if (r)
11822 return r;
11823
11824 /*
Thomas Gleixner641a2112018-07-13 16:23:19 +020011825 * Must be called after kvm_init() so enable_ept is properly set
11826 * up. Hand the parameter mitigation value in which was stored in
11827 * the pre module init parser. If no parameter was given, it will
11828 * contain 'auto' which will be turned into the default 'cond'
11829 * mitigation mode.
Thomas Gleixner4186ae82018-07-13 16:23:18 +020011830 */
Thomas Gleixner641a2112018-07-13 16:23:19 +020011831 if (boot_cpu_has(X86_BUG_L1TF)) {
11832 r = vmx_setup_l1d_flush(vmentry_l1d_flush_param);
11833 if (r) {
11834 vmx_exit();
11835 return r;
11836 }
Thomas Gleixner4186ae82018-07-13 16:23:18 +020011837 }
11838
11839#ifdef CONFIG_KEXEC_CORE
11840 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
11841 crash_vmclear_local_loaded_vmcss);
11842#endif
11843
11844 return 0;
11845}
11846module_init(vmx_init)