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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * ahci.c - AHCI SATA support
3 *
Jeff Garzikaf36d7f2005-08-28 20:18:39 -04004 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
Linus Torvalds1da177e2005-04-16 15:20:36 -07007 *
Jeff Garzikaf36d7f2005-08-28 20:18:39 -04008 * Copyright 2004-2005 Red Hat, Inc.
Linus Torvalds1da177e2005-04-16 15:20:36 -07009 *
Linus Torvalds1da177e2005-04-16 15:20:36 -070010 *
Jeff Garzikaf36d7f2005-08-28 20:18:39 -040011 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
Linus Torvalds1da177e2005-04-16 15:20:36 -070030 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
Jeff Garzikaf36d7f2005-08-28 20:18:39 -040031 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
Linus Torvalds1da177e2005-04-16 15:20:36 -070032 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
38#include <linux/init.h>
39#include <linux/blkdev.h>
40#include <linux/delay.h>
41#include <linux/interrupt.h>
domen@coderock.org87507cf2005-04-08 09:53:06 +020042#include <linux/dma-mapping.h>
Jeff Garzika9524a72005-10-30 14:39:11 -050043#include <linux/device.h>
Tejun Heoedc93052007-10-25 14:59:16 +090044#include <linux/dmi.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070045#include <scsi/scsi_host.h>
Jeff Garzik193515d2005-11-07 00:59:37 -050046#include <scsi/scsi_cmnd.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070047#include <linux/libata.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070048
49#define DRV_NAME "ahci"
Tejun Heo7d50b602007-09-23 13:19:54 +090050#define DRV_VERSION "3.0"
Linus Torvalds1da177e2005-04-16 15:20:36 -070051
David Milburn87943ac2008-10-13 14:38:36 -050052/* Enclosure Management Control */
53#define EM_CTRL_MSG_TYPE 0x000f0000
54
55/* Enclosure Management LED Message Type */
56#define EM_MSG_LED_HBA_PORT 0x0000000f
57#define EM_MSG_LED_PMP_SLOT 0x0000ff00
58#define EM_MSG_LED_VALUE 0xffff0000
59#define EM_MSG_LED_VALUE_ACTIVITY 0x00070000
60#define EM_MSG_LED_VALUE_OFF 0xfff80000
61#define EM_MSG_LED_VALUE_ON 0x00010000
62
Tejun Heoa22e6442008-03-10 10:25:25 +090063static int ahci_skip_host_reset;
Arjan van de Venf3d7f232009-01-26 02:05:44 -080064static int ahci_ignore_sss;
65
Tejun Heoa22e6442008-03-10 10:25:25 +090066module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444);
67MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)");
68
Arjan van de Venf3d7f232009-01-26 02:05:44 -080069module_param_named(ignore_sss, ahci_ignore_sss, int, 0444);
70MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)");
71
Kristen Carlson Accardi31556592007-10-25 01:33:26 -040072static int ahci_enable_alpm(struct ata_port *ap,
73 enum link_pm policy);
74static void ahci_disable_alpm(struct ata_port *ap);
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -070075static ssize_t ahci_led_show(struct ata_port *ap, char *buf);
76static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
77 size_t size);
78static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
79 ssize_t size);
Linus Torvalds1da177e2005-04-16 15:20:36 -070080
81enum {
82 AHCI_PCI_BAR = 5,
Tejun Heo648a88b2006-11-09 15:08:40 +090083 AHCI_MAX_PORTS = 32,
Linus Torvalds1da177e2005-04-16 15:20:36 -070084 AHCI_MAX_SG = 168, /* hardware max is 64K */
85 AHCI_DMA_BOUNDARY = 0xffffffff,
Tejun Heo12fad3f2006-05-15 21:03:55 +090086 AHCI_MAX_CMDS = 32,
Tejun Heodd410ff2006-05-15 21:03:50 +090087 AHCI_CMD_SZ = 32,
Tejun Heo12fad3f2006-05-15 21:03:55 +090088 AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
Linus Torvalds1da177e2005-04-16 15:20:36 -070089 AHCI_RX_FIS_SZ = 256,
Jeff Garzika0ea7322005-06-04 01:13:15 -040090 AHCI_CMD_TBL_CDB = 0x40,
Tejun Heodd410ff2006-05-15 21:03:50 +090091 AHCI_CMD_TBL_HDR_SZ = 0x80,
92 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
93 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
94 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
Linus Torvalds1da177e2005-04-16 15:20:36 -070095 AHCI_RX_FIS_SZ,
96 AHCI_IRQ_ON_SG = (1 << 31),
97 AHCI_CMD_ATAPI = (1 << 5),
98 AHCI_CMD_WRITE = (1 << 6),
Tejun Heo4b10e552006-03-12 11:25:27 +090099 AHCI_CMD_PREFETCH = (1 << 7),
Tejun Heo22b49982006-01-23 21:38:44 +0900100 AHCI_CMD_RESET = (1 << 8),
101 AHCI_CMD_CLR_BUSY = (1 << 10),
Linus Torvalds1da177e2005-04-16 15:20:36 -0700102
103 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
Tejun Heo0291f952007-01-25 19:16:28 +0900104 RX_FIS_SDB = 0x58, /* offset of SDB FIS data */
Tejun Heo78cd52d2006-05-15 20:58:29 +0900105 RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700106
107 board_ahci = 0,
Tejun Heo7a234af2007-09-03 12:44:57 +0900108 board_ahci_vt8251 = 1,
109 board_ahci_ign_iferr = 2,
110 board_ahci_sb600 = 3,
111 board_ahci_mv = 4,
Shane Huange427fe02008-12-30 10:53:41 +0800112 board_ahci_sb700 = 5, /* for SB700 and SB800 */
Tejun Heoe297d992008-06-10 00:13:04 +0900113 board_ahci_mcp65 = 6,
Tejun Heo9a3b1032008-06-18 20:56:58 -0400114 board_ahci_nopmp = 7,
Tejun Heoaa431dd2009-04-08 14:25:31 -0700115 board_ahci_yesncq = 8,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700116
117 /* global controller registers */
118 HOST_CAP = 0x00, /* host capabilities */
119 HOST_CTL = 0x04, /* global host control */
120 HOST_IRQ_STAT = 0x08, /* interrupt status */
121 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
122 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -0700123 HOST_EM_LOC = 0x1c, /* Enclosure Management location */
124 HOST_EM_CTL = 0x20, /* Enclosure Management Control */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700125
126 /* HOST_CTL bits */
127 HOST_RESET = (1 << 0), /* reset controller; self-clear */
128 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
129 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
130
131 /* HOST_CAP bits */
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -0700132 HOST_CAP_EMS = (1 << 6), /* Enclosure Management support */
Tejun Heo0be0aa92006-07-26 15:59:26 +0900133 HOST_CAP_SSC = (1 << 14), /* Slumber capable */
Tejun Heo7d50b602007-09-23 13:19:54 +0900134 HOST_CAP_PMP = (1 << 17), /* Port Multiplier support */
Tejun Heo22b49982006-01-23 21:38:44 +0900135 HOST_CAP_CLO = (1 << 24), /* Command List Override support */
Kristen Carlson Accardi31556592007-10-25 01:33:26 -0400136 HOST_CAP_ALPM = (1 << 26), /* Aggressive Link PM support */
Tejun Heo0be0aa92006-07-26 15:59:26 +0900137 HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
Tejun Heo203ef6c2007-07-16 14:29:40 +0900138 HOST_CAP_SNTF = (1 << 29), /* SNotification register */
Tejun Heo979db802006-05-15 21:03:52 +0900139 HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
Tejun Heodd410ff2006-05-15 21:03:50 +0900140 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700141
142 /* registers for each SATA port */
143 PORT_LST_ADDR = 0x00, /* command list DMA addr */
144 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
145 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
146 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
147 PORT_IRQ_STAT = 0x10, /* interrupt status */
148 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
149 PORT_CMD = 0x18, /* port command */
150 PORT_TFDATA = 0x20, /* taskfile data */
151 PORT_SIG = 0x24, /* device TF signature */
152 PORT_CMD_ISSUE = 0x38, /* command issue */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700153 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
154 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
155 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
156 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
Tejun Heo203ef6c2007-07-16 14:29:40 +0900157 PORT_SCR_NTF = 0x3c, /* SATA phy register: SNotification */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700158
159 /* PORT_IRQ_{STAT,MASK} bits */
160 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
161 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
162 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
163 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
164 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
165 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
166 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
167 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
168
169 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
170 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
171 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
172 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
173 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
174 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
175 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
176 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
177 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
178
Tejun Heo78cd52d2006-05-15 20:58:29 +0900179 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
180 PORT_IRQ_IF_ERR |
181 PORT_IRQ_CONNECT |
Tejun Heo42969712006-05-31 18:28:18 +0900182 PORT_IRQ_PHYRDY |
Tejun Heo7d50b602007-09-23 13:19:54 +0900183 PORT_IRQ_UNK_FIS |
184 PORT_IRQ_BAD_PMP,
Tejun Heo78cd52d2006-05-15 20:58:29 +0900185 PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
186 PORT_IRQ_TF_ERR |
187 PORT_IRQ_HBUS_DATA_ERR,
188 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
189 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
190 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700191
192 /* PORT_CMD bits */
Kristen Carlson Accardi31556592007-10-25 01:33:26 -0400193 PORT_CMD_ASP = (1 << 27), /* Aggressive Slumber/Partial */
194 PORT_CMD_ALPE = (1 << 26), /* Aggressive Link PM enable */
Jeff Garzik02eaa662005-11-12 01:32:19 -0500195 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
Tejun Heo7d50b602007-09-23 13:19:54 +0900196 PORT_CMD_PMP = (1 << 17), /* PMP attached */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700197 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
198 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
199 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
Tejun Heo22b49982006-01-23 21:38:44 +0900200 PORT_CMD_CLO = (1 << 3), /* Command list override */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700201 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
202 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
203 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
204
Tejun Heo0be0aa92006-07-26 15:59:26 +0900205 PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700206 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
207 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
208 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
Jeff Garzik4b0060f2005-06-04 00:50:22 -0400209
Tejun Heo417a1a62007-09-23 13:19:55 +0900210 /* hpriv->flags bits */
211 AHCI_HFLAG_NO_NCQ = (1 << 0),
212 AHCI_HFLAG_IGN_IRQ_IF_ERR = (1 << 1), /* ignore IRQ_IF_ERR */
213 AHCI_HFLAG_IGN_SERR_INTERNAL = (1 << 2), /* ignore SERR_INTERNAL */
214 AHCI_HFLAG_32BIT_ONLY = (1 << 3), /* force 32bit */
215 AHCI_HFLAG_MV_PATA = (1 << 4), /* PATA port */
216 AHCI_HFLAG_NO_MSI = (1 << 5), /* no PCI MSI */
Tejun Heo6949b912007-09-23 13:19:55 +0900217 AHCI_HFLAG_NO_PMP = (1 << 6), /* no PMP */
Kristen Carlson Accardi31556592007-10-25 01:33:26 -0400218 AHCI_HFLAG_NO_HOTPLUG = (1 << 7), /* ignore PxSERR.DIAG.N */
Jeff Garzika8785392008-02-28 15:43:48 -0500219 AHCI_HFLAG_SECT255 = (1 << 8), /* max 255 sectors */
Tejun Heoe297d992008-06-10 00:13:04 +0900220 AHCI_HFLAG_YES_NCQ = (1 << 9), /* force NCQ cap on */
Tejun Heo9b10ae82009-05-30 20:50:12 +0900221 AHCI_HFLAG_NO_SUSPEND = (1 << 10), /* don't suspend */
Tejun Heo55946392009-08-04 14:30:08 +0900222 AHCI_HFLAG_SRST_TOUT_IS_OFFLINE = (1 << 11), /* treat SRST timeout as
223 link offline */
Tejun Heo417a1a62007-09-23 13:19:55 +0900224
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +0200225 /* ap->flags bits */
Tejun Heo1188c0d2007-04-23 02:41:05 +0900226
227 AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
228 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
Kristen Carlson Accardi31556592007-10-25 01:33:26 -0400229 ATA_FLAG_ACPI_SATA | ATA_FLAG_AN |
230 ATA_FLAG_IPM,
Tejun Heoc4f77922007-12-06 15:09:43 +0900231
232 ICH_MAP = 0x90, /* ICH MAP register */
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -0700233
Tejun Heod50ce072009-05-12 10:57:41 +0900234 /* em constants */
235 EM_MAX_SLOTS = 8,
236 EM_MAX_RETRY = 5,
237
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -0700238 /* em_ctl bits */
239 EM_CTL_RST = (1 << 9), /* Reset */
240 EM_CTL_TM = (1 << 8), /* Transmit Message */
241 EM_CTL_ALHD = (1 << 26), /* Activity LED */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700242};
243
244struct ahci_cmd_hdr {
Al Viro4ca4e432007-12-30 09:32:22 +0000245 __le32 opts;
246 __le32 status;
247 __le32 tbl_addr;
248 __le32 tbl_addr_hi;
249 __le32 reserved[4];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700250};
251
252struct ahci_sg {
Al Viro4ca4e432007-12-30 09:32:22 +0000253 __le32 addr;
254 __le32 addr_hi;
255 __le32 reserved;
256 __le32 flags_size;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700257};
258
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -0700259struct ahci_em_priv {
260 enum sw_activity blink_policy;
261 struct timer_list timer;
262 unsigned long saved_activity;
263 unsigned long activity;
264 unsigned long led_state;
265};
266
Linus Torvalds1da177e2005-04-16 15:20:36 -0700267struct ahci_host_priv {
Tejun Heo417a1a62007-09-23 13:19:55 +0900268 unsigned int flags; /* AHCI_HFLAG_* */
Tejun Heod447df12007-03-18 22:15:33 +0900269 u32 cap; /* cap to use */
270 u32 port_map; /* port map to use */
271 u32 saved_cap; /* saved initial cap */
272 u32 saved_port_map; /* saved initial port_map */
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -0700273 u32 em_loc; /* enclosure management location */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700274};
275
276struct ahci_port_priv {
Tejun Heo7d50b602007-09-23 13:19:54 +0900277 struct ata_link *active_link;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700278 struct ahci_cmd_hdr *cmd_slot;
279 dma_addr_t cmd_slot_dma;
280 void *cmd_tbl;
281 dma_addr_t cmd_tbl_dma;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700282 void *rx_fis;
283 dma_addr_t rx_fis_dma;
Tejun Heo0291f952007-01-25 19:16:28 +0900284 /* for NCQ spurious interrupt analysis */
Tejun Heo0291f952007-01-25 19:16:28 +0900285 unsigned int ncq_saw_d2h:1;
286 unsigned int ncq_saw_dmas:1;
Tejun Heoafb2d552007-02-27 13:24:19 +0900287 unsigned int ncq_saw_sdb:1;
Kristen Carlson Accardia7384922007-08-09 14:23:41 -0700288 u32 intr_mask; /* interrupts to enable */
Tejun Heod50ce072009-05-12 10:57:41 +0900289 /* enclosure management info per PM slot */
290 struct ahci_em_priv em_priv[EM_MAX_SLOTS];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700291};
292
Tejun Heo82ef04f2008-07-31 17:02:40 +0900293static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
294static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400295static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
Tejun Heo9a3d9eb2006-01-23 13:09:36 +0900296static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
Tejun Heo4c9bf4e2008-04-07 22:47:20 +0900297static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700298static int ahci_port_start(struct ata_port *ap);
299static void ahci_port_stop(struct ata_port *ap);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700300static void ahci_qc_prep(struct ata_queued_cmd *qc);
Tejun Heo78cd52d2006-05-15 20:58:29 +0900301static void ahci_freeze(struct ata_port *ap);
302static void ahci_thaw(struct ata_port *ap);
Tejun Heo7d50b602007-09-23 13:19:54 +0900303static void ahci_pmp_attach(struct ata_port *ap);
304static void ahci_pmp_detach(struct ata_port *ap);
Tejun Heoa1efdab2008-03-25 12:22:50 +0900305static int ahci_softreset(struct ata_link *link, unsigned int *class,
306 unsigned long deadline);
Shane Huangbd172432008-06-10 15:52:04 +0800307static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
308 unsigned long deadline);
Tejun Heoa1efdab2008-03-25 12:22:50 +0900309static int ahci_hardreset(struct ata_link *link, unsigned int *class,
310 unsigned long deadline);
311static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
312 unsigned long deadline);
313static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
314 unsigned long deadline);
315static void ahci_postreset(struct ata_link *link, unsigned int *class);
Tejun Heo78cd52d2006-05-15 20:58:29 +0900316static void ahci_error_handler(struct ata_port *ap);
317static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
Jeff Garzikdf69c9c2007-05-26 20:46:51 -0400318static int ahci_port_resume(struct ata_port *ap);
Jeff Garzika8785392008-02-28 15:43:48 -0500319static void ahci_dev_config(struct ata_device *dev);
Jeff Garzikdab632e2007-05-28 08:33:01 -0400320static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
321 u32 opts);
Tejun Heo438ac6d2007-03-02 17:31:26 +0900322#ifdef CONFIG_PM
Tejun Heoc1332872006-07-26 15:59:26 +0900323static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
Tejun Heoc1332872006-07-26 15:59:26 +0900324static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
325static int ahci_pci_device_resume(struct pci_dev *pdev);
Tejun Heo438ac6d2007-03-02 17:31:26 +0900326#endif
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -0700327static ssize_t ahci_activity_show(struct ata_device *dev, char *buf);
328static ssize_t ahci_activity_store(struct ata_device *dev,
329 enum sw_activity val);
330static void ahci_init_sw_activity(struct ata_link *link);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700331
Tony Jonesee959b02008-02-22 00:13:36 +0100332static struct device_attribute *ahci_shost_attrs[] = {
333 &dev_attr_link_power_management_policy,
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -0700334 &dev_attr_em_message_type,
335 &dev_attr_em_message,
336 NULL
337};
338
339static struct device_attribute *ahci_sdev_attrs[] = {
340 &dev_attr_sw_activity,
Elias Oltmanns45fabbb2008-09-21 11:54:08 +0200341 &dev_attr_unload_heads,
Kristen Carlson Accardi31556592007-10-25 01:33:26 -0400342 NULL
343};
344
Jeff Garzik193515d2005-11-07 00:59:37 -0500345static struct scsi_host_template ahci_sht = {
Tejun Heo68d1d072008-03-25 12:22:49 +0900346 ATA_NCQ_SHT(DRV_NAME),
Tejun Heo12fad3f2006-05-15 21:03:55 +0900347 .can_queue = AHCI_MAX_CMDS - 1,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700348 .sg_tablesize = AHCI_MAX_SG,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700349 .dma_boundary = AHCI_DMA_BOUNDARY,
Kristen Carlson Accardi31556592007-10-25 01:33:26 -0400350 .shost_attrs = ahci_shost_attrs,
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -0700351 .sdev_attrs = ahci_sdev_attrs,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700352};
353
Tejun Heo029cfd62008-03-25 12:22:49 +0900354static struct ata_port_operations ahci_ops = {
355 .inherits = &sata_pmp_port_ops,
356
Tejun Heo7d50b602007-09-23 13:19:54 +0900357 .qc_defer = sata_pmp_qc_defer_cmd_switch,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700358 .qc_prep = ahci_qc_prep,
359 .qc_issue = ahci_qc_issue,
Tejun Heo4c9bf4e2008-04-07 22:47:20 +0900360 .qc_fill_rtf = ahci_qc_fill_rtf,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700361
Tejun Heo78cd52d2006-05-15 20:58:29 +0900362 .freeze = ahci_freeze,
363 .thaw = ahci_thaw,
Tejun Heoa1efdab2008-03-25 12:22:50 +0900364 .softreset = ahci_softreset,
365 .hardreset = ahci_hardreset,
366 .postreset = ahci_postreset,
Tejun Heo071f44b2008-04-07 22:47:22 +0900367 .pmp_softreset = ahci_softreset,
Tejun Heo78cd52d2006-05-15 20:58:29 +0900368 .error_handler = ahci_error_handler,
369 .post_internal_cmd = ahci_post_internal_cmd,
Tejun Heo029cfd62008-03-25 12:22:49 +0900370 .dev_config = ahci_dev_config,
Tejun Heo78cd52d2006-05-15 20:58:29 +0900371
Tejun Heo029cfd62008-03-25 12:22:49 +0900372 .scr_read = ahci_scr_read,
373 .scr_write = ahci_scr_write,
Tejun Heo7d50b602007-09-23 13:19:54 +0900374 .pmp_attach = ahci_pmp_attach,
375 .pmp_detach = ahci_pmp_detach,
Tejun Heo7d50b602007-09-23 13:19:54 +0900376
Tejun Heo029cfd62008-03-25 12:22:49 +0900377 .enable_pm = ahci_enable_alpm,
378 .disable_pm = ahci_disable_alpm,
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -0700379 .em_show = ahci_led_show,
380 .em_store = ahci_led_store,
381 .sw_activity_show = ahci_activity_show,
382 .sw_activity_store = ahci_activity_store,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900383#ifdef CONFIG_PM
Tejun Heoc1332872006-07-26 15:59:26 +0900384 .port_suspend = ahci_port_suspend,
385 .port_resume = ahci_port_resume,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900386#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700387 .port_start = ahci_port_start,
388 .port_stop = ahci_port_stop,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700389};
390
Tejun Heo029cfd62008-03-25 12:22:49 +0900391static struct ata_port_operations ahci_vt8251_ops = {
392 .inherits = &ahci_ops,
Tejun Heoa1efdab2008-03-25 12:22:50 +0900393 .hardreset = ahci_vt8251_hardreset,
Tejun Heoad616ff2006-11-01 18:00:24 +0900394};
395
Tejun Heo029cfd62008-03-25 12:22:49 +0900396static struct ata_port_operations ahci_p5wdh_ops = {
397 .inherits = &ahci_ops,
Tejun Heoa1efdab2008-03-25 12:22:50 +0900398 .hardreset = ahci_p5wdh_hardreset,
Tejun Heoedc93052007-10-25 14:59:16 +0900399};
400
Shane Huangbd172432008-06-10 15:52:04 +0800401static struct ata_port_operations ahci_sb600_ops = {
402 .inherits = &ahci_ops,
403 .softreset = ahci_sb600_softreset,
404 .pmp_softreset = ahci_sb600_softreset,
405};
406
Tejun Heo417a1a62007-09-23 13:19:55 +0900407#define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
408
Arjan van de Ven98ac62d2005-11-28 10:06:23 +0100409static const struct ata_port_info ahci_port_info[] = {
Jeff Garzik4da646b2009-04-08 02:00:13 -0400410 [board_ahci] =
Linus Torvalds1da177e2005-04-16 15:20:36 -0700411 {
Tejun Heo1188c0d2007-04-23 02:41:05 +0900412 .flags = AHCI_FLAG_COMMON,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100413 .pio_mask = ATA_PIO4,
Jeff Garzik469248a2007-07-08 01:13:16 -0400414 .udma_mask = ATA_UDMA6,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700415 .port_ops = &ahci_ops,
416 },
Jeff Garzik4da646b2009-04-08 02:00:13 -0400417 [board_ahci_vt8251] =
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +0200418 {
Tejun Heo6949b912007-09-23 13:19:55 +0900419 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
Tejun Heo417a1a62007-09-23 13:19:55 +0900420 .flags = AHCI_FLAG_COMMON,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100421 .pio_mask = ATA_PIO4,
Jeff Garzik469248a2007-07-08 01:13:16 -0400422 .udma_mask = ATA_UDMA6,
Tejun Heoad616ff2006-11-01 18:00:24 +0900423 .port_ops = &ahci_vt8251_ops,
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +0200424 },
Jeff Garzik4da646b2009-04-08 02:00:13 -0400425 [board_ahci_ign_iferr] =
Tejun Heo41669552006-11-29 11:33:14 +0900426 {
Tejun Heo417a1a62007-09-23 13:19:55 +0900427 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
428 .flags = AHCI_FLAG_COMMON,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100429 .pio_mask = ATA_PIO4,
Jeff Garzik469248a2007-07-08 01:13:16 -0400430 .udma_mask = ATA_UDMA6,
Tejun Heo41669552006-11-29 11:33:14 +0900431 .port_ops = &ahci_ops,
432 },
Jeff Garzik4da646b2009-04-08 02:00:13 -0400433 [board_ahci_sb600] =
Conke Hu55a61602007-03-27 18:33:05 +0800434 {
Tejun Heo417a1a62007-09-23 13:19:55 +0900435 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
Shane Huang58a09b32009-05-27 15:04:43 +0800436 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255),
Tejun Heo417a1a62007-09-23 13:19:55 +0900437 .flags = AHCI_FLAG_COMMON,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100438 .pio_mask = ATA_PIO4,
Jeff Garzik469248a2007-07-08 01:13:16 -0400439 .udma_mask = ATA_UDMA6,
Shane Huangbd172432008-06-10 15:52:04 +0800440 .port_ops = &ahci_sb600_ops,
Conke Hu55a61602007-03-27 18:33:05 +0800441 },
Jeff Garzik4da646b2009-04-08 02:00:13 -0400442 [board_ahci_mv] =
Jeff Garzikcd70c262007-07-08 02:29:42 -0400443 {
Tejun Heo417a1a62007-09-23 13:19:55 +0900444 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
Tejun Heo17248462008-08-29 16:03:59 +0200445 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
Jeff Garzikcd70c262007-07-08 02:29:42 -0400446 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
Tejun Heo417a1a62007-09-23 13:19:55 +0900447 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100448 .pio_mask = ATA_PIO4,
Jeff Garzikcd70c262007-07-08 02:29:42 -0400449 .udma_mask = ATA_UDMA6,
450 .port_ops = &ahci_ops,
451 },
Jeff Garzik4da646b2009-04-08 02:00:13 -0400452 [board_ahci_sb700] = /* for SB700 and SB800 */
Shane Huange39fc8c2008-02-22 05:00:31 -0800453 {
Shane Huangbd172432008-06-10 15:52:04 +0800454 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
Shane Huange39fc8c2008-02-22 05:00:31 -0800455 .flags = AHCI_FLAG_COMMON,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100456 .pio_mask = ATA_PIO4,
Shane Huange39fc8c2008-02-22 05:00:31 -0800457 .udma_mask = ATA_UDMA6,
Shane Huangbd172432008-06-10 15:52:04 +0800458 .port_ops = &ahci_sb600_ops,
Shane Huange39fc8c2008-02-22 05:00:31 -0800459 },
Jeff Garzik4da646b2009-04-08 02:00:13 -0400460 [board_ahci_mcp65] =
Tejun Heoe297d992008-06-10 00:13:04 +0900461 {
462 AHCI_HFLAGS (AHCI_HFLAG_YES_NCQ),
463 .flags = AHCI_FLAG_COMMON,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100464 .pio_mask = ATA_PIO4,
Tejun Heoe297d992008-06-10 00:13:04 +0900465 .udma_mask = ATA_UDMA6,
466 .port_ops = &ahci_ops,
467 },
Jeff Garzik4da646b2009-04-08 02:00:13 -0400468 [board_ahci_nopmp] =
Tejun Heo9a3b1032008-06-18 20:56:58 -0400469 {
470 AHCI_HFLAGS (AHCI_HFLAG_NO_PMP),
471 .flags = AHCI_FLAG_COMMON,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100472 .pio_mask = ATA_PIO4,
Tejun Heo9a3b1032008-06-18 20:56:58 -0400473 .udma_mask = ATA_UDMA6,
474 .port_ops = &ahci_ops,
475 },
Tejun Heoaa431dd2009-04-08 14:25:31 -0700476 /* board_ahci_yesncq */
477 {
478 AHCI_HFLAGS (AHCI_HFLAG_YES_NCQ),
479 .flags = AHCI_FLAG_COMMON,
480 .pio_mask = ATA_PIO4,
481 .udma_mask = ATA_UDMA6,
482 .port_ops = &ahci_ops,
483 },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700484};
485
Jeff Garzik3b7d6972005-11-10 11:04:11 -0500486static const struct pci_device_id ahci_pci_tbl[] = {
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400487 /* Intel */
Jeff Garzik54bb3a942006-09-27 22:20:11 -0400488 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
489 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
490 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
491 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
492 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
Tejun Heo82490c02007-01-23 15:13:39 +0900493 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
Jeff Garzik54bb3a942006-09-27 22:20:11 -0400494 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
495 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
496 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
497 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
Tejun Heo7a234af2007-09-03 12:44:57 +0900498 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
499 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* ICH8 */
500 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
501 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
502 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
503 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
504 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
505 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
506 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
507 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
508 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
509 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
510 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
511 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
512 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
513 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
514 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
Jason Gastond4155e62007-09-20 17:35:00 -0400515 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
516 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
Jason Gaston16ad1ad2008-01-28 17:34:14 -0800517 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
Mark Goodwinb2dde6a2009-06-26 10:44:11 -0500518 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
Jason Gaston16ad1ad2008-01-28 17:34:14 -0800519 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
David Milburnc1f57d92009-07-22 15:15:56 -0500520 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
521 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
Seth Heasleyadcb5302008-08-11 17:03:09 -0700522 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
Seth Heasley8e48b6b2008-08-27 16:47:22 -0700523 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
David Milburnc1f57d92009-07-22 15:15:56 -0500524 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
Seth Heasleyadcb5302008-08-11 17:03:09 -0700525 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
Seth Heasley8e48b6b2008-08-27 16:47:22 -0700526 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
David Milburnc1f57d92009-07-22 15:15:56 -0500527 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400528
Tejun Heoe34bb372007-02-26 20:24:03 +0900529 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
530 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
531 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400532
533 /* ATI */
Conke Huc65ec1c2007-04-11 18:23:14 +0800534 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
Shane Huange39fc8c2008-02-22 05:00:31 -0800535 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
536 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
537 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
538 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
539 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
540 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400541
542 /* VIA */
Jeff Garzik54bb3a942006-09-27 22:20:11 -0400543 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
Tejun Heobf335542007-04-11 17:27:14 +0900544 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400545
546 /* NVIDIA */
Tejun Heoe297d992008-06-10 00:13:04 +0900547 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
548 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
549 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
550 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
551 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
552 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
553 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
554 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
Tejun Heoaa431dd2009-04-08 14:25:31 -0700555 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_yesncq }, /* MCP67 */
556 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_yesncq }, /* MCP67 */
557 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_yesncq }, /* MCP67 */
558 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_yesncq }, /* MCP67 */
559 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_yesncq }, /* MCP67 */
560 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_yesncq }, /* MCP67 */
561 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_yesncq }, /* MCP67 */
562 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_yesncq }, /* MCP67 */
563 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_yesncq }, /* MCP67 */
564 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_yesncq }, /* MCP67 */
565 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_yesncq }, /* MCP67 */
566 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_yesncq }, /* MCP67 */
567 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_yesncq }, /* MCP73 */
568 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_yesncq }, /* MCP73 */
569 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_yesncq }, /* MCP73 */
570 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_yesncq }, /* MCP73 */
571 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_yesncq }, /* MCP73 */
572 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_yesncq }, /* MCP73 */
573 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_yesncq }, /* MCP73 */
574 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_yesncq }, /* MCP73 */
575 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_yesncq }, /* MCP73 */
576 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_yesncq }, /* MCP73 */
577 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_yesncq }, /* MCP73 */
578 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_yesncq }, /* MCP73 */
Peer Chen0522b282007-06-07 18:05:12 +0800579 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci }, /* MCP77 */
580 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci }, /* MCP77 */
581 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci }, /* MCP77 */
582 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci }, /* MCP77 */
583 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci }, /* MCP77 */
584 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci }, /* MCP77 */
585 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci }, /* MCP77 */
586 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci }, /* MCP77 */
587 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci }, /* MCP77 */
588 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci }, /* MCP77 */
589 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci }, /* MCP77 */
590 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci }, /* MCP77 */
peerchen6ba86952007-12-03 22:20:37 +0800591 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci }, /* MCP79 */
592 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci }, /* MCP79 */
593 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci }, /* MCP79 */
594 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci }, /* MCP79 */
Peer Chen71008192007-09-24 10:16:25 +0800595 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci }, /* MCP79 */
596 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci }, /* MCP79 */
597 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci }, /* MCP79 */
598 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci }, /* MCP79 */
599 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci }, /* MCP79 */
600 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci }, /* MCP79 */
601 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci }, /* MCP79 */
602 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci }, /* MCP79 */
peerchen7adbe462009-02-27 16:58:41 +0800603 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci }, /* MCP89 */
604 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci }, /* MCP89 */
605 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci }, /* MCP89 */
606 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci }, /* MCP89 */
607 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci }, /* MCP89 */
608 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci }, /* MCP89 */
609 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci }, /* MCP89 */
610 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci }, /* MCP89 */
611 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci }, /* MCP89 */
612 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci }, /* MCP89 */
613 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci }, /* MCP89 */
614 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci }, /* MCP89 */
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400615
Jeff Garzik95916ed2006-07-29 04:10:14 -0400616 /* SiS */
Tejun Heo20e2de42008-08-01 12:51:43 +0900617 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
618 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
619 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
Jeff Garzik95916ed2006-07-29 04:10:14 -0400620
Jeff Garzikcd70c262007-07-08 02:29:42 -0400621 /* Marvell */
622 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
Jose Alberto Regueroc40e7cb2008-03-13 23:22:24 +0100623 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
Jeff Garzikcd70c262007-07-08 02:29:42 -0400624
Mark Nelsonc77a0362008-10-23 14:08:16 +1100625 /* Promise */
626 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
627
Jeff Garzik415ae2b2006-11-01 05:10:42 -0500628 /* Generic, PCI class code for AHCI */
629 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
Conke Huc9f89472007-01-09 05:32:51 -0500630 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
Jeff Garzik415ae2b2006-11-01 05:10:42 -0500631
Linus Torvalds1da177e2005-04-16 15:20:36 -0700632 { } /* terminate list */
633};
634
635
636static struct pci_driver ahci_pci_driver = {
637 .name = DRV_NAME,
638 .id_table = ahci_pci_tbl,
639 .probe = ahci_init_one,
Tejun Heo24dc5f32007-01-20 16:00:28 +0900640 .remove = ata_pci_remove_one,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900641#ifdef CONFIG_PM
Tejun Heoc1332872006-07-26 15:59:26 +0900642 .suspend = ahci_pci_device_suspend,
643 .resume = ahci_pci_device_resume,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900644#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700645};
646
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -0700647static int ahci_em_messages = 1;
648module_param(ahci_em_messages, int, 0444);
649/* add other LED protocol types when they become supported */
650MODULE_PARM_DESC(ahci_em_messages,
651 "Set AHCI Enclosure Management Message type (0 = disabled, 1 = LED");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700652
Alan Cox5b66c822008-09-03 14:48:34 +0100653#if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
654static int marvell_enable;
655#else
656static int marvell_enable = 1;
657#endif
658module_param(marvell_enable, int, 0644);
659MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
660
661
Tejun Heo98fa4b62006-11-02 12:17:23 +0900662static inline int ahci_nr_ports(u32 cap)
663{
664 return (cap & 0x1f) + 1;
665}
666
Jeff Garzikdab632e2007-05-28 08:33:01 -0400667static inline void __iomem *__ahci_port_base(struct ata_host *host,
668 unsigned int port_no)
669{
670 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
671
672 return mmio + 0x100 + (port_no * 0x80);
673}
674
Tejun Heo4447d352007-04-17 23:44:08 +0900675static inline void __iomem *ahci_port_base(struct ata_port *ap)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700676{
Jeff Garzikdab632e2007-05-28 08:33:01 -0400677 return __ahci_port_base(ap->host, ap->port_no);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700678}
679
Tejun Heob710a1f2008-01-05 23:11:57 +0900680static void ahci_enable_ahci(void __iomem *mmio)
681{
Tejun Heo15fe9822008-04-23 20:52:58 +0900682 int i;
Tejun Heob710a1f2008-01-05 23:11:57 +0900683 u32 tmp;
684
685 /* turn on AHCI_EN */
686 tmp = readl(mmio + HOST_CTL);
Tejun Heo15fe9822008-04-23 20:52:58 +0900687 if (tmp & HOST_AHCI_EN)
688 return;
689
690 /* Some controllers need AHCI_EN to be written multiple times.
691 * Try a few times before giving up.
692 */
693 for (i = 0; i < 5; i++) {
Tejun Heob710a1f2008-01-05 23:11:57 +0900694 tmp |= HOST_AHCI_EN;
695 writel(tmp, mmio + HOST_CTL);
696 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */
Tejun Heo15fe9822008-04-23 20:52:58 +0900697 if (tmp & HOST_AHCI_EN)
698 return;
699 msleep(10);
Tejun Heob710a1f2008-01-05 23:11:57 +0900700 }
Tejun Heo15fe9822008-04-23 20:52:58 +0900701
702 WARN_ON(1);
Tejun Heob710a1f2008-01-05 23:11:57 +0900703}
704
Tejun Heod447df12007-03-18 22:15:33 +0900705/**
706 * ahci_save_initial_config - Save and fixup initial config values
Tejun Heo4447d352007-04-17 23:44:08 +0900707 * @pdev: target PCI device
Tejun Heo4447d352007-04-17 23:44:08 +0900708 * @hpriv: host private area to store config values
Tejun Heod447df12007-03-18 22:15:33 +0900709 *
710 * Some registers containing configuration info might be setup by
711 * BIOS and might be cleared on reset. This function saves the
712 * initial values of those registers into @hpriv such that they
713 * can be restored after controller reset.
714 *
715 * If inconsistent, config values are fixed up by this function.
716 *
717 * LOCKING:
718 * None.
719 */
Tejun Heo4447d352007-04-17 23:44:08 +0900720static void ahci_save_initial_config(struct pci_dev *pdev,
Tejun Heo4447d352007-04-17 23:44:08 +0900721 struct ahci_host_priv *hpriv)
Tejun Heod447df12007-03-18 22:15:33 +0900722{
Tejun Heo4447d352007-04-17 23:44:08 +0900723 void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
Tejun Heod447df12007-03-18 22:15:33 +0900724 u32 cap, port_map;
Tejun Heo17199b12007-03-18 22:26:53 +0900725 int i;
Jose Alberto Regueroc40e7cb2008-03-13 23:22:24 +0100726 int mv;
Tejun Heod447df12007-03-18 22:15:33 +0900727
Tejun Heob710a1f2008-01-05 23:11:57 +0900728 /* make sure AHCI mode is enabled before accessing CAP */
729 ahci_enable_ahci(mmio);
730
Tejun Heod447df12007-03-18 22:15:33 +0900731 /* Values prefixed with saved_ are written back to host after
732 * reset. Values without are used for driver operation.
733 */
734 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
735 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
736
Tejun Heo274c1fd2007-07-16 14:29:40 +0900737 /* some chips have errata preventing 64bit use */
Tejun Heo417a1a62007-09-23 13:19:55 +0900738 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
Tejun Heoc7a42152007-05-18 16:23:19 +0200739 dev_printk(KERN_INFO, &pdev->dev,
740 "controller can't do 64bit DMA, forcing 32bit\n");
741 cap &= ~HOST_CAP_64;
742 }
743
Tejun Heo417a1a62007-09-23 13:19:55 +0900744 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
Tejun Heo274c1fd2007-07-16 14:29:40 +0900745 dev_printk(KERN_INFO, &pdev->dev,
746 "controller can't do NCQ, turning off CAP_NCQ\n");
747 cap &= ~HOST_CAP_NCQ;
748 }
749
Tejun Heoe297d992008-06-10 00:13:04 +0900750 if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) {
751 dev_printk(KERN_INFO, &pdev->dev,
752 "controller can do NCQ, turning on CAP_NCQ\n");
753 cap |= HOST_CAP_NCQ;
754 }
755
Roel Kluin258cd842008-03-09 21:42:40 +0100756 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
Tejun Heo6949b912007-09-23 13:19:55 +0900757 dev_printk(KERN_INFO, &pdev->dev,
758 "controller can't do PMP, turning off CAP_PMP\n");
759 cap &= ~HOST_CAP_PMP;
760 }
761
Tejun Heod799e082008-06-17 12:46:30 +0900762 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361 &&
763 port_map != 1) {
764 dev_printk(KERN_INFO, &pdev->dev,
765 "JMB361 has only one port, port_map 0x%x -> 0x%x\n",
766 port_map, 1);
767 port_map = 1;
768 }
769
Jeff Garzikcd70c262007-07-08 02:29:42 -0400770 /*
771 * Temporary Marvell 6145 hack: PATA port presence
772 * is asserted through the standard AHCI port
773 * presence register, as bit 4 (counting from 0)
774 */
Tejun Heo417a1a62007-09-23 13:19:55 +0900775 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
Jose Alberto Regueroc40e7cb2008-03-13 23:22:24 +0100776 if (pdev->device == 0x6121)
777 mv = 0x3;
778 else
779 mv = 0xf;
Jeff Garzikcd70c262007-07-08 02:29:42 -0400780 dev_printk(KERN_ERR, &pdev->dev,
781 "MV_AHCI HACK: port_map %x -> %x\n",
Jose Alberto Regueroc40e7cb2008-03-13 23:22:24 +0100782 port_map,
783 port_map & mv);
Alan Cox5b66c822008-09-03 14:48:34 +0100784 dev_printk(KERN_ERR, &pdev->dev,
785 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
Jeff Garzikcd70c262007-07-08 02:29:42 -0400786
Jose Alberto Regueroc40e7cb2008-03-13 23:22:24 +0100787 port_map &= mv;
Jeff Garzikcd70c262007-07-08 02:29:42 -0400788 }
789
Tejun Heo17199b12007-03-18 22:26:53 +0900790 /* cross check port_map and cap.n_ports */
Tejun Heo7a234af2007-09-03 12:44:57 +0900791 if (port_map) {
Tejun Heo837f5f82008-02-06 15:13:51 +0900792 int map_ports = 0;
Tejun Heo17199b12007-03-18 22:26:53 +0900793
Tejun Heo837f5f82008-02-06 15:13:51 +0900794 for (i = 0; i < AHCI_MAX_PORTS; i++)
795 if (port_map & (1 << i))
796 map_ports++;
Tejun Heo17199b12007-03-18 22:26:53 +0900797
Tejun Heo837f5f82008-02-06 15:13:51 +0900798 /* If PI has more ports than n_ports, whine, clear
799 * port_map and let it be generated from n_ports.
Tejun Heo17199b12007-03-18 22:26:53 +0900800 */
Tejun Heo837f5f82008-02-06 15:13:51 +0900801 if (map_ports > ahci_nr_ports(cap)) {
Tejun Heo4447d352007-04-17 23:44:08 +0900802 dev_printk(KERN_WARNING, &pdev->dev,
Tejun Heo837f5f82008-02-06 15:13:51 +0900803 "implemented port map (0x%x) contains more "
804 "ports than nr_ports (%u), using nr_ports\n",
805 port_map, ahci_nr_ports(cap));
Tejun Heo7a234af2007-09-03 12:44:57 +0900806 port_map = 0;
807 }
808 }
809
810 /* fabricate port_map from cap.nr_ports */
811 if (!port_map) {
Tejun Heo17199b12007-03-18 22:26:53 +0900812 port_map = (1 << ahci_nr_ports(cap)) - 1;
Tejun Heo7a234af2007-09-03 12:44:57 +0900813 dev_printk(KERN_WARNING, &pdev->dev,
814 "forcing PORTS_IMPL to 0x%x\n", port_map);
815
816 /* write the fixed up value to the PI register */
817 hpriv->saved_port_map = port_map;
Tejun Heo17199b12007-03-18 22:26:53 +0900818 }
819
Tejun Heod447df12007-03-18 22:15:33 +0900820 /* record values to use during operation */
821 hpriv->cap = cap;
822 hpriv->port_map = port_map;
823}
824
825/**
826 * ahci_restore_initial_config - Restore initial config
Tejun Heo4447d352007-04-17 23:44:08 +0900827 * @host: target ATA host
Tejun Heod447df12007-03-18 22:15:33 +0900828 *
829 * Restore initial config stored by ahci_save_initial_config().
830 *
831 * LOCKING:
832 * None.
833 */
Tejun Heo4447d352007-04-17 23:44:08 +0900834static void ahci_restore_initial_config(struct ata_host *host)
Tejun Heod447df12007-03-18 22:15:33 +0900835{
Tejun Heo4447d352007-04-17 23:44:08 +0900836 struct ahci_host_priv *hpriv = host->private_data;
837 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
838
Tejun Heod447df12007-03-18 22:15:33 +0900839 writel(hpriv->saved_cap, mmio + HOST_CAP);
840 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
841 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
842}
843
Tejun Heo203ef6c2007-07-16 14:29:40 +0900844static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700845{
Tejun Heo203ef6c2007-07-16 14:29:40 +0900846 static const int offset[] = {
847 [SCR_STATUS] = PORT_SCR_STAT,
848 [SCR_CONTROL] = PORT_SCR_CTL,
849 [SCR_ERROR] = PORT_SCR_ERR,
850 [SCR_ACTIVE] = PORT_SCR_ACT,
851 [SCR_NOTIFICATION] = PORT_SCR_NTF,
852 };
853 struct ahci_host_priv *hpriv = ap->host->private_data;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700854
Tejun Heo203ef6c2007-07-16 14:29:40 +0900855 if (sc_reg < ARRAY_SIZE(offset) &&
856 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
857 return offset[sc_reg];
Tejun Heoda3dbb12007-07-16 14:29:40 +0900858 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700859}
860
Tejun Heo82ef04f2008-07-31 17:02:40 +0900861static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700862{
Tejun Heo82ef04f2008-07-31 17:02:40 +0900863 void __iomem *port_mmio = ahci_port_base(link->ap);
864 int offset = ahci_scr_offset(link->ap, sc_reg);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700865
Tejun Heo203ef6c2007-07-16 14:29:40 +0900866 if (offset) {
867 *val = readl(port_mmio + offset);
868 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700869 }
Tejun Heo203ef6c2007-07-16 14:29:40 +0900870 return -EINVAL;
871}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700872
Tejun Heo82ef04f2008-07-31 17:02:40 +0900873static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
Tejun Heo203ef6c2007-07-16 14:29:40 +0900874{
Tejun Heo82ef04f2008-07-31 17:02:40 +0900875 void __iomem *port_mmio = ahci_port_base(link->ap);
876 int offset = ahci_scr_offset(link->ap, sc_reg);
Tejun Heo203ef6c2007-07-16 14:29:40 +0900877
878 if (offset) {
879 writel(val, port_mmio + offset);
880 return 0;
881 }
882 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700883}
884
Tejun Heo4447d352007-04-17 23:44:08 +0900885static void ahci_start_engine(struct ata_port *ap)
Tejun Heo7c76d1e2005-12-19 22:36:34 +0900886{
Tejun Heo4447d352007-04-17 23:44:08 +0900887 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo7c76d1e2005-12-19 22:36:34 +0900888 u32 tmp;
889
Tejun Heod8fcd112006-07-26 15:59:25 +0900890 /* start DMA */
Tejun Heo9f592052006-07-26 15:59:26 +0900891 tmp = readl(port_mmio + PORT_CMD);
Tejun Heo7c76d1e2005-12-19 22:36:34 +0900892 tmp |= PORT_CMD_START;
893 writel(tmp, port_mmio + PORT_CMD);
894 readl(port_mmio + PORT_CMD); /* flush */
895}
896
Tejun Heo4447d352007-04-17 23:44:08 +0900897static int ahci_stop_engine(struct ata_port *ap)
Tejun Heo254950c2006-07-26 15:59:25 +0900898{
Tejun Heo4447d352007-04-17 23:44:08 +0900899 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo254950c2006-07-26 15:59:25 +0900900 u32 tmp;
901
902 tmp = readl(port_mmio + PORT_CMD);
903
Tejun Heod8fcd112006-07-26 15:59:25 +0900904 /* check if the HBA is idle */
Tejun Heo254950c2006-07-26 15:59:25 +0900905 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
906 return 0;
907
Tejun Heod8fcd112006-07-26 15:59:25 +0900908 /* setting HBA to idle */
Tejun Heo254950c2006-07-26 15:59:25 +0900909 tmp &= ~PORT_CMD_START;
910 writel(tmp, port_mmio + PORT_CMD);
911
Tejun Heod8fcd112006-07-26 15:59:25 +0900912 /* wait for engine to stop. This could be as long as 500 msec */
Tejun Heo254950c2006-07-26 15:59:25 +0900913 tmp = ata_wait_register(port_mmio + PORT_CMD,
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400914 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
Tejun Heod8fcd112006-07-26 15:59:25 +0900915 if (tmp & PORT_CMD_LIST_ON)
Tejun Heo254950c2006-07-26 15:59:25 +0900916 return -EIO;
917
918 return 0;
919}
920
Tejun Heo4447d352007-04-17 23:44:08 +0900921static void ahci_start_fis_rx(struct ata_port *ap)
Tejun Heo0be0aa92006-07-26 15:59:26 +0900922{
Tejun Heo4447d352007-04-17 23:44:08 +0900923 void __iomem *port_mmio = ahci_port_base(ap);
924 struct ahci_host_priv *hpriv = ap->host->private_data;
925 struct ahci_port_priv *pp = ap->private_data;
Tejun Heo0be0aa92006-07-26 15:59:26 +0900926 u32 tmp;
927
928 /* set FIS registers */
Tejun Heo4447d352007-04-17 23:44:08 +0900929 if (hpriv->cap & HOST_CAP_64)
930 writel((pp->cmd_slot_dma >> 16) >> 16,
931 port_mmio + PORT_LST_ADDR_HI);
932 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
Tejun Heo0be0aa92006-07-26 15:59:26 +0900933
Tejun Heo4447d352007-04-17 23:44:08 +0900934 if (hpriv->cap & HOST_CAP_64)
935 writel((pp->rx_fis_dma >> 16) >> 16,
936 port_mmio + PORT_FIS_ADDR_HI);
937 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
Tejun Heo0be0aa92006-07-26 15:59:26 +0900938
939 /* enable FIS reception */
940 tmp = readl(port_mmio + PORT_CMD);
941 tmp |= PORT_CMD_FIS_RX;
942 writel(tmp, port_mmio + PORT_CMD);
943
944 /* flush */
945 readl(port_mmio + PORT_CMD);
946}
947
Tejun Heo4447d352007-04-17 23:44:08 +0900948static int ahci_stop_fis_rx(struct ata_port *ap)
Tejun Heo0be0aa92006-07-26 15:59:26 +0900949{
Tejun Heo4447d352007-04-17 23:44:08 +0900950 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo0be0aa92006-07-26 15:59:26 +0900951 u32 tmp;
952
953 /* disable FIS reception */
954 tmp = readl(port_mmio + PORT_CMD);
955 tmp &= ~PORT_CMD_FIS_RX;
956 writel(tmp, port_mmio + PORT_CMD);
957
958 /* wait for completion, spec says 500ms, give it 1000 */
959 tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
960 PORT_CMD_FIS_ON, 10, 1000);
961 if (tmp & PORT_CMD_FIS_ON)
962 return -EBUSY;
963
964 return 0;
965}
966
Tejun Heo4447d352007-04-17 23:44:08 +0900967static void ahci_power_up(struct ata_port *ap)
Tejun Heo0be0aa92006-07-26 15:59:26 +0900968{
Tejun Heo4447d352007-04-17 23:44:08 +0900969 struct ahci_host_priv *hpriv = ap->host->private_data;
970 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo0be0aa92006-07-26 15:59:26 +0900971 u32 cmd;
972
973 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
974
975 /* spin up device */
Tejun Heo4447d352007-04-17 23:44:08 +0900976 if (hpriv->cap & HOST_CAP_SSS) {
Tejun Heo0be0aa92006-07-26 15:59:26 +0900977 cmd |= PORT_CMD_SPIN_UP;
978 writel(cmd, port_mmio + PORT_CMD);
979 }
980
981 /* wake up link */
982 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
983}
984
Kristen Carlson Accardi31556592007-10-25 01:33:26 -0400985static void ahci_disable_alpm(struct ata_port *ap)
986{
987 struct ahci_host_priv *hpriv = ap->host->private_data;
988 void __iomem *port_mmio = ahci_port_base(ap);
989 u32 cmd;
990 struct ahci_port_priv *pp = ap->private_data;
991
992 /* IPM bits should be disabled by libata-core */
993 /* get the existing command bits */
994 cmd = readl(port_mmio + PORT_CMD);
995
996 /* disable ALPM and ASP */
997 cmd &= ~PORT_CMD_ASP;
998 cmd &= ~PORT_CMD_ALPE;
999
1000 /* force the interface back to active */
1001 cmd |= PORT_CMD_ICC_ACTIVE;
1002
1003 /* write out new cmd value */
1004 writel(cmd, port_mmio + PORT_CMD);
1005 cmd = readl(port_mmio + PORT_CMD);
1006
1007 /* wait 10ms to be sure we've come out of any low power state */
1008 msleep(10);
1009
1010 /* clear out any PhyRdy stuff from interrupt status */
1011 writel(PORT_IRQ_PHYRDY, port_mmio + PORT_IRQ_STAT);
1012
1013 /* go ahead and clean out PhyRdy Change from Serror too */
Tejun Heo82ef04f2008-07-31 17:02:40 +09001014 ahci_scr_write(&ap->link, SCR_ERROR, ((1 << 16) | (1 << 18)));
Kristen Carlson Accardi31556592007-10-25 01:33:26 -04001015
1016 /*
1017 * Clear flag to indicate that we should ignore all PhyRdy
1018 * state changes
1019 */
1020 hpriv->flags &= ~AHCI_HFLAG_NO_HOTPLUG;
1021
1022 /*
1023 * Enable interrupts on Phy Ready.
1024 */
1025 pp->intr_mask |= PORT_IRQ_PHYRDY;
1026 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1027
1028 /*
1029 * don't change the link pm policy - we can be called
1030 * just to turn of link pm temporarily
1031 */
1032}
1033
1034static int ahci_enable_alpm(struct ata_port *ap,
1035 enum link_pm policy)
1036{
1037 struct ahci_host_priv *hpriv = ap->host->private_data;
1038 void __iomem *port_mmio = ahci_port_base(ap);
1039 u32 cmd;
1040 struct ahci_port_priv *pp = ap->private_data;
1041 u32 asp;
1042
1043 /* Make sure the host is capable of link power management */
1044 if (!(hpriv->cap & HOST_CAP_ALPM))
1045 return -EINVAL;
1046
1047 switch (policy) {
1048 case MAX_PERFORMANCE:
1049 case NOT_AVAILABLE:
1050 /*
1051 * if we came here with NOT_AVAILABLE,
1052 * it just means this is the first time we
1053 * have tried to enable - default to max performance,
1054 * and let the user go to lower power modes on request.
1055 */
1056 ahci_disable_alpm(ap);
1057 return 0;
1058 case MIN_POWER:
1059 /* configure HBA to enter SLUMBER */
1060 asp = PORT_CMD_ASP;
1061 break;
1062 case MEDIUM_POWER:
1063 /* configure HBA to enter PARTIAL */
1064 asp = 0;
1065 break;
1066 default:
1067 return -EINVAL;
1068 }
1069
1070 /*
1071 * Disable interrupts on Phy Ready. This keeps us from
1072 * getting woken up due to spurious phy ready interrupts
1073 * TBD - Hot plug should be done via polling now, is
1074 * that even supported?
1075 */
1076 pp->intr_mask &= ~PORT_IRQ_PHYRDY;
1077 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1078
1079 /*
1080 * Set a flag to indicate that we should ignore all PhyRdy
1081 * state changes since these can happen now whenever we
1082 * change link state
1083 */
1084 hpriv->flags |= AHCI_HFLAG_NO_HOTPLUG;
1085
1086 /* get the existing command bits */
1087 cmd = readl(port_mmio + PORT_CMD);
1088
1089 /*
1090 * Set ASP based on Policy
1091 */
1092 cmd |= asp;
1093
1094 /*
1095 * Setting this bit will instruct the HBA to aggressively
1096 * enter a lower power link state when it's appropriate and
1097 * based on the value set above for ASP
1098 */
1099 cmd |= PORT_CMD_ALPE;
1100
1101 /* write out new cmd value */
1102 writel(cmd, port_mmio + PORT_CMD);
1103 cmd = readl(port_mmio + PORT_CMD);
1104
1105 /* IPM bits should be set by libata-core */
1106 return 0;
1107}
1108
Tejun Heo438ac6d2007-03-02 17:31:26 +09001109#ifdef CONFIG_PM
Tejun Heo4447d352007-04-17 23:44:08 +09001110static void ahci_power_down(struct ata_port *ap)
Tejun Heo0be0aa92006-07-26 15:59:26 +09001111{
Tejun Heo4447d352007-04-17 23:44:08 +09001112 struct ahci_host_priv *hpriv = ap->host->private_data;
1113 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo0be0aa92006-07-26 15:59:26 +09001114 u32 cmd, scontrol;
1115
Tejun Heo4447d352007-04-17 23:44:08 +09001116 if (!(hpriv->cap & HOST_CAP_SSS))
Tejun Heo07c53da2007-01-21 02:10:11 +09001117 return;
1118
1119 /* put device into listen mode, first set PxSCTL.DET to 0 */
1120 scontrol = readl(port_mmio + PORT_SCR_CTL);
1121 scontrol &= ~0xf;
1122 writel(scontrol, port_mmio + PORT_SCR_CTL);
1123
1124 /* then set PxCMD.SUD to 0 */
Tejun Heo0be0aa92006-07-26 15:59:26 +09001125 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
Tejun Heo07c53da2007-01-21 02:10:11 +09001126 cmd &= ~PORT_CMD_SPIN_UP;
1127 writel(cmd, port_mmio + PORT_CMD);
Tejun Heo0be0aa92006-07-26 15:59:26 +09001128}
Tejun Heo438ac6d2007-03-02 17:31:26 +09001129#endif
Tejun Heo0be0aa92006-07-26 15:59:26 +09001130
Jeff Garzikdf69c9c2007-05-26 20:46:51 -04001131static void ahci_start_port(struct ata_port *ap)
Tejun Heo0be0aa92006-07-26 15:59:26 +09001132{
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001133 struct ahci_port_priv *pp = ap->private_data;
1134 struct ata_link *link;
1135 struct ahci_em_priv *emp;
David Milburn4c1e9aa2009-04-03 15:36:41 -05001136 ssize_t rc;
1137 int i;
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001138
Tejun Heo0be0aa92006-07-26 15:59:26 +09001139 /* enable FIS reception */
Tejun Heo4447d352007-04-17 23:44:08 +09001140 ahci_start_fis_rx(ap);
Tejun Heo0be0aa92006-07-26 15:59:26 +09001141
1142 /* enable DMA */
Tejun Heo4447d352007-04-17 23:44:08 +09001143 ahci_start_engine(ap);
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001144
1145 /* turn on LEDs */
1146 if (ap->flags & ATA_FLAG_EM) {
Tejun Heo1eca4362008-11-03 20:03:17 +09001147 ata_for_each_link(link, ap, EDGE) {
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001148 emp = &pp->em_priv[link->pmp];
David Milburn4c1e9aa2009-04-03 15:36:41 -05001149
1150 /* EM Transmit bit maybe busy during init */
Tejun Heod50ce072009-05-12 10:57:41 +09001151 for (i = 0; i < EM_MAX_RETRY; i++) {
David Milburn4c1e9aa2009-04-03 15:36:41 -05001152 rc = ahci_transmit_led_message(ap,
1153 emp->led_state,
1154 4);
1155 if (rc == -EBUSY)
Tejun Heod50ce072009-05-12 10:57:41 +09001156 msleep(1);
David Milburn4c1e9aa2009-04-03 15:36:41 -05001157 else
1158 break;
1159 }
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001160 }
1161 }
1162
1163 if (ap->flags & ATA_FLAG_SW_ACTIVITY)
Tejun Heo1eca4362008-11-03 20:03:17 +09001164 ata_for_each_link(link, ap, EDGE)
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001165 ahci_init_sw_activity(link);
1166
Tejun Heo0be0aa92006-07-26 15:59:26 +09001167}
1168
Tejun Heo4447d352007-04-17 23:44:08 +09001169static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
Tejun Heo0be0aa92006-07-26 15:59:26 +09001170{
1171 int rc;
1172
1173 /* disable DMA */
Tejun Heo4447d352007-04-17 23:44:08 +09001174 rc = ahci_stop_engine(ap);
Tejun Heo0be0aa92006-07-26 15:59:26 +09001175 if (rc) {
1176 *emsg = "failed to stop engine";
1177 return rc;
1178 }
1179
1180 /* disable FIS reception */
Tejun Heo4447d352007-04-17 23:44:08 +09001181 rc = ahci_stop_fis_rx(ap);
Tejun Heo0be0aa92006-07-26 15:59:26 +09001182 if (rc) {
1183 *emsg = "failed stop FIS RX";
1184 return rc;
1185 }
1186
Tejun Heo0be0aa92006-07-26 15:59:26 +09001187 return 0;
1188}
1189
Tejun Heo4447d352007-04-17 23:44:08 +09001190static int ahci_reset_controller(struct ata_host *host)
Tejun Heod91542c2006-07-26 15:59:26 +09001191{
Tejun Heo4447d352007-04-17 23:44:08 +09001192 struct pci_dev *pdev = to_pci_dev(host->dev);
Tejun Heo49f29092007-11-19 16:03:44 +09001193 struct ahci_host_priv *hpriv = host->private_data;
Tejun Heo4447d352007-04-17 23:44:08 +09001194 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
Tejun Heod447df12007-03-18 22:15:33 +09001195 u32 tmp;
Tejun Heod91542c2006-07-26 15:59:26 +09001196
Jeff Garzik3cc3eb12007-09-26 00:02:41 -04001197 /* we must be in AHCI mode, before using anything
1198 * AHCI-specific, such as HOST_RESET.
1199 */
Tejun Heob710a1f2008-01-05 23:11:57 +09001200 ahci_enable_ahci(mmio);
Jeff Garzik3cc3eb12007-09-26 00:02:41 -04001201
1202 /* global controller reset */
Tejun Heoa22e6442008-03-10 10:25:25 +09001203 if (!ahci_skip_host_reset) {
1204 tmp = readl(mmio + HOST_CTL);
1205 if ((tmp & HOST_RESET) == 0) {
1206 writel(tmp | HOST_RESET, mmio + HOST_CTL);
1207 readl(mmio + HOST_CTL); /* flush */
1208 }
Tejun Heod91542c2006-07-26 15:59:26 +09001209
Zhang Rui24920c82008-07-04 13:32:17 +08001210 /*
1211 * to perform host reset, OS should set HOST_RESET
1212 * and poll until this bit is read to be "0".
1213 * reset must complete within 1 second, or
Tejun Heoa22e6442008-03-10 10:25:25 +09001214 * the hardware should be considered fried.
1215 */
Zhang Rui24920c82008-07-04 13:32:17 +08001216 tmp = ata_wait_register(mmio + HOST_CTL, HOST_RESET,
1217 HOST_RESET, 10, 1000);
Tejun Heod91542c2006-07-26 15:59:26 +09001218
Tejun Heoa22e6442008-03-10 10:25:25 +09001219 if (tmp & HOST_RESET) {
1220 dev_printk(KERN_ERR, host->dev,
1221 "controller reset failed (0x%x)\n", tmp);
1222 return -EIO;
1223 }
Tejun Heod91542c2006-07-26 15:59:26 +09001224
Tejun Heoa22e6442008-03-10 10:25:25 +09001225 /* turn on AHCI mode */
1226 ahci_enable_ahci(mmio);
Tejun Heo98fa4b62006-11-02 12:17:23 +09001227
Tejun Heoa22e6442008-03-10 10:25:25 +09001228 /* Some registers might be cleared on reset. Restore
1229 * initial values.
1230 */
1231 ahci_restore_initial_config(host);
1232 } else
1233 dev_printk(KERN_INFO, host->dev,
1234 "skipping global host reset\n");
Tejun Heod91542c2006-07-26 15:59:26 +09001235
1236 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
1237 u16 tmp16;
1238
1239 /* configure PCS */
1240 pci_read_config_word(pdev, 0x92, &tmp16);
Tejun Heo49f29092007-11-19 16:03:44 +09001241 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
1242 tmp16 |= hpriv->port_map;
1243 pci_write_config_word(pdev, 0x92, tmp16);
1244 }
Tejun Heod91542c2006-07-26 15:59:26 +09001245 }
1246
1247 return 0;
1248}
1249
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001250static void ahci_sw_activity(struct ata_link *link)
1251{
1252 struct ata_port *ap = link->ap;
1253 struct ahci_port_priv *pp = ap->private_data;
1254 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1255
1256 if (!(link->flags & ATA_LFLAG_SW_ACTIVITY))
1257 return;
1258
1259 emp->activity++;
1260 if (!timer_pending(&emp->timer))
1261 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10));
1262}
1263
1264static void ahci_sw_activity_blink(unsigned long arg)
1265{
1266 struct ata_link *link = (struct ata_link *)arg;
1267 struct ata_port *ap = link->ap;
1268 struct ahci_port_priv *pp = ap->private_data;
1269 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1270 unsigned long led_message = emp->led_state;
1271 u32 activity_led_state;
David Milburneb409632008-10-16 09:26:19 -05001272 unsigned long flags;
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001273
David Milburn87943ac2008-10-13 14:38:36 -05001274 led_message &= EM_MSG_LED_VALUE;
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001275 led_message |= ap->port_no | (link->pmp << 8);
1276
1277 /* check to see if we've had activity. If so,
1278 * toggle state of LED and reset timer. If not,
1279 * turn LED to desired idle state.
1280 */
David Milburneb409632008-10-16 09:26:19 -05001281 spin_lock_irqsave(ap->lock, flags);
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001282 if (emp->saved_activity != emp->activity) {
1283 emp->saved_activity = emp->activity;
1284 /* get the current LED state */
David Milburn87943ac2008-10-13 14:38:36 -05001285 activity_led_state = led_message & EM_MSG_LED_VALUE_ON;
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001286
1287 if (activity_led_state)
1288 activity_led_state = 0;
1289 else
1290 activity_led_state = 1;
1291
1292 /* clear old state */
David Milburn87943ac2008-10-13 14:38:36 -05001293 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001294
1295 /* toggle state */
1296 led_message |= (activity_led_state << 16);
1297 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100));
1298 } else {
1299 /* switch to idle */
David Milburn87943ac2008-10-13 14:38:36 -05001300 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001301 if (emp->blink_policy == BLINK_OFF)
1302 led_message |= (1 << 16);
1303 }
David Milburneb409632008-10-16 09:26:19 -05001304 spin_unlock_irqrestore(ap->lock, flags);
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001305 ahci_transmit_led_message(ap, led_message, 4);
1306}
1307
1308static void ahci_init_sw_activity(struct ata_link *link)
1309{
1310 struct ata_port *ap = link->ap;
1311 struct ahci_port_priv *pp = ap->private_data;
1312 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1313
1314 /* init activity stats, setup timer */
1315 emp->saved_activity = emp->activity = 0;
1316 setup_timer(&emp->timer, ahci_sw_activity_blink, (unsigned long)link);
1317
1318 /* check our blink policy and set flag for link if it's enabled */
1319 if (emp->blink_policy)
1320 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1321}
1322
1323static int ahci_reset_em(struct ata_host *host)
1324{
1325 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1326 u32 em_ctl;
1327
1328 em_ctl = readl(mmio + HOST_EM_CTL);
1329 if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST))
1330 return -EINVAL;
1331
1332 writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL);
1333 return 0;
1334}
1335
1336static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
1337 ssize_t size)
1338{
1339 struct ahci_host_priv *hpriv = ap->host->private_data;
1340 struct ahci_port_priv *pp = ap->private_data;
1341 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
1342 u32 em_ctl;
1343 u32 message[] = {0, 0};
Linus Torvalds93082f02008-07-25 10:56:36 -07001344 unsigned long flags;
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001345 int pmp;
1346 struct ahci_em_priv *emp;
1347
1348 /* get the slot number from the message */
David Milburn87943ac2008-10-13 14:38:36 -05001349 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
Tejun Heod50ce072009-05-12 10:57:41 +09001350 if (pmp < EM_MAX_SLOTS)
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001351 emp = &pp->em_priv[pmp];
1352 else
1353 return -EINVAL;
1354
1355 spin_lock_irqsave(ap->lock, flags);
1356
1357 /*
1358 * if we are still busy transmitting a previous message,
1359 * do not allow
1360 */
1361 em_ctl = readl(mmio + HOST_EM_CTL);
1362 if (em_ctl & EM_CTL_TM) {
1363 spin_unlock_irqrestore(ap->lock, flags);
David Milburn4c1e9aa2009-04-03 15:36:41 -05001364 return -EBUSY;
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001365 }
1366
1367 /*
1368 * create message header - this is all zero except for
1369 * the message size, which is 4 bytes.
1370 */
1371 message[0] |= (4 << 8);
1372
1373 /* ignore 0:4 of byte zero, fill in port info yourself */
David Milburn87943ac2008-10-13 14:38:36 -05001374 message[1] = ((state & ~EM_MSG_LED_HBA_PORT) | ap->port_no);
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001375
1376 /* write message to EM_LOC */
1377 writel(message[0], mmio + hpriv->em_loc);
1378 writel(message[1], mmio + hpriv->em_loc+4);
1379
1380 /* save off new led state for port/slot */
David Milburn208f2a82009-03-20 14:14:23 -05001381 emp->led_state = state;
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001382
1383 /*
1384 * tell hardware to transmit the message
1385 */
1386 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
1387
1388 spin_unlock_irqrestore(ap->lock, flags);
1389 return size;
1390}
1391
1392static ssize_t ahci_led_show(struct ata_port *ap, char *buf)
1393{
1394 struct ahci_port_priv *pp = ap->private_data;
1395 struct ata_link *link;
1396 struct ahci_em_priv *emp;
1397 int rc = 0;
1398
Tejun Heo1eca4362008-11-03 20:03:17 +09001399 ata_for_each_link(link, ap, EDGE) {
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001400 emp = &pp->em_priv[link->pmp];
1401 rc += sprintf(buf, "%lx\n", emp->led_state);
1402 }
1403 return rc;
1404}
1405
1406static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
1407 size_t size)
1408{
1409 int state;
1410 int pmp;
1411 struct ahci_port_priv *pp = ap->private_data;
1412 struct ahci_em_priv *emp;
1413
1414 state = simple_strtoul(buf, NULL, 0);
1415
1416 /* get the slot number from the message */
David Milburn87943ac2008-10-13 14:38:36 -05001417 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
Tejun Heod50ce072009-05-12 10:57:41 +09001418 if (pmp < EM_MAX_SLOTS)
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001419 emp = &pp->em_priv[pmp];
1420 else
1421 return -EINVAL;
1422
1423 /* mask off the activity bits if we are in sw_activity
1424 * mode, user should turn off sw_activity before setting
1425 * activity led through em_message
1426 */
1427 if (emp->blink_policy)
David Milburn87943ac2008-10-13 14:38:36 -05001428 state &= ~EM_MSG_LED_VALUE_ACTIVITY;
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001429
1430 return ahci_transmit_led_message(ap, state, size);
1431}
1432
1433static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val)
1434{
1435 struct ata_link *link = dev->link;
1436 struct ata_port *ap = link->ap;
1437 struct ahci_port_priv *pp = ap->private_data;
1438 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1439 u32 port_led_state = emp->led_state;
1440
1441 /* save the desired Activity LED behavior */
1442 if (val == OFF) {
1443 /* clear LFLAG */
1444 link->flags &= ~(ATA_LFLAG_SW_ACTIVITY);
1445
1446 /* set the LED to OFF */
David Milburn87943ac2008-10-13 14:38:36 -05001447 port_led_state &= EM_MSG_LED_VALUE_OFF;
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001448 port_led_state |= (ap->port_no | (link->pmp << 8));
1449 ahci_transmit_led_message(ap, port_led_state, 4);
1450 } else {
1451 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1452 if (val == BLINK_OFF) {
1453 /* set LED to ON for idle */
David Milburn87943ac2008-10-13 14:38:36 -05001454 port_led_state &= EM_MSG_LED_VALUE_OFF;
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001455 port_led_state |= (ap->port_no | (link->pmp << 8));
David Milburn87943ac2008-10-13 14:38:36 -05001456 port_led_state |= EM_MSG_LED_VALUE_ON; /* check this */
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001457 ahci_transmit_led_message(ap, port_led_state, 4);
1458 }
1459 }
1460 emp->blink_policy = val;
1461 return 0;
1462}
1463
1464static ssize_t ahci_activity_show(struct ata_device *dev, char *buf)
1465{
1466 struct ata_link *link = dev->link;
1467 struct ata_port *ap = link->ap;
1468 struct ahci_port_priv *pp = ap->private_data;
1469 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1470
1471 /* display the saved value of activity behavior for this
1472 * disk.
1473 */
1474 return sprintf(buf, "%d\n", emp->blink_policy);
1475}
1476
Jeff Garzik2bcd8662007-05-28 07:45:27 -04001477static void ahci_port_init(struct pci_dev *pdev, struct ata_port *ap,
1478 int port_no, void __iomem *mmio,
1479 void __iomem *port_mmio)
1480{
1481 const char *emsg = NULL;
1482 int rc;
1483 u32 tmp;
1484
1485 /* make sure port is not active */
1486 rc = ahci_deinit_port(ap, &emsg);
1487 if (rc)
1488 dev_printk(KERN_WARNING, &pdev->dev,
1489 "%s (%d)\n", emsg, rc);
1490
1491 /* clear SError */
1492 tmp = readl(port_mmio + PORT_SCR_ERR);
1493 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1494 writel(tmp, port_mmio + PORT_SCR_ERR);
1495
1496 /* clear port IRQ */
1497 tmp = readl(port_mmio + PORT_IRQ_STAT);
1498 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1499 if (tmp)
1500 writel(tmp, port_mmio + PORT_IRQ_STAT);
1501
1502 writel(1 << port_no, mmio + HOST_IRQ_STAT);
1503}
1504
Tejun Heo4447d352007-04-17 23:44:08 +09001505static void ahci_init_controller(struct ata_host *host)
Tejun Heod91542c2006-07-26 15:59:26 +09001506{
Tejun Heo417a1a62007-09-23 13:19:55 +09001507 struct ahci_host_priv *hpriv = host->private_data;
Tejun Heo4447d352007-04-17 23:44:08 +09001508 struct pci_dev *pdev = to_pci_dev(host->dev);
1509 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
Jeff Garzik2bcd8662007-05-28 07:45:27 -04001510 int i;
Jeff Garzikcd70c262007-07-08 02:29:42 -04001511 void __iomem *port_mmio;
Tejun Heod91542c2006-07-26 15:59:26 +09001512 u32 tmp;
Jose Alberto Regueroc40e7cb2008-03-13 23:22:24 +01001513 int mv;
Tejun Heod91542c2006-07-26 15:59:26 +09001514
Tejun Heo417a1a62007-09-23 13:19:55 +09001515 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
Jose Alberto Regueroc40e7cb2008-03-13 23:22:24 +01001516 if (pdev->device == 0x6121)
1517 mv = 2;
1518 else
1519 mv = 4;
1520 port_mmio = __ahci_port_base(host, mv);
Jeff Garzikcd70c262007-07-08 02:29:42 -04001521
1522 writel(0, port_mmio + PORT_IRQ_MASK);
1523
1524 /* clear port IRQ */
1525 tmp = readl(port_mmio + PORT_IRQ_STAT);
1526 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1527 if (tmp)
1528 writel(tmp, port_mmio + PORT_IRQ_STAT);
1529 }
1530
Tejun Heo4447d352007-04-17 23:44:08 +09001531 for (i = 0; i < host->n_ports; i++) {
1532 struct ata_port *ap = host->ports[i];
Tejun Heod91542c2006-07-26 15:59:26 +09001533
Jeff Garzikcd70c262007-07-08 02:29:42 -04001534 port_mmio = ahci_port_base(ap);
Tejun Heo4447d352007-04-17 23:44:08 +09001535 if (ata_port_is_dummy(ap))
Tejun Heod91542c2006-07-26 15:59:26 +09001536 continue;
Tejun Heod91542c2006-07-26 15:59:26 +09001537
Jeff Garzik2bcd8662007-05-28 07:45:27 -04001538 ahci_port_init(pdev, ap, i, mmio, port_mmio);
Tejun Heod91542c2006-07-26 15:59:26 +09001539 }
1540
1541 tmp = readl(mmio + HOST_CTL);
1542 VPRINTK("HOST_CTL 0x%x\n", tmp);
1543 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1544 tmp = readl(mmio + HOST_CTL);
1545 VPRINTK("HOST_CTL 0x%x\n", tmp);
1546}
1547
Jeff Garzika8785392008-02-28 15:43:48 -05001548static void ahci_dev_config(struct ata_device *dev)
1549{
1550 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;
1551
Jeff Garzik4cde32f2008-03-24 22:40:40 -04001552 if (hpriv->flags & AHCI_HFLAG_SECT255) {
Jeff Garzika8785392008-02-28 15:43:48 -05001553 dev->max_sectors = 255;
Jeff Garzik4cde32f2008-03-24 22:40:40 -04001554 ata_dev_printk(dev, KERN_INFO,
1555 "SB600 AHCI: limiting to 255 sectors per cmd\n");
1556 }
Jeff Garzika8785392008-02-28 15:43:48 -05001557}
1558
Tejun Heo422b7592005-12-19 22:37:17 +09001559static unsigned int ahci_dev_classify(struct ata_port *ap)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001560{
Tejun Heo4447d352007-04-17 23:44:08 +09001561 void __iomem *port_mmio = ahci_port_base(ap);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001562 struct ata_taskfile tf;
Tejun Heo422b7592005-12-19 22:37:17 +09001563 u32 tmp;
1564
1565 tmp = readl(port_mmio + PORT_SIG);
1566 tf.lbah = (tmp >> 24) & 0xff;
1567 tf.lbam = (tmp >> 16) & 0xff;
1568 tf.lbal = (tmp >> 8) & 0xff;
1569 tf.nsect = (tmp) & 0xff;
1570
1571 return ata_dev_classify(&tf);
1572}
1573
Tejun Heo12fad3f2006-05-15 21:03:55 +09001574static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
1575 u32 opts)
Tejun Heocc9278e2006-02-10 17:25:47 +09001576{
Tejun Heo12fad3f2006-05-15 21:03:55 +09001577 dma_addr_t cmd_tbl_dma;
1578
1579 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
1580
1581 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
1582 pp->cmd_slot[tag].status = 0;
1583 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
1584 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
Tejun Heocc9278e2006-02-10 17:25:47 +09001585}
1586
Tejun Heod2e75df2007-07-16 14:29:39 +09001587static int ahci_kick_engine(struct ata_port *ap, int force_restart)
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +02001588{
Tejun Heo350756f2008-04-07 22:47:21 +09001589 void __iomem *port_mmio = ahci_port_base(ap);
Jeff Garzikcca39742006-08-24 03:19:22 -04001590 struct ahci_host_priv *hpriv = ap->host->private_data;
Tejun Heo520d06f2008-04-07 22:47:21 +09001591 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +02001592 u32 tmp;
Tejun Heod2e75df2007-07-16 14:29:39 +09001593 int busy, rc;
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +02001594
Tejun Heod2e75df2007-07-16 14:29:39 +09001595 /* do we need to kick the port? */
Tejun Heo520d06f2008-04-07 22:47:21 +09001596 busy = status & (ATA_BUSY | ATA_DRQ);
Tejun Heod2e75df2007-07-16 14:29:39 +09001597 if (!busy && !force_restart)
1598 return 0;
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +02001599
Tejun Heod2e75df2007-07-16 14:29:39 +09001600 /* stop engine */
1601 rc = ahci_stop_engine(ap);
1602 if (rc)
1603 goto out_restart;
1604
1605 /* need to do CLO? */
1606 if (!busy) {
1607 rc = 0;
1608 goto out_restart;
1609 }
1610
1611 if (!(hpriv->cap & HOST_CAP_CLO)) {
1612 rc = -EOPNOTSUPP;
1613 goto out_restart;
1614 }
1615
1616 /* perform CLO */
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +02001617 tmp = readl(port_mmio + PORT_CMD);
1618 tmp |= PORT_CMD_CLO;
1619 writel(tmp, port_mmio + PORT_CMD);
1620
Tejun Heod2e75df2007-07-16 14:29:39 +09001621 rc = 0;
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +02001622 tmp = ata_wait_register(port_mmio + PORT_CMD,
1623 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1624 if (tmp & PORT_CMD_CLO)
Tejun Heod2e75df2007-07-16 14:29:39 +09001625 rc = -EIO;
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +02001626
Tejun Heod2e75df2007-07-16 14:29:39 +09001627 /* restart engine */
1628 out_restart:
1629 ahci_start_engine(ap);
1630 return rc;
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +02001631}
1632
Tejun Heo91c4a2e2007-07-16 14:29:39 +09001633static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1634 struct ata_taskfile *tf, int is_cmd, u16 flags,
1635 unsigned long timeout_msec)
1636{
1637 const u32 cmd_fis_len = 5; /* five dwords */
1638 struct ahci_port_priv *pp = ap->private_data;
1639 void __iomem *port_mmio = ahci_port_base(ap);
1640 u8 *fis = pp->cmd_tbl;
1641 u32 tmp;
1642
1643 /* prep the command */
1644 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1645 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1646
1647 /* issue & wait */
1648 writel(1, port_mmio + PORT_CMD_ISSUE);
1649
1650 if (timeout_msec) {
1651 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1,
1652 1, timeout_msec);
1653 if (tmp & 0x1) {
1654 ahci_kick_engine(ap, 1);
1655 return -EBUSY;
1656 }
1657 } else
1658 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1659
1660 return 0;
1661}
1662
Shane Huangbd172432008-06-10 15:52:04 +08001663static int ahci_do_softreset(struct ata_link *link, unsigned int *class,
1664 int pmp, unsigned long deadline,
1665 int (*check_ready)(struct ata_link *link))
Tejun Heo4658f792006-03-22 21:07:03 +09001666{
Tejun Heocc0680a2007-08-06 18:36:23 +09001667 struct ata_port *ap = link->ap;
Tejun Heo55946392009-08-04 14:30:08 +09001668 struct ahci_host_priv *hpriv = ap->host->private_data;
Tejun Heo4658f792006-03-22 21:07:03 +09001669 const char *reason = NULL;
Tejun Heo2cbb79e2007-07-16 14:29:38 +09001670 unsigned long now, msecs;
Tejun Heo4658f792006-03-22 21:07:03 +09001671 struct ata_taskfile tf;
Tejun Heo4658f792006-03-22 21:07:03 +09001672 int rc;
1673
1674 DPRINTK("ENTER\n");
1675
1676 /* prepare for SRST (AHCI-1.1 10.4.1) */
Tejun Heod2e75df2007-07-16 14:29:39 +09001677 rc = ahci_kick_engine(ap, 1);
Tejun Heo994056d2007-12-06 15:02:48 +09001678 if (rc && rc != -EOPNOTSUPP)
Tejun Heocc0680a2007-08-06 18:36:23 +09001679 ata_link_printk(link, KERN_WARNING,
Tejun Heo994056d2007-12-06 15:02:48 +09001680 "failed to reset engine (errno=%d)\n", rc);
Tejun Heo4658f792006-03-22 21:07:03 +09001681
Tejun Heocc0680a2007-08-06 18:36:23 +09001682 ata_tf_init(link->device, &tf);
Tejun Heo4658f792006-03-22 21:07:03 +09001683
1684 /* issue the first D2H Register FIS */
Tejun Heo2cbb79e2007-07-16 14:29:38 +09001685 msecs = 0;
1686 now = jiffies;
1687 if (time_after(now, deadline))
1688 msecs = jiffies_to_msecs(deadline - now);
1689
Tejun Heo4658f792006-03-22 21:07:03 +09001690 tf.ctl |= ATA_SRST;
Tejun Heoa9cf5e82007-07-16 14:29:39 +09001691 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
Tejun Heo91c4a2e2007-07-16 14:29:39 +09001692 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
Tejun Heo4658f792006-03-22 21:07:03 +09001693 rc = -EIO;
1694 reason = "1st FIS failed";
1695 goto fail;
1696 }
1697
1698 /* spec says at least 5us, but be generous and sleep for 1ms */
1699 msleep(1);
1700
1701 /* issue the second D2H Register FIS */
Tejun Heo4658f792006-03-22 21:07:03 +09001702 tf.ctl &= ~ATA_SRST;
Tejun Heoa9cf5e82007-07-16 14:29:39 +09001703 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
Tejun Heo4658f792006-03-22 21:07:03 +09001704
Tejun Heo705e76b2008-04-07 22:47:19 +09001705 /* wait for link to become ready */
Shane Huangbd172432008-06-10 15:52:04 +08001706 rc = ata_wait_after_reset(link, deadline, check_ready);
Tejun Heo55946392009-08-04 14:30:08 +09001707 if (rc == -EBUSY && hpriv->flags & AHCI_HFLAG_SRST_TOUT_IS_OFFLINE) {
1708 /*
1709 * Workaround for cases where link online status can't
1710 * be trusted. Treat device readiness timeout as link
1711 * offline.
1712 */
1713 ata_link_printk(link, KERN_INFO,
1714 "device not ready, treating as offline\n");
1715 *class = ATA_DEV_NONE;
1716 } else if (rc) {
1717 /* link occupied, -ENODEV too is an error */
Tejun Heo9b893912007-02-02 16:50:52 +09001718 reason = "device not ready";
1719 goto fail;
Tejun Heo55946392009-08-04 14:30:08 +09001720 } else
1721 *class = ahci_dev_classify(ap);
Tejun Heo4658f792006-03-22 21:07:03 +09001722
1723 DPRINTK("EXIT, class=%u\n", *class);
1724 return 0;
1725
Tejun Heo4658f792006-03-22 21:07:03 +09001726 fail:
Tejun Heocc0680a2007-08-06 18:36:23 +09001727 ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason);
Tejun Heo4658f792006-03-22 21:07:03 +09001728 return rc;
1729}
1730
Shane Huangbd172432008-06-10 15:52:04 +08001731static int ahci_check_ready(struct ata_link *link)
1732{
1733 void __iomem *port_mmio = ahci_port_base(link->ap);
1734 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1735
1736 return ata_check_ready(status);
1737}
1738
1739static int ahci_softreset(struct ata_link *link, unsigned int *class,
1740 unsigned long deadline)
1741{
1742 int pmp = sata_srst_pmp(link);
1743
1744 DPRINTK("ENTER\n");
1745
1746 return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
1747}
1748
1749static int ahci_sb600_check_ready(struct ata_link *link)
1750{
1751 void __iomem *port_mmio = ahci_port_base(link->ap);
1752 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1753 u32 irq_status = readl(port_mmio + PORT_IRQ_STAT);
1754
1755 /*
1756 * There is no need to check TFDATA if BAD PMP is found due to HW bug,
1757 * which can save timeout delay.
1758 */
1759 if (irq_status & PORT_IRQ_BAD_PMP)
1760 return -EIO;
1761
1762 return ata_check_ready(status);
1763}
1764
1765static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
1766 unsigned long deadline)
1767{
1768 struct ata_port *ap = link->ap;
1769 void __iomem *port_mmio = ahci_port_base(ap);
1770 int pmp = sata_srst_pmp(link);
1771 int rc;
1772 u32 irq_sts;
1773
1774 DPRINTK("ENTER\n");
1775
1776 rc = ahci_do_softreset(link, class, pmp, deadline,
1777 ahci_sb600_check_ready);
1778
1779 /*
1780 * Soft reset fails on some ATI chips with IPMS set when PMP
1781 * is enabled but SATA HDD/ODD is connected to SATA port,
1782 * do soft reset again to port 0.
1783 */
1784 if (rc == -EIO) {
1785 irq_sts = readl(port_mmio + PORT_IRQ_STAT);
1786 if (irq_sts & PORT_IRQ_BAD_PMP) {
1787 ata_link_printk(link, KERN_WARNING,
Shane Huangb6931c12009-08-05 10:10:41 +08001788 "applying SB600 PMP SRST workaround "
1789 "and retrying\n");
Shane Huangbd172432008-06-10 15:52:04 +08001790 rc = ahci_do_softreset(link, class, 0, deadline,
1791 ahci_check_ready);
1792 }
1793 }
1794
1795 return rc;
1796}
1797
Tejun Heocc0680a2007-08-06 18:36:23 +09001798static int ahci_hardreset(struct ata_link *link, unsigned int *class,
Tejun Heod4b2bab2007-02-02 16:50:52 +09001799 unsigned long deadline)
Tejun Heo422b7592005-12-19 22:37:17 +09001800{
Tejun Heo9dadd452008-04-07 22:47:19 +09001801 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
Tejun Heocc0680a2007-08-06 18:36:23 +09001802 struct ata_port *ap = link->ap;
Tejun Heo42969712006-05-31 18:28:18 +09001803 struct ahci_port_priv *pp = ap->private_data;
1804 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1805 struct ata_taskfile tf;
Tejun Heo9dadd452008-04-07 22:47:19 +09001806 bool online;
Tejun Heo4bd00f62006-02-11 16:26:02 +09001807 int rc;
1808
1809 DPRINTK("ENTER\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001810
Tejun Heo4447d352007-04-17 23:44:08 +09001811 ahci_stop_engine(ap);
Tejun Heo42969712006-05-31 18:28:18 +09001812
1813 /* clear D2H reception area to properly wait for D2H FIS */
Tejun Heocc0680a2007-08-06 18:36:23 +09001814 ata_tf_init(link->device, &tf);
Tejun Heodfd7a3d2007-01-26 15:37:20 +09001815 tf.command = 0x80;
Tejun Heo99771262007-07-16 14:29:38 +09001816 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
Tejun Heo42969712006-05-31 18:28:18 +09001817
Tejun Heo9dadd452008-04-07 22:47:19 +09001818 rc = sata_link_hardreset(link, timing, deadline, &online,
1819 ahci_check_ready);
Tejun Heo42969712006-05-31 18:28:18 +09001820
Tejun Heo4447d352007-04-17 23:44:08 +09001821 ahci_start_engine(ap);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001822
Tejun Heo9dadd452008-04-07 22:47:19 +09001823 if (online)
Tejun Heo4bd00f62006-02-11 16:26:02 +09001824 *class = ahci_dev_classify(ap);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001825
Tejun Heo4bd00f62006-02-11 16:26:02 +09001826 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1827 return rc;
1828}
1829
Tejun Heocc0680a2007-08-06 18:36:23 +09001830static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
Tejun Heod4b2bab2007-02-02 16:50:52 +09001831 unsigned long deadline)
Tejun Heoad616ff2006-11-01 18:00:24 +09001832{
Tejun Heocc0680a2007-08-06 18:36:23 +09001833 struct ata_port *ap = link->ap;
Tejun Heo9dadd452008-04-07 22:47:19 +09001834 bool online;
Tejun Heoad616ff2006-11-01 18:00:24 +09001835 int rc;
1836
1837 DPRINTK("ENTER\n");
1838
Tejun Heo4447d352007-04-17 23:44:08 +09001839 ahci_stop_engine(ap);
Tejun Heoad616ff2006-11-01 18:00:24 +09001840
Tejun Heocc0680a2007-08-06 18:36:23 +09001841 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
Tejun Heo9dadd452008-04-07 22:47:19 +09001842 deadline, &online, NULL);
Tejun Heoad616ff2006-11-01 18:00:24 +09001843
Tejun Heo4447d352007-04-17 23:44:08 +09001844 ahci_start_engine(ap);
Tejun Heoad616ff2006-11-01 18:00:24 +09001845
1846 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1847
1848 /* vt8251 doesn't clear BSY on signature FIS reception,
1849 * request follow-up softreset.
1850 */
Tejun Heo9dadd452008-04-07 22:47:19 +09001851 return online ? -EAGAIN : rc;
Tejun Heoad616ff2006-11-01 18:00:24 +09001852}
1853
Tejun Heoedc93052007-10-25 14:59:16 +09001854static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
1855 unsigned long deadline)
1856{
1857 struct ata_port *ap = link->ap;
1858 struct ahci_port_priv *pp = ap->private_data;
1859 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1860 struct ata_taskfile tf;
Tejun Heo9dadd452008-04-07 22:47:19 +09001861 bool online;
Tejun Heoedc93052007-10-25 14:59:16 +09001862 int rc;
1863
1864 ahci_stop_engine(ap);
1865
1866 /* clear D2H reception area to properly wait for D2H FIS */
1867 ata_tf_init(link->device, &tf);
1868 tf.command = 0x80;
1869 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1870
1871 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
Tejun Heo9dadd452008-04-07 22:47:19 +09001872 deadline, &online, NULL);
Tejun Heoedc93052007-10-25 14:59:16 +09001873
1874 ahci_start_engine(ap);
1875
Tejun Heoedc93052007-10-25 14:59:16 +09001876 /* The pseudo configuration device on SIMG4726 attached to
1877 * ASUS P5W-DH Deluxe doesn't send signature FIS after
1878 * hardreset if no device is attached to the first downstream
1879 * port && the pseudo device locks up on SRST w/ PMP==0. To
1880 * work around this, wait for !BSY only briefly. If BSY isn't
1881 * cleared, perform CLO and proceed to IDENTIFY (achieved by
1882 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
1883 *
1884 * Wait for two seconds. Devices attached to downstream port
1885 * which can't process the following IDENTIFY after this will
1886 * have to be reset again. For most cases, this should
1887 * suffice while making probing snappish enough.
1888 */
Tejun Heo9dadd452008-04-07 22:47:19 +09001889 if (online) {
1890 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
1891 ahci_check_ready);
1892 if (rc)
1893 ahci_kick_engine(ap, 0);
1894 }
Tejun Heo9dadd452008-04-07 22:47:19 +09001895 return rc;
Tejun Heoedc93052007-10-25 14:59:16 +09001896}
1897
Tejun Heocc0680a2007-08-06 18:36:23 +09001898static void ahci_postreset(struct ata_link *link, unsigned int *class)
Tejun Heo4bd00f62006-02-11 16:26:02 +09001899{
Tejun Heocc0680a2007-08-06 18:36:23 +09001900 struct ata_port *ap = link->ap;
Tejun Heo4447d352007-04-17 23:44:08 +09001901 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo4bd00f62006-02-11 16:26:02 +09001902 u32 new_tmp, tmp;
1903
Tejun Heo203c75b2008-04-07 22:47:18 +09001904 ata_std_postreset(link, class);
Jeff Garzik02eaa662005-11-12 01:32:19 -05001905
1906 /* Make sure port's ATAPI bit is set appropriately */
1907 new_tmp = tmp = readl(port_mmio + PORT_CMD);
Tejun Heo4bd00f62006-02-11 16:26:02 +09001908 if (*class == ATA_DEV_ATAPI)
Jeff Garzik02eaa662005-11-12 01:32:19 -05001909 new_tmp |= PORT_CMD_ATAPI;
1910 else
1911 new_tmp &= ~PORT_CMD_ATAPI;
1912 if (new_tmp != tmp) {
1913 writel(new_tmp, port_mmio + PORT_CMD);
1914 readl(port_mmio + PORT_CMD); /* flush */
1915 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001916}
1917
Tejun Heo12fad3f2006-05-15 21:03:55 +09001918static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001919{
Jeff Garzikcedc9a42005-10-05 07:13:30 -04001920 struct scatterlist *sg;
Tejun Heoff2aeb12007-12-05 16:43:11 +09001921 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1922 unsigned int si;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001923
1924 VPRINTK("ENTER\n");
1925
1926 /*
1927 * Next, the S/G list.
1928 */
Tejun Heoff2aeb12007-12-05 16:43:11 +09001929 for_each_sg(qc->sg, sg, qc->n_elem, si) {
Jeff Garzikcedc9a42005-10-05 07:13:30 -04001930 dma_addr_t addr = sg_dma_address(sg);
1931 u32 sg_len = sg_dma_len(sg);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001932
Tejun Heoff2aeb12007-12-05 16:43:11 +09001933 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
1934 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
1935 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001936 }
Jeff Garzik828d09d2005-11-12 01:27:07 -05001937
Tejun Heoff2aeb12007-12-05 16:43:11 +09001938 return si;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001939}
1940
1941static void ahci_qc_prep(struct ata_queued_cmd *qc)
1942{
Jeff Garzika0ea7322005-06-04 01:13:15 -04001943 struct ata_port *ap = qc->ap;
1944 struct ahci_port_priv *pp = ap->private_data;
Tejun Heo405e66b2007-11-27 19:28:53 +09001945 int is_atapi = ata_is_atapi(qc->tf.protocol);
Tejun Heo12fad3f2006-05-15 21:03:55 +09001946 void *cmd_tbl;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001947 u32 opts;
1948 const u32 cmd_fis_len = 5; /* five dwords */
Jeff Garzik828d09d2005-11-12 01:27:07 -05001949 unsigned int n_elem;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001950
1951 /*
Linus Torvalds1da177e2005-04-16 15:20:36 -07001952 * Fill in command table information. First, the header,
1953 * a SATA Register - Host to Device command FIS.
1954 */
Tejun Heo12fad3f2006-05-15 21:03:55 +09001955 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1956
Tejun Heo7d50b602007-09-23 13:19:54 +09001957 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
Tejun Heocc9278e2006-02-10 17:25:47 +09001958 if (is_atapi) {
Tejun Heo12fad3f2006-05-15 21:03:55 +09001959 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1960 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
Jeff Garzika0ea7322005-06-04 01:13:15 -04001961 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001962
Tejun Heocc9278e2006-02-10 17:25:47 +09001963 n_elem = 0;
1964 if (qc->flags & ATA_QCFLAG_DMAMAP)
Tejun Heo12fad3f2006-05-15 21:03:55 +09001965 n_elem = ahci_fill_sg(qc, cmd_tbl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001966
Tejun Heocc9278e2006-02-10 17:25:47 +09001967 /*
1968 * Fill in command slot information.
1969 */
Tejun Heo7d50b602007-09-23 13:19:54 +09001970 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
Tejun Heocc9278e2006-02-10 17:25:47 +09001971 if (qc->tf.flags & ATA_TFLAG_WRITE)
1972 opts |= AHCI_CMD_WRITE;
1973 if (is_atapi)
Tejun Heo4b10e552006-03-12 11:25:27 +09001974 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
Jeff Garzik828d09d2005-11-12 01:27:07 -05001975
Tejun Heo12fad3f2006-05-15 21:03:55 +09001976 ahci_fill_cmd_slot(pp, qc->tag, opts);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001977}
1978
Tejun Heo78cd52d2006-05-15 20:58:29 +09001979static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001980{
Tejun Heo417a1a62007-09-23 13:19:55 +09001981 struct ahci_host_priv *hpriv = ap->host->private_data;
Tejun Heo78cd52d2006-05-15 20:58:29 +09001982 struct ahci_port_priv *pp = ap->private_data;
Tejun Heo7d50b602007-09-23 13:19:54 +09001983 struct ata_eh_info *host_ehi = &ap->link.eh_info;
1984 struct ata_link *link = NULL;
1985 struct ata_queued_cmd *active_qc;
1986 struct ata_eh_info *active_ehi;
Tejun Heo78cd52d2006-05-15 20:58:29 +09001987 u32 serror;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001988
Tejun Heo7d50b602007-09-23 13:19:54 +09001989 /* determine active link */
Tejun Heo1eca4362008-11-03 20:03:17 +09001990 ata_for_each_link(link, ap, EDGE)
Tejun Heo7d50b602007-09-23 13:19:54 +09001991 if (ata_link_active(link))
1992 break;
1993 if (!link)
1994 link = &ap->link;
1995
1996 active_qc = ata_qc_from_tag(ap, link->active_tag);
1997 active_ehi = &link->eh_info;
1998
1999 /* record irq stat */
2000 ata_ehi_clear_desc(host_ehi);
2001 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
Jeff Garzik9f68a242005-11-15 14:03:47 -05002002
Tejun Heo78cd52d2006-05-15 20:58:29 +09002003 /* AHCI needs SError cleared; otherwise, it might lock up */
Tejun Heo82ef04f2008-07-31 17:02:40 +09002004 ahci_scr_read(&ap->link, SCR_ERROR, &serror);
2005 ahci_scr_write(&ap->link, SCR_ERROR, serror);
Tejun Heo7d50b602007-09-23 13:19:54 +09002006 host_ehi->serror |= serror;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002007
Tejun Heo41669552006-11-29 11:33:14 +09002008 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
Tejun Heo417a1a62007-09-23 13:19:55 +09002009 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
Tejun Heo41669552006-11-29 11:33:14 +09002010 irq_stat &= ~PORT_IRQ_IF_ERR;
2011
Conke Hu55a61602007-03-27 18:33:05 +08002012 if (irq_stat & PORT_IRQ_TF_ERR) {
Tejun Heo7d50b602007-09-23 13:19:54 +09002013 /* If qc is active, charge it; otherwise, the active
2014 * link. There's no active qc on NCQ errors. It will
2015 * be determined by EH by reading log page 10h.
2016 */
2017 if (active_qc)
2018 active_qc->err_mask |= AC_ERR_DEV;
2019 else
2020 active_ehi->err_mask |= AC_ERR_DEV;
2021
Tejun Heo417a1a62007-09-23 13:19:55 +09002022 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
Tejun Heo7d50b602007-09-23 13:19:54 +09002023 host_ehi->serror &= ~SERR_INTERNAL;
Tejun Heo78cd52d2006-05-15 20:58:29 +09002024 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002025
Tejun Heo78cd52d2006-05-15 20:58:29 +09002026 if (irq_stat & PORT_IRQ_UNK_FIS) {
2027 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002028
Tejun Heo7d50b602007-09-23 13:19:54 +09002029 active_ehi->err_mask |= AC_ERR_HSM;
Tejun Heocf480622008-01-24 00:05:14 +09002030 active_ehi->action |= ATA_EH_RESET;
Tejun Heo7d50b602007-09-23 13:19:54 +09002031 ata_ehi_push_desc(active_ehi,
2032 "unknown FIS %08x %08x %08x %08x" ,
Tejun Heo78cd52d2006-05-15 20:58:29 +09002033 unk[0], unk[1], unk[2], unk[3]);
2034 }
Jeff Garzikb8f61532005-08-25 22:01:20 -04002035
Tejun Heo071f44b2008-04-07 22:47:22 +09002036 if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) {
Tejun Heo7d50b602007-09-23 13:19:54 +09002037 active_ehi->err_mask |= AC_ERR_HSM;
Tejun Heocf480622008-01-24 00:05:14 +09002038 active_ehi->action |= ATA_EH_RESET;
Tejun Heo7d50b602007-09-23 13:19:54 +09002039 ata_ehi_push_desc(active_ehi, "incorrect PMP");
2040 }
Tejun Heo78cd52d2006-05-15 20:58:29 +09002041
Tejun Heo7d50b602007-09-23 13:19:54 +09002042 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
2043 host_ehi->err_mask |= AC_ERR_HOST_BUS;
Tejun Heocf480622008-01-24 00:05:14 +09002044 host_ehi->action |= ATA_EH_RESET;
Tejun Heo7d50b602007-09-23 13:19:54 +09002045 ata_ehi_push_desc(host_ehi, "host bus error");
2046 }
2047
2048 if (irq_stat & PORT_IRQ_IF_ERR) {
2049 host_ehi->err_mask |= AC_ERR_ATA_BUS;
Tejun Heocf480622008-01-24 00:05:14 +09002050 host_ehi->action |= ATA_EH_RESET;
Tejun Heo7d50b602007-09-23 13:19:54 +09002051 ata_ehi_push_desc(host_ehi, "interface fatal error");
2052 }
2053
2054 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
2055 ata_ehi_hotplugged(host_ehi);
2056 ata_ehi_push_desc(host_ehi, "%s",
2057 irq_stat & PORT_IRQ_CONNECT ?
2058 "connection status changed" : "PHY RDY changed");
2059 }
2060
2061 /* okay, let's hand over to EH */
Linus Torvalds1da177e2005-04-16 15:20:36 -07002062
Tejun Heo78cd52d2006-05-15 20:58:29 +09002063 if (irq_stat & PORT_IRQ_FREEZE)
2064 ata_port_freeze(ap);
2065 else
2066 ata_port_abort(ap);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002067}
2068
Jeff Garzikdf69c9c2007-05-26 20:46:51 -04002069static void ahci_port_intr(struct ata_port *ap)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002070{
Tejun Heo350756f2008-04-07 22:47:21 +09002071 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo9af5c9c2007-08-06 18:36:22 +09002072 struct ata_eh_info *ehi = &ap->link.eh_info;
Tejun Heo0291f952007-01-25 19:16:28 +09002073 struct ahci_port_priv *pp = ap->private_data;
Tejun Heo5f226c62007-10-09 15:02:23 +09002074 struct ahci_host_priv *hpriv = ap->host->private_data;
Tejun Heob06ce3e2007-10-09 15:06:48 +09002075 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
Tejun Heo12fad3f2006-05-15 21:03:55 +09002076 u32 status, qc_active;
Tejun Heo459ad682007-12-07 12:46:23 +09002077 int rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002078
2079 status = readl(port_mmio + PORT_IRQ_STAT);
2080 writel(status, port_mmio + PORT_IRQ_STAT);
2081
Tejun Heob06ce3e2007-10-09 15:06:48 +09002082 /* ignore BAD_PMP while resetting */
2083 if (unlikely(resetting))
2084 status &= ~PORT_IRQ_BAD_PMP;
2085
Kristen Carlson Accardi31556592007-10-25 01:33:26 -04002086 /* If we are getting PhyRdy, this is
2087 * just a power state change, we should
2088 * clear out this, plus the PhyRdy/Comm
2089 * Wake bits from Serror
2090 */
2091 if ((hpriv->flags & AHCI_HFLAG_NO_HOTPLUG) &&
2092 (status & PORT_IRQ_PHYRDY)) {
2093 status &= ~PORT_IRQ_PHYRDY;
Tejun Heo82ef04f2008-07-31 17:02:40 +09002094 ahci_scr_write(&ap->link, SCR_ERROR, ((1 << 16) | (1 << 18)));
Kristen Carlson Accardi31556592007-10-25 01:33:26 -04002095 }
2096
Tejun Heo78cd52d2006-05-15 20:58:29 +09002097 if (unlikely(status & PORT_IRQ_ERROR)) {
2098 ahci_error_intr(ap, status);
2099 return;
2100 }
2101
Kristen Carlson Accardi2f294962007-08-15 04:11:25 -04002102 if (status & PORT_IRQ_SDB_FIS) {
Tejun Heo5f226c62007-10-09 15:02:23 +09002103 /* If SNotification is available, leave notification
2104 * handling to sata_async_notification(). If not,
2105 * emulate it by snooping SDB FIS RX area.
2106 *
2107 * Snooping FIS RX area is probably cheaper than
2108 * poking SNotification but some constrollers which
2109 * implement SNotification, ICH9 for example, don't
2110 * store AN SDB FIS into receive area.
Kristen Carlson Accardi2f294962007-08-15 04:11:25 -04002111 */
Tejun Heo5f226c62007-10-09 15:02:23 +09002112 if (hpriv->cap & HOST_CAP_SNTF)
Tejun Heo7d77b242007-09-23 13:14:13 +09002113 sata_async_notification(ap);
Tejun Heo5f226c62007-10-09 15:02:23 +09002114 else {
2115 /* If the 'N' bit in word 0 of the FIS is set,
2116 * we just received asynchronous notification.
2117 * Tell libata about it.
2118 */
2119 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
2120 u32 f0 = le32_to_cpu(f[0]);
2121
2122 if (f0 & (1 << 15))
2123 sata_async_notification(ap);
2124 }
Kristen Carlson Accardi2f294962007-08-15 04:11:25 -04002125 }
2126
Tejun Heo7d50b602007-09-23 13:19:54 +09002127 /* pp->active_link is valid iff any command is in flight */
2128 if (ap->qc_active && pp->active_link->sactive)
Tejun Heo12fad3f2006-05-15 21:03:55 +09002129 qc_active = readl(port_mmio + PORT_SCR_ACT);
2130 else
2131 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
2132
Tejun Heo79f97da2008-04-07 22:47:20 +09002133 rc = ata_qc_complete_multiple(ap, qc_active);
Tejun Heob06ce3e2007-10-09 15:06:48 +09002134
Tejun Heo459ad682007-12-07 12:46:23 +09002135 /* while resetting, invalid completions are expected */
2136 if (unlikely(rc < 0 && !resetting)) {
Tejun Heo12fad3f2006-05-15 21:03:55 +09002137 ehi->err_mask |= AC_ERR_HSM;
Tejun Heocf480622008-01-24 00:05:14 +09002138 ehi->action |= ATA_EH_RESET;
Tejun Heo12fad3f2006-05-15 21:03:55 +09002139 ata_port_freeze(ap);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002140 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002141}
2142
David Howells7d12e782006-10-05 14:55:46 +01002143static irqreturn_t ahci_interrupt(int irq, void *dev_instance)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002144{
Jeff Garzikcca39742006-08-24 03:19:22 -04002145 struct ata_host *host = dev_instance;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002146 struct ahci_host_priv *hpriv;
2147 unsigned int i, handled = 0;
Jeff Garzikea6ba102005-08-30 05:18:18 -04002148 void __iomem *mmio;
Tejun Heod28f87a2008-07-05 13:10:50 +09002149 u32 irq_stat, irq_masked;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002150
2151 VPRINTK("ENTER\n");
2152
Jeff Garzikcca39742006-08-24 03:19:22 -04002153 hpriv = host->private_data;
Tejun Heo0d5ff562007-02-01 15:06:36 +09002154 mmio = host->iomap[AHCI_PCI_BAR];
Linus Torvalds1da177e2005-04-16 15:20:36 -07002155
2156 /* sigh. 0xffffffff is a valid return from h/w */
2157 irq_stat = readl(mmio + HOST_IRQ_STAT);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002158 if (!irq_stat)
2159 return IRQ_NONE;
2160
Tejun Heod28f87a2008-07-05 13:10:50 +09002161 irq_masked = irq_stat & hpriv->port_map;
2162
Jeff Garzik2dcb4072007-10-19 06:42:56 -04002163 spin_lock(&host->lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002164
Jeff Garzik2dcb4072007-10-19 06:42:56 -04002165 for (i = 0; i < host->n_ports; i++) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002166 struct ata_port *ap;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002167
Tejun Heod28f87a2008-07-05 13:10:50 +09002168 if (!(irq_masked & (1 << i)))
Jeff Garzik67846b32005-10-05 02:58:32 -04002169 continue;
2170
Jeff Garzikcca39742006-08-24 03:19:22 -04002171 ap = host->ports[i];
Jeff Garzik67846b32005-10-05 02:58:32 -04002172 if (ap) {
Jeff Garzikdf69c9c2007-05-26 20:46:51 -04002173 ahci_port_intr(ap);
Jeff Garzik67846b32005-10-05 02:58:32 -04002174 VPRINTK("port %u\n", i);
2175 } else {
2176 VPRINTK("port %u (no irq)\n", i);
Tejun Heo6971ed12006-03-11 12:47:54 +09002177 if (ata_ratelimit())
Jeff Garzikcca39742006-08-24 03:19:22 -04002178 dev_printk(KERN_WARNING, host->dev,
Jeff Garzika9524a72005-10-30 14:39:11 -05002179 "interrupt on disabled port %u\n", i);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002180 }
Jeff Garzik67846b32005-10-05 02:58:32 -04002181
Linus Torvalds1da177e2005-04-16 15:20:36 -07002182 handled = 1;
2183 }
2184
Tejun Heod28f87a2008-07-05 13:10:50 +09002185 /* HOST_IRQ_STAT behaves as level triggered latch meaning that
2186 * it should be cleared after all the port events are cleared;
2187 * otherwise, it will raise a spurious interrupt after each
2188 * valid one. Please read section 10.6.2 of ahci 1.1 for more
2189 * information.
2190 *
2191 * Also, use the unmasked value to clear interrupt as spurious
2192 * pending event on a dummy port might cause screaming IRQ.
2193 */
Tejun Heoea0c62f2008-06-28 01:49:02 +09002194 writel(irq_stat, mmio + HOST_IRQ_STAT);
2195
Jeff Garzikcca39742006-08-24 03:19:22 -04002196 spin_unlock(&host->lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002197
2198 VPRINTK("EXIT\n");
2199
2200 return IRQ_RETVAL(handled);
2201}
2202
Tejun Heo9a3d9eb2006-01-23 13:09:36 +09002203static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002204{
2205 struct ata_port *ap = qc->ap;
Tejun Heo4447d352007-04-17 23:44:08 +09002206 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo7d50b602007-09-23 13:19:54 +09002207 struct ahci_port_priv *pp = ap->private_data;
2208
2209 /* Keep track of the currently active link. It will be used
2210 * in completion path to determine whether NCQ phase is in
2211 * progress.
2212 */
2213 pp->active_link = qc->dev->link;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002214
Tejun Heo12fad3f2006-05-15 21:03:55 +09002215 if (qc->tf.protocol == ATA_PROT_NCQ)
2216 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
2217 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002218
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07002219 ahci_sw_activity(qc->dev->link);
2220
Linus Torvalds1da177e2005-04-16 15:20:36 -07002221 return 0;
2222}
2223
Tejun Heo4c9bf4e2008-04-07 22:47:20 +09002224static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
2225{
2226 struct ahci_port_priv *pp = qc->ap->private_data;
2227 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
2228
2229 ata_tf_from_fis(d2h_fis, &qc->result_tf);
2230 return true;
2231}
2232
Tejun Heo78cd52d2006-05-15 20:58:29 +09002233static void ahci_freeze(struct ata_port *ap)
2234{
Tejun Heo4447d352007-04-17 23:44:08 +09002235 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo78cd52d2006-05-15 20:58:29 +09002236
2237 /* turn IRQ off */
2238 writel(0, port_mmio + PORT_IRQ_MASK);
2239}
2240
2241static void ahci_thaw(struct ata_port *ap)
2242{
Tejun Heo0d5ff562007-02-01 15:06:36 +09002243 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
Tejun Heo4447d352007-04-17 23:44:08 +09002244 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo78cd52d2006-05-15 20:58:29 +09002245 u32 tmp;
Kristen Carlson Accardia7384922007-08-09 14:23:41 -07002246 struct ahci_port_priv *pp = ap->private_data;
Tejun Heo78cd52d2006-05-15 20:58:29 +09002247
2248 /* clear IRQ */
2249 tmp = readl(port_mmio + PORT_IRQ_STAT);
2250 writel(tmp, port_mmio + PORT_IRQ_STAT);
Tejun Heoa7187282007-01-27 11:04:26 +09002251 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
Tejun Heo78cd52d2006-05-15 20:58:29 +09002252
Tejun Heo1c954a42007-10-09 15:01:37 +09002253 /* turn IRQ back on */
2254 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
Tejun Heo78cd52d2006-05-15 20:58:29 +09002255}
2256
2257static void ahci_error_handler(struct ata_port *ap)
2258{
Tejun Heob51e9e52006-06-29 01:29:30 +09002259 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
Tejun Heo78cd52d2006-05-15 20:58:29 +09002260 /* restart engine */
Tejun Heo4447d352007-04-17 23:44:08 +09002261 ahci_stop_engine(ap);
2262 ahci_start_engine(ap);
Tejun Heo78cd52d2006-05-15 20:58:29 +09002263 }
2264
Tejun Heoa1efdab2008-03-25 12:22:50 +09002265 sata_pmp_error_handler(ap);
Tejun Heoedc93052007-10-25 14:59:16 +09002266}
2267
Tejun Heo78cd52d2006-05-15 20:58:29 +09002268static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
2269{
2270 struct ata_port *ap = qc->ap;
2271
Tejun Heod2e75df2007-07-16 14:29:39 +09002272 /* make DMA engine forget about the failed command */
2273 if (qc->flags & ATA_QCFLAG_FAILED)
2274 ahci_kick_engine(ap, 1);
Tejun Heo78cd52d2006-05-15 20:58:29 +09002275}
2276
Tejun Heo7d50b602007-09-23 13:19:54 +09002277static void ahci_pmp_attach(struct ata_port *ap)
2278{
2279 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo1c954a42007-10-09 15:01:37 +09002280 struct ahci_port_priv *pp = ap->private_data;
Tejun Heo7d50b602007-09-23 13:19:54 +09002281 u32 cmd;
2282
2283 cmd = readl(port_mmio + PORT_CMD);
2284 cmd |= PORT_CMD_PMP;
2285 writel(cmd, port_mmio + PORT_CMD);
Tejun Heo1c954a42007-10-09 15:01:37 +09002286
2287 pp->intr_mask |= PORT_IRQ_BAD_PMP;
2288 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
Tejun Heo7d50b602007-09-23 13:19:54 +09002289}
2290
2291static void ahci_pmp_detach(struct ata_port *ap)
2292{
2293 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo1c954a42007-10-09 15:01:37 +09002294 struct ahci_port_priv *pp = ap->private_data;
Tejun Heo7d50b602007-09-23 13:19:54 +09002295 u32 cmd;
2296
2297 cmd = readl(port_mmio + PORT_CMD);
2298 cmd &= ~PORT_CMD_PMP;
2299 writel(cmd, port_mmio + PORT_CMD);
Tejun Heo1c954a42007-10-09 15:01:37 +09002300
2301 pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
2302 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
Tejun Heo7d50b602007-09-23 13:19:54 +09002303}
2304
Alexey Dobriyan028a2592007-07-17 23:48:48 +04002305static int ahci_port_resume(struct ata_port *ap)
2306{
2307 ahci_power_up(ap);
2308 ahci_start_port(ap);
2309
Tejun Heo071f44b2008-04-07 22:47:22 +09002310 if (sata_pmp_attached(ap))
Tejun Heo7d50b602007-09-23 13:19:54 +09002311 ahci_pmp_attach(ap);
2312 else
2313 ahci_pmp_detach(ap);
2314
Alexey Dobriyan028a2592007-07-17 23:48:48 +04002315 return 0;
2316}
2317
Tejun Heo438ac6d2007-03-02 17:31:26 +09002318#ifdef CONFIG_PM
Tejun Heoc1332872006-07-26 15:59:26 +09002319static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
2320{
Tejun Heoc1332872006-07-26 15:59:26 +09002321 const char *emsg = NULL;
2322 int rc;
2323
Tejun Heo4447d352007-04-17 23:44:08 +09002324 rc = ahci_deinit_port(ap, &emsg);
Tejun Heo8e16f942006-11-20 15:42:36 +09002325 if (rc == 0)
Tejun Heo4447d352007-04-17 23:44:08 +09002326 ahci_power_down(ap);
Tejun Heo8e16f942006-11-20 15:42:36 +09002327 else {
Tejun Heoc1332872006-07-26 15:59:26 +09002328 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
Jeff Garzikdf69c9c2007-05-26 20:46:51 -04002329 ahci_start_port(ap);
Tejun Heoc1332872006-07-26 15:59:26 +09002330 }
2331
2332 return rc;
2333}
2334
Tejun Heoc1332872006-07-26 15:59:26 +09002335static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
2336{
Jeff Garzikcca39742006-08-24 03:19:22 -04002337 struct ata_host *host = dev_get_drvdata(&pdev->dev);
Tejun Heo9b10ae82009-05-30 20:50:12 +09002338 struct ahci_host_priv *hpriv = host->private_data;
Tejun Heo0d5ff562007-02-01 15:06:36 +09002339 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
Tejun Heoc1332872006-07-26 15:59:26 +09002340 u32 ctl;
2341
Tejun Heo9b10ae82009-05-30 20:50:12 +09002342 if (mesg.event & PM_EVENT_SUSPEND &&
2343 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
2344 dev_printk(KERN_ERR, &pdev->dev,
2345 "BIOS update required for suspend/resume\n");
2346 return -EIO;
2347 }
2348
Rafael J. Wysocki3a2d5b72008-02-23 19:13:25 +01002349 if (mesg.event & PM_EVENT_SLEEP) {
Tejun Heoc1332872006-07-26 15:59:26 +09002350 /* AHCI spec rev1.1 section 8.3.3:
2351 * Software must disable interrupts prior to requesting a
2352 * transition of the HBA to D3 state.
2353 */
2354 ctl = readl(mmio + HOST_CTL);
2355 ctl &= ~HOST_IRQ_EN;
2356 writel(ctl, mmio + HOST_CTL);
2357 readl(mmio + HOST_CTL); /* flush */
2358 }
2359
2360 return ata_pci_device_suspend(pdev, mesg);
2361}
2362
2363static int ahci_pci_device_resume(struct pci_dev *pdev)
2364{
Jeff Garzikcca39742006-08-24 03:19:22 -04002365 struct ata_host *host = dev_get_drvdata(&pdev->dev);
Tejun Heoc1332872006-07-26 15:59:26 +09002366 int rc;
2367
Tejun Heo553c4aa2006-12-26 19:39:50 +09002368 rc = ata_pci_device_do_resume(pdev);
2369 if (rc)
2370 return rc;
Tejun Heoc1332872006-07-26 15:59:26 +09002371
2372 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
Tejun Heo4447d352007-04-17 23:44:08 +09002373 rc = ahci_reset_controller(host);
Tejun Heoc1332872006-07-26 15:59:26 +09002374 if (rc)
2375 return rc;
2376
Tejun Heo4447d352007-04-17 23:44:08 +09002377 ahci_init_controller(host);
Tejun Heoc1332872006-07-26 15:59:26 +09002378 }
2379
Jeff Garzikcca39742006-08-24 03:19:22 -04002380 ata_host_resume(host);
Tejun Heoc1332872006-07-26 15:59:26 +09002381
2382 return 0;
2383}
Tejun Heo438ac6d2007-03-02 17:31:26 +09002384#endif
Tejun Heoc1332872006-07-26 15:59:26 +09002385
Tejun Heo254950c2006-07-26 15:59:25 +09002386static int ahci_port_start(struct ata_port *ap)
2387{
Jeff Garzikcca39742006-08-24 03:19:22 -04002388 struct device *dev = ap->host->dev;
Tejun Heo254950c2006-07-26 15:59:25 +09002389 struct ahci_port_priv *pp;
Tejun Heo254950c2006-07-26 15:59:25 +09002390 void *mem;
2391 dma_addr_t mem_dma;
Tejun Heo254950c2006-07-26 15:59:25 +09002392
Tejun Heo24dc5f32007-01-20 16:00:28 +09002393 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
Tejun Heo254950c2006-07-26 15:59:25 +09002394 if (!pp)
2395 return -ENOMEM;
Tejun Heo254950c2006-07-26 15:59:25 +09002396
Tejun Heo24dc5f32007-01-20 16:00:28 +09002397 mem = dmam_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma,
2398 GFP_KERNEL);
2399 if (!mem)
Tejun Heo254950c2006-07-26 15:59:25 +09002400 return -ENOMEM;
Tejun Heo254950c2006-07-26 15:59:25 +09002401 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
2402
2403 /*
2404 * First item in chunk of DMA memory: 32-slot command table,
2405 * 32 bytes each in size
2406 */
2407 pp->cmd_slot = mem;
2408 pp->cmd_slot_dma = mem_dma;
2409
2410 mem += AHCI_CMD_SLOT_SZ;
2411 mem_dma += AHCI_CMD_SLOT_SZ;
2412
2413 /*
2414 * Second item: Received-FIS area
2415 */
2416 pp->rx_fis = mem;
2417 pp->rx_fis_dma = mem_dma;
2418
2419 mem += AHCI_RX_FIS_SZ;
2420 mem_dma += AHCI_RX_FIS_SZ;
2421
2422 /*
2423 * Third item: data area for storing a single command
2424 * and its scatter-gather table
2425 */
2426 pp->cmd_tbl = mem;
2427 pp->cmd_tbl_dma = mem_dma;
2428
Kristen Carlson Accardia7384922007-08-09 14:23:41 -07002429 /*
Jeff Garzik2dcb4072007-10-19 06:42:56 -04002430 * Save off initial list of interrupts to be enabled.
2431 * This could be changed later
2432 */
Kristen Carlson Accardia7384922007-08-09 14:23:41 -07002433 pp->intr_mask = DEF_PORT_IRQ;
2434
Tejun Heo254950c2006-07-26 15:59:25 +09002435 ap->private_data = pp;
2436
Jeff Garzikdf69c9c2007-05-26 20:46:51 -04002437 /* engage engines, captain */
2438 return ahci_port_resume(ap);
Tejun Heo254950c2006-07-26 15:59:25 +09002439}
2440
2441static void ahci_port_stop(struct ata_port *ap)
2442{
Tejun Heo0be0aa92006-07-26 15:59:26 +09002443 const char *emsg = NULL;
2444 int rc;
Tejun Heo254950c2006-07-26 15:59:25 +09002445
Tejun Heo0be0aa92006-07-26 15:59:26 +09002446 /* de-initialize port */
Tejun Heo4447d352007-04-17 23:44:08 +09002447 rc = ahci_deinit_port(ap, &emsg);
Tejun Heo0be0aa92006-07-26 15:59:26 +09002448 if (rc)
2449 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
Tejun Heo254950c2006-07-26 15:59:25 +09002450}
2451
Tejun Heo4447d352007-04-17 23:44:08 +09002452static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002453{
Linus Torvalds1da177e2005-04-16 15:20:36 -07002454 int rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002455
Linus Torvalds1da177e2005-04-16 15:20:36 -07002456 if (using_dac &&
Yang Hongyang6a355282009-04-06 19:01:13 -07002457 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
2458 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
Linus Torvalds1da177e2005-04-16 15:20:36 -07002459 if (rc) {
Yang Hongyang284901a2009-04-06 19:01:15 -07002460 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
Linus Torvalds1da177e2005-04-16 15:20:36 -07002461 if (rc) {
Jeff Garzika9524a72005-10-30 14:39:11 -05002462 dev_printk(KERN_ERR, &pdev->dev,
2463 "64-bit DMA enable failed\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07002464 return rc;
2465 }
2466 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002467 } else {
Yang Hongyang284901a2009-04-06 19:01:15 -07002468 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
Linus Torvalds1da177e2005-04-16 15:20:36 -07002469 if (rc) {
Jeff Garzika9524a72005-10-30 14:39:11 -05002470 dev_printk(KERN_ERR, &pdev->dev,
2471 "32-bit DMA enable failed\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07002472 return rc;
2473 }
Yang Hongyang284901a2009-04-06 19:01:15 -07002474 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
Linus Torvalds1da177e2005-04-16 15:20:36 -07002475 if (rc) {
Jeff Garzika9524a72005-10-30 14:39:11 -05002476 dev_printk(KERN_ERR, &pdev->dev,
2477 "32-bit consistent DMA enable failed\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07002478 return rc;
2479 }
2480 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002481 return 0;
2482}
2483
Tejun Heo4447d352007-04-17 23:44:08 +09002484static void ahci_print_info(struct ata_host *host)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002485{
Tejun Heo4447d352007-04-17 23:44:08 +09002486 struct ahci_host_priv *hpriv = host->private_data;
2487 struct pci_dev *pdev = to_pci_dev(host->dev);
2488 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
Linus Torvalds1da177e2005-04-16 15:20:36 -07002489 u32 vers, cap, impl, speed;
2490 const char *speed_s;
2491 u16 cc;
2492 const char *scc_s;
2493
2494 vers = readl(mmio + HOST_VERSION);
2495 cap = hpriv->cap;
2496 impl = hpriv->port_map;
2497
2498 speed = (cap >> 20) & 0xf;
2499 if (speed == 1)
2500 speed_s = "1.5";
2501 else if (speed == 2)
2502 speed_s = "3";
Shane Huang8522ee22008-12-30 11:00:37 +08002503 else if (speed == 3)
2504 speed_s = "6";
Linus Torvalds1da177e2005-04-16 15:20:36 -07002505 else
2506 speed_s = "?";
2507
2508 pci_read_config_word(pdev, 0x0a, &cc);
Conke Huc9f89472007-01-09 05:32:51 -05002509 if (cc == PCI_CLASS_STORAGE_IDE)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002510 scc_s = "IDE";
Conke Huc9f89472007-01-09 05:32:51 -05002511 else if (cc == PCI_CLASS_STORAGE_SATA)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002512 scc_s = "SATA";
Conke Huc9f89472007-01-09 05:32:51 -05002513 else if (cc == PCI_CLASS_STORAGE_RAID)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002514 scc_s = "RAID";
2515 else
2516 scc_s = "unknown";
2517
Jeff Garzika9524a72005-10-30 14:39:11 -05002518 dev_printk(KERN_INFO, &pdev->dev,
2519 "AHCI %02x%02x.%02x%02x "
Linus Torvalds1da177e2005-04-16 15:20:36 -07002520 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
Jeff Garzik2dcb4072007-10-19 06:42:56 -04002521 ,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002522
Jeff Garzik2dcb4072007-10-19 06:42:56 -04002523 (vers >> 24) & 0xff,
2524 (vers >> 16) & 0xff,
2525 (vers >> 8) & 0xff,
2526 vers & 0xff,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002527
2528 ((cap >> 8) & 0x1f) + 1,
2529 (cap & 0x1f) + 1,
2530 speed_s,
2531 impl,
2532 scc_s);
2533
Jeff Garzika9524a72005-10-30 14:39:11 -05002534 dev_printk(KERN_INFO, &pdev->dev,
2535 "flags: "
Tejun Heo203ef6c2007-07-16 14:29:40 +09002536 "%s%s%s%s%s%s%s"
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07002537 "%s%s%s%s%s%s%s"
2538 "%s\n"
Jeff Garzik2dcb4072007-10-19 06:42:56 -04002539 ,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002540
2541 cap & (1 << 31) ? "64bit " : "",
2542 cap & (1 << 30) ? "ncq " : "",
Tejun Heo203ef6c2007-07-16 14:29:40 +09002543 cap & (1 << 29) ? "sntf " : "",
Linus Torvalds1da177e2005-04-16 15:20:36 -07002544 cap & (1 << 28) ? "ilck " : "",
2545 cap & (1 << 27) ? "stag " : "",
2546 cap & (1 << 26) ? "pm " : "",
2547 cap & (1 << 25) ? "led " : "",
2548
2549 cap & (1 << 24) ? "clo " : "",
2550 cap & (1 << 19) ? "nz " : "",
2551 cap & (1 << 18) ? "only " : "",
2552 cap & (1 << 17) ? "pmp " : "",
2553 cap & (1 << 15) ? "pio " : "",
2554 cap & (1 << 14) ? "slum " : "",
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07002555 cap & (1 << 13) ? "part " : "",
2556 cap & (1 << 6) ? "ems ": ""
Linus Torvalds1da177e2005-04-16 15:20:36 -07002557 );
2558}
2559
Tejun Heoedc93052007-10-25 14:59:16 +09002560/* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
2561 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
2562 * support PMP and the 4726 either directly exports the device
2563 * attached to the first downstream port or acts as a hardware storage
2564 * controller and emulate a single ATA device (can be RAID 0/1 or some
2565 * other configuration).
2566 *
2567 * When there's no device attached to the first downstream port of the
2568 * 4726, "Config Disk" appears, which is a pseudo ATA device to
2569 * configure the 4726. However, ATA emulation of the device is very
2570 * lame. It doesn't send signature D2H Reg FIS after the initial
2571 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
2572 *
2573 * The following function works around the problem by always using
2574 * hardreset on the port and not depending on receiving signature FIS
2575 * afterward. If signature FIS isn't received soon, ATA class is
2576 * assumed without follow-up softreset.
2577 */
2578static void ahci_p5wdh_workaround(struct ata_host *host)
2579{
2580 static struct dmi_system_id sysids[] = {
2581 {
2582 .ident = "P5W DH Deluxe",
2583 .matches = {
2584 DMI_MATCH(DMI_SYS_VENDOR,
2585 "ASUSTEK COMPUTER INC"),
2586 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
2587 },
2588 },
2589 { }
2590 };
2591 struct pci_dev *pdev = to_pci_dev(host->dev);
2592
2593 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
2594 dmi_check_system(sysids)) {
2595 struct ata_port *ap = host->ports[1];
2596
2597 dev_printk(KERN_INFO, &pdev->dev, "enabling ASUS P5W DH "
2598 "Deluxe on-board SIMG4726 workaround\n");
2599
2600 ap->ops = &ahci_p5wdh_ops;
2601 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
2602 }
2603}
2604
Shane Huang58a09b32009-05-27 15:04:43 +08002605/*
2606 * SB600 ahci controller on ASUS M2A-VM can't do 64bit DMA with older
2607 * BIOS. The oldest version known to be broken is 0901 and working is
2608 * 1501 which was released on 2007-10-26. Force 32bit DMA on anything
2609 * older than 1501. Please read bko#9412 for more info.
2610 */
2611static bool ahci_asus_m2a_vm_32bit_only(struct pci_dev *pdev)
2612{
2613 static const struct dmi_system_id sysids[] = {
2614 {
2615 .ident = "ASUS M2A-VM",
2616 .matches = {
2617 DMI_MATCH(DMI_BOARD_VENDOR,
2618 "ASUSTeK Computer INC."),
2619 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
2620 },
2621 },
2622 { }
2623 };
2624 const char *cutoff_mmdd = "10/26";
2625 const char *date;
2626 int year;
2627
2628 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
2629 !dmi_check_system(sysids))
2630 return false;
2631
2632 /*
2633 * Argh.... both version and date are free form strings.
2634 * Let's hope they're using the same date format across
2635 * different versions.
2636 */
2637 date = dmi_get_system_info(DMI_BIOS_DATE);
2638 year = dmi_get_year(DMI_BIOS_DATE);
2639 if (date && strlen(date) >= 10 && date[2] == '/' && date[5] == '/' &&
2640 (year > 2007 ||
2641 (year == 2007 && strncmp(date, cutoff_mmdd, 5) >= 0)))
2642 return false;
2643
2644 dev_printk(KERN_WARNING, &pdev->dev, "ASUS M2A-VM: BIOS too old, "
2645 "forcing 32bit DMA, update BIOS\n");
2646
2647 return true;
2648}
2649
Rafael J. Wysocki1fd68432009-01-19 20:57:36 +01002650static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
2651{
2652 static const struct dmi_system_id broken_systems[] = {
2653 {
2654 .ident = "HP Compaq nx6310",
2655 .matches = {
2656 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
2657 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
2658 },
2659 /* PCI slot number of the controller */
2660 .driver_data = (void *)0x1FUL,
2661 },
Maciej Ruteckid2f9c062009-03-20 00:06:46 +01002662 {
2663 .ident = "HP Compaq 6720s",
2664 .matches = {
2665 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
2666 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
2667 },
2668 /* PCI slot number of the controller */
2669 .driver_data = (void *)0x1FUL,
2670 },
Rafael J. Wysocki1fd68432009-01-19 20:57:36 +01002671
2672 { } /* terminate list */
2673 };
2674 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
2675
2676 if (dmi) {
2677 unsigned long slot = (unsigned long)dmi->driver_data;
2678 /* apply the quirk only to on-board controllers */
2679 return slot == PCI_SLOT(pdev->devfn);
2680 }
2681
2682 return false;
2683}
2684
Tejun Heo9b10ae82009-05-30 20:50:12 +09002685static bool ahci_broken_suspend(struct pci_dev *pdev)
2686{
2687 static const struct dmi_system_id sysids[] = {
2688 /*
2689 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
2690 * to the harddisk doesn't become online after
2691 * resuming from STR. Warn and fail suspend.
2692 */
2693 {
2694 .ident = "dv4",
2695 .matches = {
2696 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
2697 DMI_MATCH(DMI_PRODUCT_NAME,
2698 "HP Pavilion dv4 Notebook PC"),
2699 },
2700 .driver_data = "F.30", /* cutoff BIOS version */
2701 },
2702 {
2703 .ident = "dv5",
2704 .matches = {
2705 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
2706 DMI_MATCH(DMI_PRODUCT_NAME,
2707 "HP Pavilion dv5 Notebook PC"),
2708 },
2709 .driver_data = "F.16", /* cutoff BIOS version */
2710 },
2711 {
2712 .ident = "dv6",
2713 .matches = {
2714 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
2715 DMI_MATCH(DMI_PRODUCT_NAME,
2716 "HP Pavilion dv6 Notebook PC"),
2717 },
2718 .driver_data = "F.21", /* cutoff BIOS version */
2719 },
2720 {
2721 .ident = "HDX18",
2722 .matches = {
2723 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
2724 DMI_MATCH(DMI_PRODUCT_NAME,
2725 "HP HDX18 Notebook PC"),
2726 },
2727 .driver_data = "F.23", /* cutoff BIOS version */
2728 },
2729 { } /* terminate list */
2730 };
2731 const struct dmi_system_id *dmi = dmi_first_match(sysids);
2732 const char *ver;
2733
2734 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
2735 return false;
2736
2737 ver = dmi_get_system_info(DMI_BIOS_VERSION);
2738
2739 return !ver || strcmp(ver, dmi->driver_data) < 0;
2740}
2741
Tejun Heo55946392009-08-04 14:30:08 +09002742static bool ahci_broken_online(struct pci_dev *pdev)
2743{
2744#define ENCODE_BUSDEVFN(bus, slot, func) \
2745 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
2746 static const struct dmi_system_id sysids[] = {
2747 /*
2748 * There are several gigabyte boards which use
2749 * SIMG5723s configured as hardware RAID. Certain
2750 * 5723 firmware revisions shipped there keep the link
2751 * online but fail to answer properly to SRST or
2752 * IDENTIFY when no device is attached downstream
2753 * causing libata to retry quite a few times leading
2754 * to excessive detection delay.
2755 *
2756 * As these firmwares respond to the second reset try
2757 * with invalid device signature, considering unknown
2758 * sig as offline works around the problem acceptably.
2759 */
2760 {
2761 .ident = "EP45-DQ6",
2762 .matches = {
2763 DMI_MATCH(DMI_BOARD_VENDOR,
2764 "Gigabyte Technology Co., Ltd."),
2765 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
2766 },
2767 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
2768 },
2769 {
2770 .ident = "EP45-DS5",
2771 .matches = {
2772 DMI_MATCH(DMI_BOARD_VENDOR,
2773 "Gigabyte Technology Co., Ltd."),
2774 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
2775 },
2776 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
2777 },
2778 { } /* terminate list */
2779 };
2780#undef ENCODE_BUSDEVFN
2781 const struct dmi_system_id *dmi = dmi_first_match(sysids);
2782 unsigned int val;
2783
2784 if (!dmi)
2785 return false;
2786
2787 val = (unsigned long)dmi->driver_data;
2788
2789 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
2790}
2791
Tejun Heo24dc5f32007-01-20 16:00:28 +09002792static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002793{
2794 static int printed_version;
Tejun Heoe297d992008-06-10 00:13:04 +09002795 unsigned int board_id = ent->driver_data;
2796 struct ata_port_info pi = ahci_port_info[board_id];
Tejun Heo4447d352007-04-17 23:44:08 +09002797 const struct ata_port_info *ppi[] = { &pi, NULL };
Tejun Heo24dc5f32007-01-20 16:00:28 +09002798 struct device *dev = &pdev->dev;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002799 struct ahci_host_priv *hpriv;
Tejun Heo4447d352007-04-17 23:44:08 +09002800 struct ata_host *host;
Tejun Heo837f5f82008-02-06 15:13:51 +09002801 int n_ports, i, rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002802
2803 VPRINTK("ENTER\n");
2804
Tejun Heo12fad3f2006-05-15 21:03:55 +09002805 WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS);
2806
Linus Torvalds1da177e2005-04-16 15:20:36 -07002807 if (!printed_version++)
Jeff Garzika9524a72005-10-30 14:39:11 -05002808 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07002809
Alan Cox5b66c822008-09-03 14:48:34 +01002810 /* The AHCI driver can only drive the SATA ports, the PATA driver
2811 can drive them all so if both drivers are selected make sure
2812 AHCI stays out of the way */
2813 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
2814 return -ENODEV;
2815
Tejun Heo4447d352007-04-17 23:44:08 +09002816 /* acquire resources */
Tejun Heo24dc5f32007-01-20 16:00:28 +09002817 rc = pcim_enable_device(pdev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002818 if (rc)
2819 return rc;
2820
Tejun Heodea55132008-03-11 19:52:31 +09002821 /* AHCI controllers often implement SFF compatible interface.
2822 * Grab all PCI BARs just in case.
2823 */
2824 rc = pcim_iomap_regions_request_all(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
Tejun Heo0d5ff562007-02-01 15:06:36 +09002825 if (rc == -EBUSY)
Tejun Heo24dc5f32007-01-20 16:00:28 +09002826 pcim_pin_device(pdev);
Tejun Heo0d5ff562007-02-01 15:06:36 +09002827 if (rc)
Tejun Heo24dc5f32007-01-20 16:00:28 +09002828 return rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002829
Tejun Heoc4f77922007-12-06 15:09:43 +09002830 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
2831 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
2832 u8 map;
2833
2834 /* ICH6s share the same PCI ID for both piix and ahci
2835 * modes. Enabling ahci mode while MAP indicates
2836 * combined mode is a bad idea. Yield to ata_piix.
2837 */
2838 pci_read_config_byte(pdev, ICH_MAP, &map);
2839 if (map & 0x3) {
2840 dev_printk(KERN_INFO, &pdev->dev, "controller is in "
2841 "combined mode, can't enable AHCI mode\n");
2842 return -ENODEV;
2843 }
2844 }
2845
Tejun Heo24dc5f32007-01-20 16:00:28 +09002846 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
2847 if (!hpriv)
2848 return -ENOMEM;
Tejun Heo417a1a62007-09-23 13:19:55 +09002849 hpriv->flags |= (unsigned long)pi.private_data;
2850
Tejun Heoe297d992008-06-10 00:13:04 +09002851 /* MCP65 revision A1 and A2 can't do MSI */
2852 if (board_id == board_ahci_mcp65 &&
2853 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
2854 hpriv->flags |= AHCI_HFLAG_NO_MSI;
2855
Shane Huange427fe02008-12-30 10:53:41 +08002856 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
2857 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
2858 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
2859
Shane Huang58a09b32009-05-27 15:04:43 +08002860 /* apply ASUS M2A_VM quirk */
2861 if (ahci_asus_m2a_vm_32bit_only(pdev))
2862 hpriv->flags |= AHCI_HFLAG_32BIT_ONLY;
2863
Tejun Heoa5bfc472009-01-23 11:31:39 +09002864 if (!(hpriv->flags & AHCI_HFLAG_NO_MSI))
2865 pci_enable_msi(pdev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002866
Tejun Heo4447d352007-04-17 23:44:08 +09002867 /* save initial config */
Tejun Heo417a1a62007-09-23 13:19:55 +09002868 ahci_save_initial_config(pdev, hpriv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002869
Tejun Heo4447d352007-04-17 23:44:08 +09002870 /* prepare host */
Tejun Heo274c1fd2007-07-16 14:29:40 +09002871 if (hpriv->cap & HOST_CAP_NCQ)
Tejun Heo4447d352007-04-17 23:44:08 +09002872 pi.flags |= ATA_FLAG_NCQ;
2873
Tejun Heo7d50b602007-09-23 13:19:54 +09002874 if (hpriv->cap & HOST_CAP_PMP)
2875 pi.flags |= ATA_FLAG_PMP;
2876
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07002877 if (ahci_em_messages && (hpriv->cap & HOST_CAP_EMS)) {
2878 u8 messages;
2879 void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
2880 u32 em_loc = readl(mmio + HOST_EM_LOC);
2881 u32 em_ctl = readl(mmio + HOST_EM_CTL);
2882
David Milburn87943ac2008-10-13 14:38:36 -05002883 messages = (em_ctl & EM_CTRL_MSG_TYPE) >> 16;
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07002884
2885 /* we only support LED message type right now */
2886 if ((messages & 0x01) && (ahci_em_messages == 1)) {
2887 /* store em_loc */
2888 hpriv->em_loc = ((em_loc >> 16) * 4);
2889 pi.flags |= ATA_FLAG_EM;
2890 if (!(em_ctl & EM_CTL_ALHD))
2891 pi.flags |= ATA_FLAG_SW_ACTIVITY;
2892 }
2893 }
2894
Rafael J. Wysocki1fd68432009-01-19 20:57:36 +01002895 if (ahci_broken_system_poweroff(pdev)) {
2896 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
2897 dev_info(&pdev->dev,
2898 "quirky BIOS, skipping spindown on poweroff\n");
2899 }
2900
Tejun Heo9b10ae82009-05-30 20:50:12 +09002901 if (ahci_broken_suspend(pdev)) {
2902 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
2903 dev_printk(KERN_WARNING, &pdev->dev,
2904 "BIOS update required for suspend/resume\n");
2905 }
2906
Tejun Heo55946392009-08-04 14:30:08 +09002907 if (ahci_broken_online(pdev)) {
2908 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
2909 dev_info(&pdev->dev,
2910 "online status unreliable, applying workaround\n");
2911 }
2912
Tejun Heo837f5f82008-02-06 15:13:51 +09002913 /* CAP.NP sometimes indicate the index of the last enabled
2914 * port, at other times, that of the last possible port, so
2915 * determining the maximum port number requires looking at
2916 * both CAP.NP and port_map.
2917 */
2918 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
2919
2920 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
Tejun Heo4447d352007-04-17 23:44:08 +09002921 if (!host)
2922 return -ENOMEM;
2923 host->iomap = pcim_iomap_table(pdev);
2924 host->private_data = hpriv;
2925
Arjan van de Venf3d7f232009-01-26 02:05:44 -08002926 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
Arjan van de Ven886ad092009-01-09 15:54:07 -08002927 host->flags |= ATA_HOST_PARALLEL_SCAN;
Arjan van de Venf3d7f232009-01-26 02:05:44 -08002928 else
2929 printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n");
Arjan van de Ven886ad092009-01-09 15:54:07 -08002930
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07002931 if (pi.flags & ATA_FLAG_EM)
2932 ahci_reset_em(host);
2933
Tejun Heo4447d352007-04-17 23:44:08 +09002934 for (i = 0; i < host->n_ports; i++) {
Jeff Garzikdab632e2007-05-28 08:33:01 -04002935 struct ata_port *ap = host->ports[i];
Tejun Heo4447d352007-04-17 23:44:08 +09002936
Tejun Heocbcdd872007-08-18 13:14:55 +09002937 ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar");
2938 ata_port_pbar_desc(ap, AHCI_PCI_BAR,
2939 0x100 + ap->port_no * 0x80, "port");
2940
Kristen Carlson Accardi31556592007-10-25 01:33:26 -04002941 /* set initial link pm policy */
2942 ap->pm_policy = NOT_AVAILABLE;
2943
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07002944 /* set enclosure management message type */
2945 if (ap->flags & ATA_FLAG_EM)
2946 ap->em_message_type = ahci_em_messages;
2947
2948
Jeff Garzikdab632e2007-05-28 08:33:01 -04002949 /* disabled/not-implemented port */
Tejun Heo350756f2008-04-07 22:47:21 +09002950 if (!(hpriv->port_map & (1 << i)))
Jeff Garzikdab632e2007-05-28 08:33:01 -04002951 ap->ops = &ata_dummy_port_ops;
Tejun Heo4447d352007-04-17 23:44:08 +09002952 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002953
Tejun Heoedc93052007-10-25 14:59:16 +09002954 /* apply workaround for ASUS P5W DH Deluxe mainboard */
2955 ahci_p5wdh_workaround(host);
2956
Linus Torvalds1da177e2005-04-16 15:20:36 -07002957 /* initialize adapter */
Tejun Heo4447d352007-04-17 23:44:08 +09002958 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002959 if (rc)
Tejun Heo24dc5f32007-01-20 16:00:28 +09002960 return rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002961
Tejun Heo4447d352007-04-17 23:44:08 +09002962 rc = ahci_reset_controller(host);
2963 if (rc)
2964 return rc;
Tejun Heo12fad3f2006-05-15 21:03:55 +09002965
Tejun Heo4447d352007-04-17 23:44:08 +09002966 ahci_init_controller(host);
2967 ahci_print_info(host);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002968
Tejun Heo4447d352007-04-17 23:44:08 +09002969 pci_set_master(pdev);
2970 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
2971 &ahci_sht);
Jeff Garzik907f4672005-05-12 15:03:42 -04002972}
Linus Torvalds1da177e2005-04-16 15:20:36 -07002973
2974static int __init ahci_init(void)
2975{
Pavel Roskinb7887192006-08-10 18:13:18 +09002976 return pci_register_driver(&ahci_pci_driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002977}
2978
Linus Torvalds1da177e2005-04-16 15:20:36 -07002979static void __exit ahci_exit(void)
2980{
2981 pci_unregister_driver(&ahci_pci_driver);
2982}
2983
2984
2985MODULE_AUTHOR("Jeff Garzik");
2986MODULE_DESCRIPTION("AHCI SATA low-level driver");
2987MODULE_LICENSE("GPL");
2988MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
Jeff Garzik68854332005-08-23 02:53:51 -04002989MODULE_VERSION(DRV_VERSION);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002990
2991module_init(ahci_init);
2992module_exit(ahci_exit);