blob: 907a53ebc6e4dc62fc7a5226b6706af72d1e0d85 [file] [log] [blame]
Ron Rindjunsky1053d352008-05-05 10:22:43 +08001/******************************************************************************
2 *
3 * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved.
4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
25 * James P. Ketrenos <ipw2100-admin@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
Tomas Winklerfd4abac2008-05-15 13:54:07 +080030#include <linux/etherdevice.h>
Ron Rindjunsky1053d352008-05-05 10:22:43 +080031#include <net/mac80211.h>
32#include "iwl-eeprom.h"
33#include "iwl-dev.h"
34#include "iwl-core.h"
35#include "iwl-sta.h"
36#include "iwl-io.h"
37#include "iwl-helpers.h"
38
Tomas Winkler30e553e2008-05-29 16:35:16 +080039static const u16 default_tid_to_tx_fifo[] = {
40 IWL_TX_FIFO_AC1,
41 IWL_TX_FIFO_AC0,
42 IWL_TX_FIFO_AC0,
43 IWL_TX_FIFO_AC1,
44 IWL_TX_FIFO_AC2,
45 IWL_TX_FIFO_AC2,
46 IWL_TX_FIFO_AC3,
47 IWL_TX_FIFO_AC3,
48 IWL_TX_FIFO_NONE,
49 IWL_TX_FIFO_NONE,
50 IWL_TX_FIFO_NONE,
51 IWL_TX_FIFO_NONE,
52 IWL_TX_FIFO_NONE,
53 IWL_TX_FIFO_NONE,
54 IWL_TX_FIFO_NONE,
55 IWL_TX_FIFO_NONE,
56 IWL_TX_FIFO_AC3
57};
58
Tomas Winkler30e553e2008-05-29 16:35:16 +080059
Ron Rindjunsky1053d352008-05-05 10:22:43 +080060/**
61 * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
62 *
63 * Does NOT advance any TFD circular buffer read/write indexes
64 * Does NOT free the TFD itself (which is within circular buffer)
65 */
Emmanuel Grumbacha33c2f42008-09-03 11:26:56 +080066static int iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
Ron Rindjunsky1053d352008-05-05 10:22:43 +080067{
68 struct iwl_tfd_frame *bd_tmp = (struct iwl_tfd_frame *)&txq->bd[0];
69 struct iwl_tfd_frame *bd = &bd_tmp[txq->q.read_ptr];
70 struct pci_dev *dev = priv->pci_dev;
71 int i;
72 int counter = 0;
73 int index, is_odd;
74
75 /* Host command buffers stay mapped in memory, nothing to clean */
76 if (txq->q.id == IWL_CMD_QUEUE_NUM)
77 return 0;
78
79 /* Sanity check on number of chunks */
80 counter = IWL_GET_BITS(*bd, num_tbs);
81 if (counter > MAX_NUM_OF_TBS) {
82 IWL_ERROR("Too many chunks: %i\n", counter);
83 /* @todo issue fatal error, it is quite serious situation */
84 return 0;
85 }
86
87 /* Unmap chunks, if any.
88 * TFD info for odd chunks is different format than for even chunks. */
89 for (i = 0; i < counter; i++) {
90 index = i / 2;
91 is_odd = i & 0x1;
92
93 if (is_odd)
94 pci_unmap_single(
95 dev,
96 IWL_GET_BITS(bd->pa[index], tb2_addr_lo16) |
97 (IWL_GET_BITS(bd->pa[index],
98 tb2_addr_hi20) << 16),
99 IWL_GET_BITS(bd->pa[index], tb2_len),
100 PCI_DMA_TODEVICE);
101
102 else if (i > 0)
103 pci_unmap_single(dev,
104 le32_to_cpu(bd->pa[index].tb1_addr),
105 IWL_GET_BITS(bd->pa[index], tb1_len),
106 PCI_DMA_TODEVICE);
107
108 /* Free SKB, if any, for this chunk */
109 if (txq->txb[txq->q.read_ptr].skb[i]) {
110 struct sk_buff *skb = txq->txb[txq->q.read_ptr].skb[i];
111
112 dev_kfree_skb(skb);
113 txq->txb[txq->q.read_ptr].skb[i] = NULL;
114 }
115 }
116 return 0;
117}
Ron Rindjunsky1053d352008-05-05 10:22:43 +0800118
Emmanuel Grumbacha33c2f42008-09-03 11:26:56 +0800119static int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv, void *ptr,
Tomas Winklerfd4abac2008-05-15 13:54:07 +0800120 dma_addr_t addr, u16 len)
121{
122 int index, is_odd;
123 struct iwl_tfd_frame *tfd = ptr;
124 u32 num_tbs = IWL_GET_BITS(*tfd, num_tbs);
125
126 /* Each TFD can point to a maximum 20 Tx buffers */
roel kluin73ae98a2008-07-21 20:29:52 -0400127 if (num_tbs >= MAX_NUM_OF_TBS) {
Tomas Winklerfd4abac2008-05-15 13:54:07 +0800128 IWL_ERROR("Error can not send more than %d chunks\n",
129 MAX_NUM_OF_TBS);
130 return -EINVAL;
131 }
132
133 index = num_tbs / 2;
134 is_odd = num_tbs & 0x1;
135
136 if (!is_odd) {
137 tfd->pa[index].tb1_addr = cpu_to_le32(addr);
138 IWL_SET_BITS(tfd->pa[index], tb1_addr_hi,
139 iwl_get_dma_hi_address(addr));
140 IWL_SET_BITS(tfd->pa[index], tb1_len, len);
141 } else {
142 IWL_SET_BITS(tfd->pa[index], tb2_addr_lo16,
143 (u32) (addr & 0xffff));
144 IWL_SET_BITS(tfd->pa[index], tb2_addr_hi20, addr >> 16);
145 IWL_SET_BITS(tfd->pa[index], tb2_len, len);
146 }
147
148 IWL_SET_BITS(*tfd, num_tbs, num_tbs + 1);
149
150 return 0;
151}
Tomas Winklerfd4abac2008-05-15 13:54:07 +0800152
153/**
154 * iwl_txq_update_write_ptr - Send new write index to hardware
155 */
156int iwl_txq_update_write_ptr(struct iwl_priv *priv, struct iwl_tx_queue *txq)
157{
158 u32 reg = 0;
159 int ret = 0;
160 int txq_id = txq->q.id;
161
162 if (txq->need_update == 0)
163 return ret;
164
165 /* if we're trying to save power */
166 if (test_bit(STATUS_POWER_PMI, &priv->status)) {
167 /* wake up nic if it's powered down ...
168 * uCode will wake up, and interrupt us again, so next
169 * time we'll skip this part. */
170 reg = iwl_read32(priv, CSR_UCODE_DRV_GP1);
171
172 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
173 IWL_DEBUG_INFO("Requesting wakeup, GP1 = 0x%x\n", reg);
174 iwl_set_bit(priv, CSR_GP_CNTRL,
175 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
176 return ret;
177 }
178
179 /* restore this queue's parameters in nic hardware. */
180 ret = iwl_grab_nic_access(priv);
181 if (ret)
182 return ret;
183 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
184 txq->q.write_ptr | (txq_id << 8));
185 iwl_release_nic_access(priv);
186
187 /* else not in power-save mode, uCode will never sleep when we're
188 * trying to tx (during RFKILL, we're not trying to tx). */
189 } else
190 iwl_write32(priv, HBUS_TARG_WRPTR,
191 txq->q.write_ptr | (txq_id << 8));
192
193 txq->need_update = 0;
194
195 return ret;
196}
197EXPORT_SYMBOL(iwl_txq_update_write_ptr);
198
199
Ron Rindjunsky1053d352008-05-05 10:22:43 +0800200/**
201 * iwl_tx_queue_free - Deallocate DMA queue.
202 * @txq: Transmit queue to deallocate.
203 *
204 * Empty queue by removing and destroying all BD's.
205 * Free all buffers.
206 * 0-fill, but do not free "txq" descriptor structure.
207 */
Gregory Greenmanda99c4b2008-08-04 16:00:40 +0800208static void iwl_tx_queue_free(struct iwl_priv *priv, int txq_id)
Ron Rindjunsky1053d352008-05-05 10:22:43 +0800209{
Gregory Greenmanda99c4b2008-08-04 16:00:40 +0800210 struct iwl_tx_queue *txq = &priv->txq[txq_id];
Tomas Winkler443cfd42008-05-15 13:53:57 +0800211 struct iwl_queue *q = &txq->q;
Ron Rindjunsky1053d352008-05-05 10:22:43 +0800212 struct pci_dev *dev = priv->pci_dev;
Gregory Greenmanda99c4b2008-08-04 16:00:40 +0800213 int i, slots_num, len;
Ron Rindjunsky1053d352008-05-05 10:22:43 +0800214
215 if (q->n_bd == 0)
216 return;
217
218 /* first, empty all BD's */
219 for (; q->write_ptr != q->read_ptr;
220 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd))
221 iwl_hw_txq_free_tfd(priv, txq);
222
223 len = sizeof(struct iwl_cmd) * q->n_window;
224 if (q->id == IWL_CMD_QUEUE_NUM)
225 len += IWL_MAX_SCAN_SIZE;
226
227 /* De-alloc array of command/tx buffers */
Gregory Greenmanda99c4b2008-08-04 16:00:40 +0800228 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
229 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
230 for (i = 0; i < slots_num; i++)
231 kfree(txq->cmd[i]);
232 if (txq_id == IWL_CMD_QUEUE_NUM)
233 kfree(txq->cmd[slots_num]);
Ron Rindjunsky1053d352008-05-05 10:22:43 +0800234
235 /* De-alloc circular buffer of TFDs */
236 if (txq->q.n_bd)
237 pci_free_consistent(dev, sizeof(struct iwl_tfd_frame) *
238 txq->q.n_bd, txq->bd, txq->q.dma_addr);
239
240 /* De-alloc array of per-TFD driver data */
241 kfree(txq->txb);
242 txq->txb = NULL;
243
244 /* 0-fill queue descriptor structure */
245 memset(txq, 0, sizeof(*txq));
246}
247
Tomas Winklerfd4abac2008-05-15 13:54:07 +0800248/*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
249 * DMA services
250 *
251 * Theory of operation
252 *
253 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
254 * of buffer descriptors, each of which points to one or more data buffers for
255 * the device to read from or fill. Driver and device exchange status of each
256 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
257 * entries in each circular buffer, to protect against confusing empty and full
258 * queue states.
259 *
260 * The device reads or writes the data in the queues via the device's several
261 * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
262 *
263 * For Tx queue, there are low mark and high mark limits. If, after queuing
264 * the packet for Tx, free space become < low mark, Tx queue stopped. When
265 * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
266 * Tx queue resumed.
267 *
268 * See more detailed info in iwl-4965-hw.h.
269 ***************************************************/
270
271int iwl_queue_space(const struct iwl_queue *q)
272{
273 int s = q->read_ptr - q->write_ptr;
274
275 if (q->read_ptr > q->write_ptr)
276 s -= q->n_bd;
277
278 if (s <= 0)
279 s += q->n_window;
280 /* keep some reserve to not confuse empty and full situations */
281 s -= 2;
282 if (s < 0)
283 s = 0;
284 return s;
285}
286EXPORT_SYMBOL(iwl_queue_space);
287
288
Ron Rindjunsky1053d352008-05-05 10:22:43 +0800289/**
Ron Rindjunsky1053d352008-05-05 10:22:43 +0800290 * iwl_queue_init - Initialize queue's high/low-water and read/write indexes
291 */
Tomas Winkler443cfd42008-05-15 13:53:57 +0800292static int iwl_queue_init(struct iwl_priv *priv, struct iwl_queue *q,
Ron Rindjunsky1053d352008-05-05 10:22:43 +0800293 int count, int slots_num, u32 id)
294{
295 q->n_bd = count;
296 q->n_window = slots_num;
297 q->id = id;
298
299 /* count must be power-of-two size, otherwise iwl_queue_inc_wrap
300 * and iwl_queue_dec_wrap are broken. */
301 BUG_ON(!is_power_of_2(count));
302
303 /* slots_num must be power-of-two size, otherwise
304 * get_cmd_index is broken. */
305 BUG_ON(!is_power_of_2(slots_num));
306
307 q->low_mark = q->n_window / 4;
308 if (q->low_mark < 4)
309 q->low_mark = 4;
310
311 q->high_mark = q->n_window / 8;
312 if (q->high_mark < 2)
313 q->high_mark = 2;
314
315 q->write_ptr = q->read_ptr = 0;
316
317 return 0;
318}
319
320/**
321 * iwl_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
322 */
323static int iwl_tx_queue_alloc(struct iwl_priv *priv,
Ron Rindjunsky16466902008-05-05 10:22:50 +0800324 struct iwl_tx_queue *txq, u32 id)
Ron Rindjunsky1053d352008-05-05 10:22:43 +0800325{
326 struct pci_dev *dev = priv->pci_dev;
327
328 /* Driver private data, only for Tx (not command) queues,
329 * not shared with device. */
330 if (id != IWL_CMD_QUEUE_NUM) {
331 txq->txb = kmalloc(sizeof(txq->txb[0]) *
332 TFD_QUEUE_SIZE_MAX, GFP_KERNEL);
333 if (!txq->txb) {
334 IWL_ERROR("kmalloc for auxiliary BD "
335 "structures failed\n");
336 goto error;
337 }
338 } else
339 txq->txb = NULL;
340
341 /* Circular buffer of transmit frame descriptors (TFDs),
342 * shared with device */
343 txq->bd = pci_alloc_consistent(dev,
344 sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX,
345 &txq->q.dma_addr);
346
347 if (!txq->bd) {
348 IWL_ERROR("pci_alloc_consistent(%zd) failed\n",
349 sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX);
350 goto error;
351 }
352 txq->q.id = id;
353
354 return 0;
355
356 error:
357 kfree(txq->txb);
358 txq->txb = NULL;
359
360 return -ENOMEM;
361}
362
363/*
364 * Tell nic where to find circular buffer of Tx Frame Descriptors for
365 * given Tx queue, and enable the DMA channel used for that queue.
366 *
367 * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
368 * channels supported in hardware.
369 */
370static int iwl_hw_tx_queue_init(struct iwl_priv *priv,
Ron Rindjunsky16466902008-05-05 10:22:50 +0800371 struct iwl_tx_queue *txq)
Ron Rindjunsky1053d352008-05-05 10:22:43 +0800372{
373 int rc;
374 unsigned long flags;
375 int txq_id = txq->q.id;
376
377 spin_lock_irqsave(&priv->lock, flags);
378 rc = iwl_grab_nic_access(priv);
379 if (rc) {
380 spin_unlock_irqrestore(&priv->lock, flags);
381 return rc;
382 }
383
384 /* Circular buffer (TFD queue in DRAM) physical base address */
385 iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
386 txq->q.dma_addr >> 8);
387
388 /* Enable DMA channel, using same id as for TFD queue */
389 iwl_write_direct32(
390 priv, FH_TCSR_CHNL_TX_CONFIG_REG(txq_id),
391 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
392 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL);
393 iwl_release_nic_access(priv);
394 spin_unlock_irqrestore(&priv->lock, flags);
395
396 return 0;
397}
398
399/**
400 * iwl_tx_queue_init - Allocate and initialize one tx/cmd queue
401 */
Tomas Winkler73b7d742008-09-03 11:18:48 +0800402static int iwl_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq,
Ron Rindjunsky1053d352008-05-05 10:22:43 +0800403 int slots_num, u32 txq_id)
404{
Gregory Greenmanda99c4b2008-08-04 16:00:40 +0800405 int i, len;
Tomas Winkler73b7d742008-09-03 11:18:48 +0800406 int ret;
Ron Rindjunsky1053d352008-05-05 10:22:43 +0800407
408 /*
409 * Alloc buffer array for commands (Tx or other types of commands).
410 * For the command queue (#4), allocate command space + one big
411 * command for scan, since scan command is very huge; the system will
412 * not have two scans at the same time, so only one is needed.
413 * For normal Tx queues (all other queues), no super-size command
414 * space is needed.
415 */
Gregory Greenmanda99c4b2008-08-04 16:00:40 +0800416 len = sizeof(struct iwl_cmd);
417 for (i = 0; i <= slots_num; i++) {
418 if (i == slots_num) {
419 if (txq_id == IWL_CMD_QUEUE_NUM)
420 len += IWL_MAX_SCAN_SIZE;
421 else
422 continue;
423 }
424
John W. Linville49898852008-09-02 15:07:18 -0400425 txq->cmd[i] = kmalloc(len, GFP_KERNEL);
Gregory Greenmanda99c4b2008-08-04 16:00:40 +0800426 if (!txq->cmd[i])
Tomas Winkler73b7d742008-09-03 11:18:48 +0800427 goto err;
Gregory Greenmanda99c4b2008-08-04 16:00:40 +0800428 }
Ron Rindjunsky1053d352008-05-05 10:22:43 +0800429
430 /* Alloc driver data array and TFD circular buffer */
Tomas Winkler73b7d742008-09-03 11:18:48 +0800431 ret = iwl_tx_queue_alloc(priv, txq, txq_id);
432 if (ret)
433 goto err;
Ron Rindjunsky1053d352008-05-05 10:22:43 +0800434
Ron Rindjunsky1053d352008-05-05 10:22:43 +0800435 txq->need_update = 0;
436
437 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
438 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
439 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
440
441 /* Initialize queue's high/low-water marks, and head/tail indexes */
442 iwl_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
443
444 /* Tell device where to find queue */
445 iwl_hw_tx_queue_init(priv, txq);
446
447 return 0;
Tomas Winkler73b7d742008-09-03 11:18:48 +0800448err:
449 for (i = 0; i < slots_num; i++) {
450 kfree(txq->cmd[i]);
451 txq->cmd[i] = NULL;
452 }
453
454 if (txq_id == IWL_CMD_QUEUE_NUM) {
455 kfree(txq->cmd[slots_num]);
456 txq->cmd[slots_num] = NULL;
457 }
458 return -ENOMEM;
Ron Rindjunsky1053d352008-05-05 10:22:43 +0800459}
Tomas Winklerda1bc452008-05-29 16:35:00 +0800460/**
461 * iwl_hw_txq_ctx_free - Free TXQ Context
462 *
463 * Destroy all TX DMA queues and structures
464 */
465void iwl_hw_txq_ctx_free(struct iwl_priv *priv)
466{
467 int txq_id;
468
469 /* Tx queues */
470 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++)
Gregory Greenmanda99c4b2008-08-04 16:00:40 +0800471 iwl_tx_queue_free(priv, txq_id);
Tomas Winklerda1bc452008-05-29 16:35:00 +0800472
473 /* Keep-warm buffer */
474 iwl_kw_free(priv);
475}
476EXPORT_SYMBOL(iwl_hw_txq_ctx_free);
477
Ron Rindjunsky1053d352008-05-05 10:22:43 +0800478/**
479 * iwl_txq_ctx_reset - Reset TX queue context
480 * Destroys all DMA structures and initialise them again
481 *
482 * @param priv
483 * @return error code
484 */
485int iwl_txq_ctx_reset(struct iwl_priv *priv)
486{
487 int ret = 0;
488 int txq_id, slots_num;
Tomas Winklerda1bc452008-05-29 16:35:00 +0800489 unsigned long flags;
Ron Rindjunsky1053d352008-05-05 10:22:43 +0800490
491 iwl_kw_free(priv);
492
493 /* Free all tx/cmd queues and keep-warm buffer */
494 iwl_hw_txq_ctx_free(priv);
495
496 /* Alloc keep-warm buffer */
497 ret = iwl_kw_alloc(priv);
498 if (ret) {
Jiri Slaby6f147922008-08-11 23:49:41 +0200499 IWL_ERROR("Keep Warm allocation failed\n");
Ron Rindjunsky1053d352008-05-05 10:22:43 +0800500 goto error_kw;
501 }
Tomas Winklerda1bc452008-05-29 16:35:00 +0800502 spin_lock_irqsave(&priv->lock, flags);
503 ret = iwl_grab_nic_access(priv);
504 if (unlikely(ret)) {
505 spin_unlock_irqrestore(&priv->lock, flags);
506 goto error_reset;
507 }
Ron Rindjunsky1053d352008-05-05 10:22:43 +0800508
509 /* Turn off all Tx DMA fifos */
Tomas Winklerda1bc452008-05-29 16:35:00 +0800510 priv->cfg->ops->lib->txq_set_sched(priv, 0);
511
512 iwl_release_nic_access(priv);
513 spin_unlock_irqrestore(&priv->lock, flags);
514
Ron Rindjunsky1053d352008-05-05 10:22:43 +0800515
516 /* Tell nic where to find the keep-warm buffer */
517 ret = iwl_kw_init(priv);
518 if (ret) {
519 IWL_ERROR("kw_init failed\n");
520 goto error_reset;
521 }
522
Tomas Winklerda1bc452008-05-29 16:35:00 +0800523 /* Alloc and init all Tx queues, including the command queue (#4) */
Ron Rindjunsky1053d352008-05-05 10:22:43 +0800524 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
525 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
526 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
527 ret = iwl_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
528 txq_id);
529 if (ret) {
530 IWL_ERROR("Tx %d queue init failed\n", txq_id);
531 goto error;
532 }
533 }
534
535 return ret;
536
537 error:
538 iwl_hw_txq_ctx_free(priv);
539 error_reset:
540 iwl_kw_free(priv);
541 error_kw:
542 return ret;
543}
Emmanuel Grumbacha33c2f42008-09-03 11:26:56 +0800544
Tomas Winklerda1bc452008-05-29 16:35:00 +0800545/**
546 * iwl_txq_ctx_stop - Stop all Tx DMA channels, free Tx queue memory
547 */
548void iwl_txq_ctx_stop(struct iwl_priv *priv)
549{
550
551 int txq_id;
552 unsigned long flags;
553
554
555 /* Turn off all Tx DMA fifos */
556 spin_lock_irqsave(&priv->lock, flags);
557 if (iwl_grab_nic_access(priv)) {
558 spin_unlock_irqrestore(&priv->lock, flags);
559 return;
560 }
561
562 priv->cfg->ops->lib->txq_set_sched(priv, 0);
563
564 /* Stop each Tx DMA channel, and wait for it to be idle */
565 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
566 iwl_write_direct32(priv,
567 FH_TCSR_CHNL_TX_CONFIG_REG(txq_id), 0x0);
568 iwl_poll_direct_bit(priv, FH_TSSR_TX_STATUS_REG,
569 FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE
570 (txq_id), 200);
571 }
572 iwl_release_nic_access(priv);
573 spin_unlock_irqrestore(&priv->lock, flags);
574
575 /* Deallocate memory for all Tx queues */
576 iwl_hw_txq_ctx_free(priv);
577}
578EXPORT_SYMBOL(iwl_txq_ctx_stop);
Tomas Winklerfd4abac2008-05-15 13:54:07 +0800579
580/*
581 * handle build REPLY_TX command notification.
582 */
583static void iwl_tx_cmd_build_basic(struct iwl_priv *priv,
584 struct iwl_tx_cmd *tx_cmd,
Johannes Berge039fa42008-05-15 12:55:29 +0200585 struct ieee80211_tx_info *info,
Tomas Winklerfd4abac2008-05-15 13:54:07 +0800586 struct ieee80211_hdr *hdr,
587 int is_unicast, u8 std_id)
588{
Harvey Harrisonfd7c8a42008-06-11 14:21:56 -0700589 __le16 fc = hdr->frame_control;
Tomas Winklerfd4abac2008-05-15 13:54:07 +0800590 __le32 tx_flags = tx_cmd->tx_flags;
591
592 tx_cmd->stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
Johannes Berge039fa42008-05-15 12:55:29 +0200593 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
Tomas Winklerfd4abac2008-05-15 13:54:07 +0800594 tx_flags |= TX_CMD_FLG_ACK_MSK;
Harvey Harrisonfd7c8a42008-06-11 14:21:56 -0700595 if (ieee80211_is_mgmt(fc))
Tomas Winklerfd4abac2008-05-15 13:54:07 +0800596 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
Harvey Harrisonfd7c8a42008-06-11 14:21:56 -0700597 if (ieee80211_is_probe_resp(fc) &&
Tomas Winklerfd4abac2008-05-15 13:54:07 +0800598 !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
599 tx_flags |= TX_CMD_FLG_TSF_MSK;
600 } else {
601 tx_flags &= (~TX_CMD_FLG_ACK_MSK);
602 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
603 }
604
Harvey Harrisonfd7c8a42008-06-11 14:21:56 -0700605 if (ieee80211_is_back_req(fc))
Tomas Winklerfd4abac2008-05-15 13:54:07 +0800606 tx_flags |= TX_CMD_FLG_ACK_MSK | TX_CMD_FLG_IMM_BA_RSP_MASK;
607
608
609 tx_cmd->sta_id = std_id;
Harvey Harrison8b7b1e02008-06-11 14:21:56 -0700610 if (ieee80211_has_morefrags(fc))
Tomas Winklerfd4abac2008-05-15 13:54:07 +0800611 tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
612
Harvey Harrisonfd7c8a42008-06-11 14:21:56 -0700613 if (ieee80211_is_data_qos(fc)) {
614 u8 *qc = ieee80211_get_qos_ctl(hdr);
Tomas Winklerfd4abac2008-05-15 13:54:07 +0800615 tx_cmd->tid_tspec = qc[0] & 0xf;
616 tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
617 } else {
618 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
619 }
620
Emmanuel Grumbacha326a5d2008-07-11 11:53:31 +0800621 priv->cfg->ops->utils->rts_tx_cmd_flag(info, &tx_flags);
Tomas Winklerfd4abac2008-05-15 13:54:07 +0800622
623 if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK))
624 tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
625
626 tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
Harvey Harrisonfd7c8a42008-06-11 14:21:56 -0700627 if (ieee80211_is_mgmt(fc)) {
628 if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc))
Tomas Winklerfd4abac2008-05-15 13:54:07 +0800629 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(3);
630 else
631 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(2);
632 } else {
633 tx_cmd->timeout.pm_frame_timeout = 0;
634 }
635
636 tx_cmd->driver_txop = 0;
637 tx_cmd->tx_flags = tx_flags;
638 tx_cmd->next_frame_len = 0;
639}
640
641#define RTS_HCCA_RETRY_LIMIT 3
642#define RTS_DFAULT_RETRY_LIMIT 60
643
644static void iwl_tx_cmd_build_rate(struct iwl_priv *priv,
645 struct iwl_tx_cmd *tx_cmd,
Johannes Berge039fa42008-05-15 12:55:29 +0200646 struct ieee80211_tx_info *info,
Harvey Harrisonfd7c8a42008-06-11 14:21:56 -0700647 __le16 fc, int sta_id,
Tomas Winklerfd4abac2008-05-15 13:54:07 +0800648 int is_hcca)
649{
650 u8 rts_retry_limit = 0;
651 u8 data_retry_limit = 0;
652 u8 rate_plcp;
653 u16 rate_flags = 0;
Johannes Berg2e92e6f2008-05-15 12:55:27 +0200654 int rate_idx;
655
Johannes Berge039fa42008-05-15 12:55:29 +0200656 rate_idx = min(ieee80211_get_tx_rate(priv->hw, info)->hw_value & 0xffff,
Johannes Berg2e92e6f2008-05-15 12:55:27 +0200657 IWL_RATE_COUNT - 1);
Tomas Winklerfd4abac2008-05-15 13:54:07 +0800658
659 rate_plcp = iwl_rates[rate_idx].plcp;
660
661 rts_retry_limit = (is_hcca) ?
662 RTS_HCCA_RETRY_LIMIT : RTS_DFAULT_RETRY_LIMIT;
663
664 if ((rate_idx >= IWL_FIRST_CCK_RATE) && (rate_idx <= IWL_LAST_CCK_RATE))
665 rate_flags |= RATE_MCS_CCK_MSK;
666
667
Harvey Harrisonfd7c8a42008-06-11 14:21:56 -0700668 if (ieee80211_is_probe_resp(fc)) {
Tomas Winklerfd4abac2008-05-15 13:54:07 +0800669 data_retry_limit = 3;
670 if (data_retry_limit < rts_retry_limit)
671 rts_retry_limit = data_retry_limit;
672 } else
673 data_retry_limit = IWL_DEFAULT_TX_RETRY;
674
675 if (priv->data_retry_limit != -1)
676 data_retry_limit = priv->data_retry_limit;
677
678
679 if (ieee80211_is_data(fc)) {
680 tx_cmd->initial_rate_index = 0;
681 tx_cmd->tx_flags |= TX_CMD_FLG_STA_RATE_MSK;
682 } else {
Harvey Harrisonfd7c8a42008-06-11 14:21:56 -0700683 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
684 case cpu_to_le16(IEEE80211_STYPE_AUTH):
685 case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
686 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
687 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
Tomas Winklerfd4abac2008-05-15 13:54:07 +0800688 if (tx_cmd->tx_flags & TX_CMD_FLG_RTS_MSK) {
689 tx_cmd->tx_flags &= ~TX_CMD_FLG_RTS_MSK;
690 tx_cmd->tx_flags |= TX_CMD_FLG_CTS_MSK;
691 }
692 break;
693 default:
694 break;
695 }
696
697 /* Alternate between antenna A and B for successive frames */
698 if (priv->use_ant_b_for_management_frame) {
699 priv->use_ant_b_for_management_frame = 0;
700 rate_flags |= RATE_MCS_ANT_B_MSK;
701 } else {
702 priv->use_ant_b_for_management_frame = 1;
703 rate_flags |= RATE_MCS_ANT_A_MSK;
704 }
705 }
706
707 tx_cmd->rts_retry_limit = rts_retry_limit;
708 tx_cmd->data_retry_limit = data_retry_limit;
Tomas Winklere7d326a2008-06-12 09:47:11 +0800709 tx_cmd->rate_n_flags = iwl_hw_set_rate_n_flags(rate_plcp, rate_flags);
Tomas Winklerfd4abac2008-05-15 13:54:07 +0800710}
711
712static void iwl_tx_cmd_build_hwcrypto(struct iwl_priv *priv,
Johannes Berge039fa42008-05-15 12:55:29 +0200713 struct ieee80211_tx_info *info,
Tomas Winklerfd4abac2008-05-15 13:54:07 +0800714 struct iwl_tx_cmd *tx_cmd,
715 struct sk_buff *skb_frag,
716 int sta_id)
717{
Johannes Berge039fa42008-05-15 12:55:29 +0200718 struct ieee80211_key_conf *keyconf = info->control.hw_key;
Tomas Winklerfd4abac2008-05-15 13:54:07 +0800719
Emmanuel Grumbachccc038a2008-05-15 13:54:09 +0800720 switch (keyconf->alg) {
Tomas Winklerfd4abac2008-05-15 13:54:07 +0800721 case ALG_CCMP:
722 tx_cmd->sec_ctl = TX_CMD_SEC_CCM;
Emmanuel Grumbachccc038a2008-05-15 13:54:09 +0800723 memcpy(tx_cmd->key, keyconf->key, keyconf->keylen);
Johannes Berge039fa42008-05-15 12:55:29 +0200724 if (info->flags & IEEE80211_TX_CTL_AMPDU)
Tomas Winklerfd4abac2008-05-15 13:54:07 +0800725 tx_cmd->tx_flags |= TX_CMD_FLG_AGG_CCMP_MSK;
726 IWL_DEBUG_TX("tx_cmd with aes hwcrypto\n");
727 break;
728
729 case ALG_TKIP:
730 tx_cmd->sec_ctl = TX_CMD_SEC_TKIP;
Emmanuel Grumbachccc038a2008-05-15 13:54:09 +0800731 ieee80211_get_tkip_key(keyconf, skb_frag,
Tomas Winklerfd4abac2008-05-15 13:54:07 +0800732 IEEE80211_TKIP_P2_KEY, tx_cmd->key);
733 IWL_DEBUG_TX("tx_cmd with tkip hwcrypto\n");
734 break;
735
736 case ALG_WEP:
Tomas Winklerfd4abac2008-05-15 13:54:07 +0800737 tx_cmd->sec_ctl |= (TX_CMD_SEC_WEP |
Emmanuel Grumbachccc038a2008-05-15 13:54:09 +0800738 (keyconf->keyidx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT);
739
740 if (keyconf->keylen == WEP_KEY_LEN_128)
741 tx_cmd->sec_ctl |= TX_CMD_SEC_KEY128;
742
743 memcpy(&tx_cmd->key[3], keyconf->key, keyconf->keylen);
Tomas Winklerfd4abac2008-05-15 13:54:07 +0800744
745 IWL_DEBUG_TX("Configuring packet for WEP encryption "
Emmanuel Grumbachccc038a2008-05-15 13:54:09 +0800746 "with key %d\n", keyconf->keyidx);
Tomas Winklerfd4abac2008-05-15 13:54:07 +0800747 break;
748
749 default:
Emmanuel Grumbachccc038a2008-05-15 13:54:09 +0800750 printk(KERN_ERR "Unknown encode alg %d\n", keyconf->alg);
Tomas Winklerfd4abac2008-05-15 13:54:07 +0800751 break;
752 }
753}
754
755static void iwl_update_tx_stats(struct iwl_priv *priv, u16 fc, u16 len)
756{
757 /* 0 - mgmt, 1 - cnt, 2 - data */
758 int idx = (fc & IEEE80211_FCTL_FTYPE) >> 2;
759 priv->tx_stats[idx].cnt++;
760 priv->tx_stats[idx].bytes += len;
761}
762
763/*
764 * start REPLY_TX command process
765 */
Johannes Berge039fa42008-05-15 12:55:29 +0200766int iwl_tx_skb(struct iwl_priv *priv, struct sk_buff *skb)
Tomas Winklerfd4abac2008-05-15 13:54:07 +0800767{
768 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
Johannes Berge039fa42008-05-15 12:55:29 +0200769 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
Tomas Winklerfd4abac2008-05-15 13:54:07 +0800770 struct iwl_tfd_frame *tfd;
Tomas Winklerf3674222008-08-04 16:00:44 +0800771 struct iwl_tx_queue *txq;
772 struct iwl_queue *q;
773 struct iwl_cmd *out_cmd;
774 struct iwl_tx_cmd *tx_cmd;
775 int swq_id, txq_id;
Tomas Winklerfd4abac2008-05-15 13:54:07 +0800776 dma_addr_t phys_addr;
777 dma_addr_t txcmd_phys;
778 dma_addr_t scratch_phys;
Tomas Winklerfd4abac2008-05-15 13:54:07 +0800779 u16 len, idx, len_org;
780 u16 seq_number = 0;
Harvey Harrisonfd7c8a42008-06-11 14:21:56 -0700781 __le16 fc;
Tomas Winklerf3674222008-08-04 16:00:44 +0800782 u8 hdr_len, unicast;
783 u8 sta_id;
Tomas Winklerfd4abac2008-05-15 13:54:07 +0800784 u8 wait_write_ptr = 0;
785 u8 tid = 0;
786 u8 *qc = NULL;
787 unsigned long flags;
788 int ret;
789
790 spin_lock_irqsave(&priv->lock, flags);
791 if (iwl_is_rfkill(priv)) {
792 IWL_DEBUG_DROP("Dropping - RF KILL\n");
793 goto drop_unlock;
794 }
795
Johannes Berge039fa42008-05-15 12:55:29 +0200796 if ((ieee80211_get_tx_rate(priv->hw, info)->hw_value & 0xFF) ==
Johannes Berg2e92e6f2008-05-15 12:55:27 +0200797 IWL_INVALID_RATE) {
Tomas Winklerfd4abac2008-05-15 13:54:07 +0800798 IWL_ERROR("ERROR: No TX rate available.\n");
799 goto drop_unlock;
800 }
801
802 unicast = !is_multicast_ether_addr(hdr->addr1);
Tomas Winklerfd4abac2008-05-15 13:54:07 +0800803
Harvey Harrisonfd7c8a42008-06-11 14:21:56 -0700804 fc = hdr->frame_control;
Tomas Winklerfd4abac2008-05-15 13:54:07 +0800805
806#ifdef CONFIG_IWLWIFI_DEBUG
807 if (ieee80211_is_auth(fc))
808 IWL_DEBUG_TX("Sending AUTH frame\n");
Harvey Harrisonfd7c8a42008-06-11 14:21:56 -0700809 else if (ieee80211_is_assoc_req(fc))
Tomas Winklerfd4abac2008-05-15 13:54:07 +0800810 IWL_DEBUG_TX("Sending ASSOC frame\n");
Harvey Harrisonfd7c8a42008-06-11 14:21:56 -0700811 else if (ieee80211_is_reassoc_req(fc))
Tomas Winklerfd4abac2008-05-15 13:54:07 +0800812 IWL_DEBUG_TX("Sending REASSOC frame\n");
813#endif
814
815 /* drop all data frame if we are not associated */
Harvey Harrisonfd7c8a42008-06-11 14:21:56 -0700816 if (ieee80211_is_data(fc) &&
Johannes Berg05c914f2008-09-11 00:01:58 +0200817 (priv->iw_mode != NL80211_IFTYPE_MONITOR ||
Stefanik Gábord10c4ec2008-09-03 11:26:59 +0800818 !(info->flags & IEEE80211_TX_CTL_INJECTED)) && /* packet injection */
819 (!iwl_is_associated(priv) ||
Johannes Berg05c914f2008-09-11 00:01:58 +0200820 ((priv->iw_mode == NL80211_IFTYPE_STATION) && !priv->assoc_id) ||
Stefanik Gábord10c4ec2008-09-03 11:26:59 +0800821 !priv->assoc_station_added)) {
Tomas Winklerfd4abac2008-05-15 13:54:07 +0800822 IWL_DEBUG_DROP("Dropping - !iwl_is_associated\n");
823 goto drop_unlock;
824 }
825
826 spin_unlock_irqrestore(&priv->lock, flags);
827
Harvey Harrison7294ec92008-07-15 18:43:59 -0700828 hdr_len = ieee80211_hdrlen(fc);
Tomas Winklerfd4abac2008-05-15 13:54:07 +0800829
830 /* Find (or create) index into station table for destination station */
831 sta_id = iwl_get_sta_id(priv, hdr);
832 if (sta_id == IWL_INVALID_STATION) {
833 DECLARE_MAC_BUF(mac);
834
835 IWL_DEBUG_DROP("Dropping - INVALID STATION: %s\n",
836 print_mac(mac, hdr->addr1));
837 goto drop;
838 }
839
840 IWL_DEBUG_TX("station Id %d\n", sta_id);
841
Tomas Winklerf3674222008-08-04 16:00:44 +0800842 swq_id = skb_get_queue_mapping(skb);
843 txq_id = swq_id;
Harvey Harrisonfd7c8a42008-06-11 14:21:56 -0700844 if (ieee80211_is_data_qos(fc)) {
845 qc = ieee80211_get_qos_ctl(hdr);
Harvey Harrison7294ec92008-07-15 18:43:59 -0700846 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
Tomas Winklerf3674222008-08-04 16:00:44 +0800847 seq_number = priv->stations[sta_id].tid[tid].seq_number;
848 seq_number &= IEEE80211_SCTL_SEQ;
849 hdr->seq_ctrl = hdr->seq_ctrl &
850 __constant_cpu_to_le16(IEEE80211_SCTL_FRAG);
851 hdr->seq_ctrl |= cpu_to_le16(seq_number);
Tomas Winklerfd4abac2008-05-15 13:54:07 +0800852 seq_number += 0x10;
Tomas Winklerfd4abac2008-05-15 13:54:07 +0800853 /* aggregation is on for this <sta,tid> */
Johannes Berge039fa42008-05-15 12:55:29 +0200854 if (info->flags & IEEE80211_TX_CTL_AMPDU)
Tomas Winklerfd4abac2008-05-15 13:54:07 +0800855 txq_id = priv->stations[sta_id].tid[tid].agg.txq_id;
856 priv->stations[sta_id].tid[tid].tfds_in_queue++;
Tomas Winklerfd4abac2008-05-15 13:54:07 +0800857 }
858
859 /* Descriptor for chosen Tx queue */
860 txq = &priv->txq[txq_id];
861 q = &txq->q;
862
863 spin_lock_irqsave(&priv->lock, flags);
864
865 /* Set up first empty TFD within this queue's circular TFD buffer */
866 tfd = &txq->bd[q->write_ptr];
867 memset(tfd, 0, sizeof(*tfd));
Tomas Winklerfd4abac2008-05-15 13:54:07 +0800868 idx = get_cmd_index(q, q->write_ptr, 0);
869
870 /* Set up driver data for this TFD */
871 memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl_tx_info));
872 txq->txb[q->write_ptr].skb[0] = skb;
Tomas Winklerfd4abac2008-05-15 13:54:07 +0800873
874 /* Set up first empty entry in queue's array of Tx/cmd buffers */
Gregory Greenmanda99c4b2008-08-04 16:00:40 +0800875 out_cmd = txq->cmd[idx];
Tomas Winklerfd4abac2008-05-15 13:54:07 +0800876 tx_cmd = &out_cmd->cmd.tx;
877 memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
878 memset(tx_cmd, 0, sizeof(struct iwl_tx_cmd));
879
880 /*
881 * Set up the Tx-command (not MAC!) header.
882 * Store the chosen Tx queue and TFD index within the sequence field;
883 * after Tx, uCode's Tx response will return this value so driver can
884 * locate the frame within the tx queue and do post-tx processing.
885 */
886 out_cmd->hdr.cmd = REPLY_TX;
887 out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
888 INDEX_TO_SEQ(q->write_ptr)));
889
890 /* Copy MAC header from skb into command buffer */
891 memcpy(tx_cmd->hdr, hdr, hdr_len);
892
893 /*
894 * Use the first empty entry in this queue's command buffer array
895 * to contain the Tx command and MAC header concatenated together
896 * (payload data will be in another buffer).
897 * Size of this varies, due to varying MAC header length.
898 * If end is not dword aligned, we'll have 2 extra bytes at the end
899 * of the MAC header (device reads on dword boundaries).
900 * We'll tell device about this padding later.
901 */
902 len = sizeof(struct iwl_tx_cmd) +
903 sizeof(struct iwl_cmd_header) + hdr_len;
904
905 len_org = len;
906 len = (len + 3) & ~3;
907
908 if (len_org != len)
909 len_org = 1;
910 else
911 len_org = 0;
912
913 /* Physical address of this Tx command's header (not MAC header!),
914 * within command buffer array. */
Gregory Greenmanda99c4b2008-08-04 16:00:40 +0800915 txcmd_phys = pci_map_single(priv->pci_dev, out_cmd,
916 sizeof(struct iwl_cmd), PCI_DMA_TODEVICE);
917 txcmd_phys += offsetof(struct iwl_cmd, hdr);
Tomas Winklerfd4abac2008-05-15 13:54:07 +0800918
919 /* Add buffer containing Tx command and MAC(!) header to TFD's
920 * first entry */
921 iwl_hw_txq_attach_buf_to_tfd(priv, tfd, txcmd_phys, len);
922
Johannes Bergd0f09802008-07-29 11:32:07 +0200923 if (info->control.hw_key)
Johannes Berge039fa42008-05-15 12:55:29 +0200924 iwl_tx_cmd_build_hwcrypto(priv, info, tx_cmd, skb, sta_id);
Tomas Winklerfd4abac2008-05-15 13:54:07 +0800925
926 /* Set up TFD's 2nd entry to point directly to remainder of skb,
927 * if any (802.11 null frames have no payload). */
928 len = skb->len - hdr_len;
929 if (len) {
930 phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len,
931 len, PCI_DMA_TODEVICE);
932 iwl_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, len);
933 }
934
935 /* Tell NIC about any 2-byte padding after MAC header */
936 if (len_org)
937 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
938
939 /* Total # bytes to be transmitted */
940 len = (u16)skb->len;
941 tx_cmd->len = cpu_to_le16(len);
942 /* TODO need this for burst mode later on */
Johannes Berge039fa42008-05-15 12:55:29 +0200943 iwl_tx_cmd_build_basic(priv, tx_cmd, info, hdr, unicast, sta_id);
Tomas Winklerfd4abac2008-05-15 13:54:07 +0800944
945 /* set is_hcca to 0; it probably will never be implemented */
Johannes Berge039fa42008-05-15 12:55:29 +0200946 iwl_tx_cmd_build_rate(priv, tx_cmd, info, fc, sta_id, 0);
Tomas Winklerfd4abac2008-05-15 13:54:07 +0800947
Harvey Harrisonfd7c8a42008-06-11 14:21:56 -0700948 iwl_update_tx_stats(priv, le16_to_cpu(fc), len);
Tomas Winklerfd4abac2008-05-15 13:54:07 +0800949
950 scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) +
951 offsetof(struct iwl_tx_cmd, scratch);
952 tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
953 tx_cmd->dram_msb_ptr = iwl_get_dma_hi_address(scratch_phys);
954
Harvey Harrison8b7b1e02008-06-11 14:21:56 -0700955 if (!ieee80211_has_morefrags(hdr->frame_control)) {
Tomas Winklerfd4abac2008-05-15 13:54:07 +0800956 txq->need_update = 1;
957 if (qc)
958 priv->stations[sta_id].tid[tid].seq_number = seq_number;
959 } else {
960 wait_write_ptr = 1;
961 txq->need_update = 0;
962 }
963
964 iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd, sizeof(*tx_cmd));
965
966 iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd->hdr, hdr_len);
967
968 /* Set up entry for this TFD in Tx byte-count array */
969 priv->cfg->ops->lib->txq_update_byte_cnt_tbl(priv, txq, len);
970
971 /* Tell device the write index *just past* this latest filled TFD */
972 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
973 ret = iwl_txq_update_write_ptr(priv, txq);
974 spin_unlock_irqrestore(&priv->lock, flags);
975
976 if (ret)
977 return ret;
978
Tomas Winkler143b09e2008-07-24 21:33:42 +0300979 if ((iwl_queue_space(q) < q->high_mark) && priv->mac80211_registered) {
Tomas Winklerfd4abac2008-05-15 13:54:07 +0800980 if (wait_write_ptr) {
981 spin_lock_irqsave(&priv->lock, flags);
982 txq->need_update = 1;
983 iwl_txq_update_write_ptr(priv, txq);
984 spin_unlock_irqrestore(&priv->lock, flags);
Tomas Winkler143b09e2008-07-24 21:33:42 +0300985 } else {
Tomas Winklerf3674222008-08-04 16:00:44 +0800986 ieee80211_stop_queue(priv->hw, swq_id);
Tomas Winklerfd4abac2008-05-15 13:54:07 +0800987 }
Tomas Winklerfd4abac2008-05-15 13:54:07 +0800988 }
989
990 return 0;
991
992drop_unlock:
993 spin_unlock_irqrestore(&priv->lock, flags);
994drop:
995 return -1;
996}
997EXPORT_SYMBOL(iwl_tx_skb);
998
999/*************** HOST COMMAND QUEUE FUNCTIONS *****/
1000
1001/**
1002 * iwl_enqueue_hcmd - enqueue a uCode command
1003 * @priv: device private data point
1004 * @cmd: a point to the ucode command structure
1005 *
1006 * The function returns < 0 values to indicate the operation is
1007 * failed. On success, it turns the index (> 0) of command in the
1008 * command queue.
1009 */
1010int iwl_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
1011{
1012 struct iwl_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM];
1013 struct iwl_queue *q = &txq->q;
1014 struct iwl_tfd_frame *tfd;
Tomas Winklerfd4abac2008-05-15 13:54:07 +08001015 struct iwl_cmd *out_cmd;
Tomas Winklerf3674222008-08-04 16:00:44 +08001016 dma_addr_t phys_addr;
1017 unsigned long flags;
1018 int len, ret;
Tomas Winklerfd4abac2008-05-15 13:54:07 +08001019 u32 idx;
1020 u16 fix_size;
Tomas Winklerfd4abac2008-05-15 13:54:07 +08001021
1022 cmd->len = priv->cfg->ops->utils->get_hcmd_size(cmd->id, cmd->len);
1023 fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr));
1024
1025 /* If any of the command structures end up being larger than
1026 * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then
1027 * we will need to increase the size of the TFD entries */
1028 BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) &&
1029 !(cmd->meta.flags & CMD_SIZE_HUGE));
1030
1031 if (iwl_is_rfkill(priv)) {
1032 IWL_DEBUG_INFO("Not sending command - RF KILL");
1033 return -EIO;
1034 }
1035
1036 if (iwl_queue_space(q) < ((cmd->meta.flags & CMD_ASYNC) ? 2 : 1)) {
1037 IWL_ERROR("No space for Tx\n");
1038 return -ENOSPC;
1039 }
1040
1041 spin_lock_irqsave(&priv->hcmd_lock, flags);
1042
1043 tfd = &txq->bd[q->write_ptr];
1044 memset(tfd, 0, sizeof(*tfd));
1045
Tomas Winklerfd4abac2008-05-15 13:54:07 +08001046
1047 idx = get_cmd_index(q, q->write_ptr, cmd->meta.flags & CMD_SIZE_HUGE);
Gregory Greenmanda99c4b2008-08-04 16:00:40 +08001048 out_cmd = txq->cmd[idx];
Tomas Winklerfd4abac2008-05-15 13:54:07 +08001049
1050 out_cmd->hdr.cmd = cmd->id;
1051 memcpy(&out_cmd->meta, &cmd->meta, sizeof(cmd->meta));
1052 memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len);
1053
1054 /* At this point, the out_cmd now has all of the incoming cmd
1055 * information */
1056
1057 out_cmd->hdr.flags = 0;
1058 out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(IWL_CMD_QUEUE_NUM) |
1059 INDEX_TO_SEQ(q->write_ptr));
1060 if (out_cmd->meta.flags & CMD_SIZE_HUGE)
Tomas Winkler9734cb22008-09-03 11:26:52 +08001061 out_cmd->hdr.sequence |= SEQ_HUGE_FRAME;
Gregory Greenmanda99c4b2008-08-04 16:00:40 +08001062 len = (idx == TFD_CMD_SLOTS) ?
1063 IWL_MAX_SCAN_SIZE : sizeof(struct iwl_cmd);
1064 phys_addr = pci_map_single(priv->pci_dev, out_cmd, len,
1065 PCI_DMA_TODEVICE);
1066 phys_addr += offsetof(struct iwl_cmd, hdr);
Tomas Winklerfd4abac2008-05-15 13:54:07 +08001067 iwl_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, fix_size);
1068
Esti Kummerded2ae72008-08-04 16:00:45 +08001069#ifdef CONFIG_IWLWIFI_DEBUG
1070 switch (out_cmd->hdr.cmd) {
1071 case REPLY_TX_LINK_QUALITY_CMD:
1072 case SENSITIVITY_CMD:
1073 IWL_DEBUG_HC_DUMP("Sending command %s (#%x), seq: 0x%04X, "
1074 "%d bytes at %d[%d]:%d\n",
1075 get_cmd_string(out_cmd->hdr.cmd),
1076 out_cmd->hdr.cmd,
1077 le16_to_cpu(out_cmd->hdr.sequence), fix_size,
1078 q->write_ptr, idx, IWL_CMD_QUEUE_NUM);
1079 break;
1080 default:
1081 IWL_DEBUG_HC("Sending command %s (#%x), seq: 0x%04X, "
1082 "%d bytes at %d[%d]:%d\n",
1083 get_cmd_string(out_cmd->hdr.cmd),
1084 out_cmd->hdr.cmd,
1085 le16_to_cpu(out_cmd->hdr.sequence), fix_size,
1086 q->write_ptr, idx, IWL_CMD_QUEUE_NUM);
1087 }
1088#endif
Tomas Winklerfd4abac2008-05-15 13:54:07 +08001089 txq->need_update = 1;
1090
1091 /* Set up entry in queue's byte count circular buffer */
1092 priv->cfg->ops->lib->txq_update_byte_cnt_tbl(priv, txq, 0);
1093
1094 /* Increment and update queue's write index */
1095 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
1096 ret = iwl_txq_update_write_ptr(priv, txq);
1097
1098 spin_unlock_irqrestore(&priv->hcmd_lock, flags);
1099 return ret ? ret : idx;
1100}
1101
Tomas Winkler17b88922008-05-29 16:35:12 +08001102int iwl_tx_queue_reclaim(struct iwl_priv *priv, int txq_id, int index)
1103{
1104 struct iwl_tx_queue *txq = &priv->txq[txq_id];
1105 struct iwl_queue *q = &txq->q;
1106 struct iwl_tx_info *tx_info;
1107 int nfreed = 0;
1108
1109 if ((index >= q->n_bd) || (iwl_queue_used(q, index) == 0)) {
1110 IWL_ERROR("Read index for DMA queue txq id (%d), index %d, "
1111 "is out of range [0-%d] %d %d.\n", txq_id,
1112 index, q->n_bd, q->write_ptr, q->read_ptr);
1113 return 0;
1114 }
1115
1116 for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
1117 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
1118
1119 tx_info = &txq->txb[txq->q.read_ptr];
1120 ieee80211_tx_status_irqsafe(priv->hw, tx_info->skb[0]);
1121 tx_info->skb[0] = NULL;
Tomas Winkler17b88922008-05-29 16:35:12 +08001122
Tomas Winkler972cf442008-05-29 16:35:13 +08001123 if (priv->cfg->ops->lib->txq_inval_byte_cnt_tbl)
1124 priv->cfg->ops->lib->txq_inval_byte_cnt_tbl(priv, txq);
1125
1126 iwl_hw_txq_free_tfd(priv, txq);
Tomas Winkler17b88922008-05-29 16:35:12 +08001127 nfreed++;
1128 }
1129 return nfreed;
1130}
1131EXPORT_SYMBOL(iwl_tx_queue_reclaim);
1132
1133
1134/**
1135 * iwl_hcmd_queue_reclaim - Reclaim TX command queue entries already Tx'd
1136 *
1137 * When FW advances 'R' index, all entries between old and new 'R' index
1138 * need to be reclaimed. As result, some free space forms. If there is
1139 * enough free space (> low mark), wake the stack that feeds us.
1140 */
1141static void iwl_hcmd_queue_reclaim(struct iwl_priv *priv, int txq_id, int index)
1142{
1143 struct iwl_tx_queue *txq = &priv->txq[txq_id];
1144 struct iwl_queue *q = &txq->q;
Gregory Greenmanda99c4b2008-08-04 16:00:40 +08001145 struct iwl_tfd_frame *bd = &txq->bd[index];
1146 dma_addr_t dma_addr;
1147 int is_odd, buf_len;
Tomas Winkler17b88922008-05-29 16:35:12 +08001148 int nfreed = 0;
1149
1150 if ((index >= q->n_bd) || (iwl_queue_used(q, index) == 0)) {
1151 IWL_ERROR("Read index for DMA queue txq id (%d), index %d, "
1152 "is out of range [0-%d] %d %d.\n", txq_id,
1153 index, q->n_bd, q->write_ptr, q->read_ptr);
1154 return;
1155 }
1156
1157 for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
1158 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
1159
1160 if (nfreed > 1) {
1161 IWL_ERROR("HCMD skipped: index (%d) %d %d\n", index,
1162 q->write_ptr, q->read_ptr);
1163 queue_work(priv->workqueue, &priv->restart);
1164 }
Gregory Greenmanda99c4b2008-08-04 16:00:40 +08001165 is_odd = (index/2) & 0x1;
1166 if (is_odd) {
1167 dma_addr = IWL_GET_BITS(bd->pa[index], tb2_addr_lo16) |
1168 (IWL_GET_BITS(bd->pa[index],
1169 tb2_addr_hi20) << 16);
1170 buf_len = IWL_GET_BITS(bd->pa[index], tb2_len);
1171 } else {
1172 dma_addr = le32_to_cpu(bd->pa[index].tb1_addr);
1173 buf_len = IWL_GET_BITS(bd->pa[index], tb1_len);
1174 }
1175
1176 pci_unmap_single(priv->pci_dev, dma_addr, buf_len,
1177 PCI_DMA_TODEVICE);
Tomas Winkler17b88922008-05-29 16:35:12 +08001178 nfreed++;
1179 }
1180}
1181
1182/**
1183 * iwl_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
1184 * @rxb: Rx buffer to reclaim
1185 *
1186 * If an Rx buffer has an async callback associated with it the callback
1187 * will be executed. The attached skb (if present) will only be freed
1188 * if the callback returns 1
1189 */
1190void iwl_tx_cmd_complete(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
1191{
1192 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
1193 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
1194 int txq_id = SEQ_TO_QUEUE(sequence);
1195 int index = SEQ_TO_INDEX(sequence);
Tomas Winkler17b88922008-05-29 16:35:12 +08001196 int cmd_index;
Tomas Winkler9734cb22008-09-03 11:26:52 +08001197 bool huge = !!(pkt->hdr.sequence & SEQ_HUGE_FRAME);
Tomas Winkler17b88922008-05-29 16:35:12 +08001198 struct iwl_cmd *cmd;
1199
1200 /* If a Tx command is being handled and it isn't in the actual
1201 * command queue then there a command routing bug has been introduced
1202 * in the queue management code. */
Johannes Berg55d6a3c2008-09-23 19:18:43 +02001203 if (WARN(txq_id != IWL_CMD_QUEUE_NUM,
1204 "wrong command queue %d, command id 0x%X\n", txq_id, pkt->hdr.cmd))
1205 return;
Tomas Winkler17b88922008-05-29 16:35:12 +08001206
1207 cmd_index = get_cmd_index(&priv->txq[IWL_CMD_QUEUE_NUM].q, index, huge);
Gregory Greenmanda99c4b2008-08-04 16:00:40 +08001208 cmd = priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_index];
Tomas Winkler17b88922008-05-29 16:35:12 +08001209
1210 /* Input error checking is done when commands are added to queue. */
1211 if (cmd->meta.flags & CMD_WANT_SKB) {
1212 cmd->meta.source->u.skb = rxb->skb;
1213 rxb->skb = NULL;
1214 } else if (cmd->meta.u.callback &&
1215 !cmd->meta.u.callback(priv, cmd, rxb->skb))
1216 rxb->skb = NULL;
1217
1218 iwl_hcmd_queue_reclaim(priv, txq_id, index);
1219
1220 if (!(cmd->meta.flags & CMD_ASYNC)) {
1221 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
1222 wake_up_interruptible(&priv->wait_command_queue);
1223 }
1224}
1225EXPORT_SYMBOL(iwl_tx_cmd_complete);
1226
Tomas Winkler30e553e2008-05-29 16:35:16 +08001227/*
1228 * Find first available (lowest unused) Tx Queue, mark it "active".
1229 * Called only when finding queue for aggregation.
1230 * Should never return anything < 7, because they should already
1231 * be in use as EDCA AC (0-3), Command (4), HCCA (5, 6).
1232 */
1233static int iwl_txq_ctx_activate_free(struct iwl_priv *priv)
1234{
1235 int txq_id;
1236
1237 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++)
1238 if (!test_and_set_bit(txq_id, &priv->txq_ctx_active_msk))
1239 return txq_id;
1240 return -1;
1241}
1242
1243int iwl_tx_agg_start(struct iwl_priv *priv, const u8 *ra, u16 tid, u16 *ssn)
1244{
1245 int sta_id;
1246 int tx_fifo;
1247 int txq_id;
1248 int ret;
1249 unsigned long flags;
1250 struct iwl_tid_data *tid_data;
1251 DECLARE_MAC_BUF(mac);
1252
1253 if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo)))
1254 tx_fifo = default_tid_to_tx_fifo[tid];
1255 else
1256 return -EINVAL;
1257
1258 IWL_WARNING("%s on ra = %s tid = %d\n",
1259 __func__, print_mac(mac, ra), tid);
1260
1261 sta_id = iwl_find_station(priv, ra);
1262 if (sta_id == IWL_INVALID_STATION)
1263 return -ENXIO;
1264
1265 if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_OFF) {
1266 IWL_ERROR("Start AGG when state is not IWL_AGG_OFF !\n");
1267 return -ENXIO;
1268 }
1269
1270 txq_id = iwl_txq_ctx_activate_free(priv);
1271 if (txq_id == -1)
1272 return -ENXIO;
1273
1274 spin_lock_irqsave(&priv->sta_lock, flags);
1275 tid_data = &priv->stations[sta_id].tid[tid];
1276 *ssn = SEQ_TO_SN(tid_data->seq_number);
1277 tid_data->agg.txq_id = txq_id;
1278 spin_unlock_irqrestore(&priv->sta_lock, flags);
1279
1280 ret = priv->cfg->ops->lib->txq_agg_enable(priv, txq_id, tx_fifo,
1281 sta_id, tid, *ssn);
1282 if (ret)
1283 return ret;
1284
1285 if (tid_data->tfds_in_queue == 0) {
1286 printk(KERN_ERR "HW queue is empty\n");
1287 tid_data->agg.state = IWL_AGG_ON;
1288 ieee80211_start_tx_ba_cb_irqsafe(priv->hw, ra, tid);
1289 } else {
1290 IWL_DEBUG_HT("HW queue is NOT empty: %d packets in HW queue\n",
1291 tid_data->tfds_in_queue);
1292 tid_data->agg.state = IWL_EMPTYING_HW_QUEUE_ADDBA;
1293 }
1294 return ret;
1295}
1296EXPORT_SYMBOL(iwl_tx_agg_start);
1297
1298int iwl_tx_agg_stop(struct iwl_priv *priv , const u8 *ra, u16 tid)
1299{
1300 int tx_fifo_id, txq_id, sta_id, ssn = -1;
1301 struct iwl_tid_data *tid_data;
1302 int ret, write_ptr, read_ptr;
1303 unsigned long flags;
1304 DECLARE_MAC_BUF(mac);
1305
1306 if (!ra) {
1307 IWL_ERROR("ra = NULL\n");
1308 return -EINVAL;
1309 }
1310
1311 if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo)))
1312 tx_fifo_id = default_tid_to_tx_fifo[tid];
1313 else
1314 return -EINVAL;
1315
1316 sta_id = iwl_find_station(priv, ra);
1317
1318 if (sta_id == IWL_INVALID_STATION)
1319 return -ENXIO;
1320
1321 if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_ON)
1322 IWL_WARNING("Stopping AGG while state not IWL_AGG_ON\n");
1323
1324 tid_data = &priv->stations[sta_id].tid[tid];
1325 ssn = (tid_data->seq_number & IEEE80211_SCTL_SEQ) >> 4;
1326 txq_id = tid_data->agg.txq_id;
1327 write_ptr = priv->txq[txq_id].q.write_ptr;
1328 read_ptr = priv->txq[txq_id].q.read_ptr;
1329
1330 /* The queue is not empty */
1331 if (write_ptr != read_ptr) {
1332 IWL_DEBUG_HT("Stopping a non empty AGG HW QUEUE\n");
1333 priv->stations[sta_id].tid[tid].agg.state =
1334 IWL_EMPTYING_HW_QUEUE_DELBA;
1335 return 0;
1336 }
1337
1338 IWL_DEBUG_HT("HW queue is empty\n");
1339 priv->stations[sta_id].tid[tid].agg.state = IWL_AGG_OFF;
1340
1341 spin_lock_irqsave(&priv->lock, flags);
1342 ret = priv->cfg->ops->lib->txq_agg_disable(priv, txq_id, ssn,
1343 tx_fifo_id);
1344 spin_unlock_irqrestore(&priv->lock, flags);
1345
1346 if (ret)
1347 return ret;
1348
1349 ieee80211_stop_tx_ba_cb_irqsafe(priv->hw, ra, tid);
1350
1351 return 0;
1352}
1353EXPORT_SYMBOL(iwl_tx_agg_stop);
1354
1355int iwl_txq_check_empty(struct iwl_priv *priv, int sta_id, u8 tid, int txq_id)
1356{
1357 struct iwl_queue *q = &priv->txq[txq_id].q;
1358 u8 *addr = priv->stations[sta_id].sta.sta.addr;
1359 struct iwl_tid_data *tid_data = &priv->stations[sta_id].tid[tid];
1360
1361 switch (priv->stations[sta_id].tid[tid].agg.state) {
1362 case IWL_EMPTYING_HW_QUEUE_DELBA:
1363 /* We are reclaiming the last packet of the */
1364 /* aggregated HW queue */
1365 if (txq_id == tid_data->agg.txq_id &&
1366 q->read_ptr == q->write_ptr) {
1367 u16 ssn = SEQ_TO_SN(tid_data->seq_number);
1368 int tx_fifo = default_tid_to_tx_fifo[tid];
1369 IWL_DEBUG_HT("HW queue empty: continue DELBA flow\n");
1370 priv->cfg->ops->lib->txq_agg_disable(priv, txq_id,
1371 ssn, tx_fifo);
1372 tid_data->agg.state = IWL_AGG_OFF;
1373 ieee80211_stop_tx_ba_cb_irqsafe(priv->hw, addr, tid);
1374 }
1375 break;
1376 case IWL_EMPTYING_HW_QUEUE_ADDBA:
1377 /* We are reclaiming the last packet of the queue */
1378 if (tid_data->tfds_in_queue == 0) {
1379 IWL_DEBUG_HT("HW queue empty: continue ADDBA flow\n");
1380 tid_data->agg.state = IWL_AGG_ON;
1381 ieee80211_start_tx_ba_cb_irqsafe(priv->hw, addr, tid);
1382 }
1383 break;
1384 }
1385 return 0;
1386}
1387EXPORT_SYMBOL(iwl_txq_check_empty);
Tomas Winkler30e553e2008-05-29 16:35:16 +08001388
Emmanuel Grumbach653fa4a2008-06-30 17:23:11 +08001389/**
1390 * iwl_tx_status_reply_compressed_ba - Update tx status from block-ack
1391 *
1392 * Go through block-ack's bitmap of ACK'd frames, update driver's record of
1393 * ACK vs. not. This gets sent to mac80211, then to rate scaling algo.
1394 */
1395static int iwl_tx_status_reply_compressed_ba(struct iwl_priv *priv,
1396 struct iwl_ht_agg *agg,
1397 struct iwl_compressed_ba_resp *ba_resp)
1398
1399{
1400 int i, sh, ack;
1401 u16 seq_ctl = le16_to_cpu(ba_resp->seq_ctl);
1402 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
1403 u64 bitmap;
1404 int successes = 0;
1405 struct ieee80211_tx_info *info;
1406
1407 if (unlikely(!agg->wait_for_ba)) {
1408 IWL_ERROR("Received BA when not expected\n");
1409 return -EINVAL;
1410 }
1411
1412 /* Mark that the expected block-ack response arrived */
1413 agg->wait_for_ba = 0;
1414 IWL_DEBUG_TX_REPLY("BA %d %d\n", agg->start_idx, ba_resp->seq_ctl);
1415
1416 /* Calculate shift to align block-ack bits with our Tx window bits */
1417 sh = agg->start_idx - SEQ_TO_INDEX(seq_ctl>>4);
1418 if (sh < 0) /* tbw something is wrong with indices */
1419 sh += 0x100;
1420
1421 /* don't use 64-bit values for now */
1422 bitmap = le64_to_cpu(ba_resp->bitmap) >> sh;
1423
1424 if (agg->frame_count > (64 - sh)) {
1425 IWL_DEBUG_TX_REPLY("more frames than bitmap size");
1426 return -1;
1427 }
1428
1429 /* check for success or failure according to the
1430 * transmitted bitmap and block-ack bitmap */
1431 bitmap &= agg->bitmap;
1432
1433 /* For each frame attempted in aggregation,
1434 * update driver's record of tx frame's status. */
1435 for (i = 0; i < agg->frame_count ; i++) {
Emmanuel Grumbach4aa41f12008-07-18 13:53:09 +08001436 ack = bitmap & (1ULL << i);
Emmanuel Grumbach653fa4a2008-06-30 17:23:11 +08001437 successes += !!ack;
1438 IWL_DEBUG_TX_REPLY("%s ON i=%d idx=%d raw=%d\n",
1439 ack? "ACK":"NACK", i, (agg->start_idx + i) & 0xff,
1440 agg->start_idx + i);
1441 }
1442
1443 info = IEEE80211_SKB_CB(priv->txq[scd_flow].txb[agg->start_idx].skb[0]);
1444 memset(&info->status, 0, sizeof(info->status));
1445 info->flags = IEEE80211_TX_STAT_ACK;
1446 info->flags |= IEEE80211_TX_STAT_AMPDU;
1447 info->status.ampdu_ack_map = successes;
1448 info->status.ampdu_ack_len = agg->frame_count;
1449 iwl_hwrate_to_tx_control(priv, agg->rate_n_flags, info);
1450
1451 IWL_DEBUG_TX_REPLY("Bitmap %llx\n", (unsigned long long)bitmap);
1452
1453 return 0;
1454}
1455
1456/**
1457 * iwl_rx_reply_compressed_ba - Handler for REPLY_COMPRESSED_BA
1458 *
1459 * Handles block-acknowledge notification from device, which reports success
1460 * of frames sent via aggregation.
1461 */
1462void iwl_rx_reply_compressed_ba(struct iwl_priv *priv,
1463 struct iwl_rx_mem_buffer *rxb)
1464{
1465 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
1466 struct iwl_compressed_ba_resp *ba_resp = &pkt->u.compressed_ba;
1467 int index;
1468 struct iwl_tx_queue *txq = NULL;
1469 struct iwl_ht_agg *agg;
1470 DECLARE_MAC_BUF(mac);
1471
1472 /* "flow" corresponds to Tx queue */
1473 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
1474
1475 /* "ssn" is start of block-ack Tx window, corresponds to index
1476 * (in Tx queue's circular buffer) of first TFD/frame in window */
1477 u16 ba_resp_scd_ssn = le16_to_cpu(ba_resp->scd_ssn);
1478
1479 if (scd_flow >= priv->hw_params.max_txq_num) {
Jiri Slaby6f147922008-08-11 23:49:41 +02001480 IWL_ERROR("BUG_ON scd_flow is bigger than number of queues\n");
Emmanuel Grumbach653fa4a2008-06-30 17:23:11 +08001481 return;
1482 }
1483
1484 txq = &priv->txq[scd_flow];
1485 agg = &priv->stations[ba_resp->sta_id].tid[ba_resp->tid].agg;
1486
1487 /* Find index just before block-ack window */
1488 index = iwl_queue_dec_wrap(ba_resp_scd_ssn & 0xff, txq->q.n_bd);
1489
1490 /* TODO: Need to get this copy more safely - now good for debug */
1491
1492 IWL_DEBUG_TX_REPLY("REPLY_COMPRESSED_BA [%d]Received from %s, "
1493 "sta_id = %d\n",
1494 agg->wait_for_ba,
1495 print_mac(mac, (u8 *) &ba_resp->sta_addr_lo32),
1496 ba_resp->sta_id);
1497 IWL_DEBUG_TX_REPLY("TID = %d, SeqCtl = %d, bitmap = 0x%llx, scd_flow = "
1498 "%d, scd_ssn = %d\n",
1499 ba_resp->tid,
1500 ba_resp->seq_ctl,
1501 (unsigned long long)le64_to_cpu(ba_resp->bitmap),
1502 ba_resp->scd_flow,
1503 ba_resp->scd_ssn);
1504 IWL_DEBUG_TX_REPLY("DAT start_idx = %d, bitmap = 0x%llx \n",
1505 agg->start_idx,
1506 (unsigned long long)agg->bitmap);
1507
1508 /* Update driver's record of ACK vs. not for each frame in window */
1509 iwl_tx_status_reply_compressed_ba(priv, agg, ba_resp);
1510
1511 /* Release all TFDs before the SSN, i.e. all TFDs in front of
1512 * block-ack window (we assume that they've been successfully
1513 * transmitted ... if not, it's too late anyway). */
1514 if (txq->q.read_ptr != (ba_resp_scd_ssn & 0xff)) {
1515 /* calculate mac80211 ampdu sw queue to wake */
1516 int ampdu_q =
1517 scd_flow - priv->hw_params.first_ampdu_q + priv->hw->queues;
1518 int freed = iwl_tx_queue_reclaim(priv, scd_flow, index);
1519 priv->stations[ba_resp->sta_id].
1520 tid[ba_resp->tid].tfds_in_queue -= freed;
1521 if (iwl_queue_space(&txq->q) > txq->q.low_mark &&
1522 priv->mac80211_registered &&
1523 agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)
1524 ieee80211_wake_queue(priv->hw, ampdu_q);
1525
1526 iwl_txq_check_empty(priv, ba_resp->sta_id,
1527 ba_resp->tid, scd_flow);
1528 }
1529}
1530EXPORT_SYMBOL(iwl_rx_reply_compressed_ba);
1531
Helmut Schaa994d31f2008-07-02 12:17:06 +02001532#ifdef CONFIG_IWLWIFI_DEBUG
Tomas Winklera332f8d2008-05-29 16:35:08 +08001533#define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
1534
1535const char *iwl_get_tx_fail_reason(u32 status)
1536{
1537 switch (status & TX_STATUS_MSK) {
1538 case TX_STATUS_SUCCESS:
1539 return "SUCCESS";
1540 TX_STATUS_ENTRY(SHORT_LIMIT);
1541 TX_STATUS_ENTRY(LONG_LIMIT);
1542 TX_STATUS_ENTRY(FIFO_UNDERRUN);
1543 TX_STATUS_ENTRY(MGMNT_ABORT);
1544 TX_STATUS_ENTRY(NEXT_FRAG);
1545 TX_STATUS_ENTRY(LIFE_EXPIRE);
1546 TX_STATUS_ENTRY(DEST_PS);
1547 TX_STATUS_ENTRY(ABORTED);
1548 TX_STATUS_ENTRY(BT_RETRY);
1549 TX_STATUS_ENTRY(STA_INVALID);
1550 TX_STATUS_ENTRY(FRAG_DROPPED);
1551 TX_STATUS_ENTRY(TID_DISABLE);
1552 TX_STATUS_ENTRY(FRAME_FLUSHED);
1553 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
1554 TX_STATUS_ENTRY(TX_LOCKED);
1555 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
1556 }
1557
1558 return "UNKNOWN";
1559}
1560EXPORT_SYMBOL(iwl_get_tx_fail_reason);
1561#endif /* CONFIG_IWLWIFI_DEBUG */